Chip, preparation method thereof, wafer, and electronic device

Abstract

The application provides a chip and a preparation method thereof, a wafer and an electronic device, and relates to the technical field of semiconductors. The chip comprises a substrate, at least two dies, and a circuit layer on the substrate. The at least two dies comprise at least one first die and at least one second die. At least one groove is formed in the substrate of the first die. The second die is located in the groove, and the circuit layer of the second die is located on the side of the substrate of the second die away from the bottom wall of the groove. The circuit layer of the first die is electrically connected to the substrate through a first connecting piece, and the circuit layer of the second die is electrically connected to the substrate through a second connecting piece. Since the second die is located in the first die, the thickness of the chip can be reduced. When the chip is applied to an electronic device, the space occupied by the chip in the electronic device is small, which is conducive to the arrangement of other structures in the electronic device and the lightweight design of the electronic device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip and its fabrication method, a wafer, and an electronic device. Background Technology

[0002] As users increasingly demand thinner and lighter products, it is an urgent problem to solve how to make the thickness and size of the components and modules on the internal circuit boards of electronic devices such as mobile phones, tablets, and smart wearable devices smaller and smaller. Summary of the Invention

[0003] To address the aforementioned technical problems, this application provides a chip and its fabrication method, a wafer, and an electronic device, which can reduce the thickness of the chip and facilitate the lightweight and miniaturized design of electronic devices.

[0004] In a first aspect, this application provides a chip comprising: a substrate; at least two dies, each die including a base and a circuit layer located on the base; the at least two dies including at least one first die and at least one second die, the base of the first die having at least one groove, the second die being located within the groove, and the circuit layer of the second die being located on the side of the base of the second die facing away from the bottom wall of the groove; the circuit layer of the first die being electrically connected to the substrate via a first connector, and the circuit layer of the second die being electrically connected to the substrate via a second connector.

[0005] In this application, since the second die is located within the groove formed by the first die, the chip thickness can be reduced compared to placing the second die on the first die (e.g., reducing the thickness of at least one second die). When this chip is applied in an electronic device, it occupies less internal space, which is beneficial for the arrangement of other structures within the electronic device and for the thinner and lighter design of the electronic device.

[0006] According to the first aspect, the chip also includes a first protective layer located between the second die and the bottom wall of the groove.

[0007] The first protective layer can not only stably fix the second die in the groove and prevent the second die from moving in the groove, but also prevent stress from damaging the first die during the process of electrically connecting the circuit layer of the second die to the substrate. Furthermore, it can prevent stress caused by the deformation of the circuit layer from damaging the second die when the chip is applied to electronic devices.

[0008] For example, the first protective layer may include a structure such as a wafer bonding film that has both a cushioning effect and an adhesive function.

[0009] According to the first aspect, or any implementation of the first aspect above, the chip further includes a second protective layer, which fills the groove and covers the sidewall of the second die.

[0010] The second protective layer is used to wrap around the second grain to provide physical protection for the second grain.

[0011] It is understandable that when the second protective layer covers the second die, the surface of the circuit layer of the second die facing away from its substrate (i.e., the surface connected to the substrate) needs to be exposed here in order to facilitate electrical connection with the substrate.

[0012] According to the first aspect, or any implementation of the first aspect above, the chip further includes a molding compound layer, which is encapsulated on a substrate and covers the first die, the first connector, and the second connector.

[0013] The first die, the first connector, and the second connector are encapsulated with a molding compound to provide physical protection for the first die, the first connector, and the second connector, thereby isolating the first die, the first connector, and the second connector from external devices.

[0014] According to the first aspect, or any implementation of the first aspect above, the second protective layer and the molding compound are integrally formed. That is, when setting the molding compound, the material of the molding compound can fill the groove and surround the second grain to form the second protective layer. In this way, there is no need to set the second protective layer separately, simplifying the process steps.

[0015] Of course, the second protective layer and the encapsulation layer can also be formed separately. This makes the selection of materials for the encapsulation layer more flexible. That is, it is not necessary to choose a material that can fill the groove and wrap around the second grain.

[0016] According to the first aspect, or any implementation of the first aspect above, the substrate of the first die includes a first surface and a second surface opposite to each other, and also includes a side surface connecting the first surface and the second surface; the first surface is located on the side of the second surface away from the circuit layer of the first die, and the opening of the groove is located on the first surface.

[0017] Of course, the opening of the groove can be located not only on the first surface, but also on the second surface or the side surface.

[0018] According to the first aspect, or any implementation of the first aspect above, the distance between the groove and the side surface is greater than 200 μm.

[0019] This design prevents edge chipping of the first grain from damaging the second grain within the groove during subsequent cutting and other processes.

[0020] For example, the groove can be a cuboid groove, which includes four sidewalls. In this case, the distance between the groove and the side surface can be the distance between one of the sidewalls and the side surface, which can be the sidewall closest to the side surface.

[0021] According to the first aspect, or any implementation of the first aspect above, the surface flatness of the first surface is less than or equal to 50 μm.

[0022] This design facilitates the connection between the first connector and the substrate.

[0023] According to the first aspect, or any implementation of the first aspect above, the total area of ​​the opening of the groove is S1, the area of ​​the first surface is S2, and (S1 / S2)×100%<70%.

[0024] This design ensures the strength of the first grain and prevents the groove from significantly affecting its strength.

[0025] According to the first aspect, or any implementation of the first aspect above, the number of grooves is odd, and when the number of grooves is one, one groove is located at the center of the substrate of the first grain; when the number of grooves is greater than or equal to three, the groove includes one first groove and at least two second grooves, the first groove is located at the center of the first surface of the first grain, and the at least two second grooves are symmetrically arranged about a symmetry axis, wherein the symmetry axis passes through the center of the first surface.

[0026] This design ensures that the stress on the grooves of the first grain is balanced, preventing cracking caused by uneven stress in subsequent processes.

[0027] For example, when the substrate of the first grain is formed as a cuboid or cube, the first surface of the substrate is a rectangle or a square, and the center of the first surface can be the intersection of the two diagonals of the rectangle or square. In this case, the axis of symmetry can be any line passing through the center of the first surface; for example, this line can be parallel to the length of the rectangle, parallel to the width of the rectangle, or coincide with the diagonal of the rectangle. When the substrate of the first grain is formed as a cylinder, the first surface of the substrate is circular, and the center of the first surface can be the center of the circle. In this case, the axis of symmetry can be any line passing through the center of the first surface; for example, this line can coincide with any diameter of the circle. In this case, the center of the groove on the first surface can be the center of the bottom wall of the groove coinciding with the center of the first surface, or it can be any position where the straight line containing the center of the first surface passes through the bottom wall of the groove, etc.

[0028] According to the first aspect, or any implementation of the first aspect above, the number of grooves is even, and the even number of grooves are symmetrically arranged about the axis of symmetry, which passes through the center of the first surface of the first grain.

[0029] This design ensures that the stress on the grooves of the first grain is balanced, preventing cracking caused by uneven stress in subsequent processes.

[0030] According to the first aspect, or any implementation of the first aspect above, the circuit layer includes a first functional module, the overlapping area of ​​the projection of the first functional module on the reference plane and the projection of the groove on the reference plane is less than or equal to S3, S3 = 50% × S4, where S4 is the area of ​​the region where the first functional module is located, and the reference plane is parallel to the substrate.

[0031] In other words, the overlapping area of ​​the projection of the first functional module onto the reference plane and the projection of the groove onto the reference plane is less than or equal to 50% of the area of ​​the region where the first functional module is located. This setting can reduce the influence of the first functional module on the second grain within the groove.

[0032] For example, the overlapping area of ​​the projection of the first functional module onto the reference plane and the projection of the groove onto the reference plane is less than or equal to 40%, 30%, 20%, or 10% of the area of ​​the region where the first functional module is located.

[0033] According to the first aspect, or any implementation of the first aspect above, the projection of the first functional module onto the reference plane and the projection of the groove onto the reference plane do not overlap.

[0034] In other words, the first functional module is not opposite to the second grain within the groove. This arrangement minimizes the impact of the first functional module on the second grain within the groove.

[0035] For example, the first functional module can be a radio frequency module, which generates radio frequency signals. The second chip in the groove is a storage chip. The storage chip is susceptible to interference from radio frequency signals. Therefore, by setting the first functional module and the second chip separately (without overlapping projections), the interference of the first functional module to the second chip can be reduced.

[0036] For example, the first functional module can be a power amplifier module, which generates a large amount of power, i.e., generates a lot of heat. The second grain in the groove is a heat-sensitive grain, which is easily affected by the power amplifier module. Therefore, by setting the first functional module and the second grain separately (without overlapping projections), the interference of the first functional module on the second grain can be reduced.

[0037] According to the first aspect, or any implementation of the first aspect above, the substrate of the first die is located on the side of the circuit layer of the first die away from the substrate; the first connector includes a conductive post, and the second connector includes a conductive line.

[0038] With this configuration, when the chip is placed on the printed circuit board, the distance between the circuit layer of the first die and the printed circuit board is relatively close, which is beneficial for the rapid transmission of signals between the functional modules on the circuit layer of the first die and the printed circuit board.

[0039] For example, when the circuit layer of the second die is electrically connected to the substrate by a bonding process, the conductive wire is also called a bonding wire.

[0040] According to the first aspect, or any implementation of the first aspect above, the circuit layer of the first die is located on the side of the substrate of the first die away from the substrate; the first connector includes a conductive line, and the second connector includes a conductive post.

[0041] With this configuration, when the chip is placed on a printed circuit board, the distance between the circuit layer of the second die and the printed circuit board is relatively close, which is beneficial for the rapid transmission of signals between the functional modules on the circuit layer of the second die and the printed circuit board.

[0042] For example, when the circuit layer of the first die is electrically connected to the substrate by a bonding process, the conductive wire is also called a bonding wire.

[0043] According to the first aspect, or any implementation of the first aspect above, at least two dies further include at least one third die; the substrate includes a first region and a second region, the first die is located in the first region; the third die is located in the second region and is electrically connected to the substrate via a third connector.

[0044] The placement of the third die increases the chip's functionality without increasing its height.

[0045] According to the first aspect, or any implementation of the first aspect above, the substrate of the third die is located on the side of the circuit layer of the third die away from the substrate; the third connector includes a conductive post.

[0046] According to the first aspect, or any implementation of the first aspect above, the circuit layer of the third die is located on the side of the substrate of the third die away from the substrate; the third connector includes conductive lines.

[0047] For example, when the circuit layer of the third die is electrically connected to the substrate by a bonding process, the conductive wire is also called a bonding wire.

[0048] According to the first aspect, or any implementation of the first aspect above, the chip further includes a third protective layer located between the third die and the substrate.

[0049] The third protective layer not only secures the third die to the substrate, preventing it from moving, but also prevents stress from damaging the third die during the process of electrically connecting the circuit layer of the third die to the substrate.

[0050] For example, the third protective layer may include a structure such as a wafer bonding film that has both a cushioning effect and an adhesive function.

[0051] According to the first aspect, or any implementation of the first aspect above, the chip further includes solder balls, the first die and the solder balls are located on opposite sides of the substrate, and the solder balls are electrically connected to the substrate.

[0052] Secondly, this application provides an electronic device comprising the chip described in the first aspect and any implementation thereof.

[0053] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the second aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0054] Thirdly, this application provides a wafer comprising: a mother substrate; a mother circuit layer located on one side of the mother substrate, the mother circuit layer comprising a plurality of spaced chip placement areas, with a dicing channel formed between two adjacent chip placement areas; wherein, a plurality of grooves are formed on the side of the mother substrate away from the mother circuit layer, each chip placement area corresponding to at least one groove; a second die is disposed in the groove, and the circuit layer of the second die is located on the side of the second die substrate away from the bottom wall of the groove.

[0055] In this application, since the second die is located in the groove, when the wafer is cut along the dicing path to form multiple first dies, and the first dies are packaged, the thickness of the formed chip (e.g., reducing the thickness of at least one second die) is lower.

[0056] The mother substrate is the substrate of the wafer before it is diced. It is understood that after the wafer is diced along the dicing lines, the mother substrate is also divided into multiple sub-substrates, which are the die substrates mentioned above. The mother circuit layer is the circuit layer of the wafer before it is diced. It is understood that after the wafer is diced along the dicing lines, the mother circuit layer is also divided into multiple sub-circuit layers, which are the die circuit layers mentioned above.

[0057] According to the third aspect, the wafer also includes multiple conductive pillars located on the side of the mother circuit layer away from the mother substrate and electrically connected to the conductive pillars, with each chip setting area corresponding to at least one conductive pillar.

[0058] The placement of conductive pillars enables the connection between the chip and the printed circuit board. Since the wafer already includes conductive pillars, subsequent processes do not require additional pillars, avoiding the impact of higher temperatures during the conductive pillar installation process on the packaging structure.

[0059] According to the third aspect, or any implementation of the third aspect above, the wafer also includes a first protective layer located between the second die and the bottom of the groove.

[0060] The first protective layer can not only stably fix the second die in the groove and prevent the second die from moving in the groove, but also prevent stress from damaging the first die during the process of electrically connecting the circuit layer of the second die to the substrate (such as the packaging process after cutting the wafer along the dicing track to form the first die), and also prevent stress caused by the deformation of the circuit layer from damaging the second die when the chip is applied to electronic devices.

[0061] For example, the first protective layer may include a structure such as a wafer bonding film that has both a cushioning effect and an adhesive function.

[0062] According to the third aspect, or any implementation of the third aspect above, the wafer further includes a second protective layer, which fills the groove and covers the sidewall of the second grain.

[0063] The second protective layer is used to wrap around the second grain to provide physical protection for the second grain.

[0064] It is understandable that when the second protective layer covers the second die, the surface of the circuit layer of the second die facing away from its substrate (i.e., the surface connected to the substrate) needs to be exposed here in order to be electrically connected to the substrate.

[0065] Fourthly, this application provides a method for fabricating a chip, the method comprising: providing a mother substrate, a wafer, and a plurality of second dies; wherein the wafer includes a mother substrate and a mother circuit layer located on one side of the mother substrate, the mother circuit layer including a plurality of spaced-apart chip placement areas, and a dicing channel forming between two adjacent chip placement areas; forming a plurality of grooves on the side of the mother substrate away from the mother circuit layer; wherein each chip placement area corresponds to at least one groove; disposing the plurality of second dies in the plurality of grooves respectively; wherein the circuit layer of the second die is located on the side of the second die substrate away from the bottom wall of the groove; cutting the wafer along the dicing channel to form a plurality of first dies; disposing at least a portion of the first dies on the mother substrate, and the circuit layer of the first dies is electrically connected to the mother substrate through a first connector, and the circuit layer of the second dies is electrically connected to the mother substrate through a second connector; cutting the mother substrate to form a chip; wherein the number of chips formed is the same as the number of first dies.

[0066] The chip fabrication method described above can be used to form the chip in the first aspect and any implementation of the first aspect. Therefore, the technical effects of the chip fabrication method of the fourth aspect and any implementation of the fourth aspect can be found in the technical effects of the first aspect and any implementation of the first aspect, and will not be repeated here.

[0067] According to the fourth aspect, before cutting the mother substrate to form a chip, the method further includes: forming a molding compound on the mother substrate; wherein the molding compound covers the first die, the first connector, and the second connector.

[0068] According to the fourth aspect, or any implementation of the fourth aspect above, after the plurality of second grains are respectively disposed in the plurality of grooves, the method further includes: filling the grooves with a second protective layer and covering the sidewalls of the second grains.

[0069] According to the fourth aspect, or any implementation of the fourth aspect above, the wafer also includes a plurality of conductive pillars located on the side of the mother circuit layer away from the mother substrate, and the conductive pillars are electrically connected to the mother circuit layer, and each chip setting area corresponds to at least one conductive pillar.

[0070] According to the fourth aspect, or any implementation of the fourth aspect above, before forming multiple grooves on the side of the mother substrate away from the mother circuit layer, the method further includes: setting a first protective film on the side of the mother circuit layer away from the mother substrate; after setting multiple second dies in multiple grooves respectively, the method further includes: peeling off the first protective film.

[0071] The circuit layer and / or conductive pillars of the first die are protected by a first protective film to prevent damage to the circuit layer and / or conductive pillars of the first die caused by the process of forming the groove and the process of placing the second die in the groove.

[0072] According to the fourth aspect, or any implementation of the fourth aspect above, the first protective film includes an ultraviolet light-cured film; peeling off the first protective film includes: irradiating the first protective film with ultraviolet light to peel off the first protective film.

[0073] In this way, damage to the circuit layer and / or conductive pillars of the first die is reduced when the first protective film is peeled off.

[0074] According to the fourth aspect, or any implementation of the fourth aspect above, the wafer is cut along the dicing path to form a plurality of first dies, including: setting a second protective film on the side of the mother substrate away from the mother circuit layer; cutting the wafer along the dicing path to form a plurality of first dies; and peeling off the second protective film.

[0075] The second protective film protects the circuit layer of the second die and the substrate surface of the first die, which are already set in the groove, to avoid damage and wear to the circuit layer of the second die and the substrate surface of the first die during the cutting process. Attached Figure Description

[0076] Figure 1 A top view of a wafer;

[0077] Figure 2 A side view of a wafer;

[0078] Figure 3 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0079] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0080] Figure 5 for Figure 4 Cross-sectional view along the AA' direction;

[0081] Figure 6 This is a schematic diagram of the structure of another chip provided in an embodiment of this application;

[0082] Figure 7 This is a schematic diagram of the structure of another chip provided in an embodiment of this application;

[0083] Figure 8a This is a schematic diagram of the structure of a first grain provided in an embodiment of this application;

[0084] Figure 8b This is a schematic diagram of the structure of another first grain provided in an embodiment of this application;

[0085] Figure 9 A diagram showing the location of a groove on the first surface of a first grain, provided in an embodiment of this application;

[0086] Figure 10 A diagram showing the location of a groove on the first surface of a first grain, as provided in an embodiment of this application.

[0087] Figure 11 A diagram showing the location of a groove on the first surface of a first grain, as provided in an embodiment of this application.

[0088] Figure 12 This is a schematic diagram of the structure of another chip provided in an embodiment of this application;

[0089] Figure 13 for Figure 12 The diagram shows the location of the grooves on the first surface of the first die in the chip.

[0090] Figure 14 This is a schematic diagram of the structure of another chip provided in an embodiment of this application;

[0091] Figure 15 This is a schematic diagram of the structure of another chip provided in an embodiment of this application;

[0092] Figure 16 This is a schematic diagram of the structure of another chip provided in an embodiment of this application;

[0093] Figure 17 This is a schematic diagram of a wafer structure provided in an embodiment of this application;

[0094] Figure 18 A flowchart illustrating a chip fabrication method provided in this application embodiment;

[0095] Figure 19a This is a schematic diagram illustrating a method for fabricating a chip packaging structure according to an embodiment of this application.

[0096] Figure 19b This is a schematic diagram illustrating a method for fabricating a chip packaging structure according to an embodiment of this application.

[0097] Figure 19c This is a schematic diagram illustrating a method for fabricating a chip packaging structure according to an embodiment of this application.

[0098] Figure 19d This is a schematic diagram illustrating a method for fabricating a chip packaging structure according to an embodiment of this application.

[0099] Figure 19e This is a schematic diagram illustrating a method for fabricating a chip packaging structure according to an embodiment of this application.

[0100] Figure 19f This is a schematic diagram illustrating a method for fabricating a chip packaging structure according to an embodiment of this application.

[0101] Figure 19g This is a schematic diagram illustrating a method for fabricating a chip packaging structure according to an embodiment of this application.

[0102] Figure 19h This is a schematic diagram illustrating a method for fabricating a chip packaging structure according to an embodiment of this application.

[0103] Figure 19i This is a schematic diagram illustrating a method for fabricating a chip packaging structure according to an embodiment of this application.

[0104] Figure 19j This is a schematic diagram illustrating a method for fabricating a chip packaging structure according to an embodiment of this application.

[0105] Figure 19k This is a schematic diagram illustrating a method for fabricating a chip packaging structure according to an embodiment of this application.

[0106] Figure 19l This is a schematic diagram illustrating a method for fabricating a chip packaging structure according to an embodiment of this application. Detailed Implementation

[0107] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0108] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0109] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0110] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0111] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0112] Wafers are often used as an intermediate product in chip manufacturing. They need to be cut into dies, and then the dies are packaged with a packaging substrate to obtain the chip.

[0113] For example, see Figure 1 and Figure 2 , Figure 1 This is a top view of a wafer. Figure 2 The diagram shows a side view of a wafer 01. Wafer 01 includes a substrate (such as a silicon substrate) 02' and a circuit layer 03' located thereon. To distinguish between the substrate and the circuit layer, the substrate 02' can also be called the mother substrate, and the circuit layer 03' can also be called the mother circuit layer. Circuit layer 03' may include multiple alternating dielectric and metal layers (not shown in the diagram). Adjacent metal layers are connected by vias in the dielectric layers, and the surface of circuit layer 03' facing away from substrate 02' has at least one pad (also called a solder joint). Circuit layer 03 is divided into multiple chip placement areas 04, with gaps between adjacent chip placement areas 04, which can be called dicing channels (or dicing grooves) 05. Each chip placement area 04 includes multiple interconnected functional modules formed by metal layers (not shown in the diagram). The dicing channels 05 can be cut to separate multiple dies, with each chip placement area 04 corresponding to one die.

[0114] A chip may include multiple dies. See, for example... Figure 3 , Figure 3 This is a schematic diagram of a chip structure provided in an embodiment of this application. Figure 3Taking a chip comprising two dies as an example, the two dies are a first die 061 and a second die 062. The pads on the circuit layer 03 of the first die 061 (i.e., the sub-circuit layer 03' that is cut after wafer dicing) are electrically connected to the pads on the first surface 081 of the substrate 08 via conductive pillars 063. The second die 062 is disposed on the substrate 02 of the first die 061 (i.e., the sub-substrate 02' that is cut after wafer dicing) via an adhesive structure 065, and the circuit layer 03 of the second die 062 is located on the side of the adhesive structure 065 facing away from the substrate 02 of the first die 061. The pads on the circuit layer 03 of the second die 062 are electrically connected to the pads on the first surface 081 of the substrate 08 via conductive lines 064. The chip also includes a molding compound 09, which surrounds the first die 061 and the second die 062. This molding compound 09 encapsulates the first die 061 and the second die 062, providing physical protection and isolating them from external devices. The second surface 082 of the substrate 08 (the surface opposite the first surface 081 along its thickness direction) has multiple solder balls 083. The chip can be mounted on the circuit board of an electronic device and electrically connected to the circuit board within the electronic device via the solder balls (also called bumps) 083, thereby enabling signal transmission between the chip and other structures within the electronic device.

[0115] In the aforementioned chip, the thickness H1 of the substrate 08 can be 150 μm; the thickness H2 of the conductive pillar 063 can be 50 μm; the thickness H3 of the first die 061 can be 150 μm; the thickness H4 of the bonding structure 065 can be 20 μm; the thickness H5 of the second die 062 can be 100 μm; the height H6 of the portion of the conductive line 064 above the second die 062 can be 80 μm; the distance H7 between the highest point of the conductive line 064 and the molding compound 09 can be 100 μm. In other words, the thickness H0 of the entire molding compound 09 can be 500 μm; and the height H7 of the solder ball 083 can be 150 μm. In this case, the total thickness of the chip is 0.8 mm, which is relatively thick.

[0116] It should be noted that the above description only exemplifies the height of various structures in one chip. Of course, the thickness of the substrate 08, the thickness of the conductive pillar 063, the thickness of the first die 061, the thickness of the bonding structure 065, the thickness of the second die 062, the height of the portion of the conductive line 064 above the second die 062, the distance between the highest point of the conductive line 064 and the molding compound 09, and / or the height of the solder ball 083 can be adapted to meet different requirements.

[0117] However, with the development of electronic devices such as mobile phones, tablets, and smart wearable devices (such as smartwatches and smart bracelets), users are increasingly demanding thinner and lighter electronic devices. At the same time, to achieve better functionality, such as photography, electronic devices are using more and more cameras, and these cameras are becoming larger. This leaves less and less space on the circuit board for chips, making it a significant challenge to incorporate thicker, larger chips onto the board. Therefore, how to reduce chip size so that chips can be better used in electronic devices is an urgent problem to be solved.

[0118] Based on this, embodiments of this application also provide a chip, a wafer, and an electronic device. A groove is formed on the substrate of the wafer, with each chip placement area corresponding to at least one groove (i.e., the projection of each chip placement area onto the substrate covers at least one groove). A second die is placed within the groove, and then multiple first dies are cut out (i.e., the substrate of the first die contains the second die). The first dies are then packaged to obtain the chip. Since the second die is located within the first die, the chip thickness can be reduced. When this chip is applied to an electronic device, it occupies less internal space, which is beneficial for the arrangement of other structures within the electronic device and facilitates the thinner and lighter design of the electronic device.

[0119] The specific structure of the chip provided in the embodiments of this application will be described below with reference to an electronic device. The electronic device 100 provided in the embodiments of this application may include mobile phones, tablet computers, laptops, televisions, smart wearable devices (such as smartwatches and smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and other electronic products. The embodiments of this application do not impose special limitations on the specific form of the electronic device 100; the following description uses a mobile phone as an example.

[0120] See Figure 4 , Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 5 for Figure 4 Cross-sectional view along the AA' direction. Electronic device 100 includes display screen 10, middle frame 20 and rear cover 30.

[0121] The display screen 10 may include, for example, a liquid crystal display (LCD) panel, an organic light-emitting diode (OLED) display screen, and an LED display screen, wherein the LED display screen may include, for example, a micro-LED display screen and a mini-LED display screen. This application embodiment does not limit the type of the display screen 10.

[0122] The material of the aforementioned back cover 30 may include, for example, opaque materials such as plastic, vegan leather, and fiberglass; or it may include translucent materials such as glass. This application does not limit the material of the back cover 30 in its embodiments.

[0123] The middle frame 20 can be a ring structure, with the display screen 10 and the middle frame 20 located on opposite sides of the middle frame 20. The display screen 10, the middle frame 20, and the back cover 30 can form a receiving cavity. The receiving cavity contains a printed circuit board (PCB) 40 and a chip 50, etc. The chip 50 is located on the PCB 40 and is electrically connected to the PCB 40 through solder balls (not shown in the figure). In this way, the chip 50 can transmit signals to other structures within the electronic device 100 (structures electrically connected to the PCB 40, such as cameras, batteries, etc.) through the PCB 40.

[0124] Chip 50 may include an RF chip and / or a processing chip, wherein the processing chip may be a system-on-chip (SoC) or a central processing unit (CPU). In some embodiments, a shielding cover 60 may be provided on the PCB 40. The shielding cover 60 and the PCB 40 form a sealed space, within which the chip 50 may be disposed, and the shielding cover 60 may shield the chip 50 located within the sealed space from interference from other signals.

[0125] See Figure 6 , Figure 6 This is a schematic diagram of the structure of another chip provided in an embodiment of this application, and... Figure 3 The difference in the chip is that the first die 061 is located on one side of the substrate 08, and the base 02 of the first die 061 is located on the side of its circuit layer 03 facing away from the substrate 08. The base 02 of the first die 061 includes a first surface 021 and a second surface 022 opposite to each other, and also includes a side surface 023 connecting the first surface 021 and the second surface 022. The first surface 021 is located on the side of the second surface 022 facing away from its circuit layer 03. The base 02 of the first die 061 has at least one groove C1, and the opening of the groove C1 is located on the first surface 021. The second die 062 is located in the groove C1, and the circuit layer 03 of the second die 062 is located on the side of its base 02 facing away from the bottom wall of the groove C1. In addition, in order to ensure the strength of the first die 061, the thickness H3 of the first die 061 can be 170 μm; in order to facilitate the placement of the second die 062 in the groove C1, the thickness H5 of the second die 062 can be 50 μm.

[0126] In this configuration, in the chip 50, the thickness H1 of the substrate 08 can be 150 μm; the thickness H2 of the conductive pillar 063 can be 50 μm; the thickness H3 of the first die 061 can be 170 μm; the height H6 of the portion of the conductive line 064 above the second die 062 can be 80 μm; the distance H7 between the highest point of the conductive line 064 and the molding compound 09 can be 100 μm, meaning the total thickness H0 of the molding compound 09 can be 380 μm; and the height H7 of the solder balls 083 can be 150 μm. In this configuration, the total thickness of the chip is 0.68 mm, compared to... Figure 3 The chip shown in this embodiment is relatively thin.

[0127] It should be noted that, in order to... Figure 3 The above description only exemplifies the height of each structure in one type of chip compared to the chips in the example. Of course, the thickness of the substrate 08, the thickness of the conductive pillar 063, the thickness of the first die 061, the thickness of the bonding structure 065, the thickness of the second die 062, the height of the portion of the conductive line 064 above the second die 062, the distance between the highest point of the conductive line 064 and the molding compound 09, and / or the height of the solder ball 083 can be adaptively changed to meet different requirements.

[0128] In the chip 50 provided in this application embodiment, the second die 062 is located within the groove C1 formed by the first die 061. Although the height of the first die 061 is increased, the increased height is still less than the height of the second die 062. Of course, the height of the first die 061 can also be... Figure 3 The examples shown have the same height for the first grain 061, such as 150 μm; or, the height of the first grain 061 can be lower. Figure 3 In the example shown, the height of the first die 061 is, for example, 140 μm. Therefore, compared to placing the second die 062 on the first die 061, the overall thickness of the chip 50 can be reduced, thus providing more opportunities for the electronic device 100 to apply the chip 50. For example, as other functional devices (such as cameras) occupy more and more space within the electronic device 100, the space that can be occupied by the chip becomes smaller and smaller. For instance, in the thickness direction of the electronic device 100, the size that can be occupied by the processing chip can only be less than or equal to 1 mm (e.g., 0.9 mm, 0.8 mm, 0.7 mm, 0.6 mm, or 0.5 mm), and the size that can be occupied by the radio frequency chip can only be less than or equal to 1 mm (e.g., 0.9 mm, 0.8 mm, 0.7 mm, 0.6 mm, or 0.5 mm). For example, the size occupied by the processing chip is 0.7 mm, while the chip provided in this embodiment is only 0.68 mm thick. Therefore, the electronic device 100 can apply... Figure 6The aforementioned chip cannot be used. Figure 3 The chip shown is thus, for Figure 6 The chip shown offers more application opportunities. At the same time, due to the small size of chip 50, it occupies less space inside the electronic device, which is beneficial for the arrangement of other structures within the electronic device and for the thinner and lighter design of the electronic device.

[0129] Since the second grain 062 is located in the groove C1 and the opening of the groove C1 is located on the first surface 021, in order to facilitate the setting of conductive lines 064 on the circuit layer 03 of the second grain 062, the surface flatness of the first surface 021 is less than or equal to 50μm, such as 50μm, 40μm, 30μm, 20μm or 10μm.

[0130] In this embodiment, the surface flatness of the first surface 021 refers to the distance between the highest point (the point on the first surface 021 that is furthest from the circuit layer 03 of the first grain 061) and the lowest point (the point on the first surface 021 that is furthest from the circuit layer 03 of the first grain 061) along the thickness direction of the first grain 061.

[0131] It should be noted that the above description is based on the example of the first die 061 having its substrate 02 located on the side of its circuit layer 03 away from the substrate 08, which does not constitute a limitation of this application.

[0132] In other alternative embodiments of this application, see Figure 7 , Figure 7 This is a schematic diagram of another chip structure provided in an embodiment of this application. The circuit layer 03 of the first die 061 is located on the side of its substrate 02 facing away from the substrate 08. In this case, the pads on the circuit layer 03 of the first die 061 are electrically connected to the pads on the first surface 081 of the substrate 08 via conductive lines 064, and the pads on the circuit layer 03 of the second die 062 are electrically connected to the pads on the first surface 081 of the substrate 08 via conductive pillars 063. In this case, a plurality of support pillars 066 are provided between the substrate 02 of the first die 061 and the substrate 08, and the projections of the plurality of support pillars 066 on the first surface 021 of the substrate 02 are evenly distributed. This arrangement can provide better support for the first die 061.

[0133] Figure 6 The first chip 061 in the chip 50 is close to the substrate 08, and the first chip 061 is electrically connected to the substrate 08 through the conductive post 063, and the signal transmission rate between the first chip 061 and the substrate 08 is relatively fast. Figure 7In the chip 50, the second die 062 is relatively close to the substrate 08, and the second die 062 is electrically connected to the substrate 08 through a conductive post 063, resulting in a faster signal transmission rate between the second die 062 and the substrate 08. In other words, the positions of the first die 061 and the second die 062 relative to the substrate 08 can be selected according to the required signal transmission rate. This broadens the application range of the chip provided in this embodiment (applicable not only to applications requiring a faster signal transmission rate between the first die 061 and the substrate 08, but also to applications requiring a faster signal transmission rate between the second die 062 and the substrate 08).

[0134] It should be noted that, unless otherwise specified, the following descriptions are based on the example where the distance between the first die 061 and the substrate 08 is relatively close, and the first die 061 is electrically connected to the substrate 08 through the conductive post 063.

[0135] In some embodiments, please continue to see Figure 6 or Figure 7 The chip 50 also includes a first protective layer 065, which is located between the second die 062 and the bottom wall of the groove C1. The first protective layer 065 may include a structure such as a die attach film (DAF) that has both a buffering effect and an adhesive function.

[0136] The first protective layer 065 can not only stably fix the second chip 062 in the groove C1, preventing the second chip 062 from moving in the groove C1, but also buffer the stress generated in the direction of the first chip 061 when the circuit layer 03 of the second chip 062 is electrically connected to the conductive line 064 of the substrate 08, preventing the stress from being transmitted to the circuit layer 03 of the first chip 061 and causing damage to it. It can also buffer the stress generated by the deformation of the PCB 40 when the chip 50 is placed on the PCB 40 in the electronic device 100, preventing the stress from being transmitted to the circuit layer 03 of the second chip 062 and causing damage to it.

[0137] In some embodiments, please continue to see Figure 6 or Figure 7 The chip 50 also includes a second protective layer 067, which fills the groove C1 and covers the sidewall of the second die 062. That is, the second protective layer 067 is located in the groove C1 and covers the sidewall of the second die 062.

[0138] It is understood that when the chip 50 also includes a first protective layer 065 located between the second die 062 and the bottom wall of the groove C1, the second protective layer 067 also covers the sidewall of the first protective layer 065. It is also understood that when the second protective layer 067 covers the second die 062, it is necessary to expose the surface of the circuit layer 03 of the second die 062 facing away from its substrate 02 (i.e., the surface connected to the substrate 08), or only expose the pads on the circuit layer 03 of the second die 062, which can be electrically connected to the pads on the first surface 081 of the substrate 08. This application embodiment does not limit this.

[0139] The second protective layer 067 can wrap around the second grain 062 to provide physical protection to the second grain 062, preventing it from being interfered with by other structures, thereby ensuring the stable performance of the second grain 062.

[0140] The second protective layer 067 can be provided separately or integrally formed with the molding layer 09. When the second protective layer 067 is provided separately, it can be formed by filling the area of ​​the groove C1 except for the area where the second grain 062 is located with capillary underfill (CUF) adhesive. (It can be understood that when the first protective layer 065 is provided between the second grain 062 and the bottom wall of the groove C1, the second protective layer 067 can be formed by filling the area of ​​the groove C1 except for the area where the first protective layer 065 and the second grain 062 are located with CUF adhesive.) When the second protective layer 067 and the molding layer 09 are integrally formed (the second protective layer 067 and the molding layer 09 are completed in one process step), it can be formed by filling the groove C1 with molded underfill (MUF) glue and other materials in areas other than the area where the second grain 062 is located. (It can be understood that when the first protective layer 065 is located between the second grain 062 and the bottom wall of the groove C1, the second protective layer 067 can be formed by filling the groove C1 with MUF glue in areas other than the area where the first protective layer 065 and the second grain 062 are located). At the same time, the MUF glue is placed on the substrate 08 and also wraps the first grain 061, the conductive pillar 063, and the conductive wire 064. That is to say, the MUF glue not only fills the groove C1 and covers the second grain 062, but also fills the gap between the first grain 061 and the substrate 08 (such as...). Figure 6 In the process, the gap between two adjacent conductive pillars 063 between the circuit layer 03 of the first die 061 and the substrate 08, and the conductive lines 064 covering all surfaces of the first die 061, are used to improve the mechanical stability of the chip 50. When the second protective layer 067 and the molding compound layer 09 are completed in one process step, costs can be reduced and production efficiency can be greatly improved.

[0141] As described above, the first die 061 is formed by cutting along the dicing channel 05 of the wafer. During the cutting of the wafer along the dicing channel 05, cracks may form in the wafer substrate. If these cracks extend to the groove C1 during the cutting process, or continue to extend to the groove C1 during subsequent processes or the use of chip 50, they may damage the second die 062 within the groove C1. Therefore, please refer to [link to relevant documentation]. Figure 6 When setting the position of the groove C1, the distance W1 between the groove C1 and the side surface 023 of the first grain 061 can be greater than 200 μm. For example, the distance W1 between the groove C1 and the side surface 023 of the first grain 061 can be 205 μm, 210 μm, 215 μm, or 220 μm. With this setting, even if a crack exists during the cutting process, or if the crack continues to extend, it will not extend to the position of the groove C1, thus avoiding damage to the second grain 062.

[0142] As described above, each chip setting area 04 includes multiple interconnected functional modules formed by a metal layer. Correspondingly, a first die 061 includes multiple functional modules, each with a different function. For example, the first die 061 may be a die with radio frequency (RF) functionality; its multiple functional modules may include a control module, an RF module, a power amplifier module, and a power supply module, etc. Furthermore, since the chip 50 includes not only the first die 061 with RF functionality but also a second die 062 with other functions, such as a die with storage functionality, the second die 062 is susceptible to interference from RF signals (generated by the RF module). The recess C1 reduces the distance between the second die 062 and the circuit layer 03 of the first die 061, thus reducing the distance between the second die 062 and the RF module in circuit layer 03. This increases the likelihood of the second die 062 being interfered with by RF signals. Furthermore, the second die 062 is a heat-sensitive die, and heat-sensitive dies are easily affected by heat (the power amplifier module generates a significant amount of heat during operation). The recess C1 further reduces the distance between the second die 062 and the circuit layer 03 of the first die 061, increasing the likelihood of the second die 062 being interfered with by the power amplifier module.

[0143] Based on this, see Figure 8a , Figure 8a This is a schematic diagram of the structure of a first die provided in an embodiment of this application. The first die 061 includes a first functional module 031, a second functional module 032, a third functional module 033 and a fourth functional module 033 disposed in its circuit layer 03.

[0144] The first functional module 031 can be a radio frequency (RF) module, the second functional module 032 can be a control module, the third functional module 033 can be a power amplifier module, and the fourth functional module 033 can be a power supply module. The projection of the first functional module 031, i.e., the RF module, onto the plane of the first surface 021 of the substrate 02 does not overlap with the projection of the groove C1 onto the reference plane. Correspondingly, the projection of the first functional module 031, i.e., the RF module, onto the plane of the first surface 021 of the substrate 02 does not overlap with the projection of the second die 062, i.e., the storage die, onto the reference plane. In other words, in the thickness direction of the chip 50, the RF module and the storage die within the groove C1 are not opposite each other. This arrangement increases the distance between the RF module and the storage die, thereby minimizing the impact of the RF module on the storage die within the groove C1.

[0145] The first functional module 031 can be a power amplifier module, the second functional module 032 can be a control module, the third functional module 033 can be an RF module, and the fourth functional module 033 can be a power supply module. The projection of the first functional module 031, i.e., the power amplifier module, onto the plane of the first surface 021 of the substrate 02 does not overlap with the projection of the groove C1 onto the reference plane. Correspondingly, the projection of the first functional module 031, i.e., the power amplifier module, onto the plane of the first surface 021 of the substrate 02 does not overlap with the projection of the second die 062, i.e., the heat-sensitive die, onto the reference plane. In other words, in the thickness direction of the chip 50, the power amplifier module and the heat-sensitive die in the groove C1 are not opposite each other. This arrangement increases the distance between the power amplifier module and the heat-sensitive die, thereby minimizing the impact of the power amplifier module on the heat-sensitive die in the groove C1.

[0146] It should be noted that, Figure 8a The description is based on the example of the first functional module 031, the second functional module 032, the third functional module 033, and the fourth functional module 033 being arranged sequentially along the surface parallel to the first surface 021. However, this does not constitute a limitation of this application. Those skilled in the art can adjust the first functional module 031, the second functional module 032, the third functional module 033, and the fourth functional module 033 according to the actual situation. Correspondingly, the position of the groove C1 can be selected according to the specific function of the second grain 062, as long as the second grain 062 and the module that affects it are staggered.

[0147] Of course, those skilled in the art can also set the relationship between the projection of the first functional module 031 onto the plane of the first surface 021 of the substrate 02 and the projection of the groove C1 onto the first surface 021 of the substrate 02, depending on the actual situation. For example, when the number of grooves C1 is large, making it impossible to avoid overlapping with the first functional module 031, or when the first functional module 031 has an impact on the grains in the groove C1 but the impact is small, see [reference needed]. Figure 8b , Figure 8b This is a schematic diagram of the structure of a first grain provided in an embodiment of this application. The overlapping area of ​​the projection of the first functional module 031 onto the plane of the first surface 021 of the substrate 02 and the projection of the groove C1 onto the first surface 021 of the substrate 02 can be set to be less than or equal to S3, where S3 = 50% × S4, and S4 is the area of ​​the region where the first functional module 031 is located. That is, the overlapping area of ​​the projection of the first functional module 031 onto the first surface 021 of the substrate 02 and the projection of the groove C1 onto the first surface 021 of the substrate 02 is less than or equal to fifty percent of the area of ​​the region where the first functional module 031 is located. For example, the overlapping area of ​​the projection of the first functional module 031 onto the first surface 021 of the substrate 02 and the projection of the groove C1 onto the first surface 021 of the substrate 02 is less than or equal to forty percent, thirty percent, twenty percent, or ten percent of the area of ​​the region where the first functional module 031 is located, etc. As can be seen from the above embodiments, each embodiment is described using one groove C1 as an example. This does not constitute a limitation on this application. In other optional embodiments of this application, the number of grooves C1 can be multiple. When the number of grooves C1 is different, the setting position of the grooves C1 is different. The following describes the different cases.

[0148] See one example. Figure 9 , Figure 9 This application provides a diagram showing the location of a groove on the first surface of a first grain. The number of grooves C1 is one, and the groove C1 is located at the center of the substrate 02 of the first grain 061.

[0149] The center of the substrate 02 of the first grain 061 can be the center position of the first surface 021 of the substrate 02.

[0150] For example, please continue to see Figure 9 When the shape of the substrate 02 of the first grain 061 is a cuboid or a cube, the corresponding first surface 021 of the substrate 02 is a rectangle or a square, and the center of the first surface 021 of the substrate 02 can be the intersection point O1 of the two diagonals of the rectangle.

[0151] For example, see Figure 10 , Figure 10Another groove provided in this application embodiment is located on the first surface of the first grain. When the shape of the substrate 02 of the first grain 061 is cylindrical, the corresponding first surface 021 of the substrate 02 is circular, and the center of the first surface 021 of the substrate 02 can be the center O2 of the circle.

[0152] In this case, the location of the groove C1 at the center of the substrate 02 of the first die 061 can be either the center of the bottom wall of the groove C1 and the center of the substrate 02 of the first die 061 coinciding; or it can be any position where the straight line containing the center of the substrate 02 of the first die 061 (a straight line along the thickness direction of the chip 50) passes through the bottom wall of the groove C1. That is, the center of the substrate 02 of the first die 061 is offset from the center of the bottom wall of the groove C1, but the projection of the center of the substrate 02 of the first die 061 onto the plane containing the bottom wall of the groove C1 is still located on the bottom wall. The explanation of the center of the substrate 02 of the first die 061 and the location of the groove C1 at the center of the substrate 02 is the same in the following examples, and will not be repeated in the following examples.

[0153] When there is only one groove C1, placing the groove C1 at the center of the first surface 021 of the substrate 02 can make the stress on the groove C1 uniform, avoiding problems such as chip 50 cracking due to uneven stress in subsequent processes.

[0154] See another example. Figure 11 , Figure 11 This application provides another embodiment of the groove location diagram on the first surface of the first grain, wherein the number of grooves C1 is odd, and the number of grooves C1 is greater than or equal to three. Figure 11 The explanation is based on the example of three grooves C1. The three grooves C1 include a first groove C11 and two second grooves C12. The first groove C11 is located at the center of the substrate 02 of the first grain 061, and the two second grooves C12 are symmetrically arranged about the axis of symmetry, which passes through the center of the first surface 021 of the substrate 02.

[0155] For example, when the substrate 02 of the first grain 061 is formed as a cuboid or a cube, the first surface 021 of the substrate 02 is a rectangle or a square. The center of the first surface 021 can be the intersection of the two diagonals of the rectangle or the square. The axis of symmetry can be any line passing through the center of the first surface 021. For example, the line can be parallel to the length of the rectangle (in this case, along the length of the rectangle, a second groove C12, a first groove C11, and another second groove C12 are arranged in sequence), or parallel to the width of the rectangle (in this case, along the width of the rectangle, a second groove C12, a first groove C11, and another second groove C12 are arranged in sequence), or coincide with the diagonal of the rectangle (in this case, along the direction of the diagonal of the rectangle, a second groove C12, a first groove C11, and another second groove C12 are arranged in sequence).

[0156] When the substrate 02 of the first grain 061 is formed as a cylinder, the first surface 021 of the substrate 02 is circular, and the center of the first surface 021 can be the center of the circle. At this time, the axis of symmetry can be any line passing through the center of the first surface 021, such as the line coinciding with any diameter of the circle.

[0157] In this case, the first groove C11 located at the center of the first surface 021 can be the center of the bottom wall of the first groove C11 coinciding with the center of the first surface, or it can be any position where the straight line containing the center of the first surface 021 passes through the bottom wall of the first groove C11, etc.

[0158] When there are multiple grooves C1, and the number is odd, the first groove C1 is located at the center of the first surface 021 of the substrate 02, and the two second grooves C12 are positioned about the axis of symmetry. This can make the stress on each groove balanced, and avoid problems such as chip 50 cracking due to uneven stress in subsequent processes.

[0159] In another example, see Figure 12 and Figure 13 , Figure 12 This is a schematic diagram of the structure of another chip provided in an embodiment of this application. Figure 13 for Figure 12 The diagram shows the location of the grooves on the first surface of the first die in the chip. The number of grooves C1 is even. Figure 12 The explanation is based on the example of two grooves C1. The two second grooves C1 are symmetrically arranged about an axis of symmetry, which passes through the center of the first surface 021 of the substrate 02.

[0160] The explanation of the axis of symmetry passing through the center of the first surface 021 of the base 02 is the same as the example above (i.e. Figure 11The corresponding example is the same; please refer to the explanation of the example above for details, which will not be repeated here.

[0161] The even number of second grooves C12 are arranged about the axis of symmetry to ensure that the stress on each groove is balanced, thus avoiding problems such as chip 50 cracking due to uneven stress in subsequent processes.

[0162] In this case (where the number of grooves C1 is even), the conductive lines 064 corresponding to the second grains 062 within the two second grooves C1 are located on opposite sides of the first grain 061. This arrangement facilitates the placement of each conductive line 064.

[0163] Of course, the arrangement of conductive lines 064 located on opposite sides of the first grain 061 is not limited to different grains (e.g., Figure 12 The conductive line 064 corresponding to the two second grains in the diagram can also be the conductive line 064 corresponding to the same grain. For example, see [link to example]. Figure 14 , Figure 14 This is a schematic diagram of another chip structure provided in an embodiment of this application. When the circuit layer 03 of the first die 061 is located on the side of its substrate 02 away from the substrate 08, and the pads on the circuit layer 03 of the first die 061 are electrically connected to the pads on the first surface 081 of the substrate 08 through multiple conductive lines 064, the multiple conductive lines 064 can be located on opposite sides of the first die 061. Of course, the multiple conductive lines 064 can be located on one side of the first die 061.

[0164] The position of the groove C1 is set according to the three examples above to ensure that the stress on the groove C1 is balanced, so as to avoid problems such as chip 50 cracking due to uneven stress in subsequent processes.

[0165] To ensure the strength of the first grain 061, in some embodiments, please refer to [link to previous document]. Figure 9 When setting the groove C1, the total area of ​​the opening of the groove C1 on the first surface 021 is S1, and the area of ​​the first surface 021 is S2. (S1 / S2)×100% < 70%, for example, (S1 / S2)×100% can be 65%, 60%, 55%, 50%, 45%, or 40%, etc. This setting can avoid a significant impact on the strength of the first grain 061 due to the setting of the groove C1.

[0166] It should be noted that when the number of grooves C1 is one, the total area S1 of the openings of grooves C1 on the first surface 021 is the area of ​​the opening of one groove C1; when the number of grooves C1 is greater than one, the total area S1 of the openings of grooves C1 on the first surface 021 is the sum of the areas of the openings of multiple grooves C1. See also... Figure 13When there are two grooves C1, the area of ​​the opening of one groove C1 is S3. Then the total area S1 of the opening of the groove C1 on the first surface 021 is the sum of the areas S3 of the openings of the two grooves C1, that is, S3+S3.

[0167] For example, if the first grain 061 is cuboid in shape, and correspondingly, the first surface 021 of its substrate 02 is rectangular, then the area S2 of the first surface 021 is the length multiplied by the width of the first surface 021. If the first grain 061 is cylindrical, and correspondingly, the first surface 021 of its substrate 02 is circular, then the area S2 of the first surface 021 is the square of π multiplied by the radius of the first surface 021. When the opening of the groove C1 on the first surface 021 is rectangular, then the area of ​​the opening of the groove C1 on the first surface 021 is the length multiplied by the width of the opening. In this case, when there are multiple grooves C1, the total area of ​​the openings of the grooves C1 on the first surface 021 is the number of grooves multiplied by the area of ​​the opening of one groove C1 on the first surface 021.

[0168] In some embodiments, see Figure 15 , Figure 15 This is a schematic diagram of another chip structure provided in an embodiment of this application. The chip 50 provided in this embodiment of the application includes not only a first die 061 and a second die 062 located within the first die 061, but may also include a third die 068. The first die 061 and the third die 068 are respectively located in different regions of the substrate 08. For example, the substrate 08 includes a first region Q1 and a second region Q2, the first die 061 is located in the first region Q1, the third die 068 is located in the second region Q2, and the third die 068 is electrically connected to the substrate 08.

[0169] This configuration ensures that even if the size of the first die 061 is too small to accommodate multiple recesses C1, and similarly, even if multiple second dies 062 cannot be placed on the first die 061, the number of dies within the chip 50 can still be guaranteed, thus ensuring the corresponding functions of the chip 50. Furthermore, since the third die 068 is arranged side-by-side with the first die 061, the placement of the third die 068 guarantees the chip's functionality without increasing the height of the chip 50.

[0170] The connection method between the third die 068 and the substrate 08 is not limited in the embodiments of this application. For one possible implementation, please refer to [link to relevant documentation]. Figure 15The substrate 02 of the third die 068 is located on the side of its circuit layer 03 facing away from the substrate 08. A conductive post 063 is also provided between the circuit layer 03 of the third die 068 and the substrate 08. This conductive post 063 connects the circuit layer 03 of the third die 068 and the PCB 40, thus achieving electrical connection between the third die 068 and the substrate 08. This configuration improves the signal transmission rate between the third die 068 and the PCB 40.

[0171] In another possible implementation, see [link to relevant documentation]. Figure 16 , Figure 16 This is a schematic diagram of another chip structure provided in an embodiment of this application. The circuit layer 03 of the third die 068 is located on the side of its substrate 02 facing away from the substrate 08. A third protective layer 069 is provided between the substrate 02 of the third die 068 and the substrate 08. The third protective layer 069 may include a structure such as DAF that has both buffering and adhesive effects. Electrical connection between the third die 068 and the substrate 08 can be achieved through conductive lines 064.

[0172] The third protective layer 069 can not only stably fix the third die 069 on the substrate 08 and prevent the third die 068 from moving on the substrate 08, but also prevent stress from damaging the third die 068 or PCB 40 during the process of electrically connecting the circuit layer 03 of the third die 068 to the substrate 08.

[0173] The structure of chip 50 has been described above. Chip 50 is obtained by packaging the dies formed after dicing a wafer. The structure of the wafer provided in the embodiments of this application is described below.

[0174] See Figure 17 , Figure 17 This is a schematic diagram of a wafer structure provided in an embodiment of this application, and... Figure 1 and Figure 2 Unlike the wafer shown, the mother substrate 02' has multiple recesses C1 on the side opposite to the mother circuit layer 03', and each chip setting area 04 corresponds to at least one recess C1. Figure 17 The explanation is based on the example of two recesses C1 corresponding to each chip setting area 04. Each recess C1 contains a second die 062, and the circuit layer 03 of the second die 062 is located on the side of the substrate 02 of the second die 062 away from the bottom wall of the recess C1.

[0175] Since the second die 062 is located within the groove C1, after the wafer 01 is cut along the dicing track 05, multiple thinner first dies 061 can be formed, and the second dies 06 are disposed within each first die 061. In this way, packaging the first dies 061 can form a chip 50 with reduced thickness.

[0176] In some embodiments, please continue to see Figure 17 The wafer 01 also includes a plurality of conductive pillars 063, which are located on the side of the parent circuit layer 03' away from the parent substrate 02' and are electrically connected to the parent circuit layer 03'. Each chip setting area 04 corresponds to at least one conductive pillar 063. Thus, after the wafer 01 is cut along the dicing track 05, the resulting first die 061 may include at least one conductive pillar 063. Figure 17 The explanation is based on the example of the first grain 061, which includes five conductive pillars 063.

[0177] When conductive pillars 063 are provided on the side of the mother circuit layer 03' away from the mother substrate 02', conductive pillars 063 do not need to be provided in subsequent processes (processes for forming chip 50), thus avoiding the impact of high temperatures on other structures (such as molding layer 09) during the process of providing conductive pillars 063.

[0178] In some embodiments, please continue to see Figure 17 The wafer 01 also includes a first protective layer 065, located between the second die 062 and the bottom of the groove C1.

[0179] In some embodiments, please continue to see Figure 17 The wafer 01 also includes a second protective layer 067, which fills the groove C1 and covers the sidewall of the second grain 062.

[0180] This application also provides a method for manufacturing a chip, which can, for example, manufacture the chip described in this embodiment. The following refers to the chip 50 mentioned above and... Figure 16 The wafer 01 shown illustrates the chip fabrication method.

[0181] like Figure 18 As shown, the chip can be fabricated through the following steps:

[0182] S101 provides a mother substrate, a wafer, and a plurality of second dies.

[0183] like Figure 19a As shown, a mother substrate 08', a wafer 01, and a plurality of second dies 062 are provided, wherein, Figure 19a The explanation is based on eight second-order grains, 062.

[0184] Figure 19a In the middle, the mother substrate 08' includes multiple regions 084, among which, Figure 19aThe explanation is based on the example of a mother substrate 08' comprising six regions 084. It can be understood that after each region 084 of the mother substrate 08' is cut, the mother substrate 08' will be cut into multiple sub-substrates, which are the substrates 08 of the chip 50 mentioned above.

[0185] Wafer 01 includes multiple conductive pillars 063, and the multiple conductive pillars 063 are located on the side of the parent circuit layer 03' away from the parent substrate 02'. Each chip setting area 04 corresponds to multiple conductive pillars 063, wherein... Figure 19a The explanation is based on the example of five conductive pillars 063 corresponding to each chip setting area 04.

[0186] The second die 062 can be formed by dicing its corresponding wafer. The second die 062 provided in this embodiment may have a first protective layer 065, which is located on the side of the substrate 02 of the second die 062 facing away from the circuit layer 03. Alternatively, the second die 062 may not have a first protective layer 065, but it can be provided in a subsequent process, such as in the following steps where the first protective layer 065 is provided before the second die 062 is placed in the groove C1.

[0187] S102. A first protective film is provided on the side of the mother circuit layer of the wafer that is away from the mother substrate.

[0188] like Figure 19b As shown, a first protective film 071 is provided on the side of the mother circuit layer 03' of wafer 01 that faces away from the mother substrate 02'. The first protective film 071 can protect the mother circuit layer 03' and / or the conductive pillar 063, and prevent subsequent processes (such as subsequent groove formation processes and processes of placing the second die in the groove, etc.) from damaging the mother circuit layer 03' and / or the conductive pillar 063.

[0189] The first protective film 07 can include films that require UV light irradiation to lose their adhesiveness, such as ultraviolet (UV) curable films, or non-UV films that do not require UV light irradiation, have low adhesiveness, and are easy to peel off. The first protective film 071 can be selected based on the performance of the crystal grains. For example, if the second crystal grain 062 is a storage crystal grain, which is easily affected by ultraviolet light, then a UV-curable film cannot be selected as the first protective film 071.

[0190] It should be noted that the embodiments in this application are illustrated using the first protective film 071 as an example of a UV-curable film.

[0191] S103. Multiple grooves are formed on the side of the mother substrate away from the mother circuit layer.

[0192] like Figure 19cAs shown, multiple grooves C1 can be formed on the side of the mother substrate 02' away from the mother circuit layer 03' by means of etching or mechanical polishing. Each chip setting area 04 corresponds to at least one groove C1. Figure 19c The explanation is based on the example of two recesses C1 corresponding to each chip setting area 04.

[0193] S104. Multiple second grains are respectively placed in multiple grooves.

[0194] like Figure 19d As shown, multiple second grains 062 are respectively disposed in multiple grooves C1. One second grain 062 can be disposed in one groove C1, or multiple (such as two or three) second grains 062 can be disposed in one groove C1. Figure 19d The explanation is based on the example of a second die 062 being disposed within a groove C1. The circuit layer 03 of the second die 062 is located on the side of its substrate 02 facing away from the bottom wall of the groove C1, and the first protective layer 065 is located between the second die 062 and the bottom wall of the groove C1.

[0195] S105. The second protective layer is filled into the groove and surrounds the second grain.

[0196] like Figure 19e As shown, the second protective layer 067 fills the groove C1 and surrounds the second die 062. It is understood that when the second protective layer 067 surrounds the second die 062, it is necessary to expose the surface of the circuit layer 03 of the second die 062 facing away from its substrate 02, or only expose the pads on the circuit layer 03; this embodiment does not limit this. The provision of the second protective layer 067 can surround the second die 062, providing physical protection to the surrounding area and preventing interference from other structures, thereby ensuring the stable performance of the second die 062.

[0197] The second protective layer 067 can be provided separately or integrally formed with the encapsulation layer in subsequent processes. If the second protective layer 067 is integrally formed with the encapsulation layer in subsequent processes, this step can be omitted.

[0198] S106. Peel off the first protective film.

[0199] like Figure 19fAs shown, the first protective film 071 is peeled off. When the first protective film 071 is a UV-cured film, it can be irradiated with ultraviolet light to cause it to lose its adhesiveness before peeling it off. This reduces damage to the circuit layer 03' and / or the conductive pillars 063 during peeling. When the first protective film 071 is a non-UV film, it can be peeled off gently.

[0200] S107. A second protective film is provided on the side of the mother substrate away from the mother circuit layer.

[0201] like Figure 19g As shown, a second protective film 072 is provided on the side of the mother substrate 02' of wafer 01 that faces away from the mother circuit layer 03'. The second protective film 072 protects the circuit layer 03 of the second die 062 already set in the groove C1 and the surface of the mother substrate 02' of wafer 01, avoiding damage and wear to the circuit layer 03 of the second die 062 and the surface of the mother substrate 02' of wafer 01 in subsequent processes (such as the process of dicing wafer 01).

[0202] In this application embodiment, the type of the second protective film 072 is not limited, as long as it can protect the circuit layer 03 of the second die 062 and the surface of the mother substrate 02' of the wafer 01. The second protective film 072 can be a single-layer film or a multilayer film, and this application embodiment does not limit this. When the second protective film 072 is a multilayer film, it may include a backside grinding (BG) film and a polymer material film, wherein the BG film is located between the surface of the mother substrate 02' of the wafer 01 and the polymer material film.

[0203] S108. The wafer is cut along the cutting path to form a plurality of first grains.

[0204] like Figure 19h As shown, the wafer 01 is cut along the dicing path 05 to form multiple first dies 061. The number of first dies 061 is the same as the number of chip setting areas 04. At this time, each first die 061 contains a second die 062, and it is provided with conductive pillars 063.

[0205] S109. Peel off the second protective film.

[0206] like Figure 19i As shown, the second protective film 072 is peeled off to expose at least the pads on the circuit board 03 of the second die 062.

[0207] S110. A plurality of first dies are disposed on a mother substrate, and the circuit layers of the first dies and the circuit layers of the second dies are electrically connected to the mother substrate.

[0208] like Figure 19j As shown, a plurality of first dies 061 are disposed on the mother substrate 08'. The number of first dies 061 can be the same as the number of regions 084 included in the mother substrate 08'. For example, when the mother substrate 08' includes six regions 084, six first dies 061 can be disposed on the mother substrate 08', and one first die 061 is provided in one region 084.

[0209] When the first die 061 is placed on the mother substrate 08', the circuit layer 03 of the first die 061 is electrically connected to the mother substrate 08' by conductive pillars 063, such as copper-tin or gold bumps, through a flip chip (FC) assembly process. The circuit layer 062 of the second die 062 is electrically connected to the mother substrate 08' by conductive wires (which can also be called bonding wires) 064 through a wire bonding (WB) process.

[0210] S111, Form a molding layer on the mother substrate.

[0211] like Figure 19k As shown, a molding compound 09 is formed on the mother substrate 08' through a packaging process. The molding compound 09 covers the first die 061, the conductive pillar 063 and the conductive line 064.

[0212] S112, Cut the mother substrate to form a chip.

[0213] like Figure 19l As shown, the mother substrate 08' is cut, and then solder balls 083 are implanted on the side of the cut sub-substrate away from the first die 061 to form a chip. The number of chips can be the same as the number of regions 084 included in the mother substrate 08'.

[0214] It should be noted that solder balls 083 can be implanted after cutting the mother substrate 08', or multiple solder balls 083 can be implanted before cutting the mother substrate 08'. Accordingly, each region 084 requires a corresponding solder ball 083.

[0215] It should be noted that the above example only illustrates the process flow of one chip fabrication method, and does not constitute a limitation of this application. The process flow of the chip fabrication method can be modified accordingly based on actual circumstances. Actual circumstances may include the size of the first die 061 and the second die 062, and / or the interconnection form (conductive pillars or conductive lines), etc.

[0216] For example, Figure 15The chip 50 shown has a small first die 061, which can only have one recess C1. Correspondingly, only one second die 062 is located in the recess C1. To ensure that the chip 50 has multiple functions, a third die 068 is also required. Therefore, in the manufacturing process of the chip 50, after the first die is placed on the mother substrate, the third die 068 also needs to be placed on the mother substrate before the packaging process is carried out.

[0217] For example, Figure 7 The chip 50 shown has a first die 061 electrically connected to the substrate 08 via a conductive line 064, and a second die 062 electrically connected to the substrate 08 via a conductive post 063. Therefore, during the fabrication of the chip 50, the wafer provided may not include the conductive posts. The conductive posts 063 are then provided when the first die 061 is placed on the mother substrate 08', so that the second die 062 is connected to the mother substrate 08' via the conductive posts 063. For example... Figure 15 The chip 50 shown in the figure requires a third die 068 to be placed on the mother substrate after the first die is placed on the mother substrate during the manufacturing process, and then the packaging process is carried out.

[0218] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A chip, characterized in that, include: substrate; The device comprises at least two dies, each die including a substrate and a circuit layer on the substrate; the at least two dies include at least one first die and at least one second die, the first die having at least one groove formed on its substrate, the second die being located within the groove, and the circuit layer of the second die being located on the side of the second die's substrate facing away from the bottom wall of the groove; the circuit layer of the first die is electrically connected to the substrate via a first connector, and the circuit layer of the second die is electrically connected to the substrate via a second connector.

2. The chip according to claim 1, characterized in that, The chip also includes a first protective layer located between the second die and the bottom wall of the groove.

3. The chip according to claim 2, characterized in that, The first protective layer includes a wafer bonding film.

4. The chip according to any one of claims 1-3, characterized in that, The chip also includes a second protective layer that fills the groove and covers the sidewalls of the second die.

5. The chip according to claim 4, characterized in that, The chip also includes a molding compound layer, which is encapsulated on the substrate and covers the first die, the first connector, and the second connector.

6. The chip according to claim 5, characterized in that, The second protective layer and the encapsulation layer are integrally formed.

7. The chip according to any one of claims 1-6, characterized in that, The substrate of the first grain includes opposing first and second surfaces, and also includes a side surface connecting the first surface and the second surface; The first surface is located on the side of the second surface opposite to the circuit layer of the first die, and the opening of the groove is located on the first surface.

8. The chip according to claim 7, characterized in that, The distance between the groove and the side surface is greater than 200 μm.

9. The chip according to claim 7 or 8, characterized in that, The surface flatness of the first surface is less than or equal to 50 μm.

10. The chip according to any one of claims 7-9, characterized in that, The total area of ​​the opening of the groove is S1, the area of ​​the first surface is S2, and (S1 / S2)×100% < 70%.

11. The chip according to any one of claims 7-10, characterized in that, The number of grooves is odd, and when the number of grooves is one, one groove is located at the center of the first surface; when the number of grooves is greater than or equal to three, the groove includes one first groove and at least two second grooves, the first groove is located at the center of the first surface, and the at least two second grooves are symmetrically arranged about an axis of symmetry, wherein the axis of symmetry passes through the center of the first surface.

12. The chip according to any one of claims 7-10, characterized in that, The number of grooves is even, and the even number of grooves are symmetrically arranged about an axis of symmetry that passes through the center of the first surface.

13. The chip according to any one of claims 1-12, characterized in that, The circuit layer includes a first functional module, the overlapping area of ​​the projection of the first functional module on the reference plane and the projection of the groove on the reference plane is less than or equal to S3, S3 = 50% × S4, where S4 is the area of ​​the region where the first functional module is located, and the reference plane is parallel to the substrate.

14. The chip according to claim 13, characterized in that, The projection of the first functional module onto the reference plane does not overlap with the projection of the groove onto the reference plane.

15. The chip according to claim 13 or 14, characterized in that, The first functional module includes a heating module and / or a radio frequency module.

16. The chip according to any one of claims 1-15, characterized in that, The substrate of the first die is located on the side of the circuit layer of the first die away from the substrate; The first connector includes a conductive post, and the second connector includes a conductive wire.

17. The chip according to any one of claims 1-15, characterized in that, The circuit layer of the first die is located on the side of the first die's substrate facing away from the substrate; The first connector includes a conductive wire, and the second connector includes a conductive post.

18. The chip according to any one of claims 1-17, characterized in that, At least two grains also include at least one third grain; The substrate includes a first region and a second region, with the first grain located in the first region; the third grain is located in the second region and is electrically connected to the substrate via a third connector.

19. The chip according to claim 18, characterized in that, The substrate of the third grain is located on the side of the circuit layer of the third grain that is away from the substrate; The third connector includes a conductive post.

20. The chip according to claim 18, characterized in that, The circuit layer of the third die is located on the side of the substrate of the third die that is away from the substrate; The third connector includes a conductive wire.

21. The chip according to claim 20, characterized in that, The chip also includes a third protective layer located between the third die and the substrate.

22. The chip according to any one of claims 1-21, characterized in that, The chip also includes solder balls, with the first die and the solder balls located on opposite sides of the substrate and electrically connected to the substrate.

23. An electronic device, characterized in that, Includes the chip described in any one of claims 1-22.

24. A wafer, characterized in that, include: Mother base; A mother circuit layer is located on one side of the mother substrate. The mother circuit layer includes a plurality of spaced chip mounting areas, and a dicing channel is formed between two adjacent chip mounting areas. The mother substrate has multiple grooves on the side away from the mother circuit layer, and each chip setting area corresponds to at least one groove; a second die is provided in the groove, and the circuit layer of the second die is located on the side of the second die's substrate away from the bottom wall of the groove.

25. The wafer according to claim 24, characterized in that, The wafer also includes a plurality of conductive pillars located on the side of the mother circuit layer away from the mother substrate and electrically connected to the conductive pillars, with each chip setting area corresponding to at least one of the conductive pillars.

26. The wafer according to claim 24 or 25, characterized in that, The wafer also includes a first protective layer located between the second grain and the bottom of the groove.

27. The wafer according to claim 26, characterized in that, The first protective layer includes a wafer bonding film.

28. The wafer according to any one of claims 24-27, characterized in that, The wafer also includes a second protective layer that fills the groove and covers the sidewalls of the second grain.

29. A method for fabricating a chip, characterized in that, include: A mother substrate, a wafer, and a plurality of second dies are provided; wherein, the wafer includes a mother substrate and a mother circuit layer located on one side of the mother substrate, the mother circuit layer includes a plurality of spaced chip placement areas, and a dicing channel is formed between two adjacent chip placement areas; Multiple grooves are formed on the side of the mother substrate opposite to the mother circuit layer; wherein each chip setting area corresponds to at least one of the grooves; Multiple second dies are respectively disposed in multiple grooves; wherein, the circuit layer of the second die is located on the side of the substrate of the second die away from the bottom wall of the groove; The wafer is cut along the dicing path to form a plurality of first grains; At least a portion of the first die is disposed on the mother substrate, and the circuit layer of the first die is electrically connected to the mother substrate through a first connector, and the circuit layer of the second die is electrically connected to the mother substrate through a second connector. The mother substrate is cut to form chips; wherein the number of chips formed is the same as the number of the first dies.

30. The preparation method according to claim 29, characterized in that, Before cutting the mother substrate to form the chip, the process further includes: A molding compound is formed on the mother substrate; wherein the molding compound covers the first die, the first connector, and the second connector.

31. The preparation method according to claim 29 or 30, characterized in that, After disposing of the plurality of second grains in the plurality of grooves, the method further includes: The second protective layer is filled into the groove and covers the sidewalls of the second grain.

32. The preparation method according to any one of claims 29-31, characterized in that, The wafer also includes a plurality of conductive pillars located on the side of the mother circuit layer away from the mother substrate, and the conductive pillars are electrically connected to the mother circuit layer, and each chip setting area corresponds to at least one of the conductive pillars.

33. The preparation method according to claim 29 or 32, characterized in that, Before forming multiple grooves on the side of the mother substrate opposite to the mother circuit layer, the method further includes: A first protective film is provided on the side of the mother circuit layer that is away from the mother substrate; After disposing of the plurality of second grains in the plurality of grooves, the method further includes: Peel off the first protective film.

34. The preparation method according to claim 33, characterized in that, The first protective film includes an ultraviolet-curable film; Peeling off the first protective film includes: The first protective film is peeled off by irradiating it with ultraviolet light.

35. The preparation method according to any one of claims 29-34, characterized in that, The wafer is diced along the dicing path to form a plurality of first grains, including: A second protective film is provided on the side of the mother substrate opposite to the mother circuit layer; The wafer is cut along the dicing path to form a plurality of first grains; Peel off the second protective film.

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