Double-trigger voltage droop detection

Abstract

The present technology relates to sag detection, and discloses a circuit for detecting a voltage sag event, the circuit configured to: receive a clock signal from a clock distribution network; monitor a measurement associated with a voltage provided to the circuit by a power delivery network; in response to the measurement reaching a first threshold, provide a first sag detection signal to the clock distribution network; cause a control entity to take a first mitigation action in response to the first sag detection signal; in response to the measurement reaching a second threshold different from the first threshold, provide a second sag detection signal to the clock distribution network; and cause the control entity to take a second mitigation action in response to the second sag detection signal.

Description

[0001] This technology relates to droop detection. Specifically, this technology relates to the detection of voltage droop events and the triggering of voltage droop mitigation actions in information processing systems.

[0002] Some computer circuits (such as the central processing unit (CPU) or graphics processing unit (GPU)) may experience performance issues. For example, a CPU may experience voltage droop due to the large variations in the current required by the power delivery network (PDN).

[0003] There is a need for mitigation measures to address these performance issues.

[0004] This technology relates to solving or mitigating such performance problems or improving known mitigation techniques.

[0005] According to a first aspect, a circuit for detecting voltage droop events is provided, the circuit being configured to: receive a clock signal from a clock distribution network; monitor a measurement associated with a voltage supplied to the circuit by a power delivery network; provide a first droop detection signal to the clock distribution network in response to the measurement reaching a first threshold; cause a control entity to take a first mitigation action in response to the first droop detection signal; provide a second droop detection signal to the clock distribution network in response to the measurement reaching a second threshold different from the first threshold; and cause the control entity to take a second mitigation action in response to the second droop detection signal.

[0006] In addition, a third threshold may be available for resetting both the first and second detection signals.

[0007] The circuit may include a clock distribution network, a power delivery network, and / or a control entity.

[0008] The first mitigation action may include modifying the frequency of the clock signal by the clock distribution network. The first mitigation action may include reducing the frequency of the clock signal by the clock distribution network. In this way, the time component can be increased. Alternatively or additionally, the first mitigation action may include increasing the frequency of the clock signal by the clock distribution network. The increase in frequency may occur before or after the decrease in frequency.

[0009] The second mitigation action may include pausing the clock. Pausing the clock allows performance to be maintained. The second mitigation action may include pausing the clock for a predetermined number of clock cycles before restarting the clock. The predetermined number of cycles may be user-configurable and / or resettable. The clock may also be restarted by a voltage rise above a third threshold. If the measurement still meets the second threshold after the clock restarts, the second mitigation action may be repeated.

[0010] The second threshold can be lower than the first threshold. In this way, the first mitigation action can be performed before the second mitigation action. In response to the measured value dropping below the first threshold, a first droop detection signal can be provided to the clock distribution network. Therefore, the first mitigation action can be triggered after the initiation of voltage droop. In response to the measured value dropping below the second threshold, a second droop detection signal can be provided to the clock distribution network. Therefore, the second mitigation action can be triggered after voltage droop continues.

[0011] Alternatively, the first threshold may be lower than the second threshold. In this alternative arrangement, a first droop detection signal can be provided to the clock distribution network in response to a measured value exceeding the first threshold. Furthermore, in this alternative arrangement, a second droop detection signal can be provided to the clock distribution network in response to a measured value exceeding the second threshold. Therefore, using this alternative arrangement, a first mitigation action and a second mitigation action can be triggered as the measured value and voltage increase.

[0012] The third threshold can be higher than the first and second thresholds. In this way, the first and second droop detection signals will have built-in hysteresis.

[0013] Alternatively, this value can be lower than the first threshold and the second threshold. In this way, the first droop detection signal and the second droop detection signal will have built-in hysteresis.

[0014] The measured value may include a fraction. This fraction may correspond to a count of the number of gate stages that pass through the delay line during a predetermined number of clock cycles. The fraction may represent the voltage at a given process batch point and a given temperature.

[0015] The predetermined number of clock cycles can be one clock cycle. Alternatively, the predetermined number of clock cycles can be more than one clock cycle, such as two, three, four, five, ten, or any other number of clock cycles. A lower number of clock cycles (such as one clock cycle) may mean that the first and second mitigation actions can be triggered quickly enough during a voltage droop event to have an effect on the voltage droop event, such as preventing the voltage droop from dropping to a critical level.

[0016] Measurements can be categorized into at least three zones, preferably four. For example, categories may include a safe zone, a droop pre-detection zone, a droop detection zone, and a sign-off violation zone. The safe zone may include all values ​​above a third threshold, where no impending voltage droop is expected. The droop pre-detection zone may include all values ​​between a first and a third threshold, where an impending voltage droop is likely. The droop detection zone may include all values ​​between a first and a second threshold. The sign-off violation zone may include all values ​​below the second threshold. When a measurement is recorded in the safe zone, the next voltage droop event can be counted as a new voltage droop event. When a measurement moves from the droop detection zone into the safe zone, or when a measurement moves from the sign-off violation zone into the droop detection zone or the droop pre-detection zone, a subsequent decrease in the measurement value may be considered a continuation of the current voltage droop event, rather than a subsequent voltage droop event.

[0017] The circuit can also be configured to perform one or more slope checks. The circuit may include appropriate storage devices to allow slope calculation. In response to a measured value reaching a first threshold and in response to a calculated slope value being higher or lower than a predetermined slope value, a first droop detection signal may be provided to the clock distribution network.

[0018] The first droop detection signal can be provided as a single bit to notify of a critical droop event. In the event of a critical droop event, remedial actions may be required to ensure reliable system functionality. The second droop detection signal can be provided as a single bit to notify of a violation of the sign-off threshold. A sign-off threshold violation is considered a sign-off event that is a droop for which the applied backoff clock frequency is insufficient to ensure proper circuit function. This can be caused by a rare deep droop event, a power failure, or a programmed response when the circuit's nominal operating point is already at the voltage lower limit, where the droop involves the risk of hold-off timing failures rather than set-off timing failures that can be resolved by frequency reduction. The response to a sign-off event is a hold-off clock and relies on the retention of static data within the circuit until the event has passed. A sign-off threshold violation may mean that immediate safety actions, such as de-energizing the associated load, may be required.

[0019] The first droop detection signal and / or the second droop detection signal can be synchronized with the rising edge of the clock function.

[0020] The second droop detection signal can trigger the generation or operation of warnings, alarms, and / or notifications. The second droop detection signal can indicate a safety problem and that the associated system must be stopped. For example, if the system includes a vehicle, the second droop detection signal can indicate that the voltage has reached an unsafe level and that immediate action (such as stopping the vehicle) may be required to ensure, for example, the necessary automotive-grade safety.

[0021] The circuit allows for the performance of test functions. For example, a forced voltage droop can be applied to the circuit, and the circuit's functionality, characteristics, and / or output can be monitored and evaluated to ensure that it meets expected functionality, characteristics, and / or output.

[0022] According to a second aspect, a method is provided, the method comprising: providing a clock signal from a clock distribution network to a circuit; monitoring a measurement associated with a voltage supplied to the circuit by a power delivery network; providing a first droop detection signal to the clock distribution network in response to the measurement reaching a first threshold; taking a first mitigation action in response to receiving the first droop detection signal; providing a second droop detection signal to the clock distribution network in response to the measurement reaching a second threshold different from the first threshold; and taking a second mitigation action in response to receiving the second droop detection signal. The first mitigation action may include modifying the frequency of the clock signal by the clock distribution network. The first mitigation action may include decreasing the frequency of the clock signal by the clock distribution network, or the first mitigation action may include increasing the frequency of the clock signal by the clock distribution network.

[0023] The second mitigation action may include pausing the clock, wherein the second mitigation action may include pausing the clock for a predetermined number of clock cycles before restarting the clock.

[0024] The second threshold may be lower than the first threshold, or alternatively, the second threshold may be higher than the first threshold.

[0025] In response to a measured value falling below a first threshold, a first droop detection signal can be provided to the clock distribution network. In response to a measured value falling below a second threshold, a second droop detection signal can be provided to the clock distribution network.

[0026] The first droop detection signal can be a first-order droop event, and the first threshold can be a droop threshold. The second droop detection signal can be a second-order or higher-order droop event, and the second threshold can be a signature threshold.

[0027] In the implementation, the first threshold may be lower than the second threshold. In response to a measured value exceeding the first threshold, a first droop detection signal may be provided to the clock distribution network; and in response to a measured value exceeding the second threshold, a second droop detection signal may be provided to the clock distribution network.

[0028] The measurement may include a fraction, which may correspond to a count of the number of gate stages that pass through the delay line during a predetermined number of clock cycles, wherein the predetermined number of clock cycles may be one clock cycle.

[0029] The method may include functional steps of any of the components discussed in the first aspect.

[0030] According to a third aspect, an apparatus is provided, comprising: a circuit; a power delivery network configured to supply current to the circuit; and a clock distribution network configured to supply a clock signal to the circuit; wherein the circuit is configured to: receive the clock signal from the clock distribution network; monitor a measurement associated with a voltage supplied to the circuit by the power delivery network; provide a first droop detection signal to the clock distribution network in response to the measurement value reaching a first threshold; and provide a second droop detection signal to the clock distribution network in response to the measurement value reaching a second threshold different from the first threshold; wherein the apparatus is configured to: take a first mitigation action in response to receiving the first droop detection signal; and take a second mitigation action in response to receiving the second droop detection signal.

[0031] The circuit can be the circuit described in the first aspect. In this respect, the third aspect may include any or every optional feature discussed with respect to the first aspect. Attached Figure Description

[0032] The implementation of this technology will now be described by way of example only, with reference to the accompanying drawings, in which:

[0033] Figure 1 A method diagram illustrating the steps of a method for droop detection is shown illustratively.

[0034] Figure 2 A top-level diagram of an example droop detector is shown illustratively;

[0035] Figure 3 An illustrative graph is shown depicting the four regions into which the fraction can be characterized;

[0036] Figure 4 The graphs illustrating the fractions over time for two example cases are shown illustratively.

[0037] Figure 5 An illustrative diagram of the trigger management process is shown, describing the actions taken during each clock cycle to manage triggers.

[0038] Figure 6 The graphs illustrating the relationship between resonance and frequency for two example cases are shown illustratively.

[0039] Figure 7 A graph illustrating the voltage versus time in an example case is shown illustratively.

[0040] Figure 8 An example of a delay monitor with a delay line is shown illustratively.

[0041] Figure 9 Examples of systems and products containing chips are given; and

[0042] Figure 10 Examples of sagging events and corresponding relief actions are given. Detailed Implementation

[0043] Figure 1 A method diagram illustrating the steps of method 100 for droop detection is shown illustratively. Specifically, method 100 is a dual-triggered droop detection method. The first step is to provide a clock signal 110 to the circuit from a clock distribution network. In this embodiment, the clock distribution network interfaces with various circuits to provide one or more clock signals to the various circuits, for example (e.g., where the clock distribution network includes a clock tree or edge tree). Furthermore, the clock distribution network is operable to receive one or more signals from the various circuits and to perform one or more actions in response to one or more signals, as will be apparent from the description herein. The next step is to monitor 120 a measurement associated with the voltage supplied to the circuit by the power delivery network.

[0044] The next step is to provide a first droop detection signal 130 to the clock distribution network in response to the measured value reaching a first threshold. This step can be considered as the first trigger of the dual-trigger method. After the step of providing the first droop detection signal 130, method 100 includes taking a first mitigation action 140 in response to receiving the first droop detection signal.

[0045] Method 100 further includes providing a second droop detection signal 150 to the clock distribution network in response to the measured value reaching a second threshold different from the first threshold. This step can be considered as the second trigger of a dual-trigger method. After the step of providing the second droop detection signal 150, method 100 includes taking a second mitigation action 160 in response to receiving the second droop detection signal.

[0046] Figure 2 A top-level diagram of an example droop detector 200 is shown illustratively. The droop detector 200 has two main parts: soft IP 210 and hard IP 220. Soft IP 210 is a combination of a monitor local interface 230 and sensor logic 240. Hard IP 220 includes a sensor core 250. The interface between soft IP 210 and hard IP 220 depends on the specific implementation of hard IP 220.

[0047] like Figure 2 As shown, TRIG_DROOP and TRIG_SOFF are the direct outputs of the droop detector. TRIG_DROOP is the trigger that provides the first droop detection signal to the clock distribution network, as shown in the reference. Figure 1The discussed TRIG_SOFF is the trigger that provides the second droop detection signal to the clock distribution network at 150, as referenced. Figure 1 The subject of discussion. References. Figure 4 The timing for triggering TRIG_DROOP and TRIF_SOFF is discussed. Both TRIG_DROOP and TRIF_SOFF are synchronized with the rising edge of the input FUNC_CLK, which is referenced... Figure 1 The clock cycle received from the clock distribution network in the first step of the described method 100.

[0048] Figure 3 A graph 300 is illustrated illustratively, depicting a fraction that can be characterized to four regions, where the x-axis indicates time and the y-axis indicates the fraction. This fraction corresponds to a count of the number of gate stages (e.g., fine gate stages) that pass through the delay line during a clock cycle. The fraction represents the voltage at a given process batch point and a given temperature. The four regions are a safe region 310, a droop pre-detection region 320, a droop detection region 330, and a sign-off violation region 340.

[0049] The safe zone 310 and the drooping pre-detection zone 320 are separated by an AVAL_PRE_DROOP threshold 315, which is an example of a third threshold described with reference to aspects of this technology. Therefore, the safe zone 310 includes all curve points whose scores are greater than or equal to the value of the AVAL_PRE_DROOP threshold 315.

[0050] The droop pre-detection region 320 and the droop detection region 330 are separated by an AVAL_DROOP threshold 325, which is an example of a first threshold described with reference to aspects of this technology. Therefore, the droop pre-detection region 320 includes all curve points whose fractions are less than the AVAL_PRE_DROOP threshold 315 but greater than or equal to the AVAL_DROOP threshold 325.

[0051] The droop detection area 330 and the approval violation area 340 are separated by an AVAL_SIGNOFF threshold 335, which is an example of a second threshold described with reference to aspects of this technology. Therefore, the droop detection area 330 includes all curve points whose scores are less than the AVAL_DROOP threshold 325 but greater than or equal to the AVAL_SIGNOFF threshold 335.

[0052] Therefore, it can be concluded that the sign-off violation zone 340 includes all curve points with scores less than the AVAL_SIGNOFF threshold of 335.

[0053] Figure 4A graph 400 is shown illustratively, depicting the fractions over time for two example cases (case 410 (case A) and case 420 (case B)). The time axis is quantized in FUNC_CLK periods, such that each vertical grid line corresponds to a single FUNC_CLK period. It can be seen that the fraction for each case 410, 420 is measured during each FUNC_CLK period. The circuit includes the necessary storage devices or memory to store the necessary number of fractions over time to indicate voltage droop. Figure 4 The signal waveforms of TRIG_DROOP and TRIG_SOFF corresponding to the first case (case A) and the second case (case B) are also depicted.

[0054] The first case 410 includes a score decrease as the score moves from the secure zone 310 beyond the AVAL_PRE_DROOP threshold 315 into the droop pre-detection zone 320. The first case 410 then includes a score decrease as the score moves from the droop pre-detection zone 320 beyond the AVAL_DROOP threshold 325 into the droop detection zone 330. The score exceeding the AVAL_DROOP threshold 325 triggers the transmission of the first droop detection signal discussed herein. The first case 410 then includes a score decrease as the score moves from the droop detection zone 330 beyond the AVAL_SIGNOFF threshold 335 into the signature violation zone 340. The score exceeding the AVAL_SIGNOFF threshold 335 triggers the transmission of the second droop detection signal discussed herein. The score increases and then decreases again. In the first case 410, the transmission of the score from the secure zone 310 into the signature violation zone 340 occurs twice, resulting in the first and second droop detection signals being provided twice.

[0055] The second case 410 includes a score decrease as the score moves from the safe zone 310 beyond the AVAL_PRE_DROOP threshold 315 into the droop pre-detection zone 320. The second case 420 then includes a score decrease as the score moves from the droop pre-detection zone 320 beyond the AVAL_DROOP threshold 325 into the droop detection zone 330. A score exceeding the AVAL_DROOP threshold 325 triggers the transmission of the first droop detection signal discussed herein. The second case 420 then includes a score increase entering the droop pre-detection zone 320 such that the score no longer meets the AVAL_SIGNOFF threshold 335 or enters the sign-off violation zone 340. Therefore, the second droop detection signal discussed herein is not transmitted. The score is not shown as reaching the safe zone 310 and then decreases again.

[0056] A fractional drop into the droop detection region 330 can be considered a first-order droop event, which is the highest resonant frequency of the power delivery network (PDN). This circuit provides protection against first-order droop events by acting in response to the first droop detection signal (e.g., by reducing the frequency of the clock signal through the clock distribution network). This functionality is not limited to protection against first-order droop events. In other examples, this functionality can provide protection against higher-order droop events (e.g., second-order droop events, third-order droop events, etc.). As an illustrative example, there are chip designs with high-density capacitors (e.g., MIM capacitors) that provide protection against shallow first-order droop events; therefore, for such designs, the mitigated droop event may not be a first-order droop event.

[0057] A score drop entering the sign-off violation zone 340 can be considered a higher-order droop event, such as a second- or third-order droop event. This circuit provides protection against higher-order droop events by taking action in response to a second droop detection signal (e.g., by pausing the clock).

[0058] Furthermore, other thresholds may exist that could lead to the generation of further mitigation signals. For example, a third threshold may be higher than the first and second thresholds. In this way, the first and second droop detection signals will have built-in hysteresis.

[0059] Alternatively, a third (or additional fourth) threshold may be lower than the first and second thresholds. In this way, the first and second droop detection signals will have built-in hysteresis.

[0060] In an exemplary example, both the first droop detection signal and the second droop detection signal are reset in response to the satisfaction of a third (or fourth) threshold.

[0061] exist Figure 4 As can be seen, both Case 410 and Case 420 involve a score decrease starting from the safe zone 310, exceeding the AVAL_PRE_DROOP threshold 315 and entering the droop pre-detection zone 320, then exceeding the AVAL_DROOP threshold 325 and entering the droop detection zone 330. Both Case 410 and Case 420 involve a score decrease, followed by a score increase, and then a further score decrease.

[0062] In the first case 410, the score increases sufficiently to bring it back above the AVAL_PRE_DROOP threshold 315 and into the safe zone 310. Once the score re-enters the safe zone 310, the voltage droop is considered complete. Subsequent score drops into the droop detection zone 330 are considered a second voltage droop event.

[0063] However, in the second case 420, the increase in the score is insufficient to bring the score back above the AVAL_PRE_DROOP threshold 315 and into the safe zone 310. Therefore, the subsequent drop in the score into the droop detection zone 330 is considered a continuation of the first voltage droop event.

[0064] In the first case 410, the droop event counter is incremented to indicate two droop events. However, in the second case 420, the droop event counter is incremented to indicate only one droop event.

[0065] and Figure 4 Generally, AVAL_PRE_DROOP 315 is described as being higher than both the AVAL_DROOP threshold 325 and the AVAL_SIGNOFF threshold 335. This functionality may occur when, for example, voltage and measured values ​​have a positive correlation. In an alternative embodiment, AVAL_PRE_DROOP 315 may be lower than the AVAL_DROOP threshold 325, which in turn may be lower than the AVAL_SIGNOFF threshold 335, for example when voltage and measured values ​​have a negative correlation (e.g., stage delay).

[0066] Figure 5 An illustrative trigger management flowchart is shown, describing the actions taken to manage triggering during each clock cycle. The process begins by calculating the score for the corresponding clock cycle and determining whether the score falls within the safe zone, droop pre-detection zone, droop detection zone, or sign-off violation zone. The circuitry includes four registers: the TRIG_DROOP register, the TRIG_SOFF register, the int_SKIP_CHECKS_TILL_NEXT_PRE_DROOP register, and the int_CLOCKS_TO_DROOP register.

[0067] If the score is in the safe zone, then each of the four registers is reset and the process ends.

[0068] If the score is within the drooping pre-detection region, the state of the int_CLOCKS_TO_DROOP register is queried. If the int_CLOCKS_TO_DROOP register does not meet the 0'xF condition, the int_CLOCKS_TO_DROOP register is incremented by 1'b1, and the process ends. If the int_CLOCKS_TO_DROOP register does meet the 0xF condition, the int_SKIP_CHECKS_TILL_NEXT_PRE_DROOP register is set to 1'b1, and the process ends.

[0069] If the score is within the droop detection zone, the int_SKIP_CHECKS_TILL_NEXT_PRE_DROOP register is queried. If the int_SKIP_CHECKS_TILL_NEXT_PRE_DROOP register is set to 1'b1, the process ends. If the int_SKIP_CHECKS_TILL_NEXT_PRE_DROOP register is not set to 1'b1, the level of int_CLOCKS_TO_DROOP is compared with the level of AVAL_CLOCKS_TO_DROOP. If int_CLOCKS_TO_DROOP is not less than or equal to AVAL_CLOCKS_TO_DROOP, the int_SKIP_CHECKS_TILL_NEXT_PRE_DROOP register is set to 1'b1, and the process ends. If int_CLOCKS_TO_DROOP is less than or equal to AVAL_CLOCKS_TO_DROOP, then TRIG_DROOP is set to 1'b1, thereby triggering the first mitigation action and ending the process.

[0070] If the score is in the sign-off violation zone, TRIG_SOFF and TRIG_DROOP are set to 1'b1, which means that both the first and second mitigation actions are triggered, the monitor trigger command is sent to MGI, and the process ends.

[0071] Figure 6 A graph 600 illustrating the relationship between resonance and frequency for two example cases is shown illustratively. Case 610 includes a first peak 611, a second peak 612, and a third peak 613. The first peak 611 has a relatively high impedance. The second peak 612 and the third peak 613 have relatively low impedances. Therefore, case 610 can be considered a first-order voltage droop. In case 610, only TRIG_DROOP may be relevant. In case 620, the first peak 621 and the second peak 622 have relatively high impedances. The third peak 623 has relatively low impedances. Therefore, case 620 can be considered a second-order voltage droop. In case 620, both TRIG_DROOP and TRIG_SOFF may be relevant.

[0072] Figure 7A graph 700 illustrating the instantaneous voltage curve depicts the voltage versus time relationship in an example scenario is shown. In the depicted example scenario, three voltage droops occur. The first droop 710 causes the voltage to fall below the AVAL_PRE_DROOP threshold, but not below it. Therefore, no mitigation action is performed. The second droop 720 does not cause the voltage to fall below the AVAL_PRE_DROOP threshold. Therefore, no mitigation action is performed. The third droop 730 is caused by a large load step of 3.5 GHz, and the voltage drops below the AVAL_PRE_DROOP threshold, and subsequently falls below it. Therefore, mitigation action is required. To ensure the continuous performance of the circuit, the clock is paused for 3 cycles, and then the frequency is set to 3 GHz. This mitigation action brings the voltage back above the AVAL_PRE_DROOP threshold and to a safe level. The clock restart causes a gradual decrease in voltage, thus bringing the voltage below the AVAL_PRE_DROOP threshold. The circuit operates at 3 GHz for 512 clock cycles, then the clock is paused and restarted four times. The number of pauses and restarts may vary depending on the level of the AVAL_PRE_DROOP threshold. Once the voltage reaches a stable level above the AVAL_PRE_DROOP threshold, 3.5 GHz operation is restarted, and... Figure 7 As can be seen, stable operations re-enter the safe zone above the AVAL_PRE_DROOP threshold.

[0073] Therefore, it can be seen that the mitigation action taken in response to the voltage dropping below the AVAL_DROOP threshold has worked to move the voltage back into the safe zone above the AVAL_PRE_DROOP threshold and away from the safe critical low voltage level.

[0074] Figure 8 An example of a delay monitor 808 with a delay line that can be used according to this technology is illustrated in the figure.

[0075] The delay monitor 808 includes a coarse delay line 802, a fine delay line 804, and an encoder 806. The delay monitor may optionally include a fractional offset 808 between the coarse and fine delays.

[0076] This measurement or score is provided by the encoder output. It corresponds to a count of the number of fine gate stages that pass through the fine delay line 804 over a predetermined number of clock cycles. This output can be measured at each output clock cycle of the clock distribution network and averaged over the predetermined number of clock cycles for analysis.

[0077] It should be understood that the delay line 804 is provided only as an example of a method for providing measurement values.

[0078] like Figure 9 As shown, one or more packaged chips 400 are manufactured by a semiconductor chip manufacturer, and the circuitry described above is implemented on a single chip or distributed across two or more chips. In some examples, the chip product 400 manufactured by the semiconductor chip manufacturer may be provided as a semiconductor package comprising a semiconductor device housing the semiconductor device implementing the circuitry described above, and a protective housing (e.g., made of metal, plastic, glass, or ceramic) for connectors (such as pads, solder balls, or pins) for connecting the semiconductor device to an external environment. Where more than one chip 400 is provided, these chips may be provided as separate integrated circuits (provided as separate packages), or may be packaged by a semiconductor provider into a multi-chip semiconductor package (e.g., using interpolators, or by using three-dimensional integration to provide a multi-layer chip product comprising two or more vertically stacked integrated circuit layers).

[0079] In some examples, a collection of chiplets (i.e., small modular chips with specific functionalities) may be referred to as a chip in itself. Chipslets may be individually packaged in semiconductor packages and / or packaged together with other chiplets in multi-chiplet semiconductor packages (e.g., using interpolators, or by using three-dimensional integration to provide multi-layer chiplet products comprising two or more vertically stacked integrated circuit layers).

[0080] One or more packaged chips 400 are assembled on a board 402 together with at least one system component 404 to provide system 406. For example, the board may include a printed circuit board. The board substrate may be made of any of a variety of materials, such as plastic, glass, ceramic, or flexible substrate materials such as paper, plastic, or textile materials. At least one system component 404 includes one or more external components that are not part of the one or more packaged chips 400. For example, at least one system component 404 may include any one or more of the following: another packaged chip (e.g., supplied by a different manufacturer or manufactured at a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor, and / or a sensor.

[0081] A chip-containing product 416 is manufactured, comprising a system 406 (including a board 402, one or more chips 400, and at least one system component 404) and one or more product components 412. Product components 412 include one or more additional components that are not part of system 406. As an example, in a non-exhaustive list, one or more product components 412 may include user input / output devices such as keyboards, touchscreens, microphones, speakers, displays, haptic devices, etc.; wireless communication transmitters / receivers; sensors; actuators for actuating mechanical motion; thermal control devices; additional packaged chips; interface modules; resistors; capacitors; inductors; transformers; diodes; and / or transistors. System 406 and one or more product components 412 may be assembled on an additional board 414.

[0082] Plate 402 or another plate 414 may be disposed on or within the equipment housing or other structural support (e.g., frame or blade) to provide a product that can be disposed of by a user and / or intended for operational use by personnel or company.

[0083] System 406 or chip-containing product 416 can be at least one of the following: end-user product, machine, medical device, computing or telecommunications infrastructure product, or automated control system. For example, as a non-exhaustive list, a chip-containing product can be any of the following: telecommunications equipment, mobile phone, tablet computer, laptop computer, computer, server (e.g., rack server or blade server), infrastructure equipment, networking equipment, vehicle or other automotive product, industrial machine, consumer device, smart card, credit card, smart glasses, avionics equipment, robotic equipment, camera, television, smart TV, DVD player, set-top box, wearable device, home appliance, smart meter, medical device, heating / lighting control equipment, sensor, and / or control system for controlling public infrastructure equipment (such as smart highways or traffic lights).

[0084] Figure 10 Examples of drooping events and corresponding mitigation actions are illustrated. Scores during a drooping event typically follow... Figure 4 The score shown in the first scenario, 410, moves from the safe zone into the sign-off violation zone and then back to the safe zone. (See reference...) Figure 4 As discussed, when the score crosses the AVAL_DROOP threshold from the droop pre-detection region into the droop detection region, the clock frequency decreases. Therefore, the system switches from a fast clock to a slow clock.

[0085] The system continues to operate on a slow clock until the score rises above the AVAL_PRE_DROOP threshold and enters the safe zone. Once the score re-enters the safe zone, the droop event is considered over or complete, and the frequency is increased back to the original frequency to bring the system back to a fast clock. Therefore, a lower frequency and slow clock arrangement is used only when the score falls into the droop detection region, until the score re-enters the safe zone.

[0086] As those skilled in the art will understand, this technology can be embodied in methods, circuits, or computer-readable media that include data and commands for constructing circuits. Therefore, this technology can take the form of a completely hardware implementation, a completely software implementation, or an implementation combining software and hardware. When the term "component" is used, those skilled in the art will understand that it refers to any part of any of the above-described embodiments.

[0087] The concepts described herein may be embodied in computer-readable code used to manufacture devices embodying the described concepts. For example, the computer-readable code may be used in one or more stages of the semiconductor design and manufacturing process, including the electronic design automation (EDA) stage, to manufacture integrated circuits including devices embodying these concepts. The aforementioned computer-readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0088] For example, computer-readable code for manufacturing a device embodying the concepts described herein may be embodied in code that defines the hardware description language (HDL) representation of these concepts. For instance, the code may define a register-transfer level (RTL) abstraction of one or more logic circuits for defining a device embodying these concepts. The code may define an HDL representation of one or more logic circuits embodying the device using Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and intermediate representations such as FIRRTL. Computer-readable code may provide definitions of the concepts or other behavioral representations of the concepts embodying the concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, which can be interpreted by a computer to enable simulation, functional and / or formal verification and testing of the concepts.

[0089] Additionally or alternatively, computer-readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer-readable representations of the integrated circuit component may be generated by applying one or more logic synthesis processes to an RTL representation to generate a definition for manufacturing a device embodying the present technology. Alternatively or additionally, one or more logic synthesis processes may generate a bitstream from the computer-readable code to be loaded into a field-programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing the concepts prior to manufacturing the integrated circuit, or the FPGA may be deployed directly in a product.

[0090] Computer-readable code may include a mixture of code representations used in the manufacture of apparatus, such as including RTL representation, netlist representation, or a mixture of one or more of another computer-readable definition used in the semiconductor design and manufacturing process to manufacture apparatus embodying the present technology. Alternatively or additionally, the concept may be defined in a combination of computer-readable definitions used in the semiconductor design and manufacturing process to manufacture apparatus and computer-readable code defining instructions that will be executed by the defined apparatus once manufactured.

[0091] Such computer-readable code can be contained in any known transient computer-readable medium (such as wired or wireless transmission of code over a network) or non-transient computer-readable medium such as semiconductors, disks, or optical discs. Integrated circuits made using computer-readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept independently or collectively.

[0092] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0093] In this application, a list of features beginning with the phrase “at least one of” means that any one or more of those features may be provided independently or in combination. For example, “at least one of [A], [B], and [C]” covers any of the following options: A only (without B or C), B only (without A or C), C only (without A or B), a combination of A and B (without C), a combination of A and C (without B), a combination of B and C (without A), or a combination of A, B, and C.

[0094] Although illustrative embodiments of the present technology have been described in detail with reference to the accompanying drawings, it should be understood that the present technology is not limited to those precise embodiments, and that various changes and modifications can be made therein without departing from the scope of the present technology as defined by the appended claims.

Claims

1. A circuit for detecting voltage droop events, said circuit being configured to: Receive clock signals from the clock distribution network; Monitor the measurements associated with the voltage supplied to the circuit by the power transmission network; In response to the measured value reaching a first threshold, a first droop detection signal is provided to the clock distribution network; The control entity responds to the first droop detection signal to take a first mitigation action; In response to the measured value reaching a second threshold different from the first threshold, a second droop detection signal is provided to the clock distribution network; as well as The control entity responds to the second droop detection signal to take a second mitigation action.

2. The circuit of claim 1, wherein the first mitigation action includes modifying the frequency of the clock signal by the clock distribution network.

3. The circuit of claim 2, wherein the first mitigation action comprises reducing the frequency of the clock signal by the clock distribution network.

4. The circuit according to claim 2 or 3, wherein the first mitigation action includes increasing the frequency of the clock signal by the clock distribution network.

5. The circuit according to any of the preceding claims, wherein the second mitigation action includes pausing the clock.

6. The circuit of claim 5, wherein the second mitigation action comprises pausing the clock for a predetermined number of clock cycles before restarting the clock.

7. The circuit according to any of the preceding claims, wherein the second threshold is lower than the first threshold, or wherein the second threshold is higher than the first threshold.

8. The circuit according to any of the preceding claims, wherein the first droop detection signal is provided to the clock distribution network in response to the measured value falling below the first threshold.

9. The circuit according to any of the preceding claims, wherein the second droop detection signal is provided to the clock distribution network in response to the measured value falling below the second threshold.

10. The circuit according to any one of claims 1 to 6, wherein: The first threshold is lower than the second threshold; In response to the measured value exceeding the first threshold, the first droop detection signal is provided to the clock distribution network; and In response to the measured value exceeding the second threshold, the second droop detection signal is provided to the clock distribution network.

11. The circuit according to any of the preceding claims, wherein the measured value includes a fraction corresponding to a count of the number of gate stages passing through the delay line during a predetermined number of clock cycles.

12. The circuit of claim 11, wherein the predetermined number of clock cycles is one clock cycle.

13. The circuit according to any of the preceding claims, wherein the circuit is configured to reset both the first detection signal and the second detection signal in response to the measurement value satisfying a third threshold.

14. A method comprising: Provide clock signals to the circuit from the clock distribution network; Monitor the measurements associated with the voltage supplied to the circuit by the power transmission network; In response to the measured value reaching a first threshold, a first droop detection signal is provided to the clock distribution network; In response to receiving the first sag detection signal, a first mitigation action is taken; In response to the measured value reaching a second threshold different from the first threshold, a second droop detection signal is provided to the clock distribution network; as well as In response to receiving the second droop detection signal, a second mitigation action is taken.

15. The method of claim 14, wherein the first mitigation action includes modifying the frequency of the clock signal by the clock distribution network.

16. The method of claim 15, wherein the first mitigation action comprises reducing the frequency of the clock signal by the clock distribution network.

17. The method of claim 15 or 16, wherein the first mitigation action comprises increasing the frequency of the clock signal by the clock distribution network.

18. The method according to any one of claims 14 to 17, wherein the second mitigation action includes pausing the clock.

19. The method of claim 18, wherein the second mitigation action comprises pausing the clock for a predetermined number of clock cycles before restarting the clock.

20. The method of any one of claims 14 to 19, wherein the first droop detection signal is provided to the clock distribution network in response to the measured value falling below the first threshold.

21. The method of any one of claims 14 to 20, wherein the second droop detection signal is provided to the clock distribution network in response to the measured value falling below the second threshold.

22. An apparatus comprising: Circuit; A power transmission network configured to supply current to the circuit; and A clock distribution network configured to provide a clock signal to the circuit; The circuit is configured as follows: Receive clock signals from the clock distribution network; Monitor the measurements associated with the voltage supplied to the circuit by the power transmission network; In response to the measured value reaching a first threshold, a first droop detection signal is provided to the clock distribution network; as well as In response to the measured value reaching a second threshold different from the first threshold, a second droop detection signal is provided to the clock distribution network; The device is configured to: In response to receiving the first sag detection signal, a first mitigation action is taken; and In response to receiving the second droop detection signal, a second mitigation action is taken.

23. A system comprising: The circuit according to any one of claims 1 to 13 is implemented in at least one packaged chip; At least one system component; and plate, The at least one packaged chip and the at least one system component are assembled on the board.

24. A chip-containing product, the chip-containing product comprising the system of claim 23, the system being assembled on an additional board together with at least one other product component.

25. A non-transitory computer-readable medium for storing computer-readable code for manufacturing a circuit for detecting a voltage droop event according to any one of claims 1 to 13.

Images