Display device and electronic device including the same

Abstract

A display device includes a pixel drive circuit portion including a transistor, a connection electrode located on the pixel drive circuit portion and electrically connected to the transistor of the pixel drive circuit portion, a first electrode layer located on the connection electrode, the first electrode layer receiving a power supply voltage and including a plurality of first electrodes, a transmission line group located in a different layer from the first electrode layer, electrically connected to the first electrode layer, and forming a mesh structure with the first electrode layer in a plan view, a partition located on the first electrode layer, and a second electrode layer located on the first electrode layer and separated into a plurality of second electrodes by the partition.

Description

Technical Field

[0001] The embodiments generally provide a display device. More specifically, the embodiments relate to a display device for providing visual information. Background Technology

[0002] With the development of information technology, display devices that connect users with information are playing an increasingly important role in people's daily lives. A display device includes a light-emitting element and a pixel driving circuit section for driving the light-emitting element. The light-emitting element is driven by the pixel driving circuit section and emits light. To improve the reliability of display devices, research on the connection between the light-emitting element and the pixel driving circuit section continues. Summary of the Invention [Technical Objective]

[0003] One object of this disclosure is to provide a display device with improved display quality.

[0004] Another object of this disclosure is to provide an electronic device including the display device.

[0005] However, this disclosure is not limited to this purpose, and various modifications can be made without departing from the spirit and scope of this disclosure. [Technical Solution]

[0006] The display device according to this disclosure includes: a pixel driving circuit section including a transistor; a connecting electrode located on the pixel driving circuit section and electrically connected to the transistor of the pixel driving circuit section; a first electrode layer located on the connecting electrode, the first electrode layer receiving a power supply voltage and including a plurality of first electrodes; a transmission line group located in a different layer from the first electrode layer, electrically connected to the first electrode layer, and forming a grid structure with the first electrode layer in a plan view; a separator located on the first electrode layer; and a second electrode layer located on the first electrode layer and separated into a plurality of second electrodes by the separator.

[0007] In an embodiment, the first electrode layer may be connected to receive power supply voltage via a transmission line group.

[0008] In an embodiment, the first electrode layer may have a grid pattern in which first electrodes extending in different directions are integrally connected.

[0009] In an embodiment, the transmission line group may include transmission lines that extend in one direction and are arranged in a cross direction that is not parallel to that one direction.

[0010] In an embodiment, the transistor may include: an active pattern comprising a semiconductor material; a gate electrode located on the active pattern; and a contact electrode located on the gate electrode and contacting the active pattern. The transmission line may be located in the same layer as the contact electrode.

[0011] In one embodiment, the transmission line may be located in the same layer as the connecting electrode.

[0012] In an embodiment, the transmission line group may include: a first transmission line extending in one direction and arranged in a cross direction that is not parallel to the one direction; and a second transmission line extending in the cross direction and arranged in the one direction.

[0013] In an embodiment, the transistor may include: an active pattern comprising a semiconductor material; a gate electrode located on the active pattern; and a contact electrode located on the gate electrode and contacting the active pattern. A first transmission line may be located in the same layer as the contact electrode. A second transmission line may be located in the same layer as the connection electrode.

[0014] In an embodiment, the first electrode layer may include electrode lines extending in one direction and arranged in intersecting directions that are not parallel to that one direction. The electrode lines may be physically separated from each other, and each of the electrode lines has a structure in which some of the first electrodes extending in different directions may be integrally connected.

[0015] In an embodiment, the first electrode layer may include electrode patterns arranged in one direction and in intersecting directions that are not parallel to the one direction. The electrode patterns may be physically separated from each other, and each of the electrode patterns may have a structure in which some of the first electrodes are integrally connected.

[0016] In an embodiment, the transmission line group may include: a first transmission line extending in the one direction and arranged in the crossing direction; and a second transmission line extending in the crossing direction and arranged in the one direction.

[0017] In an embodiment, the first transmission line and the second transmission line may be connected to at least one of the electrode patterns. The first transmission line, the second transmission line, and the electrode patterns may form a mesh structure.

[0018] In an embodiment, the electrode patterns can be electrically connected to each other via a first transmission line and a second transmission line.

[0019] In an embodiment, the transistor may include: an active pattern comprising a semiconductor material; a gate electrode located on the active pattern; and a contact electrode located on the gate electrode and contacting the active pattern. A first transmission line may be located in the same layer as the contact electrode. A second transmission line may be located in the same layer as the connection electrode.

[0020] In an embodiment, the first electrode may be arranged in one direction and in intersecting directions that are not parallel to that one direction, and the first electrodes may be physically separated from each other.

[0021] In an embodiment, the display device may further include: an intermediate layer located between the first electrode layer and the second electrode layer, and including a light-emitting material.

[0022] In an embodiment, at least one of the second electrodes may be electrically connected to the connection electrode, and may be electrically connected to the transistor of the pixel driving circuit section via the connection electrode.

[0023] The display device according to this disclosure includes: a pixel driving circuit section including a transistor; a connecting electrode located on the pixel driving circuit section and electrically connected to the transistor of the pixel driving circuit section; a first electrode layer located on the connecting electrode, the first electrode layer receiving a power supply voltage and including a plurality of first electrodes; a transmission line group located in a different layer from the first electrode layer, electrically connected to the first electrode layer, and forming a grid structure with the first electrode layer in a plan view; a pixel defining layer located on the first electrode layer and defining a light-emitting area; a connecting pattern electrically connected to the connecting electrode and surrounding the light-emitting area in a plan view; a separator located on the pixel defining layer and the connecting pattern and covering at least a portion of the connecting pattern; and a second electrode layer located on the first electrode layer and separated into a plurality of second electrodes by the separator.

[0024] In an embodiment, at least one of the second electrodes may contact the connecting pattern at a position adjacent to or overlapping with the separator, and may be electrically connected to the transistor of the pixel driving circuit section via the connecting electrode and the connecting pattern.

[0025] The electronic device disclosed herein includes a display device and a power module that supplies power voltage to the display device. The display device includes: a pixel driving circuit section including a transistor; a connecting electrode located on the pixel driving circuit section and electrically connected to the transistor of the pixel driving circuit section; a first electrode layer located on the connecting electrode, the first electrode layer receiving the power voltage and including a plurality of first electrodes; a transmission line group located in a different layer from the first electrode layer, electrically connected to the first electrode layer, and forming a grid structure with the first electrode layer in a plan view; a separator located on the first electrode layer; and a second electrode layer located on the first electrode layer and separated into a plurality of second electrodes by the separator. [Beneficial Effects]

[0026] In the display device according to an embodiment of the present disclosure, the cathode located on the anode can be connected to the pixel driving circuit section. Specifically, the cathode located on the anode can be connected to the drain of the driving transistor in the pixel driving circuit section. Accordingly, even when the light-emitting element deteriorates, the gate-source voltage (Vgs) of the driving transistor will not change. Accordingly, the amount of change in driving current due to the deterioration of the light-emitting element can be reduced. Accordingly, the afterimage defects of the display device with increasing usage time can be reduced, and the lifespan of the display device can be improved.

[0027] Furthermore, according to embodiments of this disclosure, the display device may include a transmission line located in a different layer from the anode to which a power supply voltage is applied and which receives the power supply voltage. The transmission line may be connected to the anode. Accordingly, the transmission line can supply the power supply voltage to the anode, and the anode and transmission line may define a grid structure in a planar view. For example, if the anode itself has a grid pattern, the grid characteristics of the power supply voltage transmission path can be further enhanced by the grid structure defined by the anode and transmission line. Alternatively, even if the anode itself does not have a grid pattern, the grid characteristics of the power supply voltage transmission path can be achieved by the grid structure defined by the anode and transmission line. Accordingly, the voltage drop of the power supply voltage can be reduced. Accordingly, the power consumption of the display device can be improved, and the brightness uniformity can be increased. Accordingly, the display quality of the display device can be improved.

[0028] However, the effects of this disclosure are not limited to those described above, and various extensions can be made within the spirit and scope of this disclosure. Attached Figure Description

[0029] Figure 1a This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0030] Figure 1b This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0031] Figure 2a The illustration includes Figure 1a and Figure 1b A circuit diagram illustrating an example of the circuit structure of pixels in a display device.

[0032] Figure 2b It is shown that it includes Figure 1a and Figure 1b A circuit diagram illustrating an example of the circuit structure of pixels in a display device.

[0033] Figure 2c It is shown that it includes Figure 1a and Figure 1b A circuit diagram illustrating yet another example of the circuit structure of pixels in a display device.

[0034] Figure 3 It is shown schematically. Figure 1a and Figure 1b A floor plan of a portion of the display device.

[0035] Figure 4 yes Figure 3 An enlarged view of one unit luminous region within a unit luminous region.

[0036] Figure 5 It is along Figure 4 The cross-sectional view taken from line I-I'.

[0037] Figure 6 It schematically shows the setting (or location) of something. Figure 1a and Figure 1b A plan view of a first embodiment showing the arrangement relationship between the first electrode layer and the transmission line group in the display area.

[0038] Figure 7 It is shown Figure 6 A magnified view of region AA.

[0039] Figure 8a It shows along Figure 7 A cross-sectional view of an example taken from line II-II'.

[0040] Figure 8b It shows along Figure 7 A cross-sectional view of an example taken from line II-II'.

[0041] Figure 9 It is a schematic illustration of the setting. Figure 1a and Figure 1b A plan view of a second embodiment showing the arrangement relationship between the first electrode layer and the transmission line group in the display area.

[0042] Figure 10 It is shown Figure 9 A magnified view of region BB.

[0043] Figure 11a It shows along Figure 10 A cross-sectional view of an example taken from line III-III'.

[0044] Figure 11b It shows along Figure 10 A cross-sectional view of an example taken from line III-III'.

[0045] Figure 12 It is a schematic illustration of the setting. Figure 1a and Figure 1b A plan view of the arrangement relationship between the first electrode layer and the transmission line group in the display area of ​​the third embodiment.

[0046] Figure 13 It is shown Figure 12 A magnified view of region CC.

[0047] Figure 14a It shows along Figure 13 A cross-sectional view of an example taken from line IV-IV'.

[0048] Figure 14b It shows along Figure 13 A cross-sectional view of an example taken from line IV-IV'.

[0049] Figure 15 It is a schematic illustration of the setting. Figure 1a and Figure 1b A plan view of the arrangement relationship between the first electrode layer and the transmission line group in the display area of ​​the fourth embodiment.

[0050] Figure 16 It is shown Figure 15 A magnified view of region DD.

[0051] Figure 17a It shows along Figure 16 A cross-sectional view of an example taken from line V-V'.

[0052] Figure 17b It shows along Figure 16 A cross-sectional view of an example taken from line V-V'.

[0053] Figure 18 It is a schematic illustration of the setting. Figure 1a and Figure 1b A plan view of the arrangement relationship between the first electrode layer and the transmission line group in the display area of ​​the fifth embodiment.

[0054] Figure 19 It is shown Figure 18 A magnified view of the EE region.

[0055] Figure 20a It shows along Figure 19 A cross-sectional view of an example taken from line VI-VI'.

[0056] Figure 20b It shows along Figure 19 A cross-sectional view of an example taken from line VI-VI'.

[0057] Figure 21 It is a schematic illustration of the setting. Figure 1a and Figure 1b A plan view of the arrangement relationship between the first electrode layer and the transmission line group in the display area of ​​the sixth embodiment.

[0058] Figure 22 It is shown Figure 21 A magnified view of region FF.

[0059] Figure 23a It shows along Figure 22 A cross-sectional view of an example taken from line VII-VII'.

[0060] Figure 23b It shows along Figure 22 A cross-sectional view of an example taken from line VII-VII'.

[0061] Figure 24It is a schematic illustration of the setting. Figure 1a and Figure 1b A plan view of the arrangement relationship between the first electrode layer and the transmission line group in the display area of ​​the seventh embodiment.

[0062] Figure 25 It is shown Figure 24 A magnified view of region GG.

[0063] Figure 26a It shows along Figure 25 A cross-sectional view of an example taken from line VIII-VIII'.

[0064] Figure 26b It shows along Figure 25 A cross-sectional view of an example taken from line VIII-VIII'.

[0065] Figure 27 It is shown schematically. Figure 1a and Figure 1b A floor plan of a portion of the display device.

[0066] Figure 28 yes Figure 27 An enlarged view of one unit luminous region within a unit luminous region.

[0067] Figure 29 It is along Figure 28 The cross-sectional view taken from line IX-IX'.

[0068] Figure 30 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0069] Figure 31 This is a schematic diagram illustrating an electronic device according to various embodiments. Detailed Implementation

[0070] The specific structural and / or functional descriptions of the embodiments of this disclosure described herein are merely illustrative for the purpose of describing embodiments of this disclosure, and the embodiments of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described herein.

[0071] Various modifications and forms may be made in this disclosure, and specific embodiments will be illustrated in the accompanying drawings and described in detail in the text. However, this is not intended to limit this disclosure to the specific forms disclosed, and it will be understood that all variations, equivalents, or substitutions falling within the spirit and scope of this disclosure should be included.

[0072] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the inventive concept. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0073] It will be understood that when an element is “connected” or “coupled” to another element, it is intended to indicate that the element is directly connected or coupled to the other element, or that there is both an intermediary element. Conversely, when an element is described as “directly connected” or “directly coupled” to another element, there is no intermediary element. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., “between” vs. “directly between”, “adjacent” vs. “directly adjacent”, etc.).

[0074] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the inventive concept. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including” as used in this specification indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0075] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another illustrated in the figures. It will be understood that, in addition to the orientations shown in the figures, the relative terms are also intended to cover different orientations of the device. For example, if a device in one of the figures is flipped, an element described as being “down” of the other elements will be oriented “up” of the other elements. Thus, depending on the specific orientation of the figure, the term “down” can cover both “down” and “up” orientations. Similarly, if a device in one of the figures is flipped, an element described as being “below” or “under” the other elements will be oriented “above” the other elements. Thus, the terms “below” or “under” can cover both “up” and “down” orientations.

[0076] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will be further understood that terms defined, for example, in common dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and not as an idealized or overly formal meaning, unless expressly defined herein.

[0077] In the following description, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions of the same parts will be omitted.

[0078] Figure 1a This is a plan view illustrating a display device according to an embodiment of the present disclosure. Figure 1b This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0079] refer to Figure 1a and Figure 1b A display device DD (or DDa) can be a device activated by an electrical signal. For example, a display device DD can be a small display device used in small electronic devices such as smartphones, mobile phones, smartwatches, game consoles, or cameras. Alternatively, a display device DDa can be a medium to large-sized display device used in medium to large-sized electronic devices such as laptops, tablet PCs, televisions, computer monitors, vehicle monitors, or external billboards. Figure 1a The illustration shows the display device DD as an example of a small display device, and Figure 1b The illustration shows the display device DDa as an example of a medium to large-sized display device.

[0080] A display device DD (or DDa) may include a display area DA and a peripheral area NDA. The display area DA may be an area that displays an image by generating light or controlling the transmittance of light provided from an external light source. The peripheral area NDA may be located around the display area DA. For example, the peripheral area NDA may surround at least a portion of the display area DA. In embodiments, the peripheral area NDA may be an area where no image is displayed. However, embodiments are not limited to this, and an image may be displayed in at least a portion of the peripheral area NDA. For example, a light-emitting element may be disposed in at least a portion of the peripheral area NDA.

[0081] The display device DD (or DDa) may include a substrate SUB, a pixel PX, a gate line GL, a data line DL, a data driver DDV, and a gate driver GDV.

[0082] The substrate SUB can serve as the substrate of a display device DD (or DDa). In embodiments, examples of materials that can be used as the substrate SUB include glass, quartz, silicon, or polymers. These can be used individually or in combination with each other. Furthermore, the substrate SUB can have a single-layer structure or a multi-layer structure comprising multiple stacked layers of different materials.

[0083] Pixels PX can be disposed on the substrate SUB and in the display area DA. Pixels PX can be electrically connected to gate lines GL and data lines DL. For example, pixels PX can be arranged in a matrix in a first direction DR1 and a second direction DR2. The first direction DR1 and the second direction DR2 can be perpendicular to each other and define a plane. An image can be displayed on a third direction DR3, which is a normal direction to this plane. That is, the third direction DR3 can be perpendicular to both the first direction DR1 and the second direction DR2. Each of the pixels PX can include a pixel driving circuit and a light-emitting element. The light-emitting element can emit light. The light-emitting element can be an organic light-emitting diode or an inorganic light-emitting diode.

[0084] Each of the gate lines GL and each of the data lines DL can intersect each other. For example, each of the gate lines GL can extend generally in a first direction DR1, and the gate lines GL can be arranged in a second direction DR2. Each of the data lines DL can extend generally in the second direction DR2, and the data lines DL can be arranged in the first direction DR1. However, the embodiments are not limited to this.

[0085] The data driver DDV can be located on the substrate SUB or in the peripheral area NDA. The data driver DDV generates a data voltage. The data driver DDV outputs the data voltage to the data line DL. The data voltage can be applied to the pixel PX through the data line DL.

[0086] In one embodiment, the data driver DDV can be mounted on the substrate SUB. However, the embodiment is not limited to this, and the data driver DDV can be disposed on a flexible film coupled to the substrate SUB. That is, the display device DD (or DDa) can have a chip-on-film (COF) structure.

[0087] In an embodiment, Figure 1b The display device DDA may include multiple data drivers DDV. For example, the data drivers DDV may be disposed on both sides of the display area DA in the second direction DR2. For example, the data drivers DDV may be disposed along each of the long sides of the display device DDA. However, the embodiments are not limited to this.

[0088] A gate driver (GDV) can be disposed on the substrate SUB, in the peripheral region NDA. The gate driver (GDV) can generate a gate signal. The gate driver (GDV) can output the gate signal to the gate line GL. The gate signal can be applied to the pixel PX through the gate line GL. In an embodiment, the gate driver (GDV) can be disposed on both sides of the display region DA in the first direction DR1. However, the embodiment is not limited to this.

[0089] In this embodiment, the transmitter driver that generates the transmitter control signal may be further disposed in the peripheral region NDA. The transmitter control signal can be applied to pixel PX via the transmitter control line.

[0090] at the same time, Figure 1a and Figure 1b The number or arrangement of data drivers (DDVs) and gate drivers (GDVs) shown in the diagram are merely examples, and the embodiments are not limited thereto.

[0091] In addition, although Figure 1a The illustration shows a display device DD having a basic rectangular planar shape including short sides extending in a first direction DR1 and long sides extending in a second direction DR2, but the embodiment is not limited to this. Furthermore, although... Figure 1b The illustration shows a display device DDa with a basic rectangular planar shape including a long side extending in a first direction DR1 and a short side extending in a second direction DR2, but the embodiment is not limited to this. That is, according to the embodiment, the planar shape of each of the display devices DD and DDa can be varied.

[0092] Meanwhile, the following description can be applied to Figure 1a Display device DD and Figure 1b The display device is DDa. Therefore, for ease of description, both display device DD and DDa will be referred to as display device DD below.

[0093] Figure 2a The illustration includes Figure 1a and Figure 1b A circuit diagram illustrating an example of the circuit structure of pixels in a display device.

[0094] refer to Figure 2a In one embodiment, pixel PX may include a light-emitting element (LED) and a pixel driving circuit section PC connected to the LED. In another embodiment, the pixel driving circuit section PC may include a first transistor T1, a second transistor T2, and a first capacitor C1. Figure 2aIn the illustration, both the first transistor T1 and the second transistor T2 are shown as n-type transistors. However, the embodiment is not limited to this; one of the first transistor T1 and the second transistor T2 may be an n-type transistor and the other may be a p-type transistor. For example, the first transistor T1 may be an n-type transistor, and the second transistor T2 may be a p-type transistor.

[0095] If pixel PX includes n-type transistors and p-type transistors, the active pattern of the n-type transistors may include an oxide semiconductor material, and the active pattern of the p-type transistors may include a silicon semiconductor material. However, embodiments are not limited thereto, and both the active patterns of the n-type transistors and the active patterns of the p-type transistors may include silicon semiconductor materials.

[0096] The pixel driving circuit PC can be connected to a first gate line GWL, a data line DL, a first voltage line VL1, and a second voltage line VL2. The first gate line GWL can transmit a first gate signal GW. The data line DL can transmit a data voltage VDATA. The first voltage line VL1 can transmit a first power supply voltage ELVDD with a relatively high voltage level. The second voltage line VL2 can transmit a second power supply voltage ELVSS with a relatively low voltage level.

[0097] The first transistor T1 may include a gate terminal, a first terminal, and a second terminal. In an embodiment, the first terminal of the first transistor T1 may be the source, and the second terminal of the first transistor T1 may be the drain. The gate terminal of the first transistor T1 may be connected to a first node N1. The first terminal of the first transistor T1 may be connected to a second node N2. The second terminal of the first transistor T1 may be connected to a third node N3. The second terminal of the first transistor T1 may be connected to a light-emitting element LED. The first transistor T1 may provide a drive current ID to the light-emitting element LED.

[0098] The second transistor T2 may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the second transistor T2 may be the source, and the second terminal of the second transistor T2 may be the drain. However, the embodiment is not limited thereto; the first terminal of the second transistor T2 may be the drain, and the second terminal of the second transistor T2 may be the source. The gate terminal of the second transistor T2 may be connected to a first gate line GWL. The first terminal of the second transistor T2 may be connected to a data line DL. The second terminal of the second transistor T2 may be connected to a first node N1.

[0099] The gate terminal of the second transistor T2 can receive the first gate signal GW through the first gate line GWL. The second transistor T2 can be turned on or off in response to the first gate signal GW. For example, if the second transistor T2 is an n-type transistor, it can be turned off in response to the first gate signal GW with a negative voltage level, and it can be turned on in response to the first gate signal GW with a positive voltage level. Alternatively, if the second transistor T2 is a p-type transistor, it can be turned off in response to the first gate signal GW with a positive voltage level, and it can be turned on in response to the first gate signal GW with a negative voltage level. The first terminal of the second transistor T2 can receive the data voltage VDATA through the data line DL. While the second transistor T2 is turned on, its second terminal can provide the data voltage VDATA to the first node N1. Accordingly, the second transistor T2 can drive the first transistor T1.

[0100] The first capacitor C1 may include a first terminal and a second terminal. The first terminal of the first capacitor C1 may be connected to a first node N1. The second terminal of the first capacitor C1 may be connected to a second node N2. Current may be charged into or discharged from the first capacitor C1 according to the data voltage VDATA transmitted to the first node N1.

[0101] The light-emitting element (LED) may include an anode and a cathode. The anode of the LED may be connected to a first voltage line VL1. The cathode of the LED may be connected to a third node N3. Specifically, the cathode of the LED may be connected to the second terminal of the first transistor T1.

[0102] Figure 2b It is shown that it includes Figure 1a and Figure 1b A circuit diagram illustrating an example of the circuit structure of pixels in a display device.

[0103] Reference Figure 2a Compared to the embodiment of the circuit structure of the described pixel PX, the following reference... Figure 2b The pixel driving circuit PC' of the embodiment of the described pixel PX circuit structure may further include third to sixth transistors T3, T4, T5 and T6 and a second capacitor C2. Therefore, redundant descriptions can be omitted or simplified.

[0104] refer to Figure 2bIn an embodiment, pixel PX may include a light-emitting element LED and a pixel driving circuit PC' connected to the light-emitting element LED. In an embodiment, the pixel driving circuit PC' may include first to sixth transistors T1', T2, T3, T4, T5, and T6, a first capacitor C1, and a second capacitor C2. Figure 2b In the illustration, all of the first to sixth transistors T1', T2, T3, T4, T5, and T6 are shown as n-type transistors. However, the embodiment is not limited to this; some of the first to sixth transistors T1', T2, T3, T4, T5, and T6 may be n-type transistors, and the others may be p-type transistors. For example, the first transistor T1' may be an n-type transistor, and some of the second to sixth transistors T2, T3, T4, T5, and T6 may be n-type transistors, while the others may be p-type transistors.

[0105] If pixel PX includes n-type transistors and p-type transistors, the active pattern of the n-type transistors may include an oxide semiconductor material, and the active pattern of the p-type transistors may include a silicon semiconductor material. However, embodiments are not limited thereto, and both the active patterns of the n-type transistors and the active patterns of the p-type transistors may include silicon semiconductor materials.

[0106] The pixel driving circuit PC can be connected to the first to third gate lines GWL, GCL, and GRL, the data line DL, the first to fourth voltage lines VL1, VL2, VL3, and VL4, the first transmit control line ECL1, and the second transmit control line ECL2. The first gate line GWL can transmit the first gate signal GW. The second gate line GCL can transmit the second gate signal GC. The third gate line GRL can transmit the third gate signal GR. The data line DL can transmit the data voltage VDATA. The first voltage line VL1 can transmit the first power supply voltage ELVDD with a high voltage level. The second voltage line VL2 can transmit the second power supply voltage ELVSS with a low voltage level. The third voltage line VL3 can transmit the first initialization voltage Vcint. The fourth voltage line VL4 can transmit the reference voltage Vref. The reference voltage Vref can have a voltage level lower than the first power supply voltage ELVDD.

[0107] Figure 2b The first transistor T1', except that its second terminal is connected to the light-emitting element LED via the fifth transistor T5, can be referenced above. Figure 2a The first transistor T1 described is essentially the same. Therefore, redundant descriptions can be omitted or simplified. That is, the first transistor T1' of the pixel driving circuit PC' can be connected to the light-emitting element LED through the fifth transistor T5, and the driving current ID can be provided to the light-emitting element LED through the fifth transistor T5.

[0108] Figure 2b The second transistor T2 can be referenced above. Figure 2a The second transistor T2 described is essentially the same. Accordingly, Figure 2a The description of the second transistor T2 can be applied to Figure 2b The second transistor T2. When the second transistor T2 is turned on, the second transistor T2 can drive the first transistor T1'.

[0109] The third transistor T3 may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the third transistor T3 may be the source, and the second terminal of the third transistor T3 may be the drain. However, the embodiment is not limited thereto; the first terminal of the third transistor T3 may be the drain, and the second terminal of the third transistor T3 may be the source. The gate terminal of the third transistor T3 may be connected to a second gate line GCL. The first terminal of the third transistor T3 may be connected to a third node N3. The second terminal of the third transistor T3 may be connected to a third voltage line VL3.

[0110] The gate terminal of the third transistor T3 can receive the second gate signal GC through the second gate line GCL. The third transistor T3 can be turned on or off in response to the second gate signal GC. For example, if the third transistor T3 is an n-type transistor, it can be turned off in response to the second gate signal GC with a negative voltage level, and it can be turned on in response to the second gate signal GC with a positive voltage level. Alternatively, if the third transistor T3 is a p-type transistor, it can be turned off in response to the second gate signal GC with a positive voltage level, and it can be turned on in response to the second gate signal GC with a negative voltage level. While the third transistor T3 is turned on, it can provide a first initialization voltage Vcint to the third node N3. Specifically, the third transistor T3 can initialize the cathode voltage by providing the first initialization voltage Vcint to the cathode of the light-emitting element LED in response to the second gate signal GC.

[0111] The fourth transistor T4 may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the fourth transistor T4 may be the source, and the second terminal of the fourth transistor T4 may be the drain. However, the embodiment is not limited thereto; the first terminal of the fourth transistor T4 may be the drain, and the second terminal of the fourth transistor T4 may be the source. The gate terminal of the fourth transistor T4 may be connected to a third gate line GRL. The first terminal of the fourth transistor T4 may be connected to a first node N1. The second terminal of the fourth transistor T4 may be connected to a fourth voltage line VL4.

[0112] The gate terminal of the fourth transistor T4 can receive the third gate signal GR through the third gate line GRL. The fourth transistor T4 can be turned on or off in response to the third gate signal GR. For example, if the fourth transistor T4 is an n-type transistor, it can be turned off in response to the third gate signal GR with a negative voltage level, and it can be turned on in response to the third gate signal GR with a positive voltage level. Conversely, if the fourth transistor T4 is a p-type transistor, it can be turned off in response to the third gate signal GR with a positive voltage level, and it can be turned on in response to the third gate signal GR with a negative voltage level. While the fourth transistor T4 is turned on, it can provide a reference voltage Vref to the first node N1.

[0113] The fifth transistor T5 may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the fifth transistor T5 may be the source, and the second terminal of the fifth transistor T5 may be the drain. However, the embodiment is not limited thereto; the first terminal of the fifth transistor T5 may be the drain, and the second terminal of the fifth transistor T5 may be the source. The gate terminal of the fifth transistor T5 may be connected to the first emitter control line ECL1. The first terminal of the fifth transistor T5 may be connected to the second terminal of the first transistor T1'. The second terminal of the fifth transistor T5 may be connected to the third node N3. The second terminal of the fifth transistor T5 may be connected to the light-emitting element LED.

[0114] The gate terminal of the fifth transistor T5 can receive the first transmit control signal EM1 via the first transmit control line ECL1. The fifth transistor T5 can be turned on or off in response to the first transmit control signal EM1. For example, if the fifth transistor T5 is an n-type transistor, it can be turned off in response to the first transmit control signal EM1 with a negative voltage level, and it can be turned on in response to the first transmit control signal EM1 with a positive voltage level. Alternatively, if the fifth transistor T5 is a p-type transistor, it can be turned off in response to the first transmit control signal EM1 with a positive voltage level, and it can be turned on in response to the first transmit control signal EM1 with a negative voltage level. While the fifth transistor T5 is turned on, it can electrically connect the first transistor T1' and the light-emitting element LED to each other. Specifically, the fifth transistor T5 can electrically connect the second terminal of the first transistor T1' and the cathode of the light-emitting element LED to each other in response to the first transmit control signal EM1.

[0115] The sixth transistor T6 may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the sixth transistor T6 may be the source, and the second terminal of the sixth transistor T6 may be the drain. However, the embodiment is not limited thereto; the first terminal of the sixth transistor T6 may be the drain, and the second terminal of the sixth transistor T6 may be the source. The gate terminal of the sixth transistor T6 may be connected to the second emitter control line ECL2. The first terminal of the sixth transistor T6 may be connected to the second voltage line VL2. The second terminal of the sixth transistor T6 may be connected to the second node N2.

[0116] The gate terminal of the sixth transistor T6 can receive the second transmit control signal EM2 via the second transmit control line ECL2. The sixth transistor T6 can be turned on or off in response to the second transmit control signal EM2. For example, if the sixth transistor T6 is an n-type transistor, it can be turned off in response to the second transmit control signal EM2 with a negative voltage level, and it can be turned on in response to the second transmit control signal EM2 with a positive voltage level. Conversely, if the sixth transistor T6 is a p-type transistor, it can be turned off in response to the second transmit control signal EM2 with a positive voltage level, and it can be turned on in response to the second transmit control signal EM2 with a negative voltage level. While the sixth transistor T6 is turned on, it can supply the second power supply voltage ELVSS to the second node N2.

[0117] although Figure 2b The illustration shows that the fifth transistor T5 and the sixth transistor T6 are driven independently by different transmit control signals, but the embodiment is not limited to this. For example, the first transmit control signal EM1 and the second transmit control signal EM2 can be provided as a substantially single transmit control signal, and the fifth transistor T5 and the sixth transistor T6 can be simultaneously turned on or off. In this case, the first transmit control line ECL1 and the second transmit control line ECL2 can be provided as a single transmit control line.

[0118] Figure 2b The first capacitor C1 can be referenced above. Figure 2a The first capacitor C1 described is essentially the same. Accordingly, Figure 2a The description of the first capacitor C1 can be applied to Figure 2b The first capacitor C1. That is, according to the data voltage VDATA transmitted to the first node N1, current can be charged into or discharged from the first capacitor C1.

[0119] The second capacitor C2 may include a first terminal and a second terminal. The first terminal of the second capacitor C2 may be connected to the second node N2. The second terminal of the second capacitor C2 may be connected to the second voltage line VL2. Specifically, the second capacitor C2 may be connected in series with the first capacitor C1. The data voltage VDATA may be transmitted to the first node N1, and the voltage may be distributed due to the series connection between the first capacitor C1 and the second capacitor C2, so that the distributed data voltage VDATA may be transmitted to the second node N2. Since the first transistor T1' generates a drive current ID based on the voltage of the first node N1 and the voltage of the second node N2, the data range can be extended.

[0120] Figure 2b The light-emitting element LED, except that its cathode is connected to the second terminal of the first transistor T1' via the fifth transistor T5, can be referenced above. Figure 2a The described light-emitting elements (LEDs) are essentially the same. Therefore, redundant descriptions can be omitted or simplified. That is, the cathode of the LED can be connected to the second terminal of the first transistor T1' via the fifth transistor T5. Additionally, the cathode of the LED can receive the first initialization voltage Vcint via the third transistor T3.

[0121] Figure 2c It is shown that it includes Figure 1a and Figure 1b A circuit diagram illustrating yet another example of the circuit structure of pixels in a display device.

[0122] Reference Figure 2b Compared to the embodiment of the circuit structure of the described pixel PX, the following reference... Figure 2c The pixel driving circuit section PC'' of the described embodiment of the circuit structure of pixel PX may further include a seventh transistor T7 and an eighth transistor T8. Therefore, redundant descriptions can be omitted or simplified.

[0123] refer to Figure 2c In an embodiment, pixel PX may include a light-emitting element LED and a pixel driving circuit PC'' connected to the light-emitting element LED. In an embodiment, the pixel driving circuit PC'' may include first to eighth transistors T1', T2, T3, T4, T5, T6, T7, and T8, a first capacitor C1, and a second capacitor C2. Figure 2cIn the illustration, all of the first to eighth transistors T1', T2, T3, T4, T5, T6, T7, and T8 are shown as n-type transistors. However, the embodiment is not limited to this; some of the first to eighth transistors T1', T2, T3, T4, T5, T6, T7, and T8 may be n-type transistors, and the others may be p-type transistors. For example, the first transistor T1' may be an n-type transistor, and some of the second to eighth transistors T2, T3, T4, T5, T6, T7, and T8 may be n-type transistors, while the others may be p-type transistors.

[0124] If pixel PX comprises a mixture of n-type and p-type transistors, the active pattern of the n-type transistors may comprise an oxide semiconductor material, and the active pattern of the p-type transistors may comprise a silicon semiconductor material. However, embodiments are not limited thereto, and both the active patterns of the n-type transistors and the active patterns of the p-type transistors may comprise silicon semiconductor materials.

[0125] The pixel driving circuit PC can be connected to the first to fourth gate lines GWL, GCL, GRL, and GIL, the data line DL, the first to fifth voltage lines VL1, VL2, VL3, VL4, and VL5, and the transmit control line ECL. The first gate line GWL can transmit the first gate signal GW. The second gate line GCL can transmit the second gate signal GC. The third gate line GRL can transmit the third gate signal GR. The fourth gate line GIL can transmit the fourth gate signal GI. The data line DL can transmit the data voltage VDATA. The first voltage line VL1 can transmit the first power supply voltage ELVDD, which has a relatively high voltage level. The second voltage line VL2 can transmit the second power supply voltage ELVSS, which has a relatively low voltage level. The third voltage line VL3 can transmit the first initialization voltage Vcint. The fourth voltage line VL4 can transmit the reference voltage Vref. The reference voltage Vref can have a voltage level lower than the first power supply voltage ELVDD. The fifth voltage line VL5 can transmit the second initialization voltage Vint. The first initialization voltage Vcint and the second initialization voltage Vint can have different voltage levels than each other.

[0126] Figure 2c The first to sixth transistors T1', T2, T3, T4, T5, and T6, the first capacitor C1, and the second capacitor C2 can be respectively connected to the reference above. Figure 2b The first to sixth transistors T1', T2, T3, T4, T5, and T6, the first capacitor C1, and the second capacitor C2 are described as being substantially the same. Accordingly, Figure 2b The descriptions of the first to sixth transistors T1', T2, T3, T4, T5, and T6, the first capacitor C1, and the second capacitor C2 can be applied respectively to Figure 2cThe first to sixth transistors T1', T2, T3, T4, T5 and T6, the first capacitor C1 and the second capacitor C2. Therefore, redundant descriptions can be omitted.

[0127] At the same time, despite Figure 2c The illustration shows that the fifth transistor T5 and the sixth transistor T6 are simultaneously driven by the emit control signal EM, but the embodiment is not limited to this. For example, as... Figure 2b As shown, the fifth transistor T5 and the sixth transistor T6 can be controlled by different transmit signals (e.g., Figure 2b The first transmit control signal EM1 and the second transmit control signal EM2 are driven independently. In this case, the transmit control line connected to the fifth transistor T5 and the transmit control line connected to the sixth transistor T6 can be different transmit control lines that are distinct from each other (e.g., Figure 2b The first launch control line (ECL1) and the second launch control line (ECL2).

[0128] The seventh transistor T7 may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the seventh transistor T7 may be the source, and the second terminal of the seventh transistor T7 may be the drain. However, the embodiment is not limited thereto; the first terminal of the seventh transistor T7 may be the drain, and the second terminal of the seventh transistor T7 may be the source. The gate terminal of the seventh transistor T7 may be connected to the second gate line GCL. The first terminal of the seventh transistor T7 may be connected to the fourth node N4. The second terminal of the seventh transistor T7 may be connected to the third voltage line VL3.

[0129] The gate terminal of the seventh transistor T7 can receive the second gate signal GC through the second gate line GCL. The seventh transistor T7 can be turned on or off in response to the second gate signal GC. For example, if the seventh transistor T7 is an n-type transistor, it can be turned off in response to the second gate signal GC with a negative voltage level, and it can be turned on in response to the second gate signal GC with a positive voltage level. If the seventh transistor T7 is a p-type transistor, it can be turned off in response to the second gate signal GC with a positive voltage level, and it can be turned on in response to the second gate signal GC with a negative voltage level. While the seventh transistor T7 is turned on, it can provide a first initialization voltage Vcint to the fourth node N4. Specifically, the seventh transistor T7 can compensate for the threshold voltage (Vth) of the first transistor T1' by providing the first initialization voltage Vcint to the fourth node N4 in response to the second gate signal GC.

[0130] At the same time, despite Figure 2cThe illustration shows that the gate line connected to the third transistor T3 and the gate line connected to the seventh transistor T7 are provided as a single gate line (i.e., a second gate line GCL), but the embodiment is not limited to this. For example, the gate line connected to the third transistor T3 and the gate line connected to the seventh transistor T7 can be different gate lines that are distinct from each other.

[0131] In addition, although Figure 2c The illustration shows that the third transistor T3 and the seventh transistor T7 are simultaneously driven by the second gate signal GC, but the embodiment is not limited to this. For example, the third transistor T3 and the seventh transistor T7 can be driven independently by different gate signals. In this case, the gate lines connected to the third transistor T3 and the gate lines connected to the seventh transistor T7 can be different gate lines that are distinct from each other.

[0132] The eighth transistor T8 may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the eighth transistor T8 may be the source, and the second terminal of the eighth transistor T8 may be the drain. However, the embodiment is not limited thereto; the first terminal of the eighth transistor T8 may be the drain, and the second terminal of the eighth transistor T8 may be the source. The gate terminal of the eighth transistor T8 may be connected to the fourth gate line GIL. The first terminal of the eighth transistor T8 may be connected to the second node N2. The second terminal of the eighth transistor T8 may be connected to the fifth voltage line VL5.

[0133] The gate terminal of the eighth transistor T8 can receive the fourth gate signal GI through the fourth gate line GIL. The eighth transistor T8 can be turned on or off in response to the fourth gate signal GI. For example, if the eighth transistor T8 is an n-type transistor, it can be turned off in response to the fourth gate signal GI with a negative voltage level, and it can be turned on in response to the fourth gate signal GI with a positive voltage level. If the eighth transistor T8 is a p-type transistor, it can be turned off in response to the fourth gate signal GI with a positive voltage level, and it can be turned on in response to the fourth gate signal GI with a negative voltage level. While the eighth transistor T8 is turned on, it can provide the second initialization voltage Vint to the second node N2.

[0134] Figure 2c The light-emitting element LED can be compared with the above reference. Figure 2b The described light-emitting elements, LEDs, are essentially the same. Accordingly, Figure 2b The description of the light-emitting element LED can be applied to Figure 2c The light-emitting element is an LED. Therefore, redundant descriptions can be omitted.

[0135] like Figures 2a to 2cAs shown, according to an embodiment, the anode of the light-emitting element LED can receive a first power supply voltage ELVDD through a first voltage line VL1, and the cathode of the light-emitting element LED can be connected to the second terminal of the first transistor T1 (or T1'). That is, the potential of the cathode of the light-emitting element LED can be controlled by electrically connecting it to the first transistor T1 (or T1').

[0136] Since the first voltage line VL1 provides a first power supply voltage ELVDD with a high voltage level and the second voltage line VL2 provides a second power supply voltage ELVSS with a low voltage level, if the first transistor T1 (or T1') is an n-type transistor, the second terminal of the first transistor T1 (or T1') can be the drain. That is, according to the embodiment, the cathode of the light-emitting element LED can be connected to the drain of the first transistor T1 (or T1').

[0137] If the first transistor T1 (or T1') is an n-type transistor, when the anode of the light-emitting element LED is connected to the source of the first transistor T1 (or T1'), the source voltage of the first transistor T1 (or T1') may shift due to the degradation of the light-emitting element LED, causing the gate-source voltage (Vgs) of the first transistor T1 (or T1') to change. As a result, the fluctuation of the drive current ID may increase, afterimage defects may occur, and the lifespan of the display device may be shortened.

[0138] According to an embodiment, the anode of the light-emitting element LED can receive a first power supply voltage ELVDD, and the cathode of the light-emitting element LED can be connected to the drain of a first transistor T1 (or T1'). Accordingly, even when the light-emitting element LED deteriorates, the gate-source voltage (Vgs) of the first transistor T1 (or T1') will not change. Consequently, the range of variation in the drive current ID due to the deterioration of the light-emitting element LED can be reduced. Therefore, the afterimage defects of the display device DD with increasing usage time can be reduced, and the lifespan of the display device DD can be improved.

[0139] at the same time, Figures 2a to 2c The circuit structure of the pixels illustrated in the figure (e.g., the number or arrangement of transistors, the number or arrangement of capacitors) is merely an example and can be varied according to embodiments.

[0140] Figure 3 It is shown schematically. Figure 1a and Figure 1b A floor plan of a portion of the display device. Figure 4 yes Figure 3 An enlarged view of one unit luminous region within a unit luminous region. Figure 5 It is along Figure 4 The cross-sectional view taken from line I-I'.

[0141] Specifically, Figure 3 Four regions are depicted in a matrix arrangement of 2 rows and 2 columns, wherein, as shown, two of these regions are unit luminous regions UEA1 placed diagonally opposite each other, and the other two regions are unit luminous regions UEA2 placed diagonally opposite each other. Figure 4 Depicting Figure 3 The first unit emitting region UEA1 is one of the unit emitting regions UEA1 and UEA2. Figure 5 Depicting along Figure 4 The cross-sectional view taken by line I-I' is shown in the figure. For ease of explanation, in Figure 3 and Figure 4 The text omits or emphasizes Figure 5 Some of the components shown. Additionally, the second electrodes E2a, E2b, and E2c are... Figure 4 As shown in the diagram, but for clarity of illustration, in Figure 3 The middle part is omitted.

[0142] refer to Figure 3 and Figure 4 The display device DD may include first to third pixel driving circuits PCa, PCb and PCc, first to third light-emitting elements LEDa, LEDb and LEDc, first to third connecting electrodes CEa, CEb and CEc, first to third connecting patterns CNPa, CNPb and CNPc and separator SPR.

[0143] Each of the first to third pixel driving circuit sections PCa, PCb, and PCc can correspond to a reference. Figures 2a to 2c At least one of the pixel driving circuit sections PC, PC', and PC'' described. That is, each of the first to third pixel driving circuit sections PCa, PCb, and PCc may include at least one transistor and at least one capacitor. For example, each of the first to third pixel driving circuit sections PCa, PCb, and PCc may include... Figure 5 The diagram shows a first transistor TR1, a second transistor TR2, a first capacitor CAP1, and a second capacitor CAP2.

[0144] at this time, Figure 5 The first transistor TR1 can be a transistor connected to the light-emitting element via connecting electrodes and connecting patterns. For example, if the first to third pixel driving circuit sections PCa, PCb, and PCc are... Figure 2a In the pixel driving circuit section PC, the first transistor TR1 can be Figure 2a The first transistor T1 and the second transistor TR2 can be Figure 2aThe second transistor T2. Additionally, if the first to third pixel driving circuit sections PCa, PCb, and PCc are... Figure 2b In the pixel driving circuit PC', the first transistor TR1 can be Figure 2b The fifth transistor T5 and the second transistor TR2 can be Figure 2b Any one of the first to fourth transistors T1', T2, T3, and T4, and the sixth transistor T6. Additionally, if the first to third pixel driving circuit sections PCa, PCb, and PCc are... Figure 2c If the pixel driving circuit PC'' is a pixel driving circuit, then the first transistor TR1 can be a pixel driving circuit PC''. Figure 2c The fifth transistor T5 and the second transistor TR2 can be Figure 2c The first to fourth transistors T1', T2, T3 and T4, and the sixth to eighth transistors T6, T7 and T8. However, embodiments of this disclosure are not limited thereto.

[0145] In an embodiment, Figure 5 The first capacitor CAP1 can correspond to Figures 2a to 2c The first capacitor C1, and Figure 5 The second capacitor CAP2 can correspond to Figure 2b and Figure 2c The second capacitor C2. That is, if the first to third pixel driving circuits PCa, PCb and PCc are Figure 2a In the pixel driving circuit PC, the second capacitor CAP2 can be omitted. However, this disclosure is not limited to this, and in embodiments, Figure 5 The first capacitor CAP1 can correspond to Figures 2a to 2c The second capacitor C2, and Figure 5 The second capacitor CAP2 can correspond to Figure 2b and Figure 2c The first capacitor C1. In this case, if the first to third pixel driving circuit sections PCa, PCb, and PCc are Figure 2a If the pixel driving circuit PC is omitted, the first capacitor CAP1 can be omitted.

[0146] Please refer to later Figure 5 The components of the first transistor TR1, the second transistor TR2, the first capacitor CAP1, and the second capacitor CAP2 are described in more detail.

[0147] At the same time, Figure 3 and Figure 4In the diagram, the first to third pixel driving circuit sections PCa, PCb, and PCc are shown arranged sequentially in a rectangular shape along the first direction DR1. However, this disclosure is not limited to this, and the shape and arrangement of the first to third pixel driving circuit sections PCa, PCb, and PCc can vary depending on the embodiment.

[0148] Each of the first to third light-emitting elements LEDa, LEDb, and LEDc can correspond to a reference. Figures 2a to 2c The light-emitting element described is an LED. For example, the first to third light-emitting elements LEDa, LEDb and LEDc include a first electrode layer (e.g., which will be described later) Figure 5 The first electrode layer E1), and the intermediate layer disposed on the first electrode layer (e.g., Figure 5 The first electrode layer (ML) and the second electrode layer (E2) disposed on the intermediate layer. In an embodiment, the first electrode layer can act as... Figures 2a to 2c The anode, and the second electrode layer E2 can act as... Figures 2a to 2c The cathode.

[0149] In an embodiment, the first electrode layer E1 may include first electrodes E1a, E1b, and E1c, which will be described later (see Figure 7 Specifically, the first electrode layer E1 may include a first electrode E1a of the first light-emitting element LEDa, a first electrode E1b of the second light-emitting element LEDb, and a first electrode E1c of the third light-emitting element LEDc. (See later...) Figure 7 This will be described in more detail.

[0150] In this embodiment, the second electrode layer E2 can be separated (or disconnected) by the separator SPR into second electrodes E2a, E2b, and E2c. Specifically, the second electrode layer E2 can be separated (or disconnected) into the second electrode E2a of the first light-emitting element LEDa, the second electrode E2b of the second light-emitting element LEDb, and the second electrode E2c of the third light-emitting element LEDc, and the second electrodes E2a, E2b, and E2c can be electrically independent of each other. This will be described in more detail later.

[0151] In other words, the first light-emitting element LEDa may include a first electrode E1a that acts as the anode (see...). Figure 7 The second light-emitting element LEDb may include a first electrode E1b (see [reference]) and a second electrode E2a that acts as the cathode. Figure 7 The third light-emitting element LEDc may include a first electrode E1c (see [reference]) and a second electrode E2b that acts as the cathode, and may also include a first electrode E1c that acts as the anode. Figure 7 ) and the second electrode E2c, which acts as the cathode.

[0152] The first to third light-emitting elements LEDa, LEDb, and LEDc can emit light of different colors. For example, the first light-emitting element LEDa can emit red light, the second light-emitting element LEDb can emit green light, and the third light-emitting element LEDc can emit blue light. However, this disclosure is not limited thereto.

[0153] In an embodiment, the display device DD may include a first unit light-emitting area UEA1 and a second unit light-emitting area UEA2. The first unit light-emitting area UEA1 and the second unit light-emitting area UEA2 may be arranged in a matrix along a first direction DR1 and a second direction DR2. Although in Figure 3 Four unit light-emitting areas are shown, but this is not a limitation of this disclosure, and more unit light-emitting areas can be shown in the display area DA (see [reference]). Figure 1a and Figure 1b The elements are arranged in a matrix along the first direction DR1 and the second direction DR2.

[0154] The first to third light-emitting elements LEDa, LEDb, and LEDc can be arranged adjacent to each other in each of the first unit light-emitting region UEA1 and the second unit light-emitting region UEA2. For example, the first to third light-emitting regions EAa, EAb, and EAc that are adjacent to each other can be defined within each of the first unit light-emitting region UEA1 and the second unit light-emitting region UEA2, and the first to third light-emitting elements LEDa, LEDb, and LEDc can be respectively arranged in the first to third light-emitting regions EAa, EAb, and EAc.

[0155] The first to third luminescent regions EAa, EAb, and EAc can be defined by the pixel-limiting layer PDL (described later) (see Figure 5 The pixel opening is defined by the first to third light-emitting regions EAa, EAb, and EAc. That is, the first to third light-emitting regions EAa, EAb, and EAc can be areas where light-emitting elements emit light. For example, the first light-emitting element LEDa can be disposed in the first light-emitting region EAa, and the first light-emitting region EAa can be the area where the first light-emitting element LEDa emits light. Similarly, the second light-emitting element LEDb can be disposed in the second light-emitting region EAb, and the second light-emitting region EAb can be the area where the second light-emitting element LEDb emits light. Furthermore, the third light-emitting element LEDc can be disposed in the third light-emitting region EAc, and the third light-emitting region EAc can be the area where the third light-emitting element LEDc emits light.

[0156] In the embodiments, the first unit light-emitting area UEA1 and the second unit light-emitting area UEA2 can be distinguished based on the arrangement of the first to third light-emitting elements LEDa, LEDb, and LEDc (or the arrangement of the first to third light-emitting areas EAa, EAb, and EAc). That is, the positions of the first to third light-emitting elements LEDa, LEDb, and LEDc (or the first to third light-emitting areas EAa, EAb, and EAc) relative to each other can be the same in each first unit light-emitting area UEA1, and the positions of the first to third light-emitting elements LEDa, LEDb, and LEDc (or the first to third light-emitting areas EAa, EAb, and EAc) relative to each other can be the same in each second unit light-emitting area UEA2.

[0157] like Figure 3 As shown, in the embodiment, the first unit light-emitting area UEA1 and the second unit light-emitting area UEA2 can be arranged alternately along the first direction DR1 (i.e., the row direction) and the second direction DR2 (i.e., the column direction). However, this disclosure is not limited to this, and the number of different unit light-emitting areas included in the display device DD or the arrangement relationship between the unit light-emitting areas can vary according to the embodiment.

[0158] At the same time, Figure 3 and Figure 4 In the diagram, the first to third luminescent regions EAa, EAb, and EAc are shown arranged in an S-stripe pattern. However, this disclosure is not limited to this, and the arrangement of the first to third luminescent regions EAa, EAb, and EAc can be varied according to embodiments.

[0159] The first to third light-emitting elements LEDa, LEDb, and LEDc can be connected to the first to third pixel driving circuit sections PCa, PCb, and PCc, respectively. For example, the first light-emitting element LEDa can be connected to the first pixel driving circuit section PCa, the second light-emitting element LEDb can be connected to the second pixel driving circuit section PCb, and the third light-emitting element LEDc can be connected to the third pixel driving circuit section PCc. Accordingly, the first pixel driving circuit section PCa and the first light-emitting element LEDa can form a pixel, the second pixel driving circuit section PCb and the second light-emitting element LEDb can form a pixel, and the third pixel driving circuit section PCc and the third light-emitting element LEDc can form a pixel.

[0160] In the following text, it will be referred to as Figure 4The connection relationships between the first to third light-emitting elements LEDa, LEDb, and LEDc and the first to third pixel driving circuit sections PCa, PCb, and PCc are described in more detail, centered on the first unit light-emitting region UEA1. The following description of the connection relationships between the first to third light-emitting elements LEDa, LEDb, and LEDc and the first to third pixel driving circuit sections PCa, PCb, and PCc can be applied to all unit light-emitting regions.

[0161] As described above, the display device DD may include first to third connecting electrodes CEa, CEb, and CEc, and first to third connecting patterns CNPa, CNPb, and CNPc. The first connecting electrode CEa and the first connecting pattern CNPa can connect the first light-emitting element LEDa and the first pixel driving circuit PCa, the second connecting electrode CEb and the second connecting pattern CNPb can connect the second light-emitting element LEDb and the second pixel driving circuit PCb, and the third connecting electrode CEc and the third connecting pattern CNPc can connect the third light-emitting element LEDc to the third pixel driving circuit PCc.

[0162] The first to third connecting electrodes CEa, CEb, and CEc can comprise conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, and transparent conductive oxides. Examples of conductive materials that can be used for the first to third connecting electrodes CEa, CEb, and CEc include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), alloys containing aluminum (Al), alloys containing silver (Ag), and other materials. Alloys containing copper (Cu), alloys containing molybdenum (Mo), aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), tin oxide (SnO), gallium oxide (GaO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc oxide (ZnO), indium oxide (InO), and aluminum zinc oxide (AZO), etc. These can be used individually or in combination. In embodiments, the first to third connecting electrodes CEa, CEb, and CEc can have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0163] In embodiments, the first to third connection patterns CNPa, CNPb, and CNPc may comprise transparent conductive oxides. Examples of transparent conductive oxides that can be used as the first to third connection patterns CNPa, CNPb, and CNPc may include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc oxide (ZnO), indium oxide (InO), tin oxide (SnO), gallium oxide (GaO), and aluminum zinc oxide (AZO), etc. These can be used individually or in combination with each other.

[0164] However, this disclosure is not limited thereto, and the first to third connection patterns CNPa, CNPb, and CNPc may include conductive materials such as metals, alloys, and conductive metal nitrides. Examples of conductive materials that can be used for the first to third connection patterns CNPa, CNPb, and CNPc may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), alloys containing aluminum (Al), alloys containing silver (Ag), alloys containing copper (Cu), alloys containing molybdenum (Mo), aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), and tantalum nitride (TaN). These can be used individually or in combination with each other.

[0165] In the embodiments, the first to third connection patterns CNPa, CNPb and CNPc can have a single-layer structure or a multi-layer structure in which multiple conductive layers are stacked.

[0166] The first connecting electrode CEa may include a first circuit connecting portion CPa and a first light-emitting connecting portion CNa.

[0167] The first circuit connection portion CPa may be the portion of the first connection electrode CEa that is connected to the first pixel driving circuit section PCa. Specifically, the first circuit connection portion CPa may be the first transistor TR1 (see [link to transistor]) that is connected to the first pixel driving circuit section PCa from the first connection electrode CEa. Figure 5 The position of the first circuit connection portion CPa can correspond to the position of the first transistor TR1 of the first pixel driving circuit portion PCa. Specifically, the position of the first circuit connection portion CPa can correspond to the position of the transistor TR1 extending through the insulating layer. Figure 5 The position of the contact hole in the fifth insulating layer (IL5) corresponds to that of the first connecting electrode CEa to allow the first transistor TR1 of the first pixel driving circuit section PCa to contact the first connecting electrode CEa.

[0168] The first light-emitting connection portion CNa can be the portion of the first connection electrode CEa that is connected to the first connection pattern CNPa. Specifically, the first light-emitting connection portion CNa can be the portion of the first connection electrode CEa that is connected to the sixth insulating layer IL6 (see...). Figure 5 ) and pixel-limited layer PDL (see Figure 5 The portion of the first light-emitting connection portion CNa is exposed to connect to the first connection pattern CNa. Accordingly, the position of the first light-emitting connection portion CNa may correspond to the position of the opening in the sixth insulating layer IL6 aligned with the opening in the pixel defining layer PDL. In a plan view, the first light-emitting connection portion CNa may not overlap with the first light-emitting region EAa. For example, in a plan view, the first light-emitting connection portion CNa may be positioned between the first light-emitting region EAa and the separator SPR (e.g., see...). Figure 4 )between.

[0169] The first connection pattern CNPa can be connected to the first connection electrode CEa. For example, the first connection pattern CNPa can contact the first light-emitting connection portion CNa of the first connection electrode CEa. However, this disclosure is not limited to this specific structure, and the first connection pattern CNPa may not directly contact the first connection electrode CEa. For example, the first connection pattern CNPa can contact the capping layer that contacts the first light-emitting connection portion CNa of the first connection electrode CEa, and can be connected to the first light-emitting connection portion CNa of the first connection electrode CEa through the capping layer. The capping layer may include a conductive material. For example, the capping layer may be connected to the first electrode layer E1, which will be described later (see...). Figure 5 They are formed simultaneously and can include the same materials.

[0170] In a plan view, the first connecting pattern CNPa may not overlap with the first light-emitting region EAa. In an embodiment, in a plan view, the first connecting pattern CNPa may surround at least a portion of the first light-emitting region EAa. For example, in a plan view, the first connecting pattern CNPa may have a closed-loop shape that completely surrounds the first light-emitting region EAa. However, this disclosure is not limited to this.

[0171] The second electrode E2a of the first light-emitting element LEDa can be connected to the first connection pattern CNPa. Specifically, the second electrode E2a of the first light-emitting element LEDa can contact the first connection pattern CNPa. Accordingly, the first connection pattern CNPa can connect the first connection electrode CEa and the second electrode E2a of the first light-emitting element LEDa. As a result, the second electrode E2a of the first light-emitting element LEDa can be connected to the first pixel driving circuit PCa through the first connection electrode CEa and the first connection pattern CNPa.

[0172] In an embodiment, the planar contour of the area where the second electrode E2a of the first light-emitting element LEDa and the first connecting pattern CNPa contact can be substantially the same as or similar to the planar contour of the edge of the first connecting pattern CNPa. For example, if the first connecting pattern CNPa has a closed shape that completely surrounds the first light-emitting region EAa in a planar view, then the area where the first connecting pattern CNPa contacts the second electrode E2a of the first light-emitting element LEDa can also have a closed shape in a planar view. That is, the first connecting pattern CNPa and the second electrode E2a of the first light-emitting element LEDa can contact each other at a position that does not overlap with the first light-emitting region EAa. Therefore, without reducing the light-emitting area of ​​the first light-emitting region EAa, the first pixel driving circuit PCa and the second electrode E2a of the first light-emitting element LEDa can be connected through the first connecting pattern CNPa and the first connecting electrode CEa.

[0173] The second connecting electrode CEb may include a second circuit connecting portion CPb and a second light-emitting connecting portion CNb.

[0174] The second circuit connection portion CPb can be the part of the second connection electrode CEb that is connected to the second pixel driving circuit section PCb. Specifically, the second circuit connection portion CPb can be the first transistor TR1 (see [link to transistor]) that is connected to the second pixel driving circuit section PCb of the second connection electrode CEb. Figure 5 The position of the second circuit connection portion CPb can correspond to the position of the first transistor TR1 of the second pixel driving circuit portion PCb. Specifically, the position of the second circuit connection portion CPb can correspond to the position of the transistor TR1 extending through the insulating layer. Figure 5 The position of the contact hole in the fifth insulating layer (IL5) corresponds to the position of the second connecting electrode CEb contacting the first transistor TR1 of the second pixel driving circuit PCb.

[0175] The second light-emitting connection portion CNb can be the portion of the second connection electrode CEb connected to the second connection pattern CNPb. Specifically, the second light-emitting connection portion CNb can be the portion of the second connection electrode CEb connected to the sixth insulating layer IL6 (see...). Figure 5 ) and pixel-limited layer PDL (see Figure 5 The portion of the second light-emitting connection portion CNb is exposed to connect to the second connection pattern CNPb. Accordingly, the position of the second light-emitting connection portion CNb can correspond to the position of the opening in the sixth insulating layer IL6 that aligns with the opening in the pixel defining layer PDL. In a plan view, the second light-emitting connection portion CNb may not overlap with the second light-emitting region EAb. For example, in a plan view, the second light-emitting connection portion CNb may be positioned between the second light-emitting region EAb and the separator SPR.

[0176] In an embodiment, the second connecting electrode CEb may be spaced apart from the first connecting electrode CEa in a plan view. In other words, the first connecting electrode CEa and the second connecting electrode CEb may be different electrodes.

[0177] The second connection pattern CNPb can be connected to the second connection electrode CEb. For example, the second connection pattern CNPb can contact the second light-emitting connection portion CNb of the second connection electrode CEb. However, this disclosure is not limited to this exact structure, and the second connection pattern CNPb may not directly contact the second connection electrode CEb. For example, the second connection pattern CNPb can contact the capping layer that contacts the second light-emitting connection portion CNb of the second connection electrode CEb, and can be connected to the second light-emitting connection portion CNb of the second connection electrode CEb through the capping layer. The capping layer may include a conductive material. For example, the capping layer may be connected to the first electrode layer E1, which will be described later (see...). Figure 5 They are formed simultaneously and can include the same materials.

[0178] In a plan view, the second connecting pattern CNPb may not overlap with the second light-emitting region EAb. In an embodiment, in a plan view, the second connecting pattern CNPb may surround at least a portion of the second light-emitting region EAb. For example, in a plan view, the second connecting pattern CNPb may have a closed-loop shape that completely surrounds the second light-emitting region EAb. However, this disclosure is not limited to this.

[0179] In an embodiment, the second connection pattern CNPb may be spaced apart from the first connection pattern CNPa. In other words, the first connection pattern CNPa and the second connection pattern CNPb may be different patterns.

[0180] The second electrode E2b of the second light-emitting element LEDb can be connected to the second connection pattern CNPb. Specifically, the second electrode E2b of the second light-emitting element LEDb can contact the second connection pattern CNPb. Accordingly, the second connection pattern CNPb can connect the second connection electrode CEb and the second electrode E2b of the second light-emitting element LEDb. As a result, the second electrode E2b of the second light-emitting element LEDb can be connected to the second pixel driving circuit PCb through the second connection electrode CEb and the second connection pattern CNPb.

[0181] In an embodiment, the planar contour of the area where the second connecting pattern CNPb and the second electrode E2b of the second light-emitting element LEDb contact can be substantially the same as or similar to the planar contour of the edge of the second connecting pattern CNPb. For example, if the second connecting pattern CNPb has a closed shape that completely surrounds the second light-emitting region EAb in a planar view, then the area where the second connecting pattern CNPb and the second electrode E2b of the second light-emitting element LEDb contact can also have a closed shape in a planar view. That is, the second connecting pattern CNPb and the second electrode E2b of the second light-emitting element LEDb can contact each other at a position that does not overlap with the second light-emitting region EAb. Therefore, without reducing the light-emitting area of ​​the second light-emitting region EAb, the second pixel driving circuit PCb and the second electrode E2b of the second light-emitting element LEDb can be connected through the second connecting pattern CNPb and the second connecting electrode CEb.

[0182] The third connecting electrode CEc may include a third circuit connecting portion CPC and a third light-emitting connecting portion CNc.

[0183] The third circuit connection portion CPc can be the part of the third connection electrode CEc that is connected to the third pixel driving circuit section PCc. Specifically, the third circuit connection portion CPc can be the first transistor TR1 (see [link to third pixel driving circuit section PCc]) that is connected to the third connection electrode CEc. Figure 5 The position of the third circuit connection portion CPC can correspond to the position of the first transistor TR1 of the third pixel driving circuit portion PCc. Specifically, the position of the third circuit connection portion CPC can correspond to the position of the transistor TR1 extending through the insulating layer. Figure 5 The position of the contact hole in the fifth insulating layer (IL5) corresponds to that of the third connection electrode CEc, so as to allow the first transistor TR1 of the third pixel drive circuit PCc to contact the third pixel drive circuit PCc.

[0184] The third light-emitting connection portion CNc can be the portion of the third connection electrode CEc that connects to the third connection pattern CNPc. Specifically, the third light-emitting connection portion CNc can be the portion of the third connection electrode CEc that connects to the sixth insulating layer IL6 (see...). Figure 5 ) and pixel-limited layer PDL (see Figure 5 The portion of the third light-emitting connection portion CNc is exposed to connect to the third connection pattern CNPc. Accordingly, the position of the third light-emitting connection portion CNc can correspond to the position of the opening in the sixth insulating layer IL6 that aligns with the opening in the pixel defining layer PDL. In a plan view, the third light-emitting connection portion CNc may not overlap with the third light-emitting region EAc. For example, in a plan view, the third light-emitting connection portion CNc may be positioned between the third light-emitting region EAc and the separator SPR.

[0185] In an embodiment, the third connecting electrode CEc may be spaced apart from the first connecting electrode CEa and the second connecting electrode CEb in a plan view. In other words, the first connecting electrode CEa, the second connecting electrode CEb, and the third connecting electrode CEc may be different electrodes.

[0186] The third connection pattern CNPc can be connected to the third connection electrode CEc. For example, the third connection pattern CNPc can contact the third light-emitting connection portion CNc of the third connection electrode CEc. However, this disclosure is not limited to this exact structure, and the third connection pattern CNPc may not directly contact the third connection electrode CEc. For example, the third connection pattern CNPc can contact a capping layer that contacts the third light-emitting connection portion CNc of the third connection electrode CEc, and can be connected to the third light-emitting connection portion CNc of the third connection electrode CEc through the capping layer. The capping layer may include a conductive material. For example, the capping layer may be connected to the first electrode layer E1 (see below) which will be described later. Figure 5 They are formed simultaneously and can include the same materials.

[0187] In a plan view, the third connecting pattern CNPc may not overlap with the third light-emitting region EAc. In an embodiment, in a plan view, the third connecting pattern CNPc may surround at least a portion of the third light-emitting region EAc. For example, in a plan view, the third connecting pattern CNPc may have a closed shape that completely surrounds the third light-emitting region EAc. However, this disclosure is not limited to this.

[0188] In an embodiment, the third connection pattern CNPc may be spaced apart from the first connection pattern CNPa and the second connection pattern CNPb. In other words, the first connection pattern CNPa, the second connection pattern CNPb, and the third connection pattern CNPc may be different patterns.

[0189] The second electrode E2c of the third light-emitting element LEDc can be connected to the third connection pattern CNPc. Specifically, the second electrode E2c of the third light-emitting element LEDc can contact the third connection pattern CNPc. Accordingly, the third connection pattern CNPc can connect the third connection electrode CEc and the second electrode E2c of the third light-emitting element LEDc. As a result, the second electrode E2c of the third light-emitting element LEDc can be connected to the third pixel driving circuit PCc through the third connection electrode CEc and the third connection pattern CNPc.

[0190] In an embodiment, the planar contour of the area where the third connecting pattern CNPc and the second electrode E2c of the third light-emitting element LEDc contact can be substantially the same as or similar to the planar contour of the edge of the third connecting pattern CNPc. For example, if the third connecting pattern CNPc has a closed shape that completely surrounds the third light-emitting region EAC in a planar view, then the area where the third connecting pattern CNPc and the second electrode E2c of the third light-emitting element LEDc contact can also have a closed shape in a planar view. That is, the third connecting pattern CNPc and the second electrode E2c of the third light-emitting element LEDc can contact each other at a position that does not overlap with the third light-emitting region EAC. Therefore, without reducing the light-emitting area of ​​the third light-emitting region EAC, the third pixel driving circuit PCc and the second electrode E2c of the third light-emitting element LEDc can be connected through the third connecting pattern CNPc and the third connecting electrode CEc.

[0191] According to embodiments of this disclosure, the second electrodes E2a, E2b, and E2c can be connected to the first to third connection patterns CNPa, CNPb, and CNPc respectively at positions that do not overlap with the first to third light-emitting regions EAa, EAb, and EAc. Accordingly, the second electrodes E2a, E2b, and E2c can contact the first to third connection patterns CNPa, CNPb, and CNPc respectively without reducing the light-emitting area.

[0192] Furthermore, according to embodiments of this disclosure, the second electrodes E2a, E2b, and E2c can be connected to the first to third pixel driving circuit sections PCa, PCb, and PCc respectively via the first to third connecting electrodes CEa, CEb, and CEc and the first to third connecting patterns CNPa, CNPb, and CNPc. Accordingly, in the design of the first to third pixel driving circuit sections PCa, PCb, and PCc, the limitations caused by the position, shape, and size of the first to third light-emitting regions EAa, EAb, and EAc can be reduced. For example, even if at least some of the first to third circuit connecting portions CPa, CPb, and CPc overlap with the first to third light-emitting regions EAa, EAb, and EAc, the second electrodes E2a, E2b, and E2c can still be easily connected to the first to third pixel driving circuit sections PCa, PCb, and PCc via the first to third connecting electrodes CEa, CEb, and CEc and the first to third connecting patterns CNPa, CNPb, and CNPc. Therefore, the shape and arrangement of the first to third pixel driving circuit sections PCa, PCb, and PCc can be designed independently of the position, shape, and size of the first to third light-emitting regions EAa, EAb, and EAc. Accordingly, the design freedom of the first to third pixel driving circuit sections PCa, PCb, and PCc can be relatively high.

[0193] In this embodiment, regardless of the position, shape, and size of the first to third light-emitting regions EAa, EAb, and EAC, the first to third pixel driving circuit sections PCa, PCb, and PCc can be designed to be identical to each other. Furthermore, as described above, the position of the first circuit connection portion CPa can be the same as the first transistor TR1 of the first pixel driving circuit section PCa (see...). Figure 5 Corresponding to the positions of the first, second, and third circuit connection portions, CPb and CPc, the second circuit connection portion CPb can correspond to the position of the first transistor TR1 of the third pixel driving circuit portion PCc. Therefore, if the first to third pixel driving circuit portions PCa, PCb, and PCc are formed to have substantially the same size and are arranged along the first direction DR1, the positions of the first circuit connection portion CPb, the second circuit connection portion CPb, and the third circuit connection portion CPc can be arranged along the first direction DR1.

[0194] At the same time, such as Figure 3 As shown, for each first unit light-emitting region UEA1, the shape or arrangement of each of the corresponding first to third connecting electrodes CEa, CEb, and CEc, as well as the arrangement relationship between the first to third connecting electrodes CEa, CEb, and CEc, can be the same. Similarly, for each second unit light-emitting region UEA2, the shape or arrangement of each of the corresponding first to third connecting electrodes CEa, CEb, and CEc, as well as the arrangement relationship between the first to third connecting electrodes CEa, CEb, and CEc, can be the same.

[0195] Furthermore, for each first unit light-emitting region UEA1, the shape or arrangement of each of the first connecting pattern CNPa, the second connecting pattern CNPb, and the third connecting pattern CNPc, as well as the arrangement relationship between the first connecting pattern CNPa, the second connecting pattern CNPb, and the third connecting pattern CNPc, can be the same. Similarly, for each second unit light-emitting region UEA2, the shape or arrangement of each of the first connecting pattern CNPa, the second connecting pattern CNPb, and the third connecting pattern CNPc, as well as the arrangement relationship between the first connecting pattern CNPa, the second connecting pattern CNPb, and the third connecting pattern CNPc, can be the same.

[0196] As described above, the display device DD may include a separator SPR.

[0197] The separator SPR can be set in the pixel-limiting layer PDL (see...) Figure 5The spacer SPR is applied to the first to third connection patterns CNPa, CNPb, and CNPc. In embodiments, the spacer SPR may comprise an organic insulating material. For example, the spacer SPR may comprise a photosensitive resin (e.g., photoresist). However, this disclosure is not limited thereto.

[0198] In the plan view, the separator SPR may overlap with the first to third connection patterns CNPa, CNPb, and CNPc. Specifically, the separator SPR may cover a portion of the first to third connection patterns CNPa, CNPb, and CNPc, as well as adjacent connection patterns. That is, in the plan view, at least a portion of the separator SPR may extend along the edges of the first to third connection patterns CNPa, CNPb, and CNPc. Correspondingly, the areas of the second electrodes E2a, E2b, and E2c that contact each other with the first to third connection patterns CNPa, CNPb, and CNPc may be adjacent to or overlap with the separator SPR in the plan view.

[0199] The second electrode layer E2 can be separated (or disconnected) by the separator SPR into second electrodes E2a, E2b, and E2c. That is, the second electrode E2a of the first light-emitting element LEDa, the second electrode E2b of the second light-emitting element LEDb, and the second electrode E2c of the third light-emitting element LEDc can be electrically independent of each other through the separator SPR.

[0200] The separator SPR can define first to third opening regions OA1, OA2, and OA3, respectively, corresponding to the second electrodes E2a, E2b, and E2c. For example, the separator SPR can have a grid structure surrounding the second electrodes E2a, E2b, and E2c in a plan view. The second electrode E2a of the first light-emitting element LEDa can be disposed in the first opening region OA1 of the separator SPR, the second electrode E2b of the second light-emitting element LEDb can be disposed in the second opening region OA2 of the separator SPR, and the second electrode E2c of the third light-emitting element LEDc can be disposed in the third opening region OA3 of the separator SPR.

[0201] In an embodiment, the outline of the first opening region OA1 in the plan view may be substantially the same as the outline of the second electrode E2a of the first light-emitting element LEDa, the outline of the second opening region OA2 in the plan view may be substantially the same as the outline of the second electrode E2b of the second light-emitting element LEDb, and the outline of the third opening region OA3 in the plan view may be substantially the same as the outline of the second electrode E2c of the third light-emitting element LEDc.

[0202] The first to third opening regions OA1, OA2, and OA3 of the separator SPR can correspond to the first to third connecting patterns CNPa, CNPb, and CNPc, respectively. For example, the first connecting pattern CNPa can overlap with the first opening region OA1, the second connecting pattern CNPb can overlap with the second opening region OA2, and the third connecting pattern CNPc can overlap with the third opening region OA3.

[0203] In the following text, reference will be based on the first luminescent region EAa. Figure 5 The cross-sectional structure of the display device DD is described in more detail below. This description of the cross-sectional structure of the display device DD can be applied to all light-emitting areas.

[0204] Further reference Figure 5 In an embodiment, the display device DD may include a substrate SUB, a first lower conductive layer BML1, a second lower conductive layer BML2, a first transistor TR1, a second transistor TR2, a first capacitor CAP1, a second capacitor CAP2, a first connecting electrode CEa, first to sixth insulating layers IL1, IL2, IL3, IL4, IL5 and IL6, a pixel defining layer PDL, a first connecting pattern CNPa, a first light-emitting element LEDa, a separator SPR, a first dummy layer DP1, a second dummy layer DP2 and an encapsulation layer ENC.

[0205] The first transistor TR1 may include a first active pattern AP1, a first gate electrode GE1, a first contact electrode SE1, and a second contact electrode DE1. The second transistor TR2 may include a second active pattern AP2, a second gate electrode GE2, a third contact electrode SE2, and a fourth contact electrode DE2. The first capacitor CAP1 may include a first capacitor electrode CPE1 and a second capacitor electrode CPE2. The second capacitor CAP2 may include a first capacitor electrode CPE1 and a third capacitor electrode CPE3. The first light-emitting element LEDa may include a first electrode E1a, an intermediate layer ML, and a second electrode E2a.

[0206] As described above, the first transistor TR1, the second transistor TR2, the first capacitor CAP1, and the second capacitor CAP2 may be components included in the first pixel driving circuit section PCa.

[0207] The substrate SUB can form the base of the display device DD. In embodiments, examples of materials that can be used as the substrate SUB include glass, quartz, silicon, or polymers. These can be used individually or in combination with each other. Furthermore, the substrate SUB can have a single-layer structure or a multi-layer structure comprising multiple stacked layers of different materials.

[0208] The first lower conductive layer BML1, the second lower conductive layer BML2, and the third capacitor electrode CPE3 can be disposed on the substrate SUB. The first lower conductive layer BML1, the second lower conductive layer BML2, and the third capacitor electrode CPE3 can include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, and transparent conductive oxides.

[0209] The first insulating layer IL1 may cover the first lower conductive layer BML1, the second lower conductive layer BML2, and the third capacitor electrode CPE3, and may be disposed on the substrate SUB. The first insulating layer IL1 can prevent metal atoms or impurities from diffusing from the substrate SUB into the first active pattern AP1 and / or the second active pattern AP2. The first insulating layer IL1 may include an insulating material. Examples of insulating materials that can be used as the first insulating layer IL1 may include silicon oxide, silicon nitride, and silicon oxynitride. These can be used individually or in combination with each other.

[0210] A first active pattern AP1 may be disposed on a first insulating layer IL1. In an embodiment, the first active pattern AP1 may overlap with a first lower conductive layer BML1. The first active pattern AP1 may include an oxide semiconductor material, a silicon semiconductor material, and / or an organic semiconductor material. The first active pattern AP1 may include a first contact region S1, a second contact region D1, and a first channel region CH1 located between the first contact region S1 and the second contact region D1. The first contact region S1 and the second contact region D1 may have a higher conductivity than the first channel region CH1.

[0211] A second active pattern AP2 may be disposed on the first insulating layer IL1. In an embodiment, the second active pattern AP2 may overlap with the second lower conductive layer BML2. The second active pattern AP2 may include an oxide semiconductor material, a silicon semiconductor material, and / or an organic semiconductor material. The second active pattern AP2 may include a third contact region S2, a fourth contact region D2, and a second channel region CH2 located between the third contact region S2 and the fourth contact region D2. The third contact region S2 and the fourth contact region D2 may have a higher conductivity than the second channel region CH2.

[0212] In embodiments, the first active pattern AP1 and the second active pattern AP2 may comprise oxide semiconductor materials. Examples of oxide semiconductor materials that can be used as the first active pattern AP1 and the second active pattern AP2 may include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium tin zinc oxide (ITZO), etc. These can be used individually or in combination with each other. However, this disclosure is not limited thereto, and the first active pattern AP1 and the second active pattern AP2 may comprise different materials.

[0213] At the same time, Figure 5In the diagram, the first active pattern AP1 and the second active pattern AP2 are shown as being disposed in the same layer. However, this disclosure is not limited to this, and the first active pattern AP1 and the second active pattern AP2 may be disposed in different layers.

[0214] The second insulating layer IL2 may cover the first active pattern AP1 and the second active pattern AP2, and may be disposed on the first insulating layer IL1. The second insulating layer ILD2 may include an insulating material. Examples of insulating materials that can be used as the second insulating layer IL2 may include silicon oxide, silicon nitride, and silicon oxynitride. These can be used individually or in combination with each other.

[0215] A first gate electrode GE1 may be disposed on the second insulating layer IL2. The first gate electrode GE1 may overlap with the first channel region CH1 of the first active pattern AP1. The first gate electrode GE1 may comprise a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. Although not shown, in an embodiment, the first gate electrode GE1 may contact the first lower conductive layer BML1.

[0216] The second gate electrode GE2 may be disposed on the second insulating layer IL2. The second gate electrode GE2 may overlap with the second channel region CH2 of the second active pattern AP2. The second gate electrode GE2 may comprise a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. Although not shown, in an embodiment, the second gate electrode GE2 may contact the second lower conductive layer BML2.

[0217] A first capacitor electrode CPE1 may be disposed on a second insulating layer IL2. The first capacitor electrode CPE1 may overlap with a third capacitor electrode CPE3. The first capacitor electrode CPE1 and the third capacitor electrode CPE3 may form a second capacitor CAP2. The first capacitor electrode CPE1 may comprise a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide.

[0218] The third insulating layer IL3 may cover the first gate electrode GE1, the second gate electrode GE2, and the first capacitor electrode CPE1, and may be disposed on the second insulating layer IL2. The third insulating layer IL3 may include an insulating material. Examples of insulating materials that can be used as the third insulating layer IL3 may include silicon oxide, silicon nitride, and silicon oxynitride. These can be used individually or in combination with each other.

[0219] The second capacitor electrode CPE2 can be disposed on the third insulating layer IL3. The second capacitor electrode CPE2 can overlap with the first capacitor electrode CPE1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 can form the first capacitor CAP1. The second capacitor electrode CPE2 can include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, and transparent conductive oxides.

[0220] The fourth insulating layer IL4 may cover the second capacitor electrode CPE2 and may be disposed on the third insulating layer IL3. The fourth insulating layer IL4 may include an insulating material. Examples of insulating materials that can be used as the fourth insulating layer IL4 may include silicon oxide, silicon nitride, and silicon oxynitride. These can be used individually or in combination with each other.

[0221] The first to fourth contact electrodes SE1, DE1, SE2, and DE2 can be disposed on the fourth insulating layer IL4. The first contact electrode SE1 can contact the first contact area S1 of the first active pattern AP1, the second contact electrode DE1 can contact the second contact area D1 of the first active pattern AP1, the third contact electrode SE2 can contact the third contact area S2 of the second active pattern AP2, and the fourth contact electrode DE2 can contact the fourth contact area D2 of the second active pattern AP2. The first to fourth contact electrodes SE1, DE1, SE2, and DE2 can comprise conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, and transparent conductive oxides.

[0222] In an embodiment, the first contact electrode SE1 may contact the first lower conductive layer BML1, and the third contact electrode SE2 may contact the second lower conductive layer BML2. However, this disclosure is not limited to this. For example, if the first gate electrode GE1 contacts the first lower conductive layer BML1, then the first contact electrode SE1 may not contact the first lower conductive layer BML1. Furthermore, if the second gate electrode GE2 contacts the second lower conductive layer BML2, then the third contact electrode SE2 may not contact the second lower conductive layer BML2.

[0223] The fifth insulating layer IL5 may cover the first to fourth contact electrodes SE1, DE1, SE2, and DE2, and may be disposed on the fourth insulating layer IL4. The fifth insulating layer IL5 may include an insulating material. For example, the fifth insulating layer IL5 may include an organic insulating material. Examples of organic insulating materials that can be used as the fifth insulating layer IL5 include photoresists, polypropylene resins, polyimide resins, polyamide resins, siloxane resins, acrylic resins, and epoxy resins. These can be used individually or in combination with each other.

[0224] The first connection electrode CEa can be disposed on the fifth insulating layer IL5. As described above, the first connection electrode CEa can be connected to the first transistor TR1. Specifically, the first connection electrode CEa can contact the first transistor TR1 through a contact hole CNT extending through the fifth insulating layer IL5. Accordingly, the position of the first circuit connection portion CPa can correspond to the position of the contact hole CNT. The first connection electrode CEa can include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, and transparent conductive oxides. In embodiments, the first connection electrode CEa can have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0225] As described above, the first transistor TR1 can be a transistor connected to the light-emitting element via a connection electrode and a connection pattern. For example, if the first pixel driving circuit PCa is... Figure 2a In the pixel driving circuit section PC, the first transistor TR1 can be Figure 2a The first transistor T1. Additionally, if the first pixel driving circuit PCa is... Figure 2b In the pixel driving circuit PC', the first transistor TR1 can be Figure 2b The fifth transistor T5. Additionally, if the first pixel drive circuit PCa is... Figure 2c If the pixel driving circuit PC'' is a pixel driving circuit, then the first transistor TR1 can be a pixel driving circuit PC''. Figure 2c The fifth transistor, T5.

[0226] The sixth insulating layer IL6 may partially cover the first connecting electrode CEa and may be disposed on the fifth insulating layer IL5. That is, the sixth insulating layer IL6 may define a first sub-opening SO1 above at least a portion of the first connecting electrode CEa. The sixth insulating layer IL6 may include an insulating material. For example, the sixth insulating layer IL6 may include an organic insulating material. Examples of organic insulating materials that can be used as the sixth insulating layer IL6 include photoresists, polypropylene resins, polyimide resins, polyamide resins, siloxane resins, acrylic resins, and epoxy resins. These can be used alone or in combination with each other.

[0227] The first electrode layer E1 can be disposed on the sixth insulating layer IL6. As described above, the first electrode layer E1 can include the first electrode E1a of the first light-emitting element LEDa. That is, the first electrode E1a can be disposed on the sixth insulating layer IL6. The first electrode layer E1 (i.e., the first electrode E1a) can include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, and transparent conductive oxides. The structure of the first electrode layer E1 will be described in more detail later.

[0228] A pixel defining layer (PDL) can be disposed on a sixth insulating layer (IL6) and a first electrode layer (E1, i.e., first electrode E1a). The pixel defining layer (PDL) can be formed of an insulating material. The pixel defining layer (PDL) can define a pixel opening that exposes at least a portion of the first electrode layer (E1, i.e., first electrode E1a). A first light-emitting region (EAa) can be defined by the pixel opening. Simultaneously, the pixel defining layer (PDL) can further define a second sub-opening (SO2) aligned with a first sub-opening (SO1) of the sixth insulating layer (IL6). The second sub-opening (SO2) can be above the first sub-opening (SO1), such that the first sub-opening (SO1) and the second sub-opening (SO2) can be connected to each other to form a continuous, deeper opening. That is, an opening (OP) in which the first sub-opening (SO1) and the second sub-opening (SO2) are connected can be defined, and at least a portion of the first connecting electrode (CEa) is at the bottom of the opening (OP).

[0229] A first connection pattern CNPa can be disposed on a first connection electrode CEa, a sixth insulating layer IL6, and a pixel defining layer PDL. As described above, the first connection pattern CNPa can be connected to the first connection electrode CEa. Specifically, the first connection pattern CNPa can be connected to the first connection electrode CEa through an opening OP extending through the sixth insulating layer IL6 and the pixel defining layer PDL. Accordingly, the position of the first light-emitting connection portion CNa can correspond to the position of the opening OP. In an embodiment, the first connection pattern CNPa can include a transparent conductive oxide. However, this disclosure is not limited to this, and the first connection pattern CNPa can include conductive materials such as metals, alloys, conductive metal oxides, and conductive metal nitrides. In an embodiment, the first connection pattern CNPa can have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0230] The separator SPR can be disposed on the pixel-defining layer PDL and the first connection pattern CNPa. In a planar view, the separator SPR can overlap with the first connection pattern CNPa. For example, the separator SPR can cover a portion of the first connection pattern CNPa.

[0231] The separator SPR can have a cross-sectional shape in which the width of the upper portion is greater than the width of the lower portion. That is, the side surface of the separator SPR that connects the upper and lower surfaces of the separator SPR can have a tapered or inclined surface. In other words, at least a portion of the cross-section of the separator SPR can be trapezoidal.

[0232] In an embodiment, such as Figure 5 As shown, the side surface of the separator SPR can have multiple inclined surfaces. That is, the separator SPR can have a tapered structure. Accordingly, it is easier to separate (or disconnect) the second electrode layer E2 through the separator SPR.

[0233] An intermediate layer ML can be disposed on the first electrode layer E1, the pixel defining layer PDL, and the first connection pattern CNPa. A portion of the intermediate layer ML can be disposed within a pixel opening of the pixel defining layer PDL. In an embodiment, the intermediate layer ML may include a first functional layer comprising an organic material, a light-emitting layer disposed on the first functional layer and comprising a light-emitting material, and a second functional layer disposed on the light-emitting layer and comprising an organic material. For example, the first functional layer may include a hole injection layer and a hole transport layer, and the second functional layer may include an electron transport layer and an electron injection layer, etc.

[0234] A shaded area may exist around the separator SPR, which has an inclined side surface, making it difficult to deposit the intermediate layer ML. Accordingly, the intermediate layer ML in and / or around the shaded area may have a structure that is disconnected by the separator SPR. For example, the first and second functional layers included in the intermediate layer ML may have a structure that is disconnected to accommodate the separator SPR. Because the intermediate layer ML has a disconnected structure, it may not cover the entire first connection pattern CNPa. That is, the intermediate layer ML may expose a portion of the first connection pattern CNPa at a location adjacent to or overlapping with the separator SPR. Accordingly, the second electrode E2a of the first light-emitting element LEDa may contact the first connection pattern CNPa.

[0235] Simultaneously, the first dummy layer DP1 can be disposed on the separator SPR. The first dummy layer DP1 can be formed by having a structure in which the intermediate layer ML is broken by the separator SPR. That is, the first dummy layer DP1 can be formed in the same process as the intermediate layer ML. In an embodiment, the first dummy layer DP1 can be omitted.

[0236] The second electrode layer E2 (i.e., the second electrodes E2a, E2b, and E2c) can be disposed on the intermediate layer ML. The second electrode layer E2 (i.e., the second electrodes E2a, E2b, and E2c) can comprise conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, and transparent conductive oxides. In embodiments, the second electrode layer E2 (i.e., the second electrodes E2a, E2b, and E2c) can have a single-layer structure. However, this disclosure is not limited to this, and the second electrode layer E2 (i.e., the second electrodes E2a, E2b, and E2c) can have a multilayer structure in which multiple conductive layers are stacked. For example, the second electrode layer E2 (i.e., the second electrodes E2a, E2b, and E2c) can have a two-layer structure comprising a first sub-electrode layer including a metallic material and a second sub-electrode layer comprising a transparent conductive oxide disposed on the first sub-electrode layer.

[0237] Because the separator SPR has a tapered, sloping side surface, a shaded region exists around the separator SPR where it is difficult to deposit the second electrode layer E2. Accordingly, the second electrode layer E2 in and / or around the shaded region may be discontinuous around the separator SPR. For example, as... Figure 4 As shown, the second electrode layer E2 can be separated into a second electrode E2a of the first light-emitting element LEDa disposed in the first opening region OA1 of the separator SPR, a second electrode E2b of the second light-emitting element LEDb disposed in the second opening region OA2 of the separator SPR, and a second electrode E2c of the third light-emitting element LEDc disposed in the third opening region OA3 of the separator SPR. That is, the second electrodes E2a, E2b and E2c can be electrically independent of each other.

[0238] like Figure 5 As shown, the second electrode E2a of the first light-emitting element LEDa can be connected to the first connection pattern CNPa. Specifically, the second electrode E2a can contact the first connection pattern CNPa at a position adjacent to or overlapping with the separator SPR. For example, if the deposition angle of the deposition process used to form the second electrode layer E2 is set to be greater than the deposition angle of the deposition process used to form the intermediate layer ML, then the second electrode layer E2 (specifically, the second electrode E2a) can be formed to cover the side surface of the disconnected intermediate layer ML and contact the first connection pattern CNPa. As a result, the second electrode E2a can be connected to the first transistor TR1 through the first connection electrode CEa and the first connection pattern CNPa.

[0239] Simultaneously, the second dummy layer DP2 can be disposed on the separator SPR. Specifically, the second dummy layer DP2 can be disposed on the first dummy layer DP1. The second dummy layer DP2 can be formed by having a structure in which the second electrode layer E2 is separated (or disconnected) by the separator SPR. That is, the second dummy layer DP2 can be formed in the same process as the second electrode layer E2. In embodiments, the second dummy layer DP2 can be omitted.

[0240] The encapsulation layer ENC can be disposed on the second electrode layer E2. The encapsulation layer ENC can completely cover the second electrode layer E2, the connection patterns CNPa, CNPb and CNPc, the separator SPR, the first dummy layer DP1, and the second dummy layer DP2. In an embodiment, the encapsulation layer ENC may include a first inorganic encapsulation layer IEL1 containing inorganic insulating material, an organic encapsulation layer OEL disposed on the first inorganic encapsulation layer IEL1 and containing organic insulating material, and a second inorganic encapsulation layer IEL2 disposed on the organic encapsulation layer OEL and containing inorganic insulating material.

[0241] Although not shown, in embodiments, the touch sensing layer may be disposed on the encapsulation layer ENC. For example, the touch sensing layer may include a plurality of touch electrode arrays for capacitively detecting user actions, a touchpad portion, and a plurality of touch lines electrically connecting the touchpad portion and the touch electrode arrays. However, this disclosure is not limited thereto. Furthermore, in embodiments, the touch sensing layer may be omitted.

[0242] According to embodiments of this disclosure, the display device DD may include connecting electrodes CEa, CEb, and CEc, connecting patterns CNPa, CNPb, and CNPc, and separators SPR. Accordingly, a second electrode layer E2 (e.g., a cathode) disposed on the first electrode layer E1 (e.g., anode) can be easily connected to pixel driving circuit sections PCa, PCb, and PCc. The second electrode layer E2 disposed on the first electrode layer E1 can be connected to the driving transistors (e.g., ...) of the pixel driving circuit sections PCa, PCb, and PCc via the connecting electrodes CEa, CEb, and CEc and the connecting patterns CNPa, CNPb, and CNPc. Figures 2a to 2c The drain of the first transistor T1 (or T1'). Accordingly, even when the light-emitting element deteriorates, the gate-source voltage (Vgs) of the driving transistor will not change. Accordingly, the amount of change in driving current due to the deterioration of the light-emitting element can be reduced. Accordingly, the afterimage defects of the display device DD with increasing usage time can be reduced, and the lifespan of the display device DD can be improved.

[0243] Figure 6 It is a schematic illustration of the setting. Figure 1a and Figure 1b A plan view of a first embodiment showing the arrangement relationship between the first electrode layer and the transmission line group in the display area. Figure 7 It is shown Figure 6 A magnified view of region AA.

[0244] refer to Figure 6 and Figure 7 The display area DA may include a unit circuit area PCU. In an embodiment, the unit circuit area PCU may be a unit area in which first to third pixel driving circuit sections PCa, PCb, and PCc arranged on the first direction DR1 are disposed. In an embodiment, the unit circuit area PCU may be repeatedly arranged along the first direction DR1 and the second direction DR2.

[0245] The display device DD may include a first electrode layer E1 and a transmission line group TLG.

[0246] In this embodiment, the first electrode layer E1 may be disposed in the display area DA. The first electrode layer E1 may receive a first power supply voltage ELVDD (see...). Figures 2a to 2cFor example, the first electrode layer E1 can be connected to the first voltage line VL1 (see...). Figures 2a to 2c It can receive the first power supply voltage ELVDD through the first voltage line VL1. In an embodiment, the first power supply voltage ELVDD can be commonly supplied to the first to third light-emitting elements LEDa, LEDb and LEDc through the first electrode layer E1.

[0247] like Figure 7 As shown, the first electrode layer E1 may include first electrodes E1a, E1b, and E1c. Specifically, the first electrode layer E1 may include the first electrode E1a of the first light-emitting element LEDa, the first electrode E1b of the second light-emitting element LEDb, and the first electrode E1c of the third light-emitting element LEDc. In an embodiment, the first electrodes E1a, E1b, and E1c may be arranged in a matrix along the first direction DR1 and the second direction DR2. For example, the first to third light-emitting regions EAa, EAb, and EAc (see...) Figure 3 and Figure 4 In embodiments configured as S-stripes, the first electrodes E1a of the first light-emitting element LEDa and the first electrodes E1b of the second light-emitting element LEDb can be arranged alternately in odd-numbered columns, and the first electrode E1c of the third light-emitting element LEDc can be arranged in even-numbered columns. Alternatively, the first electrodes E1a of the first light-emitting element LEDa and the first electrodes E1c of the third light-emitting element LEDc can be arranged alternately in odd-numbered rows, and the first electrodes E1b of the second light-emitting element LEDb and the first electrodes E1c of the third light-emitting element LEDc can be arranged alternately in even-numbered rows. However, this disclosure is not limited to these arrangements.

[0248] In this embodiment, the transmission line group (TLG) can be disposed in the display area DA. The TLG can be disposed in a different layer than the first electrode layer E1. Specifically, the TLG can be disposed in a layer closer to the substrate SUB than the first electrode layer E1.

[0249] The transmission line group (TLG) can receive the first power supply voltage ELVDD (see...). Figures 2a to 2c For example, the transmission line group TLG can be connected to the first voltage line VL1 (see...). Figures 2a to 2cThe first electrode layer E1 can receive the first power supply voltage ELVDD via the first voltage line VL1. In an embodiment, the transmission line group TLG can be directly connected to a power supply located in the peripheral region NDA and can receive the first power supply voltage ELVDD. In this case, the power supply can provide the first power supply voltage ELVDD, and the transmission line group TLG can extend to the peripheral region NDA. The transmission line group TLG can be connected to the first electrode layer E1. Accordingly, the first electrode layer E1 can receive the first power supply voltage ELVDD via the transmission line group TLG. For example, the first electrode layer E1 can receive the first power supply voltage ELVDD directly from the first voltage line VL1 and can also receive the first power supply voltage ELVDD via the transmission line group TLG.

[0250] A transmission line group (TLG) may include multiple transmission lines extending in one direction and arranged in another direction intersecting that direction. The transmission lines may be connected to a first electrode layer E1. Accordingly, the TLG (i.e., the transmission lines) may form a mesh structure with the first electrode layer E1 in a planar view.

[0251] In an embodiment, the first electrode layer E1 may have a grid pattern in which the first electrodes E1a, E1b, and E1c are integrally connected. For example, all of the first electrodes E1a, E1b, and E1c may be integrally connected to each other via bridges BR1 and BR2. For example, the first electrode layer E1 may include a first bridge BR1 connecting the first electrodes of the first electrodes E1a, E1b, and E1c that are adjacent to each other in a first direction DR1. Additionally, the first electrode layer E1 may include a second bridge BR2 connecting the first electrodes of the first electrodes E1a, E1b, and E1c that are adjacent to each other in a second direction DR2. The first bridge BR1 and the second bridge BR2 may be integral with the first electrodes E1a, E1b, and E1c. Because the first electrode layer E1 has a grid pattern, the transmission path of the first power supply voltage ELVDD can have grid characteristics. Accordingly, the voltage drop of the first power supply voltage ELVDD can be reduced. Accordingly, the power consumption of the display device DD can be improved, and the brightness uniformity can be improved. Accordingly, the display quality of the display device DD can be improved.

[0252] In an embodiment, a transmission line group (TLG) may include a first transmission line (TL1). For example, a TLG may be a collection of first transmission lines (TL1).

[0253] The first transmission line TL1 may include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, and transparent conductive oxides. The first transmission line TL1 may have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0254] The first transmission line TL1 can receive the first power supply voltage ELVDD (see...). Figures 2a to 2c For example, the first transmission line TL1 can be connected to the first voltage line VL1 (see...). Figures 2a to 2c The first power supply voltage ELVDD can be applied via the first voltage line VL1. In an embodiment, the first transmission line TL1 can be directly connected to the power supply located in the peripheral region NDA and can receive the first power supply voltage ELVDD. In this case, the first transmission line TL1 can extend to the peripheral region NDA. The first transmission line TL1 can be connected to the first electrode layer E1. For example, the first transmission line TL1 can be electrically connected to the first electrode layer E1 through the first contact hole CNT1. Accordingly, the first electrode layer E1 can receive the first power supply voltage ELVDD via the first transmission line TL1. For example, the first electrode layer E1 can receive the first power supply voltage ELVDD directly from the first voltage line VL1 and can also receive the first power supply voltage ELVDD via the first transmission line TL1.

[0255] In this embodiment, the first transmission line TL1 may extend along the second direction DR2 and be arranged along the first direction DR1. Accordingly, the first transmission line TL1 and the first electrode layer E1 may form a grid structure in a planar view. That is, in addition to the first electrode layer E1 itself having a grid pattern, the first electrode layer E1 may further form a grid structure together with the first transmission line TL1.

[0256] Figure 6 and Figure 7 The diagram depicts first transmission lines TL1 arranged in a first direction DR1 such that three first transmission lines TL1 correspond to each unit circuit region (PCU). However, this disclosure is not limited thereto. For example, if the first transmission lines TL1 form a mesh structure together with the first electrode layer E1, the repeating interval of the first transmission lines TL1 can be varied according to embodiments.

[0257] According to embodiments of this disclosure, a first transmission line TL1 receiving the first power supply voltage ELVDD can be connected to a first electrode layer E1. Accordingly, the first transmission line TL1 can supply the first power supply voltage ELVDD to the first electrode layer E1. Furthermore, the first transmission line TL1 and the first electrode layer E1 can form a grid structure in a planar view. Accordingly, the grid characteristics of the transmission path of the first power supply voltage ELVDD can be further enhanced. Accordingly, the voltage drop of the first power supply voltage ELVDD can be further reduced. Accordingly, the power consumption of the display device DD can be improved, and the brightness uniformity can be enhanced. Accordingly, the display quality of the display device DD can be improved.

[0258] Figure 8a It shows along Figure 7A cross-sectional view of an example taken from line II-II'.

[0259] For ease of explanation, Figure 8a The first transmission line TL1 and the first electrode layer E1 are mainly shown; details are omitted. Figures 3 to 5 Some of the components shown.

[0260] Further reference Figure 8a In an embodiment, the first transmission line TL1 can be connected to the first contact electrode SE1 (see...). Figure 5 ) and the second contact electrode DE1 (see Figure 5 The first transmission line TL1 can be disposed on the fourth insulating layer IL4 and can be at least partially covered by the fifth insulating layer IL5. In this case, the first contact hole CNT1 can extend through the fifth insulating layer IL5 and the sixth insulating layer IL6 to expose the first transmission line TL1, and the first electrode layer E1 can be electrically connected to the first transmission line TL1 through the first contact hole CNT1.

[0261] In an embodiment, the first transmission line TL1 can be connected to the first contact electrode SE1 (see...). Figure 5 ) and the second contact electrode DE1 (see Figure 5 The first contact electrode SE1 and the second contact electrode DE1 are formed together in the same process and may include the same material as the first contact electrode SE1 and the second contact electrode DE1. For example, a preliminary conductive layer may be formed on the fourth insulating layer IL4 and may be patterned to form the first transmission line TL1, the first contact electrode SE1 and the second contact electrode DE1 together. However, this disclosure is not limited thereto.

[0262] Figure 8b It shows along Figure 7 A cross-sectional view of an example taken from line II-II'.

[0263] For ease of explanation, Figure 8b The first transmission line TL1 and the first electrode layer E1 are mainly shown; details are omitted. Figures 3 to 5 Some of the components shown.

[0264] refer to Figure 8b In an embodiment, the first transmission line TL1 can be connected to the first to third connection electrodes CEa, CEb and CEc (see... Figures 3 to 5 The first transmission line TL1 can be disposed on the fifth insulating layer IL5 and can be at least partially covered by the sixth insulating layer IL6. In this case, the first contact hole CNT1 can extend through the sixth insulating layer IL6 to expose the first transmission line TL1, and the first electrode layer E1 can be electrically connected to the first transmission line TL1 through the first contact hole CNT1.

[0265] In an embodiment, the first transmission line TL1 can be connected to the first to third connecting electrodes CEa, CEb and CEc (see... Figures 3 to 5 Together with the first to third connecting electrodes CEa, CEb and CEc, they are formed in the same process and may include the first to third connecting electrodes CEa, CEb and CEc (see Figures 3 to 5 The material is the same as that used for the first transmission line TL1 and the first to third connecting electrodes CEa, CEb and CEc. For example, a preliminary conductive layer may be formed on the fifth insulating layer IL5, and the preliminary conductive layer may be patterned to form the first transmission line TL1 and the first to third connecting electrodes CEa, CEb and CEc together. However, this disclosure is not limited thereto.

[0266] Figure 9 It is a schematic illustration of the setting. Figure 1a and Figure 1b A plan view of a second embodiment showing the arrangement relationship between the first electrode layer and the transmission line group in the display area. Figure 10 It is shown Figure 9 A magnified view of region BB.

[0267] In addition to the transmission line group TLG', refer to Figure 9 and Figure 10 The embodiments of the described display device DD can be compared with those in the reference. Figure 6 and Figure 7 The embodiments of the described display device DD are substantially the same. Therefore, redundant descriptions are omitted or simplified.

[0268] refer to Figure 9 and Figure 10 The display device DD may include a first electrode layer E1 and a transmission line group TLG'. (See reference) Figure 6 and Figure 7 The description of the first electrode layer E1 can be applied to Figure 9 and Figure 10 The first electrode layer is E1. Therefore, redundant descriptions are omitted or simplified.

[0269] In this embodiment, the transmission line group TLG' can be disposed in the display area DA. The transmission line group TLG' can be disposed in a different layer from the first electrode layer E1. Specifically, the transmission line group TLG' can be positioned closer to the substrate SUB than the first electrode layer E1.

[0270] Transmission line group TLG' can receive the first power supply voltage ELVDD (see Figures 2a to 2c For example, transmission line group TLG' can be connected to the first voltage line VL1 (see...). Figures 2a to 2cThe first electrode layer E1 can receive the first power supply voltage ELVDD via the first voltage line VL1. In an embodiment, the transmission line group TLG' can be directly connected to the power supply located in the peripheral region NDA and can receive the first power supply voltage ELVDD. In this case, the transmission line group TLG' can extend to the peripheral region NDA. The transmission line group TLG' can be connected to the first electrode layer E1. Accordingly, the first electrode layer E1 can receive the first power supply voltage ELVDD via the transmission line group TLG'. For example, the first electrode layer E1 can receive the first power supply voltage ELVDD directly from the first voltage line VL1 and can also receive the first power supply voltage ELVDD via the transmission line group TLG'.

[0271] The transmission line group TLG' may include multiple transmission lines extending in one direction and arranged in another direction intersecting that direction. The transmission lines may be connected to the first electrode layer E1. Accordingly, the transmission line group TLG' (i.e., the transmission lines) may form a mesh structure with the first electrode layer E1 in a planar view.

[0272] In an embodiment, a transmission line group TLG' may include a second transmission line TL2. For example, a transmission line group TLG' may be a collection of second transmission lines TL2.

[0273] The second transmission line TL2 may include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, and transparent conductive oxides. The second transmission line TL2 may have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0274] The second transmission line TL2 can receive the first power supply voltage ELVDD (see...). Figures 2a to 2c For example, the second transmission line TL2 can be connected to the first voltage line VL1 (see...). Figures 2a to 2c The first power supply voltage ELVDD can be applied via the first voltage line VL1. In an embodiment, the second transmission line TL2 can be directly connected to the power supply located in the peripheral region NDA and can receive the first power supply voltage ELVDD. In this case, the second transmission line TL2 can extend to the peripheral region NDA. The second transmission line TL2 can be connected to the first electrode layer E1. For example, the second transmission line TL2 can be electrically connected to the first electrode layer E1 via the second contact hole CNT2. Accordingly, the first electrode layer E1 can receive the first power supply voltage ELVDD via the second transmission line TL2. For example, the first electrode layer E1 can receive the first power supply voltage ELVDD directly from the first voltage line VL1 and can also receive the first power supply voltage ELVDD via the second transmission line TL2.

[0275] In this embodiment, the second transmission line TL2 can extend along the first direction DR1 and can be arranged along the second direction DR2. Accordingly, the second transmission line TL2 and the first electrode layer E1 can form a grid structure in a planar view. That is, in addition to the first electrode layer E1 itself having a grid pattern, the first electrode layer E1 can form a grid structure together with the second transmission line TL2.

[0276] At the same time, Figure 9 and Figure 10 In the diagram, the second transmission lines TL2 are shown arranged in the second direction DR2 such that three second transmission lines TL2 correspond to each unit circuit region PCU. However, this disclosure is not limited thereto. For example, if the second transmission lines TL2 form a mesh structure together with the first electrode layer E1, the repeating interval of the second transmission lines TL2 can be varied according to the embodiment.

[0277] According to embodiments of this disclosure, a second transmission line TL2 receiving the first power supply voltage ELVDD can be connected to the first electrode layer E1. Accordingly, the second transmission line TL2 can supply the first power supply voltage ELVDD to the first electrode layer E1. Furthermore, the second transmission line TL2 and the first electrode layer E1 can form a grid structure in a planar view. Accordingly, the grid characteristics of the transmission path of the first power supply voltage ELVDD can be further enhanced. Consequently, the voltage drop of the first power supply voltage ELVDD can be further reduced, improving the power consumption of the display device DD and enhancing brightness uniformity. In addition, the display quality of the display device DD can be improved.

[0278] Figure 11a It shows along Figure 10 A cross-sectional view of an example taken from line III-III'.

[0279] For ease of explanation, Figure 11a The second transmission line TL2 and the first electrode layer E1 are mainly shown; details are omitted. Figures 3 to 5 Some of the components shown.

[0280] Further reference Figure 11a In this embodiment, the second transmission line TL2 can be connected to the first to third connection electrodes CEa, CEb and CEc (see... Figures 3 to 5 The first electrode layer E1 can be electrically connected to the second transmission line TL2 through the second contact hole CNT2 in the same layer. For example, the second transmission line TL2 can be disposed on the fifth insulating layer IL5 and can be at least partially covered by the sixth insulating layer IL6. In this case, the second contact hole CNT2 can extend through the sixth insulating layer IL6 to the second transmission line TL2, and the first electrode layer E1 can be electrically connected to the second transmission line TL2 through the second contact hole CNT2.

[0281] In an embodiment, the second transmission line TL2 can be connected to the first to third connection electrodes CEa, CEb and CEc (see... Figures 3 to 5 The first to third connecting electrodes CEa, CEb, and CEc are formed together in the same process and may include the same material as the first to third connecting electrodes CEa, CEb, and CEc. For example, a preliminary conductive layer may be formed on the fifth insulating layer IL5, and the preliminary conductive layer may be patterned to form the second transmission line TL2 and the first to third connecting electrodes CEa, CEb, and CEc together. However, this disclosure is not limited thereto.

[0282] Figure 11b It shows along Figure 10 A cross-sectional view of an example taken from line III-III'.

[0283] For ease of explanation, Figure 11b The second transmission line TL2 and the first electrode layer E1 are mainly shown; details are omitted. Figures 3 to 5 Some of the components shown.

[0284] Further reference Figure 11b In an embodiment, the second transmission line TL2 can be connected to the first contact electrode SE1 (see...). Figure 5 ) and the second contact electrode DE1 (see Figure 5 The first electrode layer E1 can be disposed in the same layer. For example, the second transmission line TL2 can be disposed on the fourth insulating layer IL4 and can be at least partially covered by the fifth insulating layer IL5. In this case, the second contact hole CNT2 can extend through the fifth insulating layer IL5 and the sixth insulating layer IL6 to the second transmission line TL2, and the first electrode layer E1 can be electrically connected to the second transmission line TL2 through the second contact hole CNT2.

[0285] In an embodiment, the second transmission line TL2 can be connected to the first contact electrode SE1 (see...). Figure 5 ) and the second contact electrode DE1 (see Figure 5 The first contact electrode SE1 and the second contact electrode DE1 can be formed together in the same process and may include the same material as the first contact electrode SE1 and the second contact electrode DE1. For example, a preliminary conductive layer can be formed on the fourth insulating layer IL4 and the preliminary conductive layer can be patterned to form the second transmission line TL2, the first contact electrode SE1 and the second contact electrode DE1 together. However, this disclosure is not limited thereto.

[0286] Figure 12 It is a schematic illustration of the setting. Figure 1a and Figure 1b A plan view of the arrangement relationship between the first electrode layer and the transmission line group in the display area of ​​the third embodiment. Figure 13 It is shown Figure 12 A magnified view of region CC.

[0287] In addition to the transmission line group TLG'', refer to Figure 12 and Figure 13 The embodiments of the described display device DD can be compared with those in the reference. Figure 6 and Figure 7 The embodiments of the described display device DD are substantially the same. Therefore, repeated descriptions are omitted.

[0288] refer to Figure 12 and Figure 13 The display device DD may include a first electrode layer E1 and a transmission line group TLG''. (See reference) Figure 6 and Figure 7 The description of the first electrode layer E1 can be applied to Figure 12 and Figure 13 The first electrode layer is E1. Therefore, repeated descriptions are omitted.

[0289] In this embodiment, the transmission line group TLG'' can be disposed in the display area DA. The transmission line group TLG'' can be disposed in a different layer from the first electrode layer E1. Specifically, the transmission line group TLG'' can be disposed below the first electrode layer E1.

[0290] Transmission line group TLG'' can receive the first power supply voltage ELVDD (see Figures 2a to 2c For example, transmission line group TLG'' can be connected to the first voltage line VL1 (see...). Figures 2a to 2c The first electrode layer E1 can receive the first power supply voltage ELVDD via the first voltage line VL1. In an embodiment, the transmission line group TLG'' can be directly connected to the power supply located in the peripheral region NDA and can receive the first power supply voltage ELVDD. In this case, the transmission line group TLG'' can extend to the peripheral region NDA. The transmission line group TLG'' can be connected to the first electrode layer E1. Accordingly, the first electrode layer E1 can receive the first power supply voltage ELVDD via the transmission line group TLG''. For example, the first electrode layer E1 can directly receive the first power supply voltage ELVDD from the first voltage line VL1 and can also receive the first power supply voltage ELVDD via the transmission line group TLG''.

[0291] The transmission line group TLG'' may include multiple first transmission lines extending in one direction and arranged in another direction intersecting that one direction. Additionally, the transmission line group TLG'' may include multiple second transmission lines extending in the other direction and arranged in the one direction. The first and second transmission lines may be connected to the first electrode layer E1. Accordingly, the transmission line group TLG'' (e.g., the first and second transmission lines) may form a mesh structure with the first electrode layer E1 in a planar view.

[0292] In an embodiment, the transmission line group TLG'' may include a first transmission line TL1 and a second transmission line TL2. For example, the transmission line group TLG'' may be a combination of the first transmission line TL1 and the second transmission line TL2.

[0293] refer to Figure 6 and Figure 7 The description of the first transmission line TL1 can be applied to Figure 12 and Figure 13 The first transmission line is TL1. Therefore, any redundant descriptions are omitted or simplified. Also, refer to... Figure 9 and Figure 10 The description of the second transmission line TL2 can be applied to Figure 12 and Figure 13 The second transmission line is TL2. Therefore, any redundant descriptions are omitted or simplified.

[0294] As described above, the first transmission line TL1 and the second transmission line TL2 can receive the first power supply voltage ELVDD (see...). Figures 2a to 2c The first transmission line TL1 can be electrically connected to the first electrode layer E1 through the first contact hole CNT1, and the second transmission line TL2 can be electrically connected to the first electrode layer E1 through the second contact hole CNT2. Accordingly, the first electrode layer E1 can receive the first power supply voltage ELVDD through the first transmission line TL1 and the second transmission line TL2.

[0295] In this embodiment, the first transmission line TL1 may extend along the second direction DR2 and be arranged along the first direction DR1. The second transmission line TL2 may extend along the first direction DR1 and be arranged along the second direction DR2. Accordingly, the first transmission line TL1, the second transmission line TL2, and the first electrode layer E1 may form a grid structure in a planar view. That is, in addition to the first electrode layer E1 itself having a grid pattern, the first electrode layer E1 may further form a grid structure together with the first transmission line TL1 and the second transmission line TL2.

[0296] According to embodiments of this disclosure, a first transmission line TL1 and a second transmission line TL2 receiving the first power supply voltage ELVDD can be connected to a first electrode layer E1. Accordingly, the first transmission line TL1 and the second transmission line TL2 can supply the first power supply voltage ELVDD to the first electrode layer E1. Furthermore, the first transmission line TL1, the second transmission line TL2, and the first electrode layer E1 can form a grid structure in a planar view. Accordingly, the grid characteristics of the transmission path of the first power supply voltage ELVDD can be further enhanced. As a result, the voltage drop of the first power supply voltage ELVDD can be further reduced, the power consumption of the display device DD can be reduced, and the brightness uniformity can be improved. In addition, the display quality of the display device DD can be improved.

[0297] Figure 14a It shows along Figure 13 A cross-sectional view of an example taken from line IV-IV'.

[0298] For ease of explanation, Figure 14a The first transmission line TL1, the second transmission line TL2, and the first electrode layer E1 are mainly shown; details are omitted. Figures 3 to 5 Some of the components shown.

[0299] refer to Figure 14a In an embodiment where the display device DD includes a first electrode layer E1 and a transmission line group TLG'', a second transmission line TL2 may be disposed on the first transmission line TL1. In an embodiment, the first transmission line TL1 may be connected to the first contact electrode SE1 (see... Figure 5 ) and the second contact electrode DE1 (see Figure 5 The first to third connection electrodes CEa, CEb, and CEc are located in the same layer, and the second transmission line TL2 can be connected to them (see [link to documentation]). Figures 3 to 5 The first transmission line TL1 can be disposed on the fourth insulating layer IL4 and can be at least partially covered by the fifth insulating layer IL5. Similarly, the second transmission line TL2 can be disposed on the fifth insulating layer IL5 and can be at least partially covered by the sixth insulating layer IL6. In this case, the first contact hole CNT1 can extend through the fifth insulating layer IL5 and the sixth insulating layer IL6 to the first transmission line TL1, and the first electrode layer E1 can be electrically connected to the first transmission line TL1 through the first contact hole CNT1. Furthermore, the second contact hole CNT2 can extend through the sixth insulating layer IL6 to the second transmission line TL2, and the first electrode layer E1 can be electrically connected to the second transmission line TL2 through the second contact hole CNT2.

[0300] Figure 14b It shows along Figure 13 A cross-sectional view of an example taken from line IV-IV'.

[0301] For ease of explanation, Figure 14b The first transmission line TL1, the second transmission line TL2, and the first electrode layer E1 are mainly shown; details are omitted. Figures 3 to 5 Some of the components shown.

[0302] refer to Figure 14b In an embodiment where the display device DD includes a first electrode layer E1 and a transmission line group TLG'', the first transmission line TL1 may be disposed on a second transmission line TL2. In an embodiment, the first transmission line TL1 may be connected to the first to third connecting electrodes CEa, CEb and CEc (see... Figures 3 to 5The second transmission line TL2 is located in the same layer as the first contact electrode SE1 (see [link]). Figure 5 ) and the second contact electrode DE1 (see Figure 5 The first transmission line TL1 can be disposed on the fifth insulating layer IL5 and can be at least partially covered by the sixth insulating layer IL6. Similarly, the second transmission line TL2 can be disposed on the fourth insulating layer IL4 and can be at least partially covered by the fifth insulating layer IL5. In this case, the first contact hole CNT1 can extend through the sixth insulating layer IL6 to the first transmission line TL1, and the first electrode layer E1 can be electrically connected to the first transmission line TL1 through the first contact hole CNT1. Furthermore, the second contact hole CNT2 can extend through both the fifth and sixth insulating layers IL5 to the second transmission line TL2, and the first electrode layer E1 can be electrically connected to the second transmission line TL2 through the second contact hole CNT2.

[0303] In addition, Figure 13 In the diagram, the second transmission line TL2 is shown as being disposed on the first transmission line TL1. However, according to... Figure 14b The embodiments shown can be modified. Figure 13 The diagram shows that the first transmission line TL1 is positioned on the second transmission line TL2.

[0304] Additionally, although not shown, in an embodiment, at least one of the first transmission lines TL1 can be connected to at least one of the second transmission lines TL2 via a contact hole. In this case, the voltage drop of the first power supply voltage ELVDD can be further reduced. However, this disclosure is not limited to this, and the contact between the first transmission line TL1 and the second transmission line TL2 can be omitted.

[0305] Figure 15 It is a schematic illustration of the setting. Figure 1a and Figure 1b A plan view of the arrangement relationship between the first electrode layer and the transmission line group in the display area of ​​the fourth embodiment. Figure 16 It is shown Figure 15 A magnified view of region DD.

[0306] In addition to the first electrode layer E1', reference Figure 15 and Figure 16 The embodiments of the described display device DD can be compared with those in the reference. Figure 9 and Figure 10 The described embodiment of the display device DD is substantially the same. Furthermore, except that the first electrode layer E1' is not integrally connected in a grid pattern and does not include physically separated first electrode lines EL1, the first electrode layer E1' can be substantially the same as the first electrode layer E1 described above. Therefore, redundant descriptions are omitted or simplified.

[0307] refer to Figure 15 and Figure 16 The display device DD may include a first electrode layer E1' and a transmission line group TLG'. (See reference) Figure 9 and Figure 10 The description of a transmission line group (TLG) can be applied to Figure 15 and 16 The transmission line group TLG'. Therefore, redundant descriptions are omitted or simplified.

[0308] In an embodiment, the first electrode layer E1' may include first electrode lines EL1. The first electrode lines EL1 may extend in one direction and may be arranged in another direction intersecting that direction. For example, the first electrode lines EL1 may extend in a second direction DR2 and be arranged in the first direction DR1. Each of the first electrode lines EL1 may have a structure in which some of the first electrodes E1a, E1b, and E1c are integrally connected. Furthermore, the first electrode lines EL1 may be physically separated from each other.

[0309] For example, such as Figure 16 As shown, all the first electrodes arranged in column i (where i is a natural number) can be integrally connected via the second bridge BR2 to form the first electrode line EL1. The first electrode lines EL1 arranged in the first direction DR1 can be physically separated from each other. That is, in the embodiment, in the plan view, the shape of the first electrode layer E1' can be the same as that of the first electrode layer E1 (see...). Figure 10 The shape of the first bridge BR1 is basically the same as that of the omitted bridge.

[0310] In this embodiment, the first electrode lines EL1 can be electrically connected to each other via transmission line group TLG'. That is, the first electrode lines EL1 can be electrically connected to each other via the second transmission line TL2. The second transmission line TL2 can be electrically connected to the first electrode lines EL1 via the third contact hole CNT3. Accordingly, the first electrode lines EL1 can be electrically connected to each other and can receive the first power supply voltage ELVDD via the second transmission line TL2. In other words, the first electrode layer E1' can receive the first power supply voltage ELVDD via the second transmission line TL2. For example, the first electrode layer E1' (i.e., the first electrode line EL1) can directly receive the first power supply voltage ELVDD from the first voltage line VL1, and can also receive the first power supply voltage ELVDD via the second transmission line TL2.

[0311] As described above, the second transmission line TL2 can extend along the first direction DR1 and can be arranged along the second direction DR2. Accordingly, the second transmission line TL2 and the first electrode line EL1 can form a grid structure in the planar view. That is, even if the first electrode layer E1' itself does not have a grid pattern and has another structure including the first electrode line EL1, the first electrode layer E1' can still form a grid structure together with the second transmission line TL2. Accordingly, the grid characteristics of the transmission path of the first power supply voltage ELVDD can be realized. Accordingly, while reducing the design difficulty of the first electrode layer E1', the voltage drop of the first power supply voltage ELVDD can be reduced.

[0312] Although not shown, in embodiments in which the display device DD includes a first electrode layer E1', the display device DD may include a reference. Figure 12 The transmission line group TLG'' described in Figure 14 is used instead of the transmission line group TLG'. That is, in one embodiment, the display device DD may further include a first transmission line TL1 connected to the first electrode layer E1' (i.e., the first electrode line EL1) (see Figure 14). Figure 12 (See Figure 14). In other words, the first electrode layer E1' (i.e., the first electrode line EL1) can receive the first power supply voltage ELVDD through the first transmission line TL1 and the second transmission line TL2.

[0313] Figure 17a It shows along Figure 16 A cross-sectional view of an example taken from line V-V'.

[0314] For ease of explanation, Figure 17a The second transmission line TL2 and the first electrode layer E1' are mainly shown; details are omitted. Figures 3 to 5 Some of the components shown.

[0315] refer to Figure 17a In an embodiment where the display device DD includes a first electrode layer E1', the second transmission line TL2 can be connected to the first to third connecting electrodes CEa, CEb and CEc (see... Figures 3 to 5 The first electrode layer E1' (i.e., the first electrode line EL1) can be disposed on the fifth insulating layer IL5 and can be at least partially covered by the sixth insulating layer IL6. In this case, the third contact hole CNT3 can extend through the sixth insulating layer IL6 to the second transmission line TL2, and the first electrode layer E1' (i.e., the first electrode line EL1) can be electrically connected to the second transmission line TL2 through the third contact hole CNT3.

[0316] Figure 17b It shows along Figure 16 A cross-sectional view of an example taken from line V-V'.

[0317] For ease of explanation, Figure 17b The second transmission line TL2 and the first electrode layer E1' are mainly shown; details are omitted. Figures 3 to 5 Some of the components shown.

[0318] refer to Figure 17b In an embodiment where the display device DD includes a first electrode layer E1', the second transmission line TL2 may be connected to the first contact electrode SE1 (see... Figure 5 ) and the second contact electrode DE1 (see Figure 5 The first electrode layer E1' (i.e., the first electrode line EL1) can be disposed in the same layer. For example, the second transmission line TL2 can be disposed on the fourth insulating layer IL4 and can be at least partially covered by the fifth insulating layer IL5. In this case, the third contact hole CNT3 can extend through the fifth insulating layer IL5 and the sixth insulating layer IL6 to the second transmission line TL2, and the first electrode layer E1' (i.e., the first electrode line EL1) can be electrically connected to the second transmission line TL2 through the third contact hole CNT3.

[0319] Figure 18 It is a schematic illustration of the setting. Figure 1a and Figure 1b A plan view of the arrangement relationship between the first electrode layer and the transmission line group in the display area of ​​the fifth embodiment. Figure 19 It is shown Figure 18 A magnified view of the EE region.

[0320] In addition to the first electrode layer E1'', reference Figure 18 and Figure 19 The embodiments of the described display device DD can be compared with those in the reference. Figure 6 and Figure 7 The described embodiment of the display device DD is substantially the same. Additionally, except that the first electrode layer E1'' is not integrally connected in a grid pattern and includes physically separated second electrode lines EL2, it can be substantially the same as the first electrode layer E1 described above. Therefore, redundant descriptions are omitted or simplified.

[0321] refer to Figure 18 and Figure 19 The display device DD may include a first electrode layer E1'' and a transmission line group TLG. (See reference) Figure 6 and Figure 7 The description of the transmission line group (TLG) can be applied to Figure 18 and Figure 19 The transmission line group (TLG) is used. Therefore, redundant descriptions are omitted or simplified.

[0322] In an embodiment, the first electrode layer E1'' may include second electrode lines EL2. The second electrode lines EL2 may extend in one direction and may be arranged in another direction intersecting that direction. For example, the second electrode lines EL2 may extend in a first direction DR1 and may be arranged in a second direction DR2. Each of the second electrode lines EL2 may have a structure in which some of the first electrodes E1a, E1b, and E1c are integrally connected. Furthermore, the second electrode lines EL2 may be physically separated from each other.

[0323] For example, such as Figure 18 and Figure 19 As shown, all of the first electrodes arranged in rows j and j+1 (where j is an odd number of 1 or greater) can be integrally connected by the first bridge BR1 to form the second electrode line EL2, and the second electrode lines EL2 arranged in the second direction DR2 can be physically separated from each other. That is, in the embodiment, in the plan view (see... Figure 7 In the first electrode layer E1'', the shape can be substantially the same as the shape of the omitted second bridge BR2 of the first electrode layer E1.

[0324] In this embodiment, the second electrode lines EL2 can be electrically connected to each other via a transmission line group TLG. That is, the second electrode lines EL2 can be electrically connected to each other via a first transmission line TL1. The first transmission line TL1 can be electrically connected to the second electrode lines EL2 via a fourth contact hole CNT4. Accordingly, the second electrode lines EL2 can be electrically connected to each other and can receive the first power supply voltage ELVDD via the first transmission line TL1. In other words, the first electrode layer E1'' can receive the first power supply voltage ELVDD via the first transmission line TL1. For example, the first electrode layer E1'' (i.e., the second electrode lines EL2) can directly receive the first power supply voltage ELVDD from the first voltage line VL1, and can also receive the first power supply voltage ELVDD via the first transmission line TL1.

[0325] As described above, the first transmission line TL1 can extend along the second direction DR2 and can be arranged along the first direction DR1. Accordingly, the first transmission line TL1 and the second electrode line EL2 can form a grid structure in the planar view. That is, even if the first electrode layer E1'' itself does not have a grid pattern and has another structure including the second electrode line EL2, the first electrode layer E1'' can form a grid structure together with the first transmission line TL1. Accordingly, the grid characteristics of the transmission path of the first power supply voltage ELVDD can be realized. Accordingly, while reducing the design difficulty of the first electrode layer E1'', the voltage drop of the first power supply voltage ELVDD can be reduced.

[0326] Although not shown, in embodiments in which the display device DD includes a first electrode layer E1'', the display device DD may include a reference. Figure 12 Instead of the transmission line group TLG'' described in Figure 14, the display device DD may further include a second transmission line TL2 connected to the first electrode layer E1'' (see Figure 14). Figure 12 (See Figure 14). In other words, the first electrode layer E1'' (i.e., the second electrode line EL2) can receive the first power supply voltage ELVDD through the first transmission lines TL1 and TL2.

[0327] Figure 20a It shows along Figure 19 A cross-sectional view of an example taken from line VI-VI'.

[0328] For ease of explanation, Figure 20a The first transmission line TL1 and the first electrode layer E1'' are mainly shown, with details omitted. Figures 3 to 5 Some of the components shown.

[0329] refer to Figure 20a In an embodiment where the display device DD includes a first electrode layer E1'', the first transmission line TL1 may be connected to the first contact electrode SE1 (see...). Figure 5 ) and the second contact electrode DE1 (see Figure 5 The first transmission line TL1 can be disposed on the fourth insulating layer IL4 and can be at least partially covered by the fifth insulating layer IL5. In this case, the fourth contact hole CNT4 can extend through the fifth insulating layer IL5 and the sixth insulating layer IL6 to the first transmission line TL1, and the first electrode layer E1'' (i.e., the second electrode line EL2) can be electrically connected to the first transmission line TL1 through the fourth contact hole CNT4.

[0330] Figure 20b It shows along Figure 19 A cross-sectional view of an example taken from line VI-VI'.

[0331] For ease of explanation, Figure 20b The first transmission line TL1 and the first electrode layer E1'' are mainly shown, with details omitted. Figures 3 to 5 Some of the components shown.

[0332] refer to Figure 20b In an embodiment where the display device DD includes a first electrode layer E1'', the first transmission line TL1 can be connected to the first to third connecting electrodes CEa, CEb and CEc (see... Figures 3 to 5The first transmission line TL1 can be disposed on the fifth insulating layer IL5 and can be at least partially covered by the sixth insulating layer IL6. In this case, the fourth contact hole CNT4 can extend through the sixth insulating layer IL6 to the first transmission line TL1, and the first electrode layer E1'' (i.e., the second electrode line EL2) can be electrically connected to the first transmission line TL1 through the fourth contact hole CNT4.

[0333] Figure 21 It is a schematic illustration of the setting. Figure 1a and Figure 1b A plan view of the arrangement relationship between the first electrode layer and the transmission line group in the display area of ​​the sixth embodiment. Figure 22 It is shown Figure 21 A magnified view of region FF.

[0334] Except for the first electrode layer E1''', reference Figure 21 and Figure 22 The embodiments of the described display device DD can be compared with those in the reference. Figure 12 and Figure 13 The described display device DD is substantially the same. Additionally, except that the first electrode layer E1''' is not integrally connected into a grid pattern and includes physically separated electrode patterns EP, the first electrode layer E1''' can be substantially the same as the first electrode layer E1 described above. Therefore, redundant descriptions are omitted or simplified.

[0335] refer to Figure 21 and Figure 22 The display device DD may include a first electrode layer E1''' and a transmission line group TLG''. For Figure 18 and Figure 19 The transmission line group TLG'' shown in the figure can be applied to the reference. Figure 12 and Figure 13 The description of the transmission line group TLG'' is modified so that each unit circuit region PCU has two first transmission lines TL1 and two second transmission lines TL2, except that the interval of transmission line repetition is changed so that each unit circuit region PCU has two first transmission lines TL1 and two second transmission lines TL2. Therefore, redundant descriptions are omitted or simplified.

[0336] In an embodiment, the first electrode layer E1''' may include electrode patterns EP. Each of the electrode patterns EP may have a structure in which a first electrode E1a, E1b, and E1c corresponding to one of the unit circuit regions PCU are integrally connected. The electrode patterns EP may be arranged in one direction and another direction intersecting that direction. For example, the electrode patterns EP may be arranged in a first direction DR1 and a second direction DR2. That is, the electrode patterns EP may be arranged in a matrix. In addition, the electrode patterns EP may be physically separated from each other.

[0337] Electrode patterns EP can be electrically connected to each other via transmission line group TLG''. That is, electrode patterns EP can be electrically connected to each other via first transmission line TL1 and second transmission line TL2. First transmission line TL1 can be electrically connected to electrode pattern EP via fifth contact hole CNT5. Second transmission line TL2 can be electrically connected to electrode pattern EP via sixth contact hole CNT6. Accordingly, electrode patterns EP can be electrically connected to each other and can receive the first power supply voltage ELVDD via first transmission line TL1 and second transmission line TL2. In other words, the first electrode layer E1''' can receive the first power supply voltage ELVDD via first transmission line TL1 and second transmission line TL2. For example, the first electrode layer E1''' (i.e., electrode pattern EP) can directly receive the first power supply voltage ELVDD from the first voltage line VL1, and can also receive the first power supply voltage ELVDD via first transmission line TL1 and second transmission line TL2.

[0338] As described above, the first transmission line TL1 can extend along the second direction DR2 and can be arranged along the first direction DR1. Similarly, the second transmission line TL2 can extend along the first direction DR1 and can be arranged along the second direction DR2. Accordingly, the first transmission line TL1, the second transmission line TL2, and the electrode pattern EP can form a grid structure in the planar view. That is, even if the first electrode layer E1''' itself does not have a grid pattern and has another structure including the electrode pattern EP, the first electrode layer E1''' can still form a grid structure together with the first transmission line TL1 and the second transmission line TL2. Accordingly, the grid characteristics of the transmission path of the first power supply voltage ELVDD can be realized. Consequently, the design difficulty of the first electrode layer E1''' is reduced, and the voltage drop of the first power supply voltage ELVDD can be reduced.

[0339] Figure 23a It shows along Figure 22 A cross-sectional view of an example taken from line VII-VII'.

[0340] For ease of explanation, Figure 23a The main diagram shows the first transmission line TL1, the second transmission line TL2, and the first electrode layer E1''', with details omitted. Figures 3 to 5 Some of the components shown.

[0341] refer to Figure 23a In an embodiment where the display device DD includes a first electrode layer E1''' and a transmission line group TLG'', a second transmission line TL2 may be disposed on the first transmission line TL1. In an embodiment, the first transmission line TL1 may be connected to the first contact electrode SE1 (see... Figure 5 ) and the second contact electrode DE1 (see Figure 5The first to third connection electrodes CEa, CEb, and CEc are located in the same layer, and the second transmission line TL2 can be connected to them (see [link to documentation]). Figures 3 to 5 The first transmission line TL1 can be disposed on the fourth insulating layer IL4 and can be at least partially covered by the fifth insulating layer IL5. Similarly, the second transmission line TL2 can be disposed on the fifth insulating layer IL5 and can be at least partially covered by the sixth insulating layer IL6. In this case, the fifth contact hole CNT5 can extend through the fifth insulating layer IL5 and the sixth insulating layer IL6 to the first transmission line TL1, and the first electrode layer E1''' (i.e., the electrode pattern EP) can be electrically connected to the first transmission line TL1 through the fifth contact hole CNT5. Furthermore, the sixth contact hole CNT6 can extend through the sixth insulating layer IL6 to the second transmission line TL2, and the first electrode layer E1''' (i.e., the electrode pattern EP) can be electrically connected to the second transmission line TL2 through the sixth contact hole CNT6.

[0342] Figure 23b It shows along Figure 22 A cross-sectional view of an example taken from line VII-VII'.

[0343] For ease of explanation, Figure 23b The main diagram shows the first transmission line TL1, the second transmission line TL2, and the first electrode layer E1''', with details omitted. Figures 3 to 5 Some of the components shown.

[0344] refer to Figure 23b In an embodiment where the display device DD includes a first electrode layer E1''' and a transmission line group TLG'', the first transmission line TL1 may be disposed on a second transmission line TL2. In an embodiment, the first transmission line TL1 may be connected to the first to third connecting electrodes CEa, CEb and CEc (see... Figures 3 to 5 The second transmission line TL2 is located in the same layer as the first contact electrode SE1 (see [link]). Figure 5 ) and the second contact electrode DE1 (see Figure 5The first transmission line TL1 can be disposed on the fifth insulating layer IL5 and can be at least partially covered by the sixth insulating layer IL6. Similarly, the second transmission line TL2 can be disposed on the fourth insulating layer IL4 and can be at least partially covered by the fifth insulating layer IL5. In this case, the fifth contact hole CNT5 can extend through the sixth insulating layer IL6 to the first transmission line TL1, and the first electrode layer E1''' (i.e., the electrode pattern EP) can be electrically connected to the first transmission line TL1 through the fifth contact hole CNT5. Furthermore, the sixth contact hole CNT6 can extend through both the fifth and sixth insulating layers IL5 to the second transmission line TL2, and the first electrode layer E1''' (i.e., the electrode pattern EP) can be electrically connected to the second transmission line TL2 through the sixth contact hole CNT6.

[0345] Figure 24 It is a schematic illustration of the setting. Figure 1a and Figure 1b A plan view of the arrangement relationship between the first electrode layer and the transmission line group in the display area of ​​the seventh embodiment. Figure 25 It is shown Figure 24 A magnified view of region GG.

[0346] Except for the first electrode layer E1'''', reference Figure 24 and Figure 25 The embodiments of the described display device DD can be compared with those in the reference. Figure 12 and Figure 13 The described display device DD is substantially the same. Additionally, except that the first electrode layer E1'''' is not integrally connected in a grid pattern and includes first electrodes E1a, E1b, and E1c that are physically separated from each other, the first electrode layer E1'''' can be substantially the same as the first electrode layer E1 described above. Therefore, any redundant descriptions are omitted or simplified.

[0347] refer to Figure 24 and Figure 25 The display device DD may include a first electrode layer E1'''' and a transmission line group TLG''. For Figure 24 and Figure 25 The transmission line group TLG'' shown in the figure can be applied to the reference. Figure 12 and Figure 13 The description of the transmission line group TLG'' is modified so that each unit circuit region PCU has two first transmission lines TL1 and two second transmission lines TL2, except that the interval of transmission line repetition is changed so that each unit circuit region PCU has two first transmission lines TL1 and two second transmission lines TL2. Therefore, redundant descriptions are omitted or simplified.

[0348] In this embodiment, all of the first electrodes E1a, E1b, and E1c included in the first electrode layer E1'''' can be physically separated from each other. Furthermore, all of the first electrodes E1a, E1b, and E1c included in the first electrode layer E1'''' can be electrically connected to each other via a transmission line group TLG''. That is, all of the first electrodes E1a, E1b, and E1c can be electrically connected to each other via a first transmission line TL1 and a second transmission line TL2. The first transmission line TL1 can be electrically connected to the first electrodes E1a, E1b, and E1c via a seventh contact hole CNT7. The second transmission line TL2 can be electrically connected to the first electrodes E1a, E1b, and E1c via an eighth contact hole CNT8. Accordingly, all of the first electrodes E1a, E1b, and E1c can be electrically connected to each other and can receive the first power supply voltage ELVDD via the first transmission line TL1 and the second transmission line TL2. In other words, the first electrode layer E1'''' can receive the first power supply voltage ELVDD via the first transmission line TL1 and the second transmission line TL2. For example, the first electrode layer E1'''' (i.e., the first electrodes E1a, E1b and E1c) can receive the first power supply voltage ELVDD directly from the first voltage line VL1, and can also receive the first power supply voltage ELVDD through the first transmission line TL1 and the second transmission line TL2.

[0349] As described above, the first transmission line TL1 can extend in the second direction DR2 and can be arranged in the first direction DR1. Similarly, the second transmission line TL2 can extend in the first direction DR1 and can be arranged in the second direction DR2. Accordingly, the first transmission line TL1, the second transmission line TL2, and the first electrodes E1a, E1b, and E1c can form a grid structure in the planar view. That is, even if the first electrode layer E1'''' itself does not have a grid pattern and has another structure including the first electrodes E1a, E1b, and E1c which are physically separated from each other, the first electrode layer E1'''' can still form a grid structure together with the first transmission line TL1 and the second transmission line TL2. Accordingly, the grid characteristics of the transmission path of the first power supply voltage ELVDD can be realized. Consequently, while reducing the design difficulty of the first electrode layer E1'''', the voltage drop of the first power supply voltage ELVDD can be reduced.

[0350] Figure 26a It shows along Figure 25 A cross-sectional view of an example taken from line VIII-VIII'.

[0351] For ease of explanation, Figure 26a The main diagram shows the first transmission line TL1, the second transmission line TL2, and the first electrode layer E1, omitting... Figures 3 to 5 Some of the components shown.

[0352] refer to Figure 26a In an embodiment where the display device DD includes a first electrode layer E1'''' and a transmission line group TLG'', a second transmission line TL2 may be disposed on the first transmission line TL1. In an embodiment, the first transmission line TL1 may be connected to the first contact electrode SE1 (see... Figure 5 ) and the second contact electrode DE1 (see Figure 5 The first to third connection electrodes CEa, CEb, and CEc are located in the same layer, and the second transmission line TL2 can be connected to them (see [link to documentation]). Figures 3 to 5 The first transmission line TL1 can be disposed on the fourth insulating layer IL4 and can be at least partially covered by the fifth insulating layer IL5. Similarly, the second transmission line TL2 can be disposed on the fifth insulating layer IL5 and can be at least partially covered by the sixth insulating layer IL6. In this case, the seventh contact hole CNT7 can extend through the fifth and sixth insulating layers IL5 to the first transmission line TL1, and the first electrode layers E1'''' (i.e., the first electrodes E1a, E1b, and E1c) can be electrically connected to the first transmission line TL1 through the seventh contact hole CNT7. Furthermore, the eighth contact hole CNT8 can extend through the sixth insulating layer IL6 to the second transmission line TL2, and the first electrode layers E1'''' (i.e., the first electrodes E1a, E1b, and E1c) can be electrically connected to the second transmission line TL2 through the eighth contact hole CNT8.

[0353] Figure 26b It shows along Figure 25 A cross-sectional view of an example taken from line VIII-VIII'.

[0354] For ease of explanation, Figure 26b The main diagram shows the first transmission line TL1, the second transmission line TL2, and the first electrode layer E1, omitting... Figures 3 to 5 Some of the components shown.

[0355] refer to Figure 26b In an embodiment where the display device DD includes a first electrode layer E1'''' and a transmission line group TLG'', the first transmission line TL1 may be disposed on a second transmission line TL2. In an embodiment, the first transmission line TL1 may be connected to the first to third connecting electrodes CEa, CEb and CEc (see... Figures 3 to 5 The second transmission line TL2 is located in the same layer as the first contact electrode SE1 (see [link]). Figure 5 ) and the second contact electrode DE1 (see Figure 5The first transmission line TL1 can be disposed on the fifth insulating layer IL5 and can be at least partially covered by the sixth insulating layer IL6. Similarly, the second transmission line TL2 can be disposed on the fourth insulating layer IL4 and can be at least partially covered by the fifth insulating layer IL5. In this case, the seventh contact hole CNT7 can extend through the sixth insulating layer IL6 to the first transmission line TL1, and the first electrode layer E1'''' (i.e., the first electrodes E1a, E1b, and E1c) can be electrically connected to the first transmission line TL1 through the seventh contact hole CNT7. Furthermore, the eighth contact hole CNT8 can extend through both the fifth and sixth insulating layers IL5 to the second transmission line TL2, and the first electrode layer E1'''' (i.e., the first electrodes E1a, E1b, and E1c) can be electrically connected to the second transmission line TL2 through the eighth contact hole CNT8.

[0356] According to embodiments of this disclosure, a display device DD may include a first electrode layer forming a light-emitting element and receiving a first power supply voltage ELVDD, and a transmission line disposed in a different layer from the first electrode layer and also receiving the first power supply voltage ELVDD. Accordingly, the transmission line can supply the first power supply voltage ELVDD to the first electrode layer, and the first electrode layer and the transmission line can form a grid structure in a planar view. For example, if the first electrode layer itself has a grid pattern, the grid characteristics of the transmission path of the first power supply voltage ELVDD can be further enhanced by the grid structure formed by the first electrode layer and the transmission line. Furthermore, even if the first electrode layer itself does not have a grid pattern, the grid characteristics of the transmission path of the first power supply voltage ELVDD can still be achieved by the grid structure formed by the first electrode layer and the transmission line. Accordingly, the voltage drop of the first power supply voltage ELVDD can be reduced, the power consumption of the display device DD can be reduced, and the brightness uniformity can be improved. In addition, the display quality of the display device DD can be improved.

[0357] Figure 27 It is shown schematically. Figure 1a and Figure 1b A floor plan of a portion of the display device. Figure 28 yes Figure 27 An enlarged view of one unit luminous region within a unit luminous region. Figure 29 It is along Figure 28 The cross-sectional view taken from line IX-IX'.

[0358] Figure 27 The region is depicted as comprising four unit luminous areas, UEA1 and UEA2, arranged in a matrix of 2 rows and 2 columns. Figure 28 Describe a first unit emitting region, UEA1, from unit emitting regions UEA1 and UEA2. For ease of illustration, in... Figure 27 and Figure 28 Omission or emphasis Figure 29 Some of the components shown. Additionally, in Figure 27 in, omit Figure 28 The second electrodes E2a', E2b', and E2c' in the component are shown.

[0359] In addition to the first to third light-emitting elements LEDa', LEDb' and LEDc', the first to third connecting electrodes CEa', CEb' and CEc', and the separator SPR', refer to Figures 27 to 29 The embodiments of the described display device DD can be compared with those in the reference. Figures 3 to 5 The described embodiment of the display device DD is substantially the same. In the following description, the focus will be on the embodiment referenced in the referenced document. Figures 3 to 5 The differences between the embodiments of the display device DD described will be omitted or simplified, and any redundant descriptions will be omitted or simplified.

[0360] refer to Figures 27 to 29 The display device DD may include first to third pixel driving circuits PCa, PCb and PCc, first to third light-emitting elements LEDa', LEDb' and LEDc', first to third connecting electrodes CEa', CEb' and CEc', and separator SPR'.

[0361] Figures 3 to 5 The descriptions of the first to third pixel driving circuit sections PCa, PCb, and PCc can be applied to Figure 27 and Figure 28 The first to third pixel driving circuits are PCa, PCb, and PCc. Therefore, repeated descriptions are omitted.

[0362] In addition, besides the intermediate layer ML' and the second electrode layer E2', reference Figures 3 to 5 The descriptions of the first to third light-emitting elements LEDa', LEDb', and LEDc' can be applied to Figures 27 to 29 The first to third light-emitting elements are LEDa', LEDb', and LEDc'. Therefore, repeated descriptions are omitted.

[0363] Specifically, the description of the first electrode layers E1, E1', E1'', E1''', and E1'''' above can be applied to Figure 29 The first electrode layer E1. That is, various embodiments of the above-described first electrode layer can be applied to... Figure 29 The first electrode layer is E1. Therefore, repeated descriptions are omitted.

[0364] Each of the first to third light-emitting elements LEDa', LEDb', and LEDc' can correspond to a reference. Figures 2a to 2cThe light-emitting element described is an LED. For example, each of the first to third light-emitting elements LEDa', LEDb', and LEDc' may include a first electrode layer (e.g., Figure 29 The first electrode layer E1), and the intermediate layer disposed on the first electrode layer (e.g., Figure 29 The first electrode layer (ML') and the second electrode layer (E2') disposed on the intermediate layer. In an embodiment, the first electrode layer can act as... Figures 2a to 2c The anode, and the second electrode layer E2' can act as... Figures 2a to 2c The cathode.

[0365] In an embodiment, the second electrode layer E2' can be separated (or disconnected) by the separator SPR' into second electrodes E2a', E2b', and E2c'. Specifically, the second electrode layer E2' can be separated (or disconnected) into the second electrode E2a' of the first light-emitting element LEDa', the second electrode E2b' of the second light-emitting element LEDb', and the second electrode E2c' of the third light-emitting element LEDc', and the second electrodes E2a', E2b', and E2c' can be electrically independent of each other. This will be described in more detail later.

[0366] The first light-emitting element LEDa' may include a first electrode E1a that acts as the anode (see...). Figure 7 The second light-emitting element LEDb' may include a first electrode E1b (see [reference]) and a second electrode E2a' that acts as the cathode. Figure 7 The third light-emitting element LEDc' may include a first electrode E1c (see [reference]) and a second electrode E2b' that acts as the cathode, and may also include a third light-emitting element LEDc' that acts as the anode. Figure 7 ) and the second electrode E2c' which acts as the cathode.

[0367] As described above, the display device DD may include first to third connecting electrodes CEa', CEb', and CEc'. The first connecting electrode CEa' can connect the first light-emitting element LEDa' and the first pixel driving circuit PCa, the second connecting electrode CEb' can connect the second light-emitting element LEDb' and the second pixel driving circuit PCb, and the third connecting electrode CEc' can connect the third light-emitting element LEDc' and the third pixel driving circuit PCc.

[0368] The first to third connecting electrodes CEa', CEb', and CEc' can comprise conductive materials such as metals, alloys, conductive metal nitrides, and transparent conductive oxides. Examples of conductive materials that can be used for the first to third connecting electrodes CEa', CEb', and CEc' include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), alloys containing aluminum (Al), and alloys containing silver (Ag). Alloys containing copper (Cu), alloys containing molybdenum (Mo), aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), tin oxide (SnO), gallium oxide (GaO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc oxide (ZnO), indium oxide (InO), and aluminum zinc oxide (AZO), etc. These can be used individually or in combination. In embodiments, the first to third connecting electrodes CEa', CEb', and CEc' can have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked. Reference will be made below. Figure 29 This will be described in more detail.

[0369] The first connecting electrode CEa' may include a first circuit connecting portion CPa' and a first light-emitting connecting portion CNa'.

[0370] The first circuit connection portion CPa' can be the portion of the first connection electrode CEa' that connects to the first pixel driving circuit section PCa. Specifically, the first circuit connection portion CPa' can be the portion of the first connection electrode CEa' that connects to the first transistor TR1 (see FIG. 8) of the first pixel driving circuit section PCa. Accordingly, the position of the first circuit connection portion CPa' can correspond to the position of the first transistor TR1 of the first pixel driving circuit section PCa. Specifically, the position of the first circuit connection portion CPa' can be the portion that extends to the first transistor TR1 of the first pixel driving circuit section PCa and extends through the fifth insulating layer IL5 (see FIG. 8). Figure 29 The positions of the contact holes correspond to those of the contacts.

[0371] The first light-emitting connection portion CNa' can be the portion of the first connection electrode CEa' that connects to the second electrode E2a' of the first light-emitting element LEDa'. Specifically, the first light-emitting connection portion CNa' can be the portion of the first connection electrode CEa' located in the sixth insulating layer IL6 (see... Figure 29 The opening in the pixel-limited layer PDL (see) and the opening in the pixel-limited layer PDL (see) Figure 29The portion of the opening in the first light-emitting connection portion CNa' contacts the second electrode E2a'. Correspondingly, the position of the first light-emitting connection portion CNa' can correspond to the position of the opening that exposes the first connection electrode CEa' and extends through the pixel defining layer PDL and the sixth insulating layer IL6.

[0372] The second electrode E2a' of the first light-emitting element LEDa' can be connected to the first connecting electrode CEa'. For example, the second electrode E2a' of the first light-emitting element LEDa' can contact the first connecting electrode CEa'. As a result, the second electrode E2a' of the first light-emitting element LEDa' can be connected to the first pixel driving circuit PCa through the first connecting electrode CEa'.

[0373] In an embodiment, the first light-emitting connection portion CNa' can be positioned at a location that does not overlap with the first light-emitting region EAa. For example, in a plan view, the first light-emitting connection portion CNa' can be positioned between the first light-emitting region EAa and the separator SPR'. For example, the second electrode E2a' of the first light-emitting element LEDa' can have a protruding portion extending from the first light-emitting region EAa to a position that does not overlap with the first light-emitting region EAa in the plan view, and the first connection electrode CEa' and the second electrode E2a' of the first light-emitting element LEDa' can contact each other at a position that does not overlap with the first light-emitting region EAa. Therefore, without reducing the light-emitting area of ​​the first light-emitting region EAa, the first pixel driving circuit section Pca and the second electrode E2a' of the first light-emitting element LEDa' can be connected through the first connection electrode CEa'.

[0374] The second connecting electrode CEb' may include a second circuit connecting portion CPb' and a second light-emitting connecting portion CNb'.

[0375] The second circuit connection portion CPb' can be the portion of the second connection electrode CEb' that is connected to the second pixel driving circuit section PCb. Specifically, the second circuit connection portion CPb' can be the first transistor TR1 (see [reference needed]) connected to the second pixel driving circuit section PCb of the second connection electrode CEb'. Figure 29 The position of the second circuit connection portion CPb' can correspond to the position of the first transistor TR1 of the second pixel driving circuit portion PCb. Specifically, the position of the second circuit connection portion CPb' can correspond to the position of the transistor TR1 passing through the fifth insulating layer IL5 (see...). Figure 29 The position of the contact hole of the first transistor TR1 extends to the second pixel drive circuit PCb.

[0376] The second light-emitting connection portion CNb' can be the portion of the second connection electrode CEb' that connects to the second electrode E2b' of the second light-emitting element LEDb'. Specifically, the second light-emitting connection portion CNb' can be the portion of the second connection electrode CEb' located in the sixth insulating layer IL6 (see... Figure 29 The opening and pixel-limiting layer PDL (see) Figure 29 The portion of the second light-emitting connection portion CNb' is in the opening and contacts the second electrode E2b'. Correspondingly, the position of the second light-emitting connection portion CNb' can correspond to the position of the opening extending through the pixel defining layer PDL and the sixth insulating layer IL6 to the second connection electrode CEb'.

[0377] In an embodiment, the second connecting electrode CEb' may be spaced apart from the first connecting electrode CEa' in a plan view. In other words, the first connecting electrode CEa' and the second connecting electrode CEb' may be different electrodes.

[0378] The second electrode E2b' of the second light-emitting element LEDb' can be connected to the second connecting electrode CEb'. For example, the second electrode E2b' of the second light-emitting element LEDb' can contact the second connecting electrode CEb'. As a result, the second electrode E2b' of the second light-emitting element LEDb' can be connected to the second pixel driving circuit PCb through the second connecting electrode CEb'.

[0379] In an embodiment, the second light-emitting connection portion CNb' can be disposed at a position that does not overlap with the second light-emitting region EAb. For example, in a plan view, the second light-emitting connection portion CNb' can be disposed between the second light-emitting region EAb and the separator SPR'. For example, the second electrode E2b' of the second light-emitting element LEDb' can have a protruding portion extending from the second light-emitting region EAb to a position that does not overlap with the second light-emitting region EAb in the plan view, and the second connection electrode CEb' and the second electrode E2b' of the second light-emitting element LEDb' can contact each other at a position that does not overlap with the second light-emitting region EAb. Therefore, without reducing the light-emitting area of ​​the second light-emitting region EAb, the second pixel driving circuit PCb and the second electrode E2b' of the second light-emitting element LEDb' can be connected through the second connection electrode CEb'.

[0380] The third connecting electrode CEc' may include a third circuit connecting portion CPc' and a third light-emitting connecting portion CNc'.

[0381] The third circuit connection portion CPc' can be the part of the third connection electrode CEc' that is connected to the third pixel driving circuit PCc. Specifically, the third circuit connection portion CPc' can be the first transistor TR1 (see [link to third pixel driving circuit PCc]) that is connected to the third connection electrode CEc'. Figure 29The position of the third circuit connection portion CPc' can correspond to the position of the first transistor TR1 of the third pixel driving circuit portion PCc. Specifically, the position of the third circuit connection portion CPc' can correspond to the position of the transistor TR1 passing through the fifth insulating layer IL5 (see...). Figure 29 The position of the contact hole of the first transistor TR1 extends to the third pixel drive circuit PCc, corresponding to the position of the first transistor TR1.

[0382] The third light-emitting connection portion CNc' can be the portion of the third connection electrode CEc' that connects to the second electrode E2c' of the third light-emitting element LEDc'. Specifically, the third light-emitting connection portion CNc' can be the portion of the third connection electrode CEc' located in the sixth insulating layer IL6 (see...). Figure 29 The opening and pixel-limiting layer PDL (see) Figure 29 The portion of the third light-emitting connection portion CNc' is in the opening and contacts the second electrode E2c'. Correspondingly, the position of the third light-emitting connection portion CNc' can correspond to the position of the opening extending through the pixel defining layer PDL and the sixth insulating layer IL6 to the third connection electrode CEc'.

[0383] In an embodiment, the third connecting electrode CEc' may be spaced apart from the first connecting electrode CEa' and the second connecting electrode CEb' in a plan view. In other words, the first connecting electrode CEa', the second connecting electrode CEb', and the third connecting electrode CEc' may be different electrodes.

[0384] The second electrode E2c' of the third light-emitting element LEDc' can be connected to the third connecting electrode CEc'. For example, the second electrode E2c' of the third light-emitting element LEDc' can contact the third connecting electrode CEc'. As a result, the second electrode E2c' of the third light-emitting element LEDc' can be connected to the third pixel driving circuit PCc through the third connecting electrode CEc'.

[0385] In an embodiment, the third light-emitting connection portion CNc' can be positioned at a location that does not overlap with the third light-emitting region EAc. For example, in a plan view, the third light-emitting connection portion CNc' can be positioned between the third light-emitting region EAc and the separator SPR'. For example, the second electrode E2c' of the third light-emitting element LEDc' can have a protruding portion extending from the third light-emitting region EAc to a position that does not overlap with the third light-emitting region EAc in the plan view, and the third connection electrode CEc' and the second electrode E2c' of the third light-emitting element LEDc' can contact each other at a position that does not overlap with the third light-emitting region EAc. Therefore, without reducing the light-emitting area of ​​the third light-emitting region EAc, the third pixel driving circuit PCc and the second electrode E2c' of the third light-emitting element LEDc' can be connected through the third connection electrode CEc'.

[0386] According to embodiments of this disclosure, the second electrodes E2a', E2b', and E2c' can be connected to the connecting electrodes CEa', CEb', and CEc' respectively at positions that do not overlap with the first to third light-emitting regions EAa, EAb, and EAc. Accordingly, without reducing the light-emitting area, the second electrodes E2a', E2b', and E2c' can be connected to the first to third connecting electrodes CEa', CEb', and CEc'.

[0387] Furthermore, according to embodiments of this disclosure, the second electrodes E2a', E2b', and E2c' can be connected to the first to third pixel driving circuit sections PCa, PCb, and PCc respectively via the first to third connecting electrodes CEa', CEb', and CEc'. Accordingly, the limitations imposed by the position, shape, and size of the first to third light-emitting regions EAa, EAb, and EAc in the design of the first to third pixel driving circuit sections PCa, PCb, and PCc can be reduced. For example, even if at least some of the first to third circuit connection portions CPa', CPb', and CPc' overlap with the first to third light-emitting regions EAa, EAb, and EAc, the second electrodes E2a', E2b', and E2c' can still be easily connected to the first to third pixel driving circuit sections PCa, PCb, and PCc respectively via the first to third connecting electrodes CEa', CEb', and CEc'. Therefore, the shape and arrangement of the first to third pixel driving circuit sections PCa, PCb, and PCc can be designed independently of the position, shape, and size of the first to third light-emitting regions EAa, EAb, and EAc. Accordingly, the design of the first to third pixel driving circuit sections PCa, PCb and PCc can have a high degree of freedom.

[0388] like Figure 27 As shown, for each first unit light-emitting region UEA1, the shape or arrangement of each of the corresponding first to third connecting electrodes CEa', CEb', and CEc', as well as the arrangement relationship between the first to third connecting electrodes CEa', CEb', and CEc', can be the same. Similarly, for each second unit light-emitting region UEA2, the shape or arrangement of each of the corresponding first to third connecting electrodes CEa', CEb', and CEc', as well as the arrangement relationship between the first to third connecting electrodes CEa', CEb', and CEc', can be the same.

[0389] As described above, the display device DD may include a separator SPR'.

[0390] The separator SPR' can be set in the pixel-limiting layer PDL (see Figure 29 In embodiments, the separator SPR' may comprise an organic insulating material. For example, the separator SPR' may comprise a photosensitive resin (e.g., photoresist). However, this disclosure is not limited thereto.

[0391] The second electrode layer E2' can be separated (or disconnected) by the separator SPR' into second electrodes E2a', E2b', and E2c'. That is, the second electrode E2a' of the first light-emitting element LEDa', the second electrode E2b' of the second light-emitting element LEDb', and the second electrode E2c' of the third light-emitting element LEDc' can be electrically independent of each other through the separator SPR'.

[0392] The separator SPR' may define first to third opening regions OA1, OA2, and OA3, respectively, corresponding to the second electrodes E2a', E2b', and E2c'. For example, the separator SPR' may have a grid pattern surrounding the second electrodes E2a', E2b', and E2c' in a planar view. The second electrode E2a' of the first light-emitting element LEDa' may be disposed in the first opening region OA1 of the separator SPR', the second electrode E2b' of the second light-emitting element LEDb' may be disposed in the second opening region OA2 of the separator SPR', and the second electrode E2c' of the third light-emitting element LEDc' may be disposed in the third opening region OA3 of the separator SPR'.

[0393] In an embodiment, the outline of the first opening region OA1 in the plan view may be substantially the same as the outline of the second electrode E2a' of the first light-emitting element LEDa', the outline of the second opening region OA2 in the plan view may be substantially the same as the outline of the second electrode E2b' of the second light-emitting element LEDb', and the outline of the third opening region OA3 in the plan view may be substantially the same as the outline of the second electrode E2c' of the third light-emitting element LEDc'.

[0394] In the following text, see references Figure 29 A more detailed description will be given based on the first luminescent region EAa. Figures 27 to 29 The following description of the cross-sectional structure of the display device DD is presented in an embodiment. The description of the cross-sectional structure of the display device DD can be applied to other light-emitting areas.

[0395] The following description will focus on the reference. Figure 5 The differences in the cross-sectional structure of the display device DD in the described embodiments will be omitted or simplified.

[0396] In an embodiment, the display device DD may include a substrate SUB, a first lower conductive layer BML1, a second lower conductive layer BML2, a first transistor TR1, a second transistor TR2, a first capacitor CAP1, a second capacitor CAP2, a first connecting electrode CEa', first to sixth insulating layers IL1, IL2, IL3, IL4, IL5 and IL6, a pixel defining layer PDL, a first light-emitting element LEDa', a separator SPR', a first dummy layer DP1, a second dummy layer DP2 and an encapsulation layer ENC.

[0397] The first connection electrode CEa' can be disposed on the fifth insulating layer IL5. As described above, the first connection electrode CEa' can be connected to the first transistor TR1. Specifically, the first connection electrode CEa' can contact the first transistor TR1 through a contact hole CNT extending through the fifth insulating layer IL5. Accordingly, the position of the first circuit connection portion CPa' can correspond to the position of the contact hole CNT.

[0398] The first connecting electrode CEa' may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, and transparent conductive oxide. In embodiments, the first connecting electrode CEa' may have a multilayer structure in which multiple conductive layers are stacked. For example, the first connecting electrode CEa' may include a first conductive layer CL1, a second conductive layer CL2, and a third conductive layer CL3 stacked sequentially.

[0399] In this embodiment, the first conductive layer CL1 may comprise a metal and / or a transparent conductive oxide. Examples of metals suitable for use as the first conductive layer CL1 include titanium (Ti) and molybdenum (Mo). Examples of transparent conductive oxides suitable for use as the first conductive layer CL1 include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (InO), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). Compared to the second conductive layer CL2, the first conductive layer CL1 may have a relatively thin thickness.

[0400] The second conductive layer CL2 may include a material different from that of the first conductive layer CL1. For example, the second conductive layer CL2 may include a metal different from that of the first conductive layer CL1. Examples of metals that can be used as the second conductive layer CL2 may include aluminum (Al) and copper (Cu). Compared to the first conductive layer CL1, the second conductive layer CL2 may have a relatively thicker thickness.

[0401] The third conductive layer CL3 may comprise a material different from that of the second conductive layer CL2. For example, the third conductive layer CL3 may comprise a metal and / or a transparent conductive oxide different from the second conductive layer CL2. Examples of metals that can be used as the third conductive layer CL3 include titanium (Ti) and molybdenum (Mo). Examples of transparent conductive oxides that can be used as the third conductive layer CL3 include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (InO), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). Compared to the second conductive layer CL2, the third conductive layer CL3 may have a relatively thin thickness.

[0402] In some embodiments, the first conductive layer CL1 and the third conductive layer CL3 may comprise the same material. However, this disclosure is not limited thereto.

[0403] The side surfaces CL1-S of the first conductive layer CL1 and CL3-S of the third conductive layer CL3 can extend beyond the side surface CL2-S of the second conductive layer CL2. Accordingly, the first connecting electrode CEa' can have a pointed structure due to the portion of the third conductive layer CL3 protruding beyond the second conductive layer CL2. For example, based on the same etching process, when the second conductive layer CL2 is etched using an etching material that has a higher etching rate than that used on the first and third conductive layers CL1 and CL3, the first connecting electrode CEa' can be formed with a pointed structure.

[0404] In addition, Figure 29 In the diagram, the first connecting electrode CEa' is shown as a three-layer structure having first to third conductive layers CL1, CL2, and CL3 stacked. However, this disclosure is not limited to this structure, and the first connecting electrode CEa' may have a two-layer structure having second conductive layer CL2 and third conductive layer CL3 stacked. That is, the first conductive layer CL1 may be omitted.

[0405] The sixth insulating layer IL6 may partially cover the first connecting electrode CEa' and may be disposed on the fifth insulating layer IL5. That is, the sixth insulating layer IL6 may define a first sub-opening SO1' that exposes at least a portion of the first connecting electrode CEa'. Specifically, the first sub-opening SO1' may expose the tip structure of the first connecting electrode CEa'.

[0406] The pixel-defining layer PDL can further define a second sub-opening SO2' corresponding to the first sub-opening SO1' of the sixth insulating layer IL6. In a plan view, the second sub-opening SO2' can overlap with the first sub-opening SO1', and the first sub-opening SO1' and the second sub-opening SO2' can be spatially connected to each other. That is, an opening OP' formed by the first sub-opening SO1' and the second sub-opening SO2' can be defined, wherein at least a portion of the first connecting electrode CEa' is at the bottom of the opening OP'. Specifically, the tip structure of the first connecting electrode CEa' can be located in the opening OP'.

[0407] The separator SPR' can be disposed on the pixel definition layer PDL. The separator SPR' can have a shape in which the width of the upper part is greater than the width of the lower part. That is, the separator SPR' connecting the upper surface and the lower surface of the separator SPR' can have a tapered cross-section including inclined side surfaces. In other words, at least a portion of the cross-section of the separator SPR' can be trapezoidal.

[0408] Figure 29 The side surface of a separator SPR' having a tapered cross-section including inclined side surfaces is depicted. However, this disclosure is not limited to this structure, and the separator SPR' may have multiple inclined side surfaces. For example, the separator SPR' may have a double-tapered structure.

[0409] An intermediate layer ML' may be disposed on the first electrode layer E1 and the pixel defining layer PDL. A portion of the intermediate layer ML' may be disposed within a pixel opening of the pixel defining layer PDL. In an embodiment, the intermediate layer ML' may include a first functional layer comprising an organic material, a light-emitting layer disposed on the first functional layer and comprising a light-emitting material, and a second functional layer disposed on the light-emitting layer and comprising an organic material. For example, the first functional layer may include a hole injection layer and a hole transport layer, and the second functional layer may include an electron transport layer and an electron injection layer, etc.

[0410] A shaded area may exist around the separator SPR' with its tapered, inclined surface, making it difficult to deposit the intermediate layer ML'. Accordingly, the intermediate layer ML' in and / or around the shaded area may have a structure separated from the separator SPR'. For example, the first and second functional layers included in the intermediate layer ML' may have a structure separated from the separator SPR'.

[0411] The first dummy layer DP1 can be disposed on the separator SPR'. The first dummy layer DP1 can be formed by having a structure in which the intermediate layer ML' is separated by the separator SPR'. That is, the first dummy layer DP1 can be formed in the same process as the intermediate layer ML'. In an embodiment, the first dummy layer DP1 can be omitted.

[0412] The intermediate layer ML' can also be separated (or disconnected) by the tip structure of the first connecting electrode CEa'. Because the intermediate layer ML' is separated (or blocked) by the tip structure of the first connecting electrode CEa', at least a portion of the side surface CL2-S of the second conductive layer CL2 can be exposed. Accordingly, the second electrode E2a' of the first light-emitting element LEDa' can be electrically connected to the second conductive layer CL2.

[0413] The second electrode layer E2' (i.e., the second electrodes E2a', E2b', and E2c') can be disposed on the intermediate layer ML'. The second electrode layer E2' (i.e., the second electrodes E2a', E2b', and E2c') can include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, and transparent conductive oxides. In embodiments, the second electrode layer E2' (i.e., the second electrodes E2a', E2b', and E2c') can have a single-layer structure. However, this disclosure is not limited to this, and the second electrode layer E2' (i.e., the second electrodes E2a', E2b', and E2c') can have a multilayer structure in which multiple conductive layers are stacked. For example, the second electrode layer E2' (i.e., the second electrodes E2a', E2b', and E2c') can have a two-layer structure in which a first sub-electrode layer including a metallic material and a second sub-electrode layer disposed on the first sub-electrode layer and including a transparent conductive oxide are stacked.

[0414] A shaded region may exist around the separator SPR', which has a tapered, sloping side surface, making it difficult to deposit the second electrode layer E2'. Accordingly, the second electrode layer E2' in and / or around the shaded region may have a structure that is interrupted by the separator SPR'. For example, as... Figure 28 As shown, the second electrode layer E2' can be disconnected into the second electrode E2a' of the first light-emitting element LEDa' disposed in the first opening region OA1 of the separator SPR', the second electrode E2b' of the second light-emitting element LEDb' disposed in the second opening region OA2 of the separator SPR', and the second electrode E2c' of the third light-emitting element LEDc' disposed in the third opening region OA3 of the separator SPR'. That is, the second electrodes E2a', E2b', and E2c' can be electrically independent of each other.

[0415] like Figure 29As shown, the second electrode E2a' of the first light-emitting element LEDa' can be connected to the first connecting electrode CEa'. For example, the second electrode E2a' can contact the side surface CL2-S of the second conductive layer CL2. For example, when the deposition angle of the deposition process used to form the second electrode layer E2' is set to be greater than the deposition angle of the deposition process used to form the intermediate layer ML', the second electrode layer E2' (specifically, the second electrode E2a') can cover the intermediate layer ML' disconnected by the tip structure and can be formed to connect to the side surface CL2-S of the second conductive layer CL2. As a result, the second electrode E2a' can be connected to the first transistor TR1 through the first connecting electrode CEa'.

[0416] In one embodiment, the second electrode layer E2' (specifically, the second electrode E2a') can be disconnected by the tip structure of the first connecting electrode CEa'. However, this disclosure is not limited thereto, and the second electrode layer E2' (specifically, the second electrode E2a') can be formed to extend without being disconnected by the tip structure.

[0417] Simultaneously, the second dummy layer DP2 can be disposed on the separator SPR'. Specifically, the second dummy layer DP2 can be disposed on the first dummy layer DP1. The second dummy layer DP2 can be formed by having a structure in which the second electrode layer E2' is disconnected by the separator SPR'. That is, the second dummy layer DP2 can be formed in the same process as the second electrode layer E2'. In embodiments, the second dummy layer DP2 can be omitted.

[0418] According to embodiments of this disclosure, the display device DD may include connection electrodes CEa', CEb', and CEc' with pointed structures and a separator SPR'. Accordingly, a second electrode layer E2' (e.g., cathode) disposed on the first electrode layer E1 (e.g., anode) can be easily connected to pixel driving circuit sections PCa, PCb, and PCc. Specifically, the second electrode layer E2' disposed on the first electrode layer E1 can be connected to the driving transistors (e.g., ...) of each of the pixel driving circuit sections PCa, PCb, and PCc via the connection electrodes CEa', CEb', and CEc'. Figures 2a to 2c The drain of the first transistor T1. Accordingly, even when the light-emitting element deteriorates, the gate-source voltage (Vgs) of the driving transistor will not change. Accordingly, the amount of change in driving current due to the deterioration of the light-emitting element can be reduced. Accordingly, the afterimage defects of the display device DD with increasing usage time can be reduced, and the lifespan of the display device DD can be improved.

[0419] Figure 30 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0420] refer to Figure 30The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0421] The display device according to the embodiment (e.g., Figures 1a to 29 The display device DD (or DDa) can be applied to various electronic devices 10. The electronic device 10 may include the aforementioned display device, and in addition to the display device, may further include modules or devices with additional functions.

[0422] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0423] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals can be sent to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0424] The power module 14 may include a power supply module such as a power adapter or battery device, and a power supply conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10. Specifically, the power module 14 can convert power (e.g., Figures 2a to 2c The ELVSS and ELVDD are supplied to the display device.

[0425] At least one of each component of the electronic device 10 described above can be included in the display device according to the above embodiment. Additionally, some modules that are functionally included in a single module can be included in the display device, and other components can be provided separately from the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided as other devices within the electronic device 10 besides the display device. In other words, the processor 12 can provide image data signals and input control signals to the display device to control the display device.

[0426] Figure 31 This is a schematic diagram illustrating an electronic device according to various embodiments.

[0427] refer to Figure 31 The display device according to the embodiment (e.g., Figures 1a to 29The various electronic devices 10 to which the display device DD (or DDa) is applied can include not only image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptops 10_1c, TVs 10_1d, and desktop monitors 10_1e, but also wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c, or automotive electronic devices including display modules such as car dashboards, central instrument panels, central information displays (CID) mounted on dashboards, and interior mirror displays.

[0428] Although this disclosure has been described with reference to embodiments, those skilled in the art will understand that various modifications and alterations can be made to this disclosure without departing from the spirit and scope of this disclosure as set forth in the claims. [Industrial Applicability]

[0429] This disclosure can be applied to display devices and electronic devices including such display devices. For example, this disclosure can be applied to high-resolution smartphones, mobile phones, smart tablets, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer monitors, and laptop computers, etc.

[0430] <Explanation of reference numerals in the attached figures>

[0431] DD, DDa: Display devices

[0432] DA: Display Area

[0433] NDA: Non-display area

[0434] SUB: Substrate

[0435] PX: pixel

[0436] GL: gate line

[0437] DL: Data cable

[0438] DDV: Data Drive

[0439] GDV: Gate Driver

[0440] LED: Light-emitting element

[0441] PC, PC', PC'': Pixel driver circuit section

[0442] UEA1: First unit luminous area

[0443] UEA2: Second unit luminous area

[0444] EAa, EAb, EAc: First to third luminous regions

[0445] PCU: Unit Circuit Area

[0446] PCa, PCb, PCc: First to third pixel driving circuit section

[0447] LEDa, LEDa': First light-emitting element

[0448] LEDb, LEDb': Second light-emitting element

[0449] LEDc, LEDc': Third light-emitting element

[0450] CEa, CEa': First connecting electrode

[0451] CEb, CEb': Second connecting electrodes

[0452] CEc, CEc': Third connecting electrode

[0453] CNPa: First Connection Pattern

[0454] CNPb: Second connection pattern

[0455] CNPc: Third connection pattern

[0456] CPa, CPa': First circuit connection part

[0457] CPb, CPb': Second circuit connection part

[0458] CPc, CPc': Third circuit connection part

[0459] CNa, CNa': First luminescent connecting part

[0460] CNb, CNb': Second light-emitting connecting part

[0461] CNc, CNc': Third light-emitting connecting part

[0462] CL1: First conductive layer

[0463] CL2: Second conductive layer

[0464] CL3: Third conductive layer

[0465] SE1, DE1, SE2, DE2: First to fourth contact electrodes

[0466] IL1, IL2, IL3, IL4, IL5, IL6: First to sixth insulating layers

[0467] PDL: Pixel Limiting Layer

[0468] CNT: Contact Hole

[0469] CNT1, CNT2, CNT3, CNT4, CNT5, CNT6: First to sixth contact holes

[0470] SO1, SO1': First sub-opening

[0471] SO2, SO2': Second sub-opening

[0472] OP, OP': Opening

[0473] E1, E1', E1'', E1''', E1''': First electrode layer

[0474] E1a, E1b, E1c: First electrode

[0475] BR1: First Bridge

[0476] BR2: Second Bridge

[0477] EL1: First electrode line

[0478] EL2: Second electrode line

[0479] EP: Electrode Pattern

[0480] ML, ML': intermediate layer

[0481] E2, E2': Second electrode layer

[0482] E2a, E2a', E2b, E2b', E2c, E2c': Second electrode

[0483] TLG, TLG', TLG'': Transmission line group

[0484] TL1: First transmission line

[0485] TL2: Second transmission line

[0486] SPR, SPR': separator

[0487] OA1, OA2, OA3: First to third opening areas

[0488] ENC: Encapsulation layer

[0489] IEL1: First Inorganic Encapsulation Layer

[0490] OEL: Organic Encapsulation Layer

[0491] IEL2: Second Inorganic Encapsulation Layer

Claims

1. A display device, comprising: The pixel driving circuit section includes transistors; A connecting electrode is located on the pixel driving circuit section and electrically connected to the transistor of the pixel driving circuit section; A first electrode layer is located on the connection electrode, the first electrode layer receives a power supply voltage and includes a plurality of first electrodes; The transmission line group is located in a different layer from the first electrode layer, is electrically connected to the first electrode layer, and forms a mesh structure with the first electrode layer in the plan view; The separator is located on the first electrode layer; as well as The second electrode layer is located on the first electrode layer and is separated into a plurality of second electrodes by the separator.

2. The display device according to claim 1, wherein, The first electrode layer is connected to receive the power supply voltage via the transmission line group.

3. The display device according to claim 1, wherein, The first electrode layer has a grid pattern in which the plurality of first electrodes extending in different directions are integrally connected.

4. The display device according to claim 3, wherein, The transmission line group includes multiple transmission lines that extend in one direction and are arranged in intersecting directions that are not parallel to the one direction.

5. The display device according to claim 4, wherein, The transistor includes: Active patterns, including semiconductor materials; The gate electrode is located on the active pattern; and A contact electrode is located on the gate electrode and contacts the active pattern, and The multiple transmission lines are located in the same layer as the contact electrodes.

6. The display device according to claim 4, wherein, The multiple transmission lines and the connecting electrodes are located in the same layer.

7. The display device according to claim 3, wherein, The transmission line group includes: Multiple first transmission lines extend in one direction and are arranged in intersecting directions that are not parallel to said one direction; and Multiple second transmission lines extend in the crossing direction and are arranged in the one direction.

8. The display device according to claim 7, wherein, The transistor includes: Active patterns, including semiconductor materials; The gate electrode is located on the active pattern; and The contact electrode is located on the gate electrode and contacts the active pattern. The plurality of first transmission lines are located in the same layer as the contact electrodes, and The multiple second transmission lines are located in the same layer as the connecting electrodes.

9. The display device according to claim 1, wherein, The first electrode layer includes multiple electrode lines extending in one direction and arranged in intersecting directions that are not parallel to said one direction. The multiple electrode lines are physically separated from each other, and Each of the plurality of electrode lines has a structure in which some of the plurality of first electrodes extending in different directions are integrally connected.

10. The display device according to claim 1, wherein, The first electrode layer includes a plurality of electrode patterns arranged in one direction and in intersecting directions that are not parallel to the one direction. The plurality of electrode patterns are physically separated from each other, and Each of the plurality of electrode patterns has a structure in which some of the plurality of first electrodes are integrally connected.

11. The display device according to claim 10, wherein, The transmission line group includes: Multiple first transmission lines extend in said one direction and are arranged in said intersecting directions; and Multiple second transmission lines extend in the crossing direction and are arranged in the one direction.

12. The display device according to claim 11, wherein, The plurality of first transmission lines and the plurality of second transmission lines are connected to at least one of the plurality of electrode patterns, and The plurality of first transmission lines, the plurality of second transmission lines, and the plurality of electrode patterns form the grid structure.

13. The display device according to claim 11, wherein, The plurality of electrode patterns are electrically connected to each other through the plurality of first transmission lines and the plurality of second transmission lines.

14. The display device according to claim 12, wherein, The transistor includes: Active patterns, including semiconductor materials; The gate electrode is located on the active pattern; and The contact electrode is located on the gate electrode and contacts the active pattern. The plurality of first transmission lines are located in the same layer as the contact electrodes, and The multiple second transmission lines are located in the same layer as the connecting electrodes.

15. The display device according to claim 1, wherein, The plurality of first electrodes are arranged in one direction and in intersecting directions that are not parallel to the one direction, and The plurality of first electrodes are physically separated from each other.

16. The display device according to claim 1, further comprising: An intermediate layer, located between the first electrode layer and the second electrode layer, includes a luminescent material.

17. The display device according to claim 1, wherein, At least one of the plurality of second electrodes is electrically connected to the connection electrode and is electrically connected to the transistor of the pixel driving circuit section through the connection electrode.

18. A display device, comprising: The pixel driving circuit section includes transistors; A connecting electrode is located on the pixel driving circuit section and electrically connected to the transistor of the pixel driving circuit section; A first electrode layer is located on the connection electrode, the first electrode layer receives a power supply voltage and includes a plurality of first electrodes; The transmission line group is located in a different layer from the first electrode layer, is electrically connected to the first electrode layer, and forms a mesh structure with the first electrode layer in the plan view; A pixel defining layer is located on the first electrode layer and defines the light-emitting area; A connection pattern is electrically connected to the connection electrode and surrounds the light-emitting area in the planar diagram; A separator is located on the pixel defining layer and the connection pattern and covers at least a portion of the connection pattern; as well as The second electrode layer is located on the first electrode layer and is separated into a plurality of second electrodes by the separator.

19. The display device according to claim 18, wherein, At least one of the plurality of second electrodes contacts the connection pattern at a position adjacent to or overlapping with the separator, and is electrically connected to the transistor of the pixel driving circuit section through the connection electrode and the connection pattern.

20. An electronic device comprising: The display device includes: The pixel driving circuit section includes transistors; A connecting electrode is located on the pixel driving circuit section and electrically connected to the transistor of the pixel driving circuit section; A first electrode layer is located on the connection electrode, the first electrode layer receives a power supply voltage and includes a plurality of first electrodes; The transmission line group is located in a different layer from the first electrode layer, is electrically connected to the first electrode layer, and forms a mesh structure with the first electrode layer in the plan view; The separator is located on the first electrode layer; and A second electrode layer, located on the first electrode layer and separated into a plurality of second electrodes by the separator; and The power module supplies the power voltage to the display device.

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