Case-to-earbud communication without interrupting charging

Abstract

An electronic device includes an input terminal and a data receiver coupled to the input terminal. The electronic device also includes a battery coupled to the input terminal. The data receiver includes a high pass filter coupled between the input terminal and an input of a comparator that produces a digital receive signal when a modulated charging voltage drives the input terminal.

Description

Technical Field

[0001] This application relates to electronic devices, and more specifically to data communication between the earphone case and the earphone without interrupting the charging of the earphone's battery. Background Technology

[0002] The battery in earbuds (in-ear headphones) is typically charged when the earbuds are received by the charging case. For example, earbuds will typically include input terminals that make electrical contact with corresponding output terminals in the case. Since earbuds usually have a limited number of terminals (e.g., only input terminals and a ground terminal), the input terminals are used not only to receive charging voltage during charging mode but also to receive data signals during data mode. However, charging the battery within the earbuds typically requires a higher voltage level for charging, such as greater than 3.3 volts. Such a higher voltage may not be suitable for the data receiver in the earbuds. Therefore, the charging mode and data mode of the earbuds are typically non-concurrent. The charging mode can then be interrupted by the data mode, which prolongs the charging time. Summary of the Invention

[0003] According to one aspect of this disclosure, an electronic device is provided, comprising: an input terminal for receiving a charging voltage; a first voltage divider configured to divide a power supply voltage into a divided voltage at a first node; a second voltage divider configured to divide the power supply voltage into a divided voltage at a second node; a high-pass filter including a high-pass filter capacitor coupled between the input terminal and the first node; and a comparator configured to compare the voltage at the first node with the voltage at the second node to form a digital received signal.

[0004] According to another aspect of this disclosure, a method for receiving data from a charging voltage to an electronic device is provided, the method comprising: high-pass filtering a modulated charging voltage to form a high-pass filtered voltage; combining the high-pass filtered voltage with a common-mode voltage to form a combined voltage; and comparing the combined voltage with the common-mode voltage to form a digital received signal when charging a battery in the electronic device using the modulated charging voltage.

[0005] According to another aspect of this disclosure, an earbud is provided, the earbud comprising: an input terminal; a charging rail for charging voltage; an input switch coupled between the input terminal and the charging rail; and a data receiver coupled to the input terminal, wherein the data receiver includes a comparator and a high-pass filter coupled between the input terminal and a first input portion of the comparator.

[0006] These and other advantageous features can be better understood through the detailed description below. Attached Figure Description

[0007] Figure 1 This is a diagram of a case including earplugs according to one aspect of this disclosure.

[0008] Figure 2 This is a circuit diagram of an earphone data receiver circuit according to one aspect of this disclosure.

[0009] Figure 3 An earphone charging voltage waveform modulated by a data signal is illustrated according to one aspect of this disclosure.

[0010] Figure 4 An internal node voltage waveform of a data receiver circuit according to one aspect of this disclosure is illustrated.

[0011] Figure 5 This is a circuit diagram of an earphone data receiver circuit according to one aspect of this disclosure.

[0012] Figure 6 This is a flowchart of an earplug operation method according to one aspect of this disclosure.

[0013] The specific embodiments of this disclosure and its advantages can be best understood by referring to the following detailed description. It should be understood that similar reference numerals are used to identify similar elements illustrated in one or more of the figures. Detailed Implementation

[0014] The inability to charge the earbuds while data is being transferred can prolong battery charging time and thus reduce user satisfaction. To address this issue, an advantageous earbud is disclosed in which data communication from the case to the earbud is possible while the earbud is being charged. Before discussing the advantageous earbud disclosed herein in further detail, some design challenges will first be discussed. It should be noted that earbuds are not typically charged via interfaces that support simultaneous data communication and battery charging, such as Universal Serial Bus (USB) interfaces. For example, earbuds are often too small for such interfaces. Furthermore, the use of a USB interface complicates the simplicity and ease with which a user could simply place the earbuds in the case and close the lid to begin charging. Regarding its electrical coupling with the case, the earbuds typically have a limited number of terminals (e.g., only two terminals). In the case of only two terminals, one terminal is typically a ground terminal, and the other terminal is an input terminal. Therefore, the input terminal is used to receive both the charging voltage and the data signal. The data encoded within the data signal is also referred to herein as a digital message. During charging mode, the input terminal receives the charging voltage (VCHG) for charging the battery in the earbud. Because of the relatively high charging voltage, it is unsuitable for high-speed data communication, as such a high voltage could damage the high-speed data receiver in the earbud. During high-speed data mode (e.g., data transmission at a clock rate of 1.5 MHz), the input terminals can therefore receive high-speed data signals with a lower voltage compared to the charging voltage.

[0015] During charging mode, the charging voltage at the input terminal is coupled to the internal charging rail or node via an input switch in the earbud. For example, the earbud may have an integrated circuit with charging pins or terminals coupled to the internal charging rail for receiving the charging voltage. However, during high-speed data mode, the reduced voltage of the high-speed data signal is generally not suitable for charging the earbud's battery. Therefore, during high-speed data mode, the earbud may disconnect the input switch to isolate the internal charging rail from the input terminal. A typical earbud can then operate in high-speed data mode, where the input switch is disconnected. However, such high-speed data mode subsequently increases charging time because charging cannot occur while the input switch isolates the internal charging rail from the input terminal.

[0016] To reduce charging time and thus increase user satisfaction while still transmitting data to the earbuds, an improved earbud is disclosed that allows the input switch to close during data mode, enabling the improved earbuds to be charged while receiving data. Therefore, during such data mode, the charging voltage is modulated using the data to be transmitted. Although low-speed data transmission and high-speed data transmission are relative concepts, without loss of generality, the resulting data mode is referred to herein as low-speed data mode. Since the input switch is closed during low-speed data mode, the charging voltage (VCHG) from the power converter (such as a buck / boost switching power converter) in the earbud case flows through the output terminals of the case and then through the input terminals and the input switch to reach the charging rails of the earbuds. It should be noted that the charging voltage will typically vary over a fairly wide range. For example, in some specific embodiments, the charging voltage may vary between 3.3V and 6.5V. This variation in charging voltage depends on various factors, including the state of charge of the earbud battery. If the earbud battery is discharged, the charging voltage begins charging at the lower end of its charging range and then increases as the earbud battery becomes increasingly charged.

[0017] Since the charging voltage is therefore related to the state of charge of the earbud battery, modulation of the charging voltage should not significantly affect its average value. Therefore, the following discussion will involve pulse modulation of the charging voltage such that the charging voltage increases from its DC value by a relatively small voltage increment (e.g., 100mV) or decreases from its DC value by a relatively small voltage decrement (e.g., -100mV). In this way, a 200mV difference exists between the increasing and decreasing states of modulation, making it easy to detect binary transitions in the modulation. However, it should be understood that other increment / decrement values ​​in the modulation of the charging voltage may be used in alternative embodiments.

[0018] The following discussion will involve various example earbuds, each capable of receiving data via an input terminal while the battery within the earbud is charging via the input terminal. However, it should be understood that any suitable electronic device (e.g., a smartwatch) that receives charging voltage and also data via the input terminal may advantageously include the data receiver discussed herein. Figure 1The diagram illustrates a case 100 that encapsulates or otherwise receives example earbud 101. Case 100 includes a switching power converter (such as a buck / boost switching power converter 120) that generates an unmodulated version of the charging voltage VCHG from the battery voltage of the case battery 115 during charging mode. During low-speed data mode, the buck / boost converter 120 modulates the unmodulated charging voltage in response to the input data stream to produce a modulated charging voltage at the case's output terminal 135. However, it should be understood that in alternative embodiments, a separate modulator may be used to modulate the charging voltage. As previously discussed, earbud 101 does not support interfaces (such as USB interfaces) that include parallel data and power paths to earbud 101. Such parallel and separate paths would make simultaneous power and data transmission a common practice. However, earbud 101 does not have the option to use such an interface, as previously discussed. Instead, earbud 101 is coupled via input terminal 130 to output terminal 135 for receiving both data and the charging voltage.

[0019] Earbud 101 can charge earbud battery 160 not only during charging mode (no data transmission) but also during low-speed data mode. Input terminal 130 is coupled to charging rail or node 140 via input switch 125. Earbud 101 includes at least one integrated circuit 105 having a charging terminal 145 coupled to charging rail 140 for receiving charging voltage (VCHG). During high-speed data mode, integrated circuit 105 uses a gate control (CTRL) signal to drive gate control terminal 150 to disconnect input switch 125. In this way, the charging terminal is isolated from the charging voltage during high-speed mode. Input terminal 130 is also coupled to communication (Comm in) terminal 155 of integrated circuit 105. A transmitter (not shown) in cartridge 100 can then drive high-speed data signals via output terminal 135, input terminal 130, and communication terminal to drive a high-speed receiver (not shown) within integrated circuit 105.

[0020] As previously discussed, the high-speed data signal has a voltage too low to charge the earbud battery. Therefore, switch 125 is open during high-speed data mode to prevent incorrect charging states of the earbud battery. In some implementations, the high-speed data signal may alternate between ground and a maximum voltage of 1.8V, and therefore cannot be used for battery charging while receiving data at high speed. Switch 125 is open during high-speed data mode to isolate any capacitance at charging terminal 140 from loading the incoming data signal. To prevent the resulting increase in charging time, data can alternatively be transmitted to earbud 101 during low-speed data mode. Unlike high-speed data mode, switch 125 is closed during low-speed data mode. Therefore, integrated circuit 105 does not interrupt the gate control signal during low-speed data mode, allowing continued charging of the earbud battery.

[0021] During low-speed data mode, the modulated charging voltage is coupled to charging terminal 145 via switch 125. Integrated circuit 105 may include charging circuitry 165 (e.g., a switching power converter) coupled between charging terminal 145 and battery terminal 170 to control charging of battery 160 during low-speed data mode. Simultaneously, the modulated charging voltage is coupled from input terminal 130 to low-speed receiver 110 via communication terminal 155. The modulation of the charging voltage may be in response to a clock signal (not illustrated) having a varying rate (e.g., from 1 kHz to 5 kHz). Within each cycle of the varying clock signal, a binary one or binary zero may be modulated according to a pulse width defining a duty cycle. Like the clock rate, the duty cycle can vary and therefore cannot be guaranteed to be 50%. The varying clock rate and duty cycle make the design of low-speed data receiver 110 challenging. For example, the low-speed data receiver may be a low-pass filter-based receiver. In such receivers, the modulated charging voltage may be divided to form a voltage divider. The comparator can then compare the low-pass filtered version of the divided voltage with the divided voltage to form a digital received signal. However, it should be noted that the average value of the modulated charging voltage will depend on its duty cycle. If the pulse-high state of the modulated charging voltage exceeds its pulse-low state, the low-pass filter may then incorrectly detect the correct average value. Furthermore, if the clock frequency used for modulation of the charging voltage is too low, the average value may oscillate. Additionally, the time constant of the low-pass filter may require relatively large resistors and capacitors, which increases manufacturing costs. Moreover, the time constant required by the low-pass filter may result in a slower turn-on time for the low-speed receiver 110.

[0022] In another option for designing the low-speed receiver 110, the voltage divider can be processed by a peak detector and a subtractor circuit to generate a reference voltage. A comparator can then compare the divided voltage with the reference voltage to generate a digital received signal. However, such a method can be relatively complex and consume a significant amount of power.

[0023] In another approach to designing the low-speed receiver 110, a fully differential operational amplifier can be used. However, given the relatively large dynamic range of the DC value of the modulated charging voltage (e.g., from 3.3V to 6.5V), the implementation of a fully differential operational amplifier may require dynamic tracking of the DC value, which can be complex to implement.

[0024] Given all these challenges, such as Figure 2 As shown, an advantageous low-speed data receiver 200 based on a high-pass filter is disclosed. A high-pass filter (HPF) 205 filters a modulated charging voltage (VCHG) to drive an internal node Vm of a first voltage divider 210 formed by resistors R1 and R2. Resistor R1 is coupled between a power node for the earphone power supply voltage VDD and the internal node Vm. The earphone power supply voltage VDD can be a well-regulated voltage generated within the earphone integrated circuit 105, such as through a switching converter or linear regulator. Resistor R2 is coupled between the internal node Vm and ground. Therefore, the internal node Vm is charged to a combination of a divided version of the power supply voltage VDD and a high-pass filtered version of the modulated charging voltage VCHG. More generally, the voltage at the internal node Vm is equal to the sum of the high-pass filtered voltage from the high-pass filter 205 and the common-mode voltage generated by the voltage division of the earphone power supply voltage VDD.

[0025] To better understand the advantages of high-pass filtering of modulated charging voltage, we will now discuss... Figure 3 and Figure 4 The waveform. Figure 3 An example waveform of the modulated charging voltage VCHG is illustrated. At time t0, the modulation switches from a pulse low state to a pulse high state. As previously discussed, the modulation should not cause the desired DC (average) voltage from VCHG to swing too high or too low. In a specific embodiment where the pulse high state is 100mV greater than the DC voltage and the pulse low state of the modulated charging voltage is 100mV lower than the DC voltage, the modulated charging voltage thus increases by 200mV at time t0. At time t1, the modulated charging voltage subsequently decreases by 200mV to transition from the pulse high state back to the pulse low state. It should be noted that in alternative embodiments, the increase and / or decrease from the DC voltage may be greater than or less than 100mV. The DC voltage may vary over a relatively wide range (such as 3.3V to 6.5V), as previously noted.

[0026] like Figure 4As shown, the Vm node voltage waveform has a DC value equal to a voltage divider version of the supply voltage VDD. This DC value can also be represented as a common-mode voltage. At time t0, the rising edge of the modulated charging voltage passes through the high-pass filter 205, causing the Vm node voltage pulse to go high. Then, due to the falling edge of the modulated charging voltage passing through the high-pass filter 205, the Vm node voltage drops to its DC value before the pulse goes low at time t1. The resulting Vm node voltage can be advantageously sensed to recover the transmitted bit. In this respect, as... Figure 2 The second voltage divider 215 shown can also generate a divided version of the supply voltage VDD at the internal node Vp. The second voltage divider 215 is formed by resistors R3 and R4. Resistor R3 is coupled between the supply node for the earphone supply voltage VDD and the internal node Vp. Resistor R4 is coupled between the internal node Vp and ground. The voltage divisions in voltage dividers 210 and 215 are ideally identical / balanced, such that the voltage at the internal node Vp is equal to the common-mode voltage at the internal node Vm.

[0027] Comparator 220, powered by the earphone power supply voltage VDD, has an inverting input coupled to an internal node Vm and a non-inverting input coupled to an internal node Vp. More generally, the comparator has a first input coupled to an internal node Vm and a second input coupled to an internal node Vp. The internal node Vm may also be referred to herein as the first node, and the internal node Vp as the second node. Given this coupling to the inputs of comparator 220, comparator 220 generates a digital receive signal that pulses high to VDD at the falling edge of the modulated charging voltage and discharges to ground at the rising edge of the modulated charging voltage. Note that this convention can be reversed if the internal node Vm is instead coupled to the non-inverting input and the internal node Vp is coupled to the inverting input. In such an embodiment, the digital receive signal from comparator 220 will pulse high to VDD at the rising edge of the modulated charging voltage and discharge to ground at the falling edge of the modulated charging voltage.

[0028] The resulting recovery of the transmitted bits from the digital received signal from comparator 220 by earpiece 101 is highly advantageous because it is substantially independent of the clock frequency and duty cycle of the charging voltage. Furthermore, the high-pass filter 205 does not draw DC current. Additionally, no reference voltage generation is required, and the low-speed data receiver only needs the earpiece power supply voltage VDD for its power. The amount of time required to fully pulse the Vm node voltage of the high-pass filter 205 to trigger comparator 220 may depend on the minimum slew rate of the modulated charging voltage (e.g., 10 kV / s in some specific implementations). However, since data transmission is relatively low-speed (e.g., from 1 kHz to 5 kHz), such a minimum slew rate is easily met. Finally, since the low-speed data receiver 200 is a high-pass filter-based receiver, it is insensitive to variations in the DC value of the modulated charging voltage.

[0029] exist Figure 5 The example low-speed receiver 500 is shown in more detail below. The first and second voltage dividers are formed by resistors R1, R2, R3, and R4, and are arranged relative to comparator 220, as shown in the diagram. Figure 2 The low-pass filter 505, formed by resistor R5 and capacitor C1, low-pass filters any high-speed ripple on the modulated charging voltage VCHG and generates a filtered voltage at node 510. Resistor R5 is coupled at input terminal 130 (…). Figure 1 A capacitor C1 is coupled between node 510 and ground. Node 510 also serves as the input node to a high-pass filter 515 formed by a high-pass filter capacitor (Chpf) and a resistor R2. The high-pass filter capacitor is coupled between node 510 and node Vm. To filter out any high-frequency variations from the earphone power supply voltage VDD, capacitor C2 is coupled between node Vm and ground to form a low-pass filter in combination with resistor R1. Similarly, capacitor C3 is coupled between node Vp and ground to form a low-pass filter in combination with resistor R3. In this way, the common-mode voltages of nodes Vm and Vp are substantially unaffected by any high-frequency variations in the earphone power supply voltage VDD. Capacitor C2 is also referred to herein as the first capacitor, and capacitor C3 is also referred to herein as the second capacitor.

[0030] To prevent any residual noise in the Vm and Vp node voltages from affecting the comparison in comparator 220, comparator 220 may have a certain amount of offset (e.g., a minimum offset of 15mV in some embodiments). Similarly, a minimum peak-to-peak voltage variation in the Vm node voltage (e.g., 100mV in some embodiments) ensures that comparator 220 will detect both rising and falling edges in the Vm node voltage. Given this offset, comparator 220 will not interrupt the digital received signal until the Vp node voltage is higher than the Vm node voltage by the offset value or amount (e.g., 15mV). Similarly, comparator 220 will not discharge the digital received signal until the Vm node voltage is higher than the Vp node voltage by the offset value. In addition to the offset, comparator 220 may also have some hysteresis to prevent jitter at the comparator output due to noise coupled from the comparator input.

[0031] Now relative to Figure 6 The flowchart discusses a method for receiving data from a charging voltage to an electronic device according to this disclosure. The method includes the action 600 of modulating the charging voltage to form a modulated charging voltage, the modulated charging voltage alternating between high values ​​greater than the average value of the charging voltage and low values ​​less than the average value of the charging voltage to form the modulated charging voltage. Modulation of the charging voltage VCHG is an example of action 600. The method also includes the action 605 of high-pass filtering the modulated charging voltage to form a high-pass filtered voltage. High-pass filtering performed by high-pass filter 205 or high-pass filter 515 is an example of action 610. The method also includes the action 615 of combining the high-pass filtered voltage with a common-mode voltage to form a combined voltage. Formation of the Vm node voltage in data receiver 500 or data receiver 200 is an example of action 615. Finally, the method includes the action 620 of comparing the combined voltage with the common-mode voltage to form a digital received signal while charging a battery in the electronic device using the modulated charging voltage. Comparison performed by comparator 220 in data receiver 200 or 500 while the battery 160 is charging is an example of action 620.

[0032] This disclosure will now be outlined in the following series of provisions: Clause 1. An electronic device comprising: Input terminal for receiving charging voltage; A first voltage divider is configured to divide the power supply voltage into a divided voltage at a first node; A second voltage divider is configured to divide the power supply voltage into the divided voltage at a second node; A high-pass filter, comprising a high-pass filter capacitor coupled between the input terminal and the first node; and A comparator configured to compare the voltage of the first node with the voltage of the second node to form a digital received signal.

[0033] Clause 2. The electronic device as described in Clause 1, wherein the electronic device includes an earpiece.

[0034] Clause 3. The electronic device according to Clause 2, wherein the earbud includes an integrated circuit, and wherein the comparator is integrated within the integrated circuit.

[0035] Clause 4. The electronic device according to Clause 3, wherein the earplug further comprises: An input switch is coupled between the input terminal and the charging terminal of the integrated circuit.

[0036] Clause 5. The electronic device according to Clause 3, wherein the high-pass filter is coupled to the input terminal via a communication terminal of the integrated circuit.

[0037] Clause 6. The electronic device according to any one of Clauses 1 to 5, wherein the electronic device further comprises: A low-pass filter, which is coupled between the input terminal and the high-pass filter capacitor.

[0038] Clause 7. The electronic device according to any one of Clauses 1 to 6, wherein the electronic device further comprises: A first capacitor is coupled between the first node and ground.

[0039] Clause 8. The electronic device according to any one of Clauses 1 to 7, wherein the electronic device further comprises: The second capacitor is coupled between the second node and ground.

[0040] Clause 9. An electronic device according to any one of Clauses 1 to 8, wherein the comparator is further configured to assert the digital received signal as a first binary value in response to the voltage of the first node exceeding the voltage of the second node by an offset value.

[0041] Clause 10. The electronic device according to Clause 9, wherein the comparator is further configured to assert the digital received signal as a second binary value in response to the voltage of the second node exceeding the voltage of the first node by the offset value.

[0042] Clause 11. The electronic device according to Clause 4, wherein the integrated circuit is configured to disconnect the input switch during a high-speed data mode and close the input switch during a low-speed data mode, wherein the data rate of the high-speed data mode is greater than the data rate of the low-speed data mode.

[0043] Clause 12. The electronic device according to Clause 2, the electronic device further comprising a housing configured to enclose the earpiece, wherein the housing includes an output terminal coupled to the input terminal when the earpiece is enclosed.

[0044] Clause 13. The electronic device according to Clause 12, wherein the case is configured to charge the earbuds using a charging voltage coupled through the output terminal.

[0045] Clause 14. The electronic device according to Clause 13, wherein the box is further configured to modulate the charging voltage using a digital message, and wherein the digital received signal includes the digital message.

[0046] Clause 15. A method for receiving data from a charging voltage to an electronic device, the method comprising: The modulated charging voltage is high-pass filtered to form a high-pass filtered voltage; The high-pass filter voltage is combined with the common-mode voltage to form a combined voltage; and When charging the battery in the electronic device using the modulated charging voltage, the combined voltage is compared with the common-mode voltage to form a digital received signal.

[0047] Clause 16. The method according to Clause 15, wherein high-pass filtering of the modulated charging voltage comprises: The modulated charging voltage is low-pass filtered to form a low-pass filtered modulated charging voltage; and The low-pass filtered modulated charging voltage is then high-pass filtered to form the high-pass filtered voltage.

[0048] Clause 17. The method according to any one of Clauses 15 to 16, the method further comprising: The common-mode voltage is generated by dividing and low-pass filtering the power supply voltage of the electronic device.

[0049] Clause 18. The method according to any one of Clauses 15 to 17, wherein the electronic device includes an earpiece, the method further comprising: When the earbud charges the battery using the modulated charging voltage, digital messages are recovered from the digital received signal.

[0050] Clause 19. The method described in Clause 18, further comprising: The modulated charging voltage is formed by alternately increasing the modulated charging voltage to be equal to the sum of the average charging voltage and a first voltage, and decreasing the modulated charging voltage to be equal to the average charging voltage minus a second voltage.

[0051] Clause 20. The method according to Clause 19, wherein the first voltage is substantially equal to the second voltage.

[0052] Clause 21. The method according to Clause 19, wherein the first voltage is approximately 100mV.

[0053] Clause 22. An earplug, said earplug comprising: Input terminals; A charging rail, wherein the charging rail is used for charging voltage; An input switch, coupled between the input terminal and the charging rail; and A data receiver coupled to the input terminal, wherein the data receiver includes a comparator and a high-pass filter, the high-pass filter being coupled between the input terminal and a first input portion of the comparator.

[0054] Clause 23. The earpiece as described in Clause 22, wherein the data receiver further comprises: A first resistor is coupled between a power supply node and the first input of the comparator; and A second resistor is coupled between the first input of the comparator and ground.

[0055] Clause 24. The earpiece as described in Clause 23, wherein the data receiver further comprises: A third resistor, coupled between the power supply node and the second input of the comparator; and A fourth resistor is coupled between the second input of the comparator and ground.

[0056] Clause 25. The earbud as described in Clause 23, wherein the high-pass filter comprises: The second resistor; and A high-pass filter capacitor is coupled between the input terminal and the first input section of the comparator.

[0057] Clause 26. The earplug as described in Clause 25, further comprising: A low-pass filter, which is coupled between the input terminal and the high-pass filter capacitor.

[0058] Clause 27. The earplug as described in Clause 24, the earplug further comprising: A first capacitor is coupled between the first input of the comparator and ground.

[0059] Clause 28. The earplugs as described in Clause 27, further comprising: The second capacitor is coupled between the second input of the comparator and ground.

[0060] Clause 29. The earbud according to Clause 24, wherein the first input of the comparator is the inverting input of the comparator, and the second input of the comparator is the non-inverting input of the comparator.

[0061] It should be understood that many modifications, substitutions, and variations can be made to the materials, apparatus, configuration, and methods of use of the equipment disclosed herein without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments illustrated and described herein (as they are merely examples), but should be fully equivalent to the appended claims and their functional equivalents.

Claims

1. An electronic device, the electronic device comprising: Input terminal for receiving charging voltage; A first voltage divider is configured to divide the power supply voltage into a divided voltage at a first node; A second voltage divider is configured to divide the power supply voltage into the divided voltage at a second node; A high-pass filter, the high-pass filter including a high-pass filter capacitor coupled between the input terminal and the first node; and A comparator configured to compare the voltage of the first node with the voltage of the second node to form a digital received signal.

2. The electronic device of claim 1, wherein the electronic device includes an earplug.

3. The electronic device of claim 2, wherein the earbud comprises an integrated circuit, and wherein the comparator is integrated within the integrated circuit.

4. The electronic device of claim 3, wherein the earplug further comprises: An input switch is coupled between the input terminal and the charging terminal of the integrated circuit.

5. The electronic device of claim 3, wherein the high-pass filter is coupled to the input terminal via a communication terminal of the integrated circuit.

6. The electronic device according to claim 1, further comprising: A low-pass filter, which is coupled between the input terminal and the high-pass filter capacitor.

7. The electronic device according to claim 1, further comprising: A first capacitor is coupled between the first node and ground.

8. The electronic device according to claim 1, further comprising: The second capacitor is coupled between the second node and ground.

9. The electronic device of claim 1, wherein the comparator is further configured to assert the digital received signal as a first binary value in response to the voltage of the first node being offset by a larger value than the voltage of the second node.

10. The electronic device of claim 9, wherein the comparator is further configured to assert the digital received signal as a second binary value in response to the voltage of the second node being greater than the voltage of the first node by the offset value.

11. The electronic device of claim 4, wherein the integrated circuit is configured to disconnect the input switch during a high-speed data mode and close the input switch during a low-speed data mode, wherein the data rate of the high-speed data mode is greater than the data rate of the low-speed data mode.

12. The electronic device of claim 2, further comprising a housing configured to enclose the earpiece, wherein the housing includes an output terminal coupled to the input terminal when the earpiece is enclosed.

13. The electronic device of claim 12, wherein the housing is configured to charge the earbud using a charging voltage coupled through the output terminal.

14. The electronic device of claim 13, wherein the housing is further configured to modulate the charging voltage using a digital message, and wherein the digital received signal includes the digital message.

15. A method for receiving data from a charging voltage to an electronic device, the method comprising: The modulated charging voltage is high-pass filtered to form a high-pass filtered voltage; The high-pass filter voltage is combined with the common-mode voltage to form a combined voltage; as well as When charging the battery in the electronic device using the modulated charging voltage, the combined voltage is compared with the common-mode voltage to form a digital received signal.

16. The method of claim 15, wherein high-pass filtering of the modulated charging voltage comprises: The modulated charging voltage is low-pass filtered to form a low-pass filtered modulated charging voltage; as well as The low-pass filtered modulated charging voltage is then high-pass filtered to form the high-pass filtered voltage.

17. The method according to claim 15, further comprising: The common-mode voltage is generated by dividing and low-pass filtering the power supply voltage of the electronic device.

18. The method of claim 15, wherein the electronic device includes an earpiece, and the method further comprises: When the earbud charges the battery using the modulated charging voltage, digital messages are recovered from the digital received signal.

19. The method according to claim 18, further comprising: The modulated charging voltage is formed by alternately increasing the modulated charging voltage to be equal to the sum of the average charging voltage and a first voltage, and decreasing the modulated charging voltage to be equal to the average charging voltage minus a second voltage.

20. The method of claim 19, wherein the first voltage is substantially equal to the second voltage.

21. The method of claim 19, wherein the first voltage is approximately 100 mV.

22. An earplug, the earplug comprising: Input terminals; A charging rail, wherein the charging rail is used for charging voltage; An input switch, the input switch being coupled between the input terminal and the charging rail; and A data receiver coupled to the input terminal, wherein the data receiver includes a comparator and a high-pass filter, the high-pass filter being coupled between the input terminal and a first input portion of the comparator.

23. The earplug of claim 22, wherein the data receiver further comprises: A first resistor is coupled between a power supply node and the first input section of the comparator; and A second resistor is coupled between the first input of the comparator and ground.

24. The earplug of claim 23, wherein the data receiver further comprises: A third resistor is coupled between the power supply node and the second input of the comparator; and A fourth resistor is coupled between the second input of the comparator and ground.

25. The earplug of claim 23, wherein the high-pass filter comprises: The second resistor; and A high-pass filter capacitor is coupled between the input terminal and the first input section of the comparator.

26. The earplug of claim 25, further comprising: A low-pass filter, which is coupled between the input terminal and the high-pass filter capacitor.

27. The earplug of claim 24, further comprising: A first capacitor is coupled between the first input of the comparator and ground.

28. The earplug of claim 27, further comprising: The second capacitor is coupled between the second input of the comparator and ground.

29. The earbud according to claim 24, wherein the first input of the comparator is the inverting input of the comparator, and the second input of the comparator is the non-inverting input of the comparator.

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