A failure analysis method and device for a chip-scale package interconnect structure

Abstract

The application provides a chip-scale package interconnection structure failure analysis method and device, comprising: determining the failure external pin corresponding to the failure CSP package interconnection structure according to the current-voltage characteristic curve corresponding to each external pin; collecting and analyzing the time-domain reflection waveform of the failure external pin by using the electro-optical terahertz pulse reflection technology, positioning the target interconnection failure area in the interconnection path where the failure external pin is located according to the amplitude, time delay and waveform distortion characteristics of the reflection pulse; scanning the target interconnection failure area by using the three-dimensional X-ray microscopic imaging technology, and determining the target position of the failure point on the interconnection path where the failure external pin is located and the corresponding structural defects based on the scanning result. The application realizes the non-destructive failure analysis of the CSP package interconnection structure by combining the electro-optical terahertz pulse reflection technology and the three-dimensional X-ray microscopic imaging technology, and improves the failure point fault positioning accuracy and efficiency.

Description

Technical Field

[0001] This application relates to the field of packaged chip failure analysis technology, and in particular to a failure analysis method and apparatus for chip-level packaged interconnect structures. Background Technology

[0002] Chip-scale packaging (CSP) is defined as a type of packaging whose package area does not exceed 1.2 times the original chip area and can be surface mounted. Since the early 1990s, it has become one of the most successful packaging technology trends.

[0003] Current non-destructive methods for analyzing the internal interconnect failure structures of chip-scale packaged integrated circuits (CSPs) often rely solely on acoustic microscopy and 2D / 3D X-rays, which are insufficient for efficiently and accurately locating the faulty interconnect structures in complex CSPs. Other failure location techniques, such as voltage contrast (VC), electron beam induced current (EBIC), and electron beam absorbed current (EBAC), frequently require destructive steps such as opening or thinning the package and chip, and polishing and cleaning the surface to accurately pinpoint the fault location in the chip interconnect. These destructive fault location processes cannot meet the practical application and reliability requirements of chips. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide at least one failure analysis method and apparatus for chip-level packaged interconnect structures, which combines electro-optic terahertz pulse reflection technology with three-dimensional X-ray microscopy to achieve lossless failure analysis of CSP packaged interconnect structures, thereby improving the accuracy and efficiency of failure point location.

[0005] This application mainly includes the following aspects: In a first aspect, embodiments of this application provide a failure analysis method for chip-level packaged interconnect structures. The method includes: performing current-voltage characteristic tests on each external pin of the failed CSP packaged interconnect structure using a semiconductor curve plotter, and acquiring the current-voltage characteristic curve corresponding to each external pin; determining the failed external pin corresponding to the failed CSP packaged interconnect structure based on the current-voltage characteristic curve corresponding to each external pin; acquiring and analyzing the time-domain reflection waveform of the failed external pin using electro-optic terahertz pulse reflection technology, and locating the target interconnect failure region in the interconnect path where the failed external pin is located based on the amplitude, delay, and waveform distortion characteristics of the reflected pulse; scanning the target interconnect failure region using three-dimensional X-ray microscopy imaging technology, and determining the target location of the failure point and the corresponding structural defect on the interconnect path where the failed external pin is located based on the scanning results.

[0006] In one possible implementation, the failed external pin corresponding to the failed CSP package interconnect structure is determined by the following process: For each external pin, the following process is performed: extract the morphological characteristics reflected by the current-voltage characteristic curve corresponding to the external pin; if the morphological characteristics are failure morphological characteristics, then determine the failure type corresponding to the external pin and identify the external pin as a failed external pin; if the morphological characteristics are normal morphological characteristics, then identify the external pin as a normal external pin.

[0007] In one possible implementation, the interconnect failure region of the interconnect path where the failed external pin is located is located by: injecting a reference electro-optic terahertz pulse between the failed external pin of the failed CSP package interconnect structure and the reference ground; acquiring the reflected pulse through asynchronous electro-optic sampling to generate an EOTPR time-domain waveform diagram with time as the horizontal axis and the reflected pulse amplitude as the vertical axis; identifying the target distance between the failed external pin and the failure point on its corresponding interconnect path based on the reflected pulse amplitude, peak polarity, and time delay characteristics reflected in the EOTPR time-domain waveform diagram; and locating the target interconnect failure region of the interconnect path where the failed external pin is located, centered on the reflected pulse detection position, based on the target distance.

[0008] In one possible implementation, the target interconnect failure region of the interconnect path where the failed external pin is located is determined by: inputting the functional attributes of the failed external pin on the interconnect structure of the failed CSP package, the corresponding target distance, the failure type, and the EOTPR time-domain waveform diagram into the trained interconnect failure region localization model, obtaining the predicted interconnect failure region output by the interconnect failure region localization model; and determining the predicted interconnect failure region as the target interconnect failure region.

[0009] In one possible implementation, the step of determining the predicted interconnect failure region as the target interconnect failure region includes: sending the predicted interconnect failure region to the auditor and obtaining the audit result from the auditor; if the audit result is approved, then directly determining the predicted interconnect failure region as the target interconnect failure region; if the audit result is unsuccessful, then obtaining the specified interconnect failure region determined by the auditor based on the target distance, failure type, and EOTPR time-domain waveform diagram corresponding to the failed external pin; and determining the specified interconnect failure region as the target interconnect failure region.

[0010] In one possible implementation, the step of scanning the target interconnect failure area using three-dimensional X-ray microscopy and determining the target location of the failure point and the corresponding structural defect on the interconnect path where the failed external pin is located based on the scanning results includes: inputting the three-dimensional volume image corresponding to the target interconnect failure area determined by the three-dimensional X-ray microscopy into a pre-trained failure location analysis model; and using the failure location analysis model to mark the target location of the failure point and the resulting failure fault on the interconnect path where the failed external pin is located.

[0011] Secondly, embodiments of this application also provide a failure analysis device for chip-level packaged interconnect structures. The device includes: a characteristic curve acquisition module, used to perform current-voltage characteristic tests on each external pin of the failed CSP packaged interconnect structure using a semiconductor curve plotter, and acquire the current-voltage characteristic curve corresponding to each external pin; a failure pin determination module, used to determine the failure external pin corresponding to the failed CSP packaged interconnect structure based on the current-voltage characteristic curve corresponding to each external pin; a waveform analysis module, used to perform time-domain reflection waveform acquisition and characteristic analysis on the failure external pin using electro-optic terahertz pulse reflection technology, and locate the target interconnect failure area in the interconnect path where the failure external pin is located based on the amplitude, delay and waveform distortion characteristics of the reflected pulse; and a scanning analysis module, used to scan the target interconnect failure area using three-dimensional X-ray microscopy imaging technology, and determine the target location of the failure point and the corresponding structural defect on the interconnect path where the failure external pin is located based on the scanning results.

[0012] In one possible implementation, the waveform analysis module is further configured to: inject a reference electro-optic terahertz pulse between the failed external pin of the failed CSP package interconnect structure and the reference ground; acquire the reflected pulse through asynchronous electro-optic sampling to generate an EOTPR time-domain waveform diagram with time as the horizontal axis and the reflected pulse amplitude as the vertical axis; identify the target distance between the failed external pin and the failure point on its corresponding interconnect path based on the reflected pulse amplitude, peak polarity, and time delay characteristics reflected in the EOTPR time-domain waveform diagram; and locate the target interconnect failure area of ​​the interconnect path where the failed external pin is located, centered on the reflected pulse detection position, based on the target distance.

[0013] Thirdly, embodiments of this application also provide an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the memory communicate via the bus. The machine-readable instructions are executed by the processor to perform the steps of the failure analysis method for the chip-level package interconnect structure provided in any of the above possible embodiments.

[0014] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when run by a processor, performs the steps of the failure analysis method for the chip-level package interconnect structure provided in any of the above possible embodiments.

[0015] This application provides a failure analysis method and apparatus for chip-level packaged interconnect structures, comprising: performing current-voltage characteristic tests on each external pin of the failed CSP packaged interconnect structure using a semiconductor curve plotter, and acquiring the current-voltage characteristic curve corresponding to each external pin; determining the failed external pin corresponding to the failed CSP packaged interconnect structure based on the current-voltage characteristic curve corresponding to each external pin; acquiring and analyzing the time-domain reflection waveform of the failed external pin using electro-optic terahertz pulse reflection technology, and locating the target interconnect failure region in the interconnect path where the failed external pin is located based on the amplitude, delay, and waveform distortion characteristics of the reflected pulse; scanning the target interconnect failure region using three-dimensional X-ray microscopy, and determining the target location of the failure point and the corresponding structural defect on the interconnect path where the failed external pin is located based on the scanning results. This application achieves lossless failure analysis of CSP packaged interconnect structures by combining electro-optic terahertz pulse reflection technology with three-dimensional X-ray microscopy, improving the accuracy and efficiency of failure point fault location.

[0016] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating a failure analysis method for a chip-level packaged interconnect structure provided in an embodiment of this application is shown. Figure 2 This document illustrates a flowchart of steps for locating the interconnect failure region of an interconnect path containing a failed external pin, as provided in an embodiment of this application. Figure 3 A schematic diagram of an EOTPR time-domain waveform diagram provided in an embodiment of this application is shown; Figure 4 A schematic diagram of a failure location analysis diagram provided in an embodiment of this application is shown; Figure 5 This paper illustrates a functional block diagram of a failure analysis device for a chip-level packaged interconnect structure provided in an embodiment of this application. Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0020] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] Chip-scale packaging (CSP) is defined as a type of packaging whose package area does not exceed 1.2 times the original chip area and can be surface mounted. Since the early 1990s, it has become one of the most successful packaging technology trends.

[0022] The core of traditional wire-leaded packaging is to connect the chip to a metal wireframe via bonding wires, and then encapsulate it with molding material to form a shell. Compared with traditional wire-leaded packaging, CSP has advantages such as smaller size, thinner package, lighter weight, relatively simpler assembly process, lower overall manufacturing cost, and better electrical performance. These advantages, coupled with the industry's push towards 2.5D and 3D System-in-Package (SiP) architectures, make it possible to stack multiple chips and heterogeneous devices in a single package to achieve highly integrated systems. However, these very features that make CSP attractive—the near-chip-size package area, the wafer-level chip-scale packaging (WLCSP) format, and the high-density multi-interface stacking—also bring significant challenges to failure analysis (FA), especially in terms of fault isolation accuracy, non-destructive imaging, and the preparation of complex samples at the package and chip levels.

[0023] Typical package-level failure modes of CSPs include: package or chip cracks, copper trace cracks, solder ball and microbump cracks, poor wetting and voids, as well as separation at the interfaces of microbumps, copper pillars, and through-silicon vias (TSVs). In advanced 2.5D / 3D SiP devices, minute defects may be buried under multiple interfaces and distributed across a large-area substrate, making it difficult to pinpoint the fault to a specific interconnect or interface using conventional tools. Meanwhile, the practical applications and reliability requirements of chips urgently necessitate a low-cost, rapid, and non-destructive analysis process while maintaining a high detection rate for minute interconnect structural defects. Therefore, traditional FA processes typically combine non-destructive imaging, such as optical and acoustic microscopy (SAM), 2D / 3D X-rays, and electrical fault isolation (FI), and finally supplement with destructive physical analysis (slicing analysis). Each step of the destructive analysis step has the potential to destroy critical evidence.

[0024] Based on the above, current conventional non-destructive chip-level package interconnect failure structure analysis methods often only utilize acoustic microscopy and 2D / 3D X-rays, which are insufficient for efficiently and accurately locating the faulty interconnect structures in complex CSPs. Other failure location techniques, such as voltage contrast (VC), electron beam induced current (EBIC), and electron beam absorbed current (EBAC), often require destructive steps such as opening or thinning the package and chip, and polishing and cleaning the surface to accurately locate the fault in the chip interconnect. These destructive fault location processes cannot meet the practical application and reliability requirements of chips.

[0025] Based on this, this application provides a failure analysis method and apparatus for chip-level packaged interconnect structures. The combination of electro-optic terahertz pulse reflection technology and three-dimensional X-ray microscopy imaging technology enables lossless failure analysis of CSP packaged interconnect structures, improving the accuracy and efficiency of fault location. The failure analysis method for chip-level packaged interconnect structures provided in this application can be applied to CSP devices, as detailed below: Please see Figure 1 , Figure 1 A flowchart illustrating a failure analysis method for a chip-level packaged interconnect structure provided in an embodiment of this application is shown. Figure 1 As shown, the method provided in this application embodiment includes the following steps: S100. Use a semiconductor curve plotter to perform current-voltage characteristic tests on each external pin of the failed CSP package interconnect structure and collect the current-voltage characteristic curve corresponding to each external pin.

[0026] S200. Based on the current-voltage characteristic curve of each external pin, determine the failed external pin corresponding to the failed CSP package interconnect structure.

[0027] S300 uses electro-optic terahertz pulse reflection technology to acquire and analyze the time-domain reflection waveform of the failed external pin. Based on the amplitude, delay and waveform distortion characteristics of the reflected pulse, the target interconnect failure area in the interconnect path where the failed external pin is located is located.

[0028] S400: The target interconnect failure area is scanned using three-dimensional X-ray microscopy imaging technology. Based on the scanning results, the target location of the failure point on the interconnect path where the failed external pin is located and the corresponding structural defect are determined.

[0029] In a preferred embodiment, in steps S100 to S400, the electro-optic terahertz pulse reflection technology is used to quickly and non-destructively locate the target failed interconnect region of the failed external pin in the interconnect path under the condition of the internal structure location of the failed CSP package interconnect structure. Then, combined with three-dimensional X-ray microscopy, the imaging data of the target failed interconnect region is observed and analyzed non-destructively. Without the need for further destructive analysis processes such as unpacking and slicing, the analysis of the failed interconnect structure can be carried out, which significantly improves the accuracy and efficiency of non-destructive analysis of failed interconnect structures. It can characterize the three-dimensional interconnect failure structure of the CSP package interconnect structure in a relatively non-destructive and efficient manner.

[0030] In step S100, the current-voltage characteristic test of the external pin specifically includes: applying a scanning voltage that varies from small to large between the external pin and the reference ground, collecting the current flowing into the external pin, and obtaining the current-voltage characteristic curve corresponding to the external pin.

[0031] In a preferred embodiment, step S200 further includes performing the following processing for each external pin: Extract the morphological characteristics reflected by the current-voltage characteristic curve corresponding to the external pin. If the morphological characteristics are failure morphological characteristics, determine the failure type of the interconnection path where the external pin is located and identify the external pin as a failure external pin. If the morphological characteristics are normal morphological characteristics, identify the external pin as a normal external pin.

[0032] In one specific embodiment, the failure types of the interconnect path where the external pin is located include at least: open circuit failure (exemplary examples such as solder ball detachment, RDL disconnection, etc.), short circuit failure (exemplary examples such as solder ball bridging, dielectric breakdown) and intermittent (unstable) interconnect failure (exemplary examples such as cold solder joint, microcracks, poor contact).

[0033] Based on the current-voltage characteristic curve, it is possible to determine whether a connection fault has occurred on the external pin and its interconnect path. Specifically, on the one hand, the failure morphology characteristics include open-circuit failure characteristics, short-circuit failure characteristics, and intermittent interconnection characteristics. Among them, the open-circuit failure characteristic is that the curve has no conduction and the current is close to 0; the short-circuit failure characteristic is that the current is abnormally large and it is low-resistance conduction; and the intermittent interconnection failure characteristic is that the curve is hysteretic, jittery, and intermittent. On the other hand, the morphological characteristics reflected by the current-voltage characteristic curve of the external pin of the effective CSP package interconnect structure of the same type as the failed CSP package interconnect structure are defined as the normal morphological characteristics of the corresponding external pin of the failed CSP package interconnect structure.

[0034] In step S300, the electro-optic terahertz pulse reflection technology (EOTPR), as an advanced TDR (Time Domain Reflectometry) technology, exhibits significantly higher accuracy in non-destructive fault isolation in complex packages, and is particularly suitable for I / O-related failure analysis in multi-chip (Chip-on-Wafer-on-Substrate, CoWoS) GPUs and interposer-based SiP systems.

[0035] In a preferred embodiment, please refer to Figure 2 , Figure 2 A flowchart illustrating the steps for locating the interconnect failure region of an interconnect path containing a failed external pin, as provided in an embodiment of this application, is shown. Figure 2 As shown, step S300 further includes: S3001, Inject a reference electro-optic terahertz pulse between the failed external pin of the failed CSP package interconnect structure and the reference ground.

[0036] S3002. The reflected pulse is acquired by asynchronous electro-optic sampling, and an EOTPR time-domain waveform diagram is generated with time as the horizontal axis and the amplitude of the reflected pulse as the vertical axis.

[0037] S3003. Based on the reflected pulse amplitude, peak polarity, and time delay characteristics reflected in the EOTPR time-domain waveform diagram, identify the target distance between the failed external pin and the failure point on its corresponding interconnect path.

[0038] S3004. Using the reflected pulse detection position as the center, locate the target interconnect failure area of ​​the interconnect path where the failed external pin is located according to the target distance.

[0039] In steps S3001 to S3003, in the first embodiment corresponding to the failed external pin, if the corresponding failure type is open circuit failure, it means that there is an open circuit in the interconnection path where it is located. Then, the reflected pulse waveform described by the EOTPR time domain waveform diagram corresponding to the failed external pin will generate an abnormal reflected pulse with a positive peak value. Compared with the standard reflected pulse waveform corresponding to the failed external pin, the amplitude of its abnormal reflected pulse is much larger than the noise fluctuation of the corresponding standard reflected pulse waveform. Specifically, the abnormal reflected pulse is determined by the pre-set standard noise fluctuation range. The target distance between the open circuit failure point and the failed external pin is determined according to the product between the signal transmission speed and the reflection delay (the time difference between the time of detecting the abnormal reflected pulse and the initial acquisition time).

[0040] Among them, the structural defects corresponding to open circuit failure include, but are not limited to, at least one of the following: solder ball detachment, RDL breakage.

[0041] In one specific embodiment, please refer to Figure 3 , Figure 3 This diagram illustrates a time-domain waveform diagram of EOTPR provided in an embodiment of this application. Figure 3 In the specific embodiment proposed, the reflected pulse waveform (red) acquired from the failed external pin has an abnormal reflected pulse with a positive peak value compared to the standard reflected waveform (blue), indicating that there is an open circuit in the interconnection path where the failed external pin is located.

[0042] In the second embodiment corresponding to the failed external pin, if the corresponding failure type is a short circuit failure, it means that there is a short circuit in the interconnect path where it is located. Then, the reflected pulse waveform described by the EOTPR time domain waveform diagram corresponding to the failed external pin will generate an abnormal reflected pulse with a negative peak. Compared with the standard reflected pulse waveform corresponding to the failed external pin, the amplitude of its abnormal reflected pulse is much larger than the noise fluctuation of the corresponding standard reflected pulse waveform. The method of determining the target distance between the short circuit failure point and the failed external pin is similar to that described above, and will not be elaborated further here.

[0043] Structural defects corresponding to short-circuit failure include, but are not limited to, at least one of the following: solder ball bridging, dielectric breakdown.

[0044] In the third embodiment corresponding to the failed external pin, if the failure type is an intermittent interconnect failure, it indicates that there is poor contact in the interconnect path. The reflected pulse waveform described by the EOTPR time domain waveform diagram corresponding to the failed external pin will show an abnormal reflected pulse with a positive peak or an abnormal reflected pulse with a negative peak. The method of determining the target distance between the intermittent interconnect failure point and the failed external pin (reflected pulse detection position) based on a certain abnormal reflected pulse is similar to that described above, and will not be elaborated further here.

[0045] Structural defects corresponding to occasional interconnect failures include, but are not limited to, at least one of the following: poor solder joints, microcracks, and poor contact.

[0046] In a preferred embodiment, step S3004 further includes: Input the functional attributes of the failed external pin on its corresponding failed CSP chip, the target distance between the failed pin and the failure point, the failure type, and the EOTPR time-domain waveform into the trained interconnect failure region localization model corresponding to the interconnect structure of the failed CSP package to which the failed external pin belongs. Obtain the predicted interconnect failure region output by the interconnect failure region localization model, and determine the predicted interconnect failure region as the target interconnect failure region.

[0047] In one specific embodiment, the training process of the interconnect failure region localization model of this application includes: Acquire multiple historical CSP failure analysis data corresponding to multiple failed CSP package interconnect structures of the same type. The historical CSP failure analysis data includes the functional attributes (e.g., power input, general I / O, etc.) of each failed external pin on the failed CSP package interconnect structure, the actual distance from the failure point, the failure type, the EOTPR time-domain waveform, and the identified interconnect failure area. Create training samples for each failed external pin, i.e., each training sample includes the functional attributes of the failed external pin, the actual distance from the failure point, the failure type, the identified interconnect failure area, and the EOTPR time-domain waveform. For each training sample, use the functional attributes of the failed external pin, the actual distance from the failure point, the failure type, and the EOTPR time-domain waveform as model input, and use the identified interconnect failure area (specified by a professional engineer) as model output to train the pre-created neural network model, resulting in a trained interconnect failure area localization model corresponding to the failed CSP package interconnect structure to which the failed external pin belongs.

[0048] In a preferred embodiment, the step of determining the predicted interconnect failure region as the target interconnect failure region further includes: The predicted interconnect failure area is sent to the auditor, and the auditor's feedback is obtained. If the audit result is approved, the predicted interconnect failure area is directly determined as the target interconnect failure area. If the audit result is unsuccessful, the specified interconnect failure area determined by the auditor based on the target distance, failure type and EOTPR time domain waveform diagram corresponding to the failed external pin is obtained, and the specified interconnect failure area is determined as the target interconnect failure area.

[0049] In this application, while improving the efficiency of interconnect failure region location through the interconnect failure region location model, the accuracy of the interconnect failure region output by the model is also considered to ensure the accuracy of the subsequent 3D XRM scanning process. To achieve this goal, after determining the predicted interconnect failure region through the interconnect failure region location model, the subsequent 3D scanning is not directly based on the predicted interconnect failure region. Instead, the predicted interconnect failure region is further pushed to a pre-designated reviewer. In this application, the reviewer can be a professional engineer with extensive experience in failure analysis of failed CSP package interconnect structures. Only after obtaining the reviewer's feedback on the predicted interconnect failure region is the predicted interconnect failure region output by the model used as the target interconnect failure region for subsequent 3D scanning.

[0050] If the predicted interconnect failure area is not approved by the auditor, that is, the audit result of the predicted interconnect failure area is that the audit is not passed, then the interconnect failure area specified by the auditor will be used as the target interconnect failure area for subsequent 3D scanning.

[0051] This ensures the accuracy of the identified target interconnect failure areas, improves the success rate of subsequent scans, and thus enhances the efficiency of the entire failure analysis.

[0052] Three-dimensional X-ray microscopy (3D XRM) has evolved into a critical non-destructive structural analysis tool in advanced semiconductor packaging. Submicron-scale 3D XRM can achieve virtual cross-sections and virtual delamination of complete devices, revealing internal defects in solder balls, microbumps, TSVs, and copper traces, such as voids, cracks, cold solder joints, and missing or partially failed interconnects.

[0053] In a preferred embodiment, step S400 further includes: The three-dimensional volumetric image corresponding to the target interconnect failure area determined by the three-dimensional X-ray microscopy is input into the pre-trained failure location analysis model. The failure location analysis model is used to mark the target location of the failure point on the interconnect path where the failed external pin is located and the resulting failure fault.

[0054] In its specific implementation, this application, based on multiple failed CSP chips of the same type that have undergone failure analysis, obtains a three-dimensional volumetric image and a failure location analysis map corresponding to the failure point of each failed external pin of the failed CSP device. In response to the failure point location box annotation operation and failure fault annotation operation performed by experts on the three-dimensional volumetric image of the corresponding failure point, a corresponding failure location analysis map is generated. The three-dimensional volumetric image, failure type and failure location analysis map corresponding to the failure point of the failed external pin are used as a training sample. The three-dimensional volumetric image and failure type of the failure point corresponding to the training sample are used as input and the failure location analysis map is used as output to train a pre-created neural network model, thereby obtaining a trained failure location analysis model.

[0055] Specifically, by inputting the three-dimensional volumetric image and failure type corresponding to the target interconnect failure area into the pre-trained failure location analysis model, the corresponding target failure location analysis map can be obtained. The target failure location analysis map includes the failure point location box and the generated failure fault.

[0056] Please see Figure 4 , Figure 4 This diagram illustrates a failure location analysis diagram provided in an embodiment of this application. Figure 4 A crack (structural defect) was found at the failure point location box (failure location) shown.

[0057] Based on the same application concept, this application also provides a chip-level package interconnect structure failure analysis device corresponding to the chip-level package interconnect structure failure analysis method provided in the above embodiments. Since the principle of the device in this application to solve the problem is similar to the chip-level package interconnect structure failure analysis method in the above embodiments of this application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0058] Please see Figure 5 , Figure 5 This diagram illustrates a functional block diagram of a failure analysis device for a chip-level packaged interconnect structure provided in an embodiment of this application. Figure 5 As shown, the device includes: The characteristic curve acquisition module 500 is used to perform current-voltage characteristic tests on each external pin of the failed CSP package interconnect structure using a semiconductor curve plotter, and to acquire the current-voltage characteristic curve corresponding to each external pin. The failure pin determination module 510 is used to determine the failure external pin corresponding to the failure CSP package interconnect structure based on the current-voltage characteristic curve corresponding to each external pin. The waveform analysis module 520 is used to acquire and analyze the time-domain reflected waveform of the failed external pin using electro-optic terahertz pulse reflection technology. Based on the amplitude, delay and waveform distortion characteristics of the reflected pulse, the target interconnect failure area in the interconnect path where the failed external pin is located is located. The scanning analysis module 530 is used to scan the target interconnect failure area using three-dimensional X-ray microscopy imaging technology, and determine the target location of the failure point on the interconnect path where the failed external pin is located and the corresponding structural defect based on the scanning results.

[0059] Preferably, the waveform analysis module 520 is further configured to: inject a reference electro-optic terahertz pulse between the failed external pin of the failed CSP package interconnect structure and the reference ground; acquire the reflected pulse through asynchronous electro-optic sampling to generate an EOTPR time-domain waveform diagram with time as the horizontal axis and the reflected pulse amplitude as the vertical axis; identify the target distance between the failed external pin and the failure point on its corresponding interconnect path based on the reflected pulse amplitude, peak polarity, and time delay characteristics reflected in the EOTPR time-domain waveform diagram; and locate the target interconnect failure area of ​​the interconnect path where the failed external pin is located, centered on the reflected pulse detection position, based on the target distance.

[0060] Based on the same application concept, please refer to Figure 6 , Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Figure 6 As shown, the electronic device 60 includes a processor 601, a memory 602, and a bus 603. The memory 602 stores machine-readable instructions that can be executed by the processor 601. When the electronic device 60 is running, the processor 601 and the memory 602 communicate through the bus 603. The machine-readable instructions are executed by the processor 601 to perform the steps of the failure analysis method of the chip-level package interconnect structure provided in any of the above embodiments.

[0061] Based on the same concept, this application also provides a computer-readable storage medium storing a computer program, which, when run by a processor, executes the steps of the failure analysis method for the chip-level packaged interconnect structure provided in the above embodiments.

[0062] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and devices described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division; in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0063] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0064] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0065] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0066] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A failure analysis method for chip-level packaged interconnect structures, characterized in that, The method includes: A semiconductor curve plotter was used to test the current-voltage characteristics of each external pin of the failed CSP package interconnect structure, and the current-voltage characteristic curves of each external pin were collected. Based on the current-voltage characteristic curves corresponding to each external pin, determine the failed external pins corresponding to the failed CSP package interconnect structure; Electro-optic terahertz pulse reflection technology is used to acquire and analyze the time-domain reflection waveform of the failed external pin. Based on the amplitude, delay and waveform distortion characteristics of the reflected pulse, the target interconnect failure area in the interconnect path where the failed external pin is located is located. The target interconnect failure area is scanned using three-dimensional X-ray microscopy, and the target location of the failure point and the corresponding structural defect on the interconnect path where the failed external pin is located are determined based on the scanning results.

2. The method according to claim 1, characterized in that, The failed external pins corresponding to the failed CSP package interconnect structure are identified using the following method: For each external pin, perform the following processing: Extract the morphological characteristics reflected by the current-voltage characteristic curve corresponding to the external pin; If the morphological feature is a failure morphological feature, then the failure type corresponding to the external pin is determined, and the external pin is identified as a failed external pin. If the morphological feature is a normal morphological feature, then the external pin is determined to be a normal external pin.

3. The method according to claim 1, characterized in that, The interconnect failure region of the interconnect path containing the failed external pin can be located using the following method: Inject a reference electro-optic terahertz pulse between the failed external pin of the failed CSP package interconnect structure and the reference ground; The reflected pulses are acquired by asynchronous electro-optic sampling, and an EOTPR time-domain waveform diagram is generated with time as the horizontal axis and the reflected pulse amplitude as the vertical axis. Based on the reflected pulse amplitude, peak polarity, and time delay characteristics reflected in the EOTPR time-domain waveform, the target distance between the failed external pin and the failure point on its corresponding interconnect path is identified. Centered on the location of the reflected pulse detection, the target interconnect failure area of ​​the interconnect path where the failed external pin is located is determined according to the target distance.

4. The method according to claim 3, characterized in that, The target interconnect failure region of the interconnect path containing the failed external pin is determined using the following method: The functional attributes of the failed external pin on the corresponding failed CSP package interconnect structure, the corresponding target distance, the failure type, and the EOTPR time-domain waveform are input into the trained interconnect failure region localization model to obtain the predicted interconnect failure region output by the interconnect failure region localization model. The predicted interconnect failure region is determined as the target interconnect failure region.

5. The method according to claim 4, characterized in that, The step of determining the predicted interconnect failure region as the target interconnect failure region includes: The predicted interconnect failure area is sent to the auditor, and the audit results are obtained from the auditor. If the audit result is "approved", then the predicted interconnect failure area is directly determined as the target interconnect failure area. If the audit result is an audit failure, then the auditer obtains the specified interconnect failure area determined by the auditer based on the target distance, failure type, and EOTPR time-domain waveform diagram corresponding to the failed external pin; The specified interconnect failure region is determined as the target interconnect failure region.

6. The method according to claim 1, characterized in that, The step of scanning the target interconnect failure area using three-dimensional X-ray microscopy and determining the target location of the failure point and the corresponding structural defect on the interconnect path where the failed external pin is located based on the scanning results includes: The three-dimensional volumetric image corresponding to the target interconnect failure region determined by three-dimensional X-ray microscopy is input into the pre-trained failure location analysis model. The failure location analysis model is used to mark the target location of the failure point on the interconnect path where the failed external pin is located and the resulting failure fault.

7. A failure analysis device for a chip-level packaged interconnect structure, characterized in that, The device includes: The characteristic curve acquisition module is used to perform current-voltage characteristic tests on each external pin of the failed CSP package interconnect structure using a semiconductor curve plotter, and to acquire the current-voltage characteristic curve corresponding to each external pin. The failure pin determination module is used to determine the failure external pin corresponding to the failure CSP package interconnect structure based on the current-voltage characteristic curve of each external pin. The waveform analysis module is used to acquire and analyze the time-domain reflected waveform of the failed external pin using electro-optic terahertz pulse reflection technology. Based on the amplitude, delay and waveform distortion characteristics of the reflected pulse, the module locates the target interconnect failure area in the interconnect path where the failed external pin is located. The scanning analysis module is used to scan the target interconnect failure area using three-dimensional X-ray microscopy imaging technology, and based on the scanning results, determine the target location of the failure point on the interconnect path where the failed external pin is located and the corresponding structural defect.

8. The apparatus according to claim 7, characterized in that, The waveform analysis module is also used for: Inject a reference electro-optic terahertz pulse between the failed external pin of the failed CSP package interconnect structure and the reference ground; The reflected pulses are acquired by asynchronous electro-optic sampling, and an EOTPR time-domain waveform diagram is generated with time as the horizontal axis and the reflected pulse amplitude as the vertical axis. Based on the reflected pulse amplitude, peak polarity, and time delay characteristics reflected in the EOTPR time-domain waveform, the target distance between the failed external pin and the failure point on its corresponding interconnect path is identified. Centered on the location of the reflected pulse detection, the target interconnect failure area of ​​the interconnect path where the failed external pin is located is determined according to the target distance.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. The machine-readable instructions are executed by the processor to perform the steps of the failure analysis method for the chip-level package interconnect structure as described in any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the failure analysis method for chip-level packaged interconnect structures as described in any one of claims 1 to 6.

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