An LDO circuit

Abstract

This invention belongs to the field of integrated circuit technology, specifically relating to an LDO circuit. This invention is a three-stage LDO structure, including a variable resistor module, a first-stage error amplifier, a buffer stage, an output power transistor, and a feedback resistor circuit. By replacing the resistor generating the zero point in the pseudo-ESR compensation loop with a variable resistor through the variable resistor module, this invention achieves precise tracking of the secondary point position by the zero point. The LDO circuit module of this invention can achieve a 1MHz loop bandwidth under a maximum output current of 400mA, accurately tracking the secondary point position change in the pseudo-ESR compensation technology, achieving a load step transient response time of less than 2µs, and an output undershoot voltage of less than 23mV caused by a load step change (load changes from 0-400mA, step time 1µs).

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, specifically to an LDO circuit. Background Technology

[0002] As the integration of on-chip systems continues to increase at advanced process nodes, their power supply networks are facing increasingly severe dynamic performance bottlenecks. As a key end-point voltage regulator in the system, the design of low-dropout linear regulators (LDOs) has shifted from simply pursuing static performance metrics to addressing the complex challenges posed by both load transients and power integrity constraints. Especially in scenarios such as multi-core computing arrays and high-speed mixed-signal modules, even minute fluctuations in the supply voltage can directly affect system timing margins, signal quality, and even overall energy efficiency. This requires LDOs not only to maintain static accuracy but also to perform precise voltage regulation within an extremely short timescale to quickly suppress transient disturbances and closely follow the system's dynamic power consumption patterns.

[0003] To achieve rapid suppression of load transients, various compensation strategies are widely used. The dominant pole-Miller compensation technique, widely adopted and continuously optimized in the industry, faces fundamental challenges. Due to its inherent right-half-plane zero problem, pursuing high bandwidth not only reduces phase margin but also significantly degrades compensation efficiency with changes in load current. This fundamentally limits its ability to simultaneously achieve high bandwidth and high stability over a wide load range. Therefore, the scheme utilizing the equivalent series resistance (ESR) of the output capacitor for compensation is widely used in LDO designs. This scheme improves phase margin by introducing a left-half-plane zero through the ESR of the output capacitor itself, thereby ensuring system stability while expanding bandwidth.

[0004] While pseudo-ESR compensation architectures offer the advantage of simple design, their loop stability is inherently constrained by the parasitic parameters of external components. The frequency position of the compensation zero, upon which this technique relies, is determined by the equivalent series resistance of the output capacitor. This characteristic introduces a fundamental design contradiction: the pole distribution of the LDO power stage shifts significantly with changes in load current, and a static zero determined by a fixed ESR cannot follow or adapt to this. Therefore, the performance of the compensation network is uneven and unreliable over a wide load range—under light loads, the excessively high zero frequency makes it difficult to effectively compensate for the phase of the low-frequency dominant pole, limiting the loop response speed; under heavy loads, the excessively low zero frequency fails to adequately improve the phase margin, causing underdamped oscillations in the transient response and even affecting the stability of the closed-loop operation.

[0005] In summary, a key problem currently exists: the lack of a control mechanism that enables the zero-point position of the pseudo-ESR compensation network to adaptively adjust with load current. This invention is proposed precisely to solve this technical challenge. Summary of the Invention

[0006] The purpose of this invention is to propose an LDO circuit that uses pseudo-ESR compensation technology to control the zero point to accurately track the position of the secondary point.

[0007] The technical solution of this invention is as follows:

[0008] An LDO circuit includes a first-stage error amplifier, a buffer stage, an output power transistor, a feedback circuit, and a variable resistor module.

[0009] The first-stage error amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a first resistor. The source of the first PMOS transistor MP1 is connected to the power supply of the first-stage error amplifier, and its gate and drain are interconnected. The drain of the first NMOS transistor MN1 is connected to the drain of the first PMOS transistor MP1, the gate of the first NMOS transistor MN1 is connected to the feedback voltage, and the source of the first NMOS transistor MN1 is connected to one end of the first resistor and the drain of the third NMOS transistor MN3. The gate of the third NMOS transistor MN3 is connected to the bias voltage, and its source is grounded. The source of the second PMOS transistor MP2 is connected to the power supply of the first-stage error amplifier, and its gate... The drain of the first PMOS transistor MP1 is connected to the drain of the second PMOS transistor MP2, which is connected to the drain and gate of the fifth NMOS transistor MN5 and the gate of the sixth NMOS transistor M6. The source of the third PMOS transistor MP3 is connected to the power supply of the first-stage error amplifier, and its gate and drain are interconnected. The drain of the second NMOS transistor MN2 is connected to the drain of the third PMOS transistor MP3, and the gate of the second NMOS transistor MN2 is connected to the reference voltage. The source of the second NMOS transistor MN2 is connected to the other end of the first resistor and the drain of the fourth NMOS transistor MN4. The source of the fourth PMOS transistor MP4 is connected to the power supply of the first-stage error amplifier, and its gate is connected to the drain of the third PMOS transistor MP3. The drain of the fourth PMOS transistor MP4 is connected to the drain of the sixth NMOS transistor MN6. The sources of the fourth NMOS transistor MN3, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 are all grounded.

[0010] The buffer stage includes a fifth PMOS transistor MP5, a seventh NMOS transistor MN7, a second resistor, and a third resistor. The source of the fifth PMOS transistor MP5 is connected to the input voltage, and its gate and drain are interconnected and connected to one end of the second resistor. The other end of the second resistor is connected to the input voltage. The drain of the seventh NMOS transistor MN7 is connected to the drain of the fifth PMOS transistor MP5, the gate of the seventh NMOS transistor MN7 is connected to the drain of the fourth PMOS transistor MP4, and the source of the seventh NMOS transistor MN7 is grounded through the third resistor.

[0011] The source of the output power transistor is connected to the input voltage, the gate is connected to one end of the second resistor, and the drain is connected to the feedback circuit.

[0012] The feedback circuit includes a fourth resistor, a fifth resistor, and a sixth resistor. One end of the fourth resistor is connected to the drain of the output power transistor, and the other end of the fourth resistor is grounded after passing through the fifth resistor and the sixth resistor in sequence. The connection point between the fourth resistor and the output power transistor is defined as the first feedback point, the connection point between the fourth resistor and the fifth resistor is defined as the second feedback point, and the connection point between the fifth resistor and the sixth resistor is defined as the third feedback point. The feedback voltage output at the third feedback point is connected to the gate of the first NMOS transistor MN1.

[0013] The variable resistor module includes a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor M11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a first capacitor, a second capacitor, a mirror MOS transistor, a controlled resistor MOS transistor, and a current-controlled resistor MOS transistor. One end of the first capacitor is connected to the third feedback point, and the other end of the first capacitor is connected to the source of the controlled resistor MOS transistor. The drain of the controlled resistor MOS transistor is connected to the first feedback point, and its gate is connected to the drain of the eighth PMOS transistor MP8. The source of the mirror MOS transistor is connected to the input voltage, its gate is connected to one end of the second resistor, and its drain is connected to the drain of the eighth NMOS transistor MN8. The source of the current-controlled resistor MOS transistor is connected to the first feedback point, its gate is connected to the drain of the eighth PMOS transistor MP8, and its drain is connected to the drain of the ninth NMOS transistor MN9 and the gate of the eleventh NMOS transistor MN11. The gate of the eighth NMOS transistor MN8 is connected to... The gate of the ninth NMOS transistor MN9, the source of the eighth NMOS transistor MN8, and the source of the ninth NMOS transistor MN9 are grounded; the source of the sixth PMOS transistor MP6 is connected to the input voltage, and its gate and drain are interconnected; the drain of the tenth NMOS transistor MN10 is connected to the drain of the sixth PMOS transistor MP6, the gate of the tenth NMOS transistor MN10 is connected to the second feedback point, and the source of the tenth NMOS transistor MN10 is connected to the source of the eleventh NMOS transistor MN11 and the drain of the twelfth NMOS transistor MN12; the seventh PMOS transistor M... The source of P7 is connected to the input voltage, and its gate is connected to the drain of the sixth PMOS transistor MP6. The drain of the seventh PMOS transistor MP7 is connected to one end of the second capacitor, the gate of the eighth PMOS transistor MP8, and the drain of the eleventh NMOS transistor MN11. The gate of the twelfth NMOS transistor MN12 is connected to the bias voltage, and its source is grounded. The source of the eighth PMOS transistor MP8 is connected to the input voltage, and its drain is connected to the other end of the second capacitor and the drain of the thirteenth NMOS transistor M13. The gate of the thirteenth NMOS transistor MN13 is connected to the bias voltage, and its source is grounded.

[0014] The beneficial effects of this invention are as follows: First, the LDO circuit described in this invention simulates ESR behavior through an internally integrated precision variable resistor module, achieving dynamic and adaptive tracking of the load current by the compensation zero-point frequency. This design fundamentally solves the inherent limitation of traditional pseudo-ESR compensation, which cannot adapt to a wide range of load variations and different output capacitors due to the fixed zero-point position. Therefore, it provides a stable and sufficient phase margin under all operating conditions, ensuring a fast and smooth transient response.

[0015] Secondly, by optimizing the transconductance and output impedance of the error amplifier and coordinating with the adaptive zero-point compensation network, this invention can significantly extend the unity-gain bandwidth of the loop without sacrificing stability. This not only directly improves the system's suppression speed of load steps, but its enhanced loop gain also helps improve the DC accuracy and power supply rejection ratio of the output.

[0016] In summary, the pseudo-ESR compensation LDO circuit with built-in controlled resistors described in this invention not only completely overcomes the core defect of traditional schemes where the compensation zero point cannot be adaptively adjusted, but also further releases bandwidth potential through loop collaborative design. This allows the pseudo-ESR compensation-based LDO to simultaneously achieve design simplicity, application flexibility, and excellent dynamic performance, greatly expanding the practical scope and application scenarios of this technology. Attached Figure Description

[0017] Figure 1 This is a circuit structure diagram of an LDO according to an embodiment of the present invention;

[0018] Figure 2 This is the schematic diagram of the LDO circuit of the present invention;

[0019] Figure 3 This is a circuit diagram of the pseudo-ESR compensation section used in this invention;

[0020] Figure 4 The gain and phase margin curves of the LDO circuit of this invention are shown.

[0021] Figure 5 This is a transient response characteristic diagram of the LDO circuit of the present invention; Detailed Implementation

[0022] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0023] Example: like Figure 1 As shown, the LDO circuit in this example includes a first-stage error amplifier, a buffer stage, an output power transistor, a feedback circuit, and a variable resistor module.

[0024] The first stage is an error amplifier, responsible for contributing a large loop gain; the second stage is a buffer stage, used to drive the larger output power transistor; the third stage is the output power transistor and feedback resistor circuit.

[0025] The variable resistor module that precisely controls the zero point achieves linear change in the zero point position following the load current by replacing the resistor in the pseudo-ESR compensation loop with a controlled resistor.

[0026] The buffer stage includes MOSFETs MN7 and MP5; resistor Rs1 is connected to the source of MN7; resistor R1 is connected to the gate of MP5 and is also connected to the input voltage VIN.

[0027] The first-stage error amplifier uses active current multiplication technology, and the gain of the control loop can reach more than 60dB. It includes devices such as input transistors, bias transistors, and mirror transistors, and controls the second-stage buffer with dual-ended input and single-ended output.

[0028] The second-stage buffer is a common-source amplifier configuration, with the load MOS gate connected to the output power transistor gate, mirroring the output current to the second-stage buffer;

[0029] The output power transistor is a PDEMOS transistor MP, and the feedback resistor circuit includes resistors RFB1', RFB1", and RFB2;

[0030] The precise zero-point control compensation module comprises three parts. The first part is the compensation section, including capacitor C. S and equivalent controlled resistance MOSFET R S The second part is the current-controlled resistor section, including the mirror transistor MS, MOSFETs MN8 and MN7, and current-controlled resistor MOSFETs MPs; the third part is the OTA amplifier, including MOSFETs MN10, MN1, MP6, MP7, MN12, MN13, MP8, and capacitor Cm; the equivalent controlled resistance Rds drain-source resistance of the compensation section MOSFET MPC changes linearly with the load current, controlling the zero point generated by MOSFET MPC and capacitor Ccl. The compensation method uses pseudo-ESR compensation. MOSFETs MN8 and MN7 in the compensation section, along with the current-controlled resistor MOSFETs MPs, control MPs to convert the mirror current of the output power transistor into the gate voltage of MPs, thereby controlling Rds. S The equivalent drain-source resistance. The LDO circuit in this example can achieve a bandwidth of up to 1MHz under an output current of 400mA. By controlling the resistance value of the variable resistor, the zero point can be controlled to track the position of the secondary point under different loads. The phase margin is above 45°. The response time is less than 2µs when the load changes from 0 to 400mA step, and the output undershoot voltage caused by the load step is less than 23mV.

[0031] like Figure 3 The diagram shown is a pseudo-ESR compensation circuit diagram used in the LDO circuit of this example, including the output power transistor, the mirror transistor, the feedback circuit, the compensation resistor, and the compensation capacitor.

[0032] The pseudo-ESR compensation circuit in V FB After the loop is broken, the resulting compensation transfer function is:

[0033]

[0034] The first-stage error amplifier uses source degradation resistors to improve output linearity and employs current multiplication technology to enhance its gain and loop bandwidth. The gain of the first-stage error amplifier can be expressed by the formula:

[0035]

[0036] Where g mN1 It is the small-signal transconductance of the input pair transistor, r o1 R is the output impedance of the first-stage error amplifier. s It is the source degradation resistor.

[0037] The gain of the buffer stage driving the output power transistor can be expressed by the formula:

[0038]

[0039] Where g mN7 It is the small-signal transconductance of the input transistor of the common-source amplifier, g mP5 R1 is the small-signal transconductance of the active load transistor of the common-source amplifier, and R1 is used to provide bias current under light load.

[0040] The output power transistor and feedback circuit are used to output a 3.3V voltage with low ripple. The gain of the output power transistor can be expressed by the formula:

[0041]

[0042] Where g mP It is the small-signal transconductance of the output power transistor, R oeq It is the output equivalent resistance, R load It is the load resistance, r ds,MP It is the equivalent resistance of the power transistor.

[0043] The pseudo-ESR compensation circuit in V FB After the loop is broken, the resulting compensation transfer function is:

[0044]

[0045] Where R FB1 R FB2 It is the feedback resistor, C cl It is a compensation capacitor, C OUT It is the load equivalent capacitance, R S It is the equivalent controlled resistance, R LOAD It is the equivalent load resistance.

[0046] By breaking the loop at the feedback point, the open-loop gain expression can be obtained as follows:

[0047]

[0048] From the open-loop gain expression, we can see that the pole and zero locations under light load are expressed as follows:

[0049]

[0050]

[0051]

[0052]

[0053]

[0054]

[0055] The precise zero-point control compensation module achieves linear change in zero-point position following the load current by replacing the resistor in the pseudo-ESR compensation loop with a controlled resistor.

[0056] like Figure 4 As shown, under light load, the controlled resistor follows the load current change, making the zero point... Compensation secondary points Position; under heavy load, continue tracking changes in the position of secondary points; transient output in this example is as follows Figure 5 As shown.

Claims

1. An LDO circuit, characterized in that, This includes a first-stage error amplifier, a buffer stage, an output power transistor, a feedback circuit, and a variable resistor module; The first-stage error amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a first resistor. The source of the first PMOS transistor MP1 is connected to the power supply of the first-stage error amplifier, and its gate and drain are interconnected. The drain of the first NMOS transistor MN1 is connected to the drain of the first PMOS transistor MP1, the gate of the first NMOS transistor MN1 is connected to the feedback voltage, and the source of the first NMOS transistor MN1 is connected to one end of the first resistor and the drain of the third NMOS transistor MN3. The gate of the third NMOS transistor MN3 is connected to the bias voltage, and its source is grounded. The source of the second PMOS transistor MP2 is connected to the power supply of the first-stage error amplifier, and its gate... The drain of the first PMOS transistor MP1 is connected to the drain of the second PMOS transistor MP2, which is connected to the drain and gate of the fifth NMOS transistor MN5 and the gate of the sixth NMOS transistor M6. The source of the third PMOS transistor MP3 is connected to the power supply of the first-stage error amplifier, and its gate and drain are interconnected. The drain of the second NMOS transistor MN2 is connected to the drain of the third PMOS transistor MP3, and the gate of the second NMOS transistor MN2 is connected to the reference voltage. The source of the second NMOS transistor MN2 is connected to the other end of the first resistor and the drain of the fourth NMOS transistor MN4. The source of the fourth PMOS transistor MP4 is connected to the power supply of the first-stage error amplifier, and its gate is connected to the drain of the third PMOS transistor MP3. The drain of the fourth PMOS transistor MP4 is connected to the drain of the sixth NMOS transistor MN6. The sources of the fourth NMOS transistor MN3, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 are all grounded. The buffer stage includes a fifth PMOS transistor MP5, a seventh NMOS transistor MN7, a second resistor, and a third resistor. The source of the fifth PMOS transistor MP5 is connected to the input voltage, and its gate and drain are interconnected and connected to one end of the second resistor. The other end of the second resistor is connected to the input voltage. The drain of the seventh NMOS transistor MN7 is connected to the drain of the fifth PMOS transistor MP5, the gate of the seventh NMOS transistor MN7 is connected to the drain of the fourth PMOS transistor MP4, and the source of the seventh NMOS transistor MN7 is grounded through the third resistor. The source of the output power transistor is connected to the input voltage, the gate is connected to one end of the second resistor, and the drain is connected to the feedback circuit. The feedback circuit includes a fourth resistor, a fifth resistor, and a sixth resistor. One end of the fourth resistor is connected to the drain of the output power transistor, and the other end of the fourth resistor is grounded after passing through the fifth resistor and the sixth resistor in sequence. The connection point between the fourth resistor and the output power transistor is defined as the first feedback point, the connection point between the fourth resistor and the fifth resistor is defined as the second feedback point, and the connection point between the fifth resistor and the sixth resistor is defined as the third feedback point. The output feedback voltage of the third feedback point is connected to the gate of the first NMOS transistor MN1. The variable resistor module includes a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor M11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a first capacitor, a second capacitor, a mirror MOS transistor, a controlled resistor MOS transistor, and a current-controlled resistor MOS transistor. One end of the first capacitor is connected to the third feedback point, and the other end of the first capacitor is connected to the source of the controlled resistor MOS transistor. The drain of the controlled resistor MOS transistor is connected to the first feedback point, and its gate is connected to the drain of the eighth PMOS transistor MP8. The source of the mirror MOS transistor is connected to the input voltage, its gate is connected to one end of the second resistor, and its drain is connected to the drain of the eighth NMOS transistor MN8. The source of the current-controlled resistor MOS transistor is connected to the first feedback point, its gate is connected to the drain of the eighth PMOS transistor MP8, and its drain is connected to the drain of the ninth NMOS transistor MN9 and the gate of the eleventh NMOS transistor MN11. The gate of the eighth NMOS transistor MN8 is connected to... The gate of the ninth NMOS transistor MN9, the source of the eighth NMOS transistor MN8, and the source of the ninth NMOS transistor MN9 are grounded; the source of the sixth PMOS transistor MP6 is connected to the input voltage, and its gate and drain are interconnected; the drain of the tenth NMOS transistor MN10 is connected to the drain of the sixth PMOS transistor MP6, the gate of the tenth NMOS transistor MN10 is connected to the second feedback point, and the source of the tenth NMOS transistor MN10 is connected to the source of the eleventh NMOS transistor MN11 and the drain of the twelfth NMOS transistor MN12; the seventh PMOS transistor M... The source of P7 is connected to the input voltage, and its gate is connected to the drain of the sixth PMOS transistor MP6. The drain of the seventh PMOS transistor MP7 is connected to one end of the second capacitor, the gate of the eighth PMOS transistor MP8, and the drain of the eleventh NMOS transistor MN11. The gate of the twelfth NMOS transistor MN12 is connected to the bias voltage, and its source is grounded. The source of the eighth PMOS transistor MP8 is connected to the input voltage, and its drain is connected to the other end of the second capacitor and the drain of the thirteenth NMOS transistor M13. The gate of the thirteenth NMOS transistor MN13 is connected to the bias voltage, and its source is grounded.

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