An esd protection circuit with full common-mode voltage low input bias current

Abstract

The application relates to an ESD protection circuit with full common-mode voltage and low input bias current, belonging to the technical field of electrostatic discharge (ESD) protection circuits. The setting of a bias circuit makes the reverse bias voltage drop of the ESD protection diodes of the ESD protection circuit, the positive ESD matching circuit and the negative ESD matching circuit consistent. The first current mirror circuit makes the generated positive ESD reverse bias copy current consistent with the reverse bias current generated by the third ESD diode in the ESD protection circuit, and the two currents are complementary because the directions of the two currents are the same. Similarly, the second current mirror circuit makes the negative ESD reverse bias copy current consistent with the reverse bias current generated by the fourth ESD diode in the ESD protection circuit, and the two currents are complementary. Because the ESD reverse bias currents are complementary, an external circuit is not needed to provide the ESD reverse bias current, and low input bias current is realized. The low input bias current can be realized in the full common-mode voltage range.

Description

Technical Field

[0001] This application belongs to the field of electrostatic discharge (ESD) protection circuit technology, and specifically relates to an ESD protection circuit with low input bias current and full common-mode voltage. Background Technology

[0002] Input bias current is one of the important specifications of operational amplifiers. Since a voltage is generated when the input bias current flows through the external impedance, a higher input bias current will introduce a certain amount of system error, which in turn will affect the amplifier's output. Taking a zero-drift operational amplifier buffer driven by a 1MΩ source impedance with non-inverting unity gain as an example, if the bias current IIB is 10nA, it will introduce an additional 10mV error. This error is not negligible in precision instruments, so the bias current should be minimized as much as possible.

[0003] Conventional operational amplifiers can achieve zero-input bias current through techniques such as bias current compensation and capacitor input. However, in practice, to improve the reliability of operational amplifiers, all external terminals in the circuit are designed with electrostatic discharge (ESD) protection circuits, as shown in the circuit structure below. Figure 1 As shown, D11 and D12 are ESD discharge diodes, which are normally not turned on. When a large external voltage surges, the diodes conduct, discharging the large current to protect internal components from damage caused by the surge. Because the diodes are located at the terminals, they are reverse-biased under normal operation, resulting in reverse-bias leakage current. This leakage current can normally reach the pA level and can reach the nA level at high temperatures, exceeding the circuit's own bias current and becoming a major component of the op-amp's input bias current.

[0004] In circuit design, the dimensions of transistors D11 and D12 can be adjusted so that when the input common-mode voltage is between the positive and negative power supply voltages (i.e., the reverse bias voltages of D11 and D12 are the same), their reverse-bias leakage currents are also the same, thus canceling each other out. However, as the common-mode voltage changes, the inconsistency in the reverse bias voltages of D11 and D12 leads to inconsistent reverse-bias leakage currents. These leakage currents cannot cancel each other out, requiring an external power supply to provide leakage current, which manifests as a need for input bias current. Therefore, conventional ESD protection circuits cannot meet the low input bias current requirement under full common-mode voltage. Summary of the Invention

[0005] In view of the above problems, this application proposes an ESD protection circuit with low input bias current across the entire common-mode voltage range. Since the ESD reverse bias currents are mutually complementary, no external circuitry is needed to provide the ESD reverse bias current, thus achieving low input bias current. Low input bias current can be achieved across the entire common-mode voltage range.

[0006] This application provides an ESD protection circuit with low input bias current across the entire common-mode voltage range, comprising:

[0007] Bias circuit, follower circuit, positive ESD matching circuit, first current mirror circuit, second current mirror circuit, negative ESD matching circuit, ESD protection circuit and internal working circuit.

[0008] The bias circuit is connected to the follower circuit; the follower circuit is connected to the positive ESD matching circuit, the first current mirror circuit, the second current mirror circuit, and the negative ESD matching circuit respectively; the ESD protection circuit is connected to the internal working circuit.

[0009] The positive ESD matching circuit is connected to the first current mirror circuit; the first current mirror circuit is connected to the second current mirror circuit and the ESD protection circuit; the second current mirror circuit is connected to the negative ESD matching circuit.

[0010] Preferably, the bias circuit includes:

[0011] Power-on startup structure, reference current generation structure, and reference current copying structure;

[0012] The output terminal of the power-on startup structure is connected to the input terminal of the reference current generation structure, and the output terminal of the reference current generation structure is connected to the reference current copy structure; the potential output of the bias circuit controls the potential input of the tail current source of the follower circuit.

[0013] Preferably, the power-on startup structure includes:

[0014] The first MOSFET, the second MOSFET, the third MOSFET, the fourth MOSFET, the fifth MOSFET, the sixth MOSFET, the seventh MOSFET, the eighteenth MOSFET, the nineteenth MOSFET, the twenty-first MOSFET, and the first resistor R1;

[0015] The source of the first MOSFET is connected to the positive power supply, the drain of the first MOSFET is connected to the source of the second MOSFET, and the gate of the first MOSFET is connected to the first terminal of the first resistor.

[0016] The drain of the second MOSFET is connected to the source of the third and fourth MOSFETs, and the gate of the second MOSFET is connected to the first terminal of the first resistor; the second terminal of the first resistor is connected to the negative power supply.

[0017] The drain of the third MOSFET is connected to the drain of the fifth MOSFET, and the gate of the third MOSFET is connected to the second terminal of the third resistor of the reference generation structure.

[0018] The source of the fourth MOSFET is connected to the source of the third MOSFET, the drain of the fourth MOSFET is connected to the drain of the sixth MOSFET, and the gate of the fourth MOSFET is connected to the first terminal of the second resistor of the reference generation structure.

[0019] The source of the fifth MOSFET is connected to the negative power supply, and the gate and drain of the fifth MOSFET are connected and connected to the gate of the sixth MOSFET.

[0020] The source of the sixth MOSFET is connected to the negative power supply; the drain of the sixth MOSFET is connected to the drain of the seventh MOSFET; the source of the seventh MOSFET is connected to the negative power supply; the gate of the seventh MOSFET is connected to the drain and is also connected to the gate of the twenty-first MOSFET.

[0021] The source of the 21st MOSFET is connected to the negative power supply, and the drain of the 21st MOSFET is connected to the source of the 18th MOSFET.

[0022] The drain of the eighteenth MOSFET is connected to the drain of the nineteenth MOSFET, and the gate of the eighteenth MOSFET is connected to the positive power supply.

[0023] The source of the nineteenth MOSFET is connected to the positive power supply. The drain of the nineteenth MOSFET is connected to the sources of the seventeenth and eighteenth MOSFETs respectively. The gate of the seventeenth MOSFET is connected to the gate of the eighteenth MOSFET and connected to the positive power supply.

[0024] Preferably, the reference current generation structure includes:

[0025] The eighth MOSFET, the ninth MOSFET, the tenth MOSFET, the eleventh MOSFET, the twelfth MOSFET, the thirteenth MOSFET, the fourteenth MOSFET, the fifteenth MOSFET, the sixteenth MOSFET, the seventeenth MOSFET, the twentieth MOSFET, the second resistor R2 and the third resistor R3;

[0026] The source of the eighth MOS transistor is connected to the positive power supply, the drain of the eighth MOS transistor is connected to the first end of the second resistor, and the gate of the eighth MOS transistor is connected to the gate of the ninth MOS transistor.

[0027] The second terminal of the second resistor is connected to the first terminal of the third resistor; the second terminal of the third resistor is connected to the collector of the eleventh transistor.

[0028] The base of the eleventh transistor is connected to the collector of the eleventh transistor, and the emitter of the eleventh transistor is connected to the negative power supply.

[0029] The source of the ninth MOSFET is connected to the positive power supply, the drain of the ninth MOSFET is connected to the collector of the twelfth MOSFET, and the gate of the ninth MOSFET is connected to the gate of the tenth MOSFET; the base and collector of the twelfth MOSFET are connected, and the emitter of the twelfth MOSFET is connected to the negative power supply.

[0030] The source of the tenth MOSFET is connected to the positive power supply, and the drain of the tenth MOSFET is connected to the sources of the thirteenth and fourteenth MOSFETs respectively. The gate of the thirteenth MOSFET is connected to the drain of the nineteenth MOSFET in the power-on startup structure.

[0031] The drain of the thirteenth MOSFET is connected to the drain of the fifteenth MOSFET, and the gate of the thirteenth MOSFET is connected to the drain of the ninth MOSFET.

[0032] The drain of the fourteenth MOSFET is connected to the drain of the sixteenth MOSFET, and the gate of the fourteenth MOSFET is connected to the first terminal of the third resistor.

[0033] The drain of the fifteenth MOSFET is connected to the gate and also connected to the gate of the sixteenth MOSFET. The source of the fifteenth MOSFET is connected to the negative power supply.

[0034] The gate of the sixteenth MOSFET is connected to the gate of the fifteenth MOSFET, the source of the sixteenth MOSFET is connected to the negative power supply, and the drain of the sixteenth MOSFET is also connected to the gate of the twentieth MOSFET.

[0035] The drain of the seventeenth MOSFET is connected to the drain of the nineteenth MOSFET in the power-on structure, the source of the seventeenth MOSFET is connected to the drain of the twentieth MOSFET, the gate of the seventeenth MOSFET is connected to the positive power supply, and the source of the twentieth MOSFET is connected to the negative power supply.

[0036] Preferably, the reference current copy structure includes:

[0037] The twenty-second MOSFET, the twenty-third MOSFET, the twenty-fourth transistor, the twenty-fifth MOSFET, the twenty-sixth MOSFET, the twenty-seventh MOSFET, the fourth resistor, and the fifth resistor;

[0038] The source of the 22nd MOSFET is connected to the positive power supply, the drain of the 22nd MOSFET is connected to the drain of the 23rd MOSFET, and the gate of the 22nd MOSFET is connected to the drain of the 19th MOSFET in the power-on structure.

[0039] The source of the 23rd MOSFET is connected to the emitter of the 24th MOSFET, and the gate and drain of the 23rd MOSFET are connected and connected to the gate of the 26th MOSFET; the base and collector of the 24th MOSFET are both connected to the negative power supply.

[0040] The first terminal of the fourth resistor is connected to the positive power supply, and the second terminal of the fourth resistor is connected to the source of the twenty-fifth MOSFET.

[0041] The drain of the 25th MOSFET is connected to the drain of the 26th MOSFET, and the gate of the 25th MOSFET is connected to the gate of the 22nd MOSFET.

[0042] The source of the 26th MOSFET is connected to the drain of the 27th MOSFET, and the gate of the 26th MOSFET is connected to the gate of the 23rd MOSFET.

[0043] The source of the 27th MOSFET is connected to the first terminal of the fifth resistor, and the gate and drain of the 27th MOSFET are connected; the second terminal of the fifth resistor is connected to the negative power supply.

[0044] Among them, the gate of the 25th MOSFET is the first potential output of the bias circuit, and the gate of the 27th MOSFET is the second potential output of the bias circuit.

[0045] Preferably, the follower circuit includes:

[0046] Copy potential input, clamp potential input, and clamp potential output;

[0047] The copy potential input is connected to the bias circuit potential output, the clamping potential input is connected to the ESD protection circuit, and the clamping potential output is connected to the positive ESD matching circuit and the negative ESD matching circuit respectively.

[0048] The clamping voltage output of the follower circuit controls the reverse bias voltage of the positive ESD matching circuit and the negative ESD matching circuit respectively.

[0049] Preferably, the follower circuit includes:

[0050] The 32nd MOSFET, the 33rd MOSFET, the 34th MOSFET, the 35th MOSFET, the 36th MOSFET, the 37th MOSFET, the 7th resistor, the 8th resistor, and the 9th resistor;

[0051] The drain of the thirty-second MOS transistor is connected to the positive power supply, the source of the thirty-second MOS transistor is connected to the drain of the thirty-fourth MOS transistor, and the gate of the thirty-second MOS transistor is connected to the positive terminal of the second diode of the positive ESD matching circuit.

[0052] The source of the 34th MOSFET is connected to the first terminal of the 7th resistor, and the second terminal of the 7th resistor is connected to the negative power supply.

[0053] The drain of the 33rd MOSFET is connected to the positive power supply, the source of the 33rd MOSFET is connected to the drain of the 34th MOSFET, and the gate of the 33rd MOSFET is connected to the negative terminal of the first diode in the negative ESD matching circuit.

[0054] The drain of the 35th MOSFET is connected to the drain of the 34th MOSFET, the source of the 35th MOSFET is connected to the first terminal of the 8th resistor, and the gate of the 35th MOSFET is connected to the gate of the 34th MOSFET.

[0055] The second terminal of the eighth resistor is connected to the negative power supply; the first terminal of the ninth resistor is connected to the positive power supply, and the second terminal is connected to the source of the thirty-sixth MOSFET; the drain of the thirty-sixth MOSFET is connected to the source of the thirty-seventh MOSFET; the drain of the thirty-seventh MOSFET is connected to the negative power supply, and the gate of the thirty-seventh MOSFET is connected to the source of the thirty-third MOSFET.

[0056] Preferably, the follower circuit further includes:

[0057] The gate of the thirty-second MOSFET is the first clamping potential output of the follower circuit, and the gate of the thirty-third MOSFET is the second clamping potential output of the follower circuit.

[0058] The gate of the 34th MOS transistor is the first copy potential input of the follower circuit and is connected to the second potential output of the bias circuit, which is the gate of the 27th MOS transistor.

[0059] The gate of the thirty-sixth MOS transistor is the second copy potential input of the follower circuit and is connected to the first potential output of the bias circuit, which is the gate of the twenty-fifth MOS transistor.

[0060] The 37th MOSFET drain is clamped to the potential input by the follower circuit.

[0061] Preferably, the positive ESD matching circuit includes:

[0062] Positive ESD reverse bias potential input and positive ESD reverse bias current output;

[0063] The positive ESD reverse bias potential input is connected to the follower circuit, and the positive ESD reverse bias current output is connected to the first current mirror circuit.

[0064] The positive ESD matching circuit controls the current of the first current mirror copy by outputting the positive ESD reverse bias current.

[0065] Preferably, the positive ESD matching circuit includes:

[0066] The second diode has its cathode connected to the positive power supply.

[0067] The anode of the second diode is the positive ESD reverse bias potential input and positive ESD reverse bias current output of the positive ESD matching circuit;

[0068] The positive ESD reverse bias potential input of the positive ESD matching circuit is connected to the first clamp output of the follower circuit.

[0069] Preferably, the first current mirror circuit includes:

[0070] The 30th MOSFET, the 31st MOSFET, the 40th MOSFET, the 41st MOSFET, and the 10th resistor;

[0071] The drain of the thirtieth MOS transistor is connected to the second terminal of the tenth resistor, the source of the thirtieth MOS transistor is connected to the drain of the thirty-first MOS transistor, and the gate of the thirtieth MOS transistor is connected to the first terminal of the tenth resistor.

[0072] The gate of the thirty-first MOSFET is connected to the second terminal of the tenth resistor, and the source of the thirty-first MOSFET is connected to the negative power supply.

[0073] The source of the 40th MOSFET is connected to the drain of the 41st MOSFET, and the gate of the 40th MOSFET is connected to the gate of the 30th MOSFET.

[0074] The source of the forty-first MOSFET is connected to the negative power supply, and the gate of the forty-first MOSFET is connected to the gate of the thirty-first MOSFET.

[0075] Preferably, the first current mirror circuit further includes:

[0076] The first terminal of the tenth resistor is the positive ESD reverse bias leakage current input of the first current mirror circuit, and the drain of the fortieth MOS transistor is the positive ESD reverse bias leakage current copy output of the first current mirror circuit.

[0077] The positive ESD reverse bias leakage current input of the first current mirror circuit is connected to the positive ESD reverse bias current output of the positive ESD matching circuit.

[0078] Preferably, the second current mirror circuit includes:

[0079] Negative ESD reverse bias leakage current input and negative ESD reverse bias leakage current copy output;

[0080] The negative ESD reverse-biased leakage current input is connected to the negative ESD matching circuit, and the negative ESD reverse-biased leakage current copy output is connected to the ESD protection circuit.

[0081] Preferably, the second current mirror circuit further includes:

[0082] The 28th MOSFET, the 29th MOSFET, the 38th MOSFET, the 39th MOSFET, and the 6th resistor;

[0083] The source of the 28th MOSFET is connected to the positive power supply, the drain of the 28th MOSFET is connected to the source of the 29th MOSFET, and the gate of the 28th MOSFET is connected to the first terminal of the sixth resistor.

[0084] The drain of the 29th MOSFET is connected to the first terminal of the 6th resistor, and the gate of the 29th MOSFET is connected to the second terminal of the 6th resistor.

[0085] The source of the thirty-eighth MOS transistor is connected to the positive power supply, the drain of the thirty-eighth MOS transistor is connected to the source of the thirty-ninth MOS transistor, and the gate of the thirty-eighth MOS transistor is connected to the gate of the twenty-eighth MOS transistor.

[0086] The gate of the 39th MOS transistor is connected to the gate of the 29th MOS transistor.

[0087] Preferably, the second current mirror circuit further includes:

[0088] The second terminal of the sixth resistor is the negative ESD reverse bias leakage current input of the second current mirror circuit, and the drain of the thirty-ninth MOS transistor is the negative ESD reverse bias leakage current copy output of the second current mirror circuit.

[0089] The negative ESD reverse-biased leakage current input of the second current mirror circuit is connected to the negative ESD reverse-biased current output of the negative ESD matching circuit.

[0090] Preferably, the negative ESD matching circuit includes:

[0091] Negative ESD reverse bias potential input and negative ESD reverse bias current output;

[0092] The negative ESD reverse bias potential input is connected to the follower circuit, and the negative ESD reverse bias current output is connected to the second current mirror circuit.

[0093] The negative ESD matching circuit's negative ESD reverse bias current output controls the current copied by the second current mirror circuit.

[0094] Preferably, the negative ESD matching circuit further includes:

[0095] The first diode; the anode of the first diode is connected to the negative power supply, and the cathode of the first diode is the negative ESD reverse bias potential input and negative ESD reverse bias current output of the negative ESD matching circuit.

[0096] The negative ESD reverse bias potential input of the negative ESD matching circuit is connected to the second clamp output of the follower circuit.

[0097] Preferably, the ESD protection circuit includes:

[0098] The circuit includes a potential output and a current input. The potential output is connected to the follower circuit and the internal working circuit, while the current input is connected to the first current mirror circuit and the second current mirror circuit.

[0099] Preferably, the ESD protection circuit further includes:

[0100] Third diode and fourth diode;

[0101] The cathode of the third diode is connected to the positive power supply, and the anode is connected to the cathode of the fourth diode; the anode of the fourth diode is connected to the negative power supply.

[0102] Preferably, the ESD protection circuit further includes:

[0103] The anode of the third diode serves as both the potential output and current input for the ESD protection circuit.

[0104] The potential output of the ESD protection circuit is connected to the clamping potential input of the follower circuit;

[0105] The ESD protection circuit current input is connected to the positive ESD reverse-biased leakage current copy output of the first current mirror circuit and the negative ESD reverse-biased leakage current copy output of the second current mirror circuit.

[0106] The beneficial effects of this application are:

[0107] Based on the above technical solution, this application generates a reference current through the reference current generation structure of the bias circuit, and copies it to the follower circuit through the reference current copying structure, thereby driving the overall circuit to work. The bias circuit ensures that the reverse bias voltage drop of the ESD protection diodes in the ESD protection circuit, positive ESD matching circuit, and negative ESD matching circuit are consistent. The first current mirror circuit ensures that the positive ESD reverse bias current generated by the positive ESD matching circuit, after being copied according to a set ratio, is consistent with the reverse bias current generated by the third ESD diode in the ESD protection circuit. Since the two currents are in the same direction, they complement each other. Similarly, the second current mirror circuit ensures that the negative ESD reverse bias copy current is consistent with the reverse bias current generated by the fourth ESD diode in the ESD protection circuit, thus complementing each other. Because the ESD reverse bias currents are mutually complementary, no external circuit is needed to provide the ESD reverse bias current, thus achieving a low input bias current. Since the clamping effect of the follower circuit is applicable under any common-mode voltage, a low input bias current can be achieved across the entire common-mode voltage range.

[0108] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures pointed out in the description and the accompanying drawings. Attached Figure Description

[0109] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0110] Figure 1 A schematic diagram of a conventional ESD protection circuit is shown.

[0111] Figure 2 A schematic diagram of an ESD protection circuit with low input bias current across the entire common-mode voltage is shown.

[0112] Figure 3 A topology diagram of an ESD protection circuit with low input bias current and full common-mode voltage is shown. Detailed Implementation

[0113] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0114] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," "longitudinal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings.

[0115] This application provides an ESD protection circuit with low input bias current across the entire common-mode voltage range. See also... Figure 2 ,include:

[0116] Bias circuit 10, follower circuit 20, positive ESD matching circuit 30, first current mirror circuit 40, second current mirror circuit 50, negative ESD matching circuit 60, ESD protection circuit 70 and internal working circuit.

[0117] The bias circuit 10 is connected to the follower circuit 20; the follower circuit 20 is connected to the positive ESD matching circuit 30, the first current mirror circuit 40, the second current mirror circuit 50 and the negative ESD matching circuit 60 respectively; the ESD protection circuit 70 is connected to the internal working circuit.

[0118] The positive ESD matching circuit 30 is connected to the first current mirror circuit 40; the first current mirror circuit 40 is connected to the second current mirror circuit 50 and the ESD protection circuit 70; the second current mirror circuit 50 is connected to the negative ESD matching circuit 60.

[0119] The bias circuit 10 includes:

[0120] Power-on startup structure, reference current generation structure, and reference current copying structure;

[0121] The output terminal of the power-on structure is connected to the input terminal of the reference current generation structure, and the output terminal of the reference current generation structure is connected to the reference current copy structure; the potential output of the bias circuit 10 controls the potential input of the tail current source of the follower circuit 20.

[0122] Specifically, see Figure 2 The bias circuit 10 functions to power on, generate and copy the reference current, and provide the reference current to the follower circuit; the follower circuit 20 provides clamping voltage drop to the positive ESD matching circuit 30 and the negative ESD matching circuit 60.

[0123] The positive ESD matching circuit 30 provides reverse leakage current to the first current mirror circuit 40; the first current mirror circuit 40 copies the reverse leakage current generated by the positive ESD matching circuit 30 to the ESD protection circuit 70; the negative ESD matching circuit 60 provides reverse leakage current to the second current mirror circuit 50; the second current mirror circuit 50 copies the reverse leakage current generated by the negative ESD matching circuit 60 to the ESD protection circuit 70.

[0124] The ESD protection circuit includes a positive ESD protection structure and a negative ESD protection structure, and provides an ESD event protection discharge current path to the internal working circuit.

[0125] The internal working circuit is an amplifier working circuit; due to the clamping effect of the follower circuit 20, the reverse bias voltage drop of the positive ESD matching circuit 30 and the positive ESD protection structure in the ESD protection circuit 70 is consistent under different common-mode voltages; and the reverse bias voltage drop of the negative ESD matching circuit 60 and the negative ESD protection structure in the ESD protection circuit is consistent under different common-mode voltages.

[0126] The reverse leakage current generated by the positive ESD matching circuit 30 (copied by the first current mirror circuit 40) is consistent with the reverse leakage current generated by the positive ESD protection circuit in the ESD protection circuit 70, and the two cancel each other out. The reverse leakage current generated by the negative ESD matching circuit 60 (copied by the second current mirror circuit) is consistent with the reverse leakage current generated by the negative ESD protection circuit in the ESD protection circuit 70, and the two cancel each other out.

[0127] Since the leakage current generated in the ESD protection circuit 70 is canceled out under different common-mode input voltages, the bias current of the internal circuit is small, thus achieving low input bias current under full common-mode voltage.

[0128] Specifically, see Figure 3 The power-on startup structure includes:

[0129] The first MOSFET Q1, the second MOSFET Q2, the third MOSFET Q3, the fourth MOSFET Q4, the fifth MOSFET Q5, the sixth MOSFET Q6, the seventh MOSFET Q7, the eighteenth MOSFET Q18, the nineteenth MOSFET Q19, the twenty-first MOSFET Q21, and the first resistor R1;

[0130] The source of the first MOSFET Q1 is connected to the positive power supply, the drain of the first MOSFET Q1 is connected to the source of the second MOSFET Q2, and the gate of the first MOSFET Q1 is connected to the first terminal of the first resistor R1.

[0131] The drain of the second MOSFET Q2 is connected to the source of the third MOSFET Q3 and the fourth MOSFET Q4, and the gate of the second MOSFET Q2 is connected to the first terminal of the first resistor R1; the second terminal of the first resistor R1 is connected to the negative power supply.

[0132] The drain of the third MOSFET Q3 is connected to the drain of the fifth MOSFET Q5, and the gate of the third MOSFET Q3 is connected to the second terminal of the third resistor R3 of the reference generation structure.

[0133] The source of the fourth MOSFET Q4 is connected to the source of the third MOSFET Q3, the drain of the fourth MOSFET Q4 is connected to the drain of the sixth MOSFET Q6, and the gate of the fourth MOSFET Q4 is connected to the first end of the second resistor R2 of the reference generation structure.

[0134] The source of the fifth MOSFET Q5 is connected to the negative power supply, and the gate and drain of the fifth MOSFET Q5 are connected and connected to the gate of the sixth MOSFET Q6.

[0135] The source of the sixth MOSFET Q6 is connected to the negative power supply; the drain of the sixth MOSFET Q6 is connected to the drain of the seventh MOSFET Q7; the source of the seventh MOSFET Q7 is connected to the negative power supply; the gate and drain of the seventh MOSFET Q7 are connected and connected to the gate of the twenty-first MOSFET Q21.

[0136] The source of the 21st MOSFET Q21 is connected to the negative power supply, and the drain of the 21st MOSFET Q21 is connected to the source of the 18th MOSFET Q18.

[0137] The drain of the eighteenth MOSFET Q18 is connected to the drain of the nineteenth MOSFET Q19, and the gate of the eighteenth MOSFET Q18 is connected to the positive power supply.

[0138] The source of the nineteenth MOSFET Q19 is connected to the positive power supply. The drain of the nineteenth MOSFET Q19 is connected to the source of the seventeenth MOSFET Q17 and the eighteenth MOSFET Q18, respectively. The gate of the seventeenth MOSFET Q17 is connected to the gate of the eighteenth MOSFET Q18 and is connected to the positive power supply.

[0139] It should be noted that, in the embodiments of this specification, the first MOSFET, the second MOSFET, the third MOSFET, the fourth MOSFET, and the nineteenth MOSFET are P-channel enhancement-type MOSFETs; and the fifth MOSFET, the sixth MOSFET, the seventh MOSFET, the eighteenth MOSFET, and the twenty-first MOSFET are N-channel enhancement-type MOSFETs.

[0140] Specifically, see Figure 3 The reference current generation structure includes:

[0141] The 8th MOSFET Q8, the 9th MOSFET Q9, the 10th MOSFET Q10, the 11th transistor Q11, the 12th transistor Q12, the 13th MOSFET Q13, the 14th MOSFET Q14, the 15th MOSFET Q15, the 16th MOSFET Q16, the 17th MOSFET Q17, the 20th MOSFET Q20, the second resistor R2R2, and the third resistor R3R3;

[0142] The source of the eighth MOS transistor Q8 is connected to the positive power supply, the drain of the eighth MOS transistor Q8 is connected to the first end of the second resistor R2, and the gate of the eighth MOS transistor Q8 is connected to the gate of the ninth MOS transistor Q9.

[0143] The second terminal of the second resistor R2 is connected to the first terminal of the third resistor R3; the second terminal of the third resistor R3 is connected to the collector of the eleventh transistor Q11.

[0144] The base of transistor Q11 is connected to the collector of transistor Q11, and the emitter of transistor Q11 is connected to the negative power supply.

[0145] The source of the ninth MOSFET Q9 is connected to the positive power supply, the drain of the ninth MOSFET Q9 is connected to the collector of the twelfth MOSFET Q12, and the gate of the ninth MOSFET Q9 is connected to the gate of the tenth MOSFET Q10; the base and collector of the twelfth MOSFET Q12 are connected, and the emitter of the twelfth MOSFET Q12 is connected to the negative power supply.

[0146] The source of the tenth MOSFET Q10 is connected to the positive power supply, and the drain of the tenth MOSFET Q10 is connected to the source of the thirteenth MOSFET Q13 and the fourteenth MOSFET Q14 respectively. The gate of the thirteenth MOSFET Q13 is connected to the drain of the nineteenth MOSFET Q19, which is part of the power-on startup structure.

[0147] The drain of the thirteenth MOSFET Q13 is connected to the drain of the fifteenth MOSFET Q15, and the gate of the thirteenth MOSFET Q13 is connected to the drain of the ninth MOSFET Q9.

[0148] The drain of the fourteenth MOSFET Q14 is connected to the drain of the sixteenth MOSFET Q16, and the gate of the fourteenth MOSFET Q14 is connected to the first terminal of the third resistor R3.

[0149] The drain of the fifteenth MOSFET Q15 is connected to the gate and is also connected to the gate of the sixteenth MOSFET Q16. The source of the fifteenth MOSFET Q15 is connected to the negative power supply.

[0150] The gate of the sixteenth MOSFET Q16 is connected to the gate of the fifteenth MOSFET Q15, the source of the sixteenth MOSFET Q16 is connected to the negative power supply, and the drain of the sixteenth MOSFET Q16 is also connected to the gate of the twentieth MOSFET Q20.

[0151] The drain of the seventeenth MOSFET Q17 is connected to the drain of the nineteenth MOSFET Q19 in the power-on structure. The source of the seventeenth MOSFET Q17 is connected to the drain of the twentieth MOSFET Q20. The gate of the seventeenth MOSFET Q17 is connected to the positive power supply. The source of the twentieth MOSFET Q20 is connected to the negative power supply.

[0152] It should be noted that, in the embodiments of this specification, the eighth, ninth, tenth, thirteenth, and fourteenth MOSFETs are P-channel enhancement-type MOSFETs; the eleventh and twelfth MOSFETs are equivalent NPN transistors composed of multiple NPN transistors, and the ratio of the number of NPN transistors in the eleventh to the twelfth MOSFETs is a1:1; the fifteenth, sixteenth, seventeenth, and twentieth MOSFETs are N-channel enhancement-type MOSFETs.

[0153] Specifically, see Figure 3 The reference current copy structure includes:

[0154] The twenty-second MOSFET Q22, the twenty-third MOSFET Q23, the twenty-fourth transistor Q24, the twenty-fifth MOSFET Q25, the twenty-sixth MOSFET Q26, the twenty-seventh MOSFET Q27, the fourth resistor R4, and the fifth resistor R5;

[0155] The source of the 22nd MOSFET Q22 is connected to the positive power supply, the drain of the 22nd MOSFET Q22 is connected to the drain of the 23rd MOSFET Q23, and the gate of the 22nd MOSFET Q22 is connected to the drain of the 19th MOSFET Q19 in the power-on structure.

[0156] The source of the 23rd MOSFET Q23 is connected to the emitter of the 24th MOSFET Q24. The gate and drain of the 23rd MOSFET Q23 are connected and also connected to the gate of the 26th MOSFET Q26. The base and collector of the 24th MOSFET are both connected to the negative power supply.

[0157] The first terminal of the fourth resistor R4 is connected to the positive power supply, and the second terminal of the fourth resistor R4 is connected to the source of the twenty-fifth MOSFET Q25.

[0158] The drain of the 25th MOSFET Q25 is connected to the drain of the 26th MOSFET Q26, and the gate of the 25th MOSFET Q25 is connected to the gate of the 22nd MOSFET Q22.

[0159] The source of the 26th MOSFET Q26 is connected to the drain of the 27th MOSFET Q27, and the gate of the 26th MOSFET Q26 is connected to the gate of the 23rd MOSFET Q23.

[0160] The source of the 27th MOSFET Q27 is connected to the first terminal of the fifth resistor R5, and the gate and drain of the 27th MOSFET Q27 are connected; the second terminal of the fifth resistor R5 is connected to the negative power supply.

[0161] Among them, the gate of the twenty-fifth MOSFET Q25 is the first potential output 11 of the bias circuit 10, and the gate of the twenty-seventh MOSFET Q27 is the second potential output 12 of the bias circuit 10.

[0162] It should be noted that in the embodiments of this specification, the 22nd and 25th MOSFETs are P-channel enhancement-type MOSFETs; the 24th transistor is a PNP transistor; and the 23rd, 26th, and 27th MOSFETs are N-channel enhancement-type MOSFETs.

[0163] When the entire circuit is powered on, the bias circuit starts working, thereby driving the overall circuit to operate. During operation, the follower circuit ensures that the reverse bias voltage drop of the ESD protection diodes in the ESD protection circuit, the positive ESD matching circuit, and the negative ESD matching circuit are consistent. Through the action of the first current mirror circuit, the positive ESD reverse bias copy current generated by the positive ESD matching circuit, after being copied according to a set ratio, is consistent with the reverse bias current generated by the ESD diode in the ESD protection circuit. Since the two currents are in the same direction, they complement each other. Similarly, through the action of the second current mirror circuit, the negative ESD reverse bias copy current is consistent with the reverse bias current generated by the ESD diode in the ESD protection circuit, complementing each other. Because the ESD reverse bias currents are mutually complementary, no external circuit is needed to provide the ESD reverse bias current, thus achieving a low input bias current. Furthermore, the clamping effect of the follower circuit is applicable under any common-mode voltage, thus achieving a low input bias current across the entire common-mode voltage range.

[0164] Specifically, see Figure 2 The follower circuit 20 includes:

[0165] Copy potential input, clamp potential input, and clamp potential output;

[0166] The copy potential input is connected to the potential output of the bias circuit 10, the clamping potential input is connected to the ESD protection circuit 70, and the clamping potential output is connected to the positive ESD matching circuit 30 and the negative ESD matching circuit 60 respectively.

[0167] The clamping voltage output of the follower circuit 20 controls the reverse bias voltage of the positive ESD matching circuit 30 and the negative ESD matching circuit 60, respectively.

[0168] Specifically, see Figure 3 The follower circuit 20 includes:

[0169] The 32nd MOSFET Q32, the 33rd MOSFET Q33, the 34th MOSFET Q34, the 35th MOSFET Q35, the 36th MOSFET Q36, the 37th MOSFET Q37, the 7th resistor R7, the 8th resistor R8, and the 9th resistor R9;

[0170] The drain of the thirty-second MOSFET Q32 is connected to the positive power supply, the source of the thirty-second MOSFET Q32 is connected to the drain of the thirty-fourth MOSFET Q34, and the gate of the thirty-second MOSFET Q32 is connected to the positive terminal of the second diode D2 of the positive ESD matching circuit 30.

[0171] The source of the 34th MOSFET Q34 is connected to the first terminal of the 7th resistor R7, and the second terminal of the 7th resistor R7 is connected to the negative power supply.

[0172] The drain of the 33rd MOSFET Q33 is connected to the positive power supply, the source of the 33rd MOSFET Q33 is connected to the drain of the 34th MOSFET Q34, and the gate of the 33rd MOSFET Q33 is connected to the negative terminal of the first diode D1 in the negative ESD matching circuit 60.

[0173] The drain of the 35th MOSFET Q35 is connected to the drain of the 34th MOSFET Q34, the source of the 35th MOSFET Q35 is connected to the first terminal of the 8th resistor R8, and the gate of the 35th MOSFET Q35 is connected to the gate of the 34th MOSFET Q34.

[0174] The second terminal of the eighth resistor R8 is connected to the negative power supply; the first terminal of the ninth resistor R9 is connected to the positive power supply, and the second terminal is connected to the source of the thirty-sixth MOSFET Q36; the drain of the thirty-sixth MOSFET Q36 is connected to the source of the thirty-seventh MOSFET Q37; the drain of the thirty-seventh MOSFET Q37 is connected to the negative power supply, and the gate of the thirty-seventh MOSFET Q37 is connected to the source of the thirty-third MOSFET Q33.

[0175] It should be noted that, in the embodiments of this specification, the 32nd, 33rd, 34th, and 35th MOSFETs are N-channel enhancement-type MOSFETs; and the 36th and 37th MOSFETs are P-channel enhancement-type MOSFETs.

[0176] The follower circuit 20 further includes:

[0177] The gate of the thirty-second MOSFET Q32 is the first clamping potential output 23 of the follower circuit 20, and the gate of the thirty-third MOSFET Q33 is the second clamping potential output 24 of the follower circuit 20.

[0178] The gate of the thirty-fourth MOSFET Q34 is the first copy potential input 21 of the follower circuit 20 and is connected to the second potential output 12 of the bias circuit 10, which is the gate of the twenty-seventh MOSFET Q27.

[0179] The gate of the thirty-sixth MOSFET Q36 is the second copy potential input 22 of the follower circuit 20, and is connected to the first potential output 11 of the bias circuit 10, which is the gate of the twenty-fifth MOSFET Q25.

[0180] The 37th MOSFET Q37 drain is followed by a clamping potential input of 25.

[0181] The first copy potential input 21 of the follower circuit 20 is connected to the second potential output 12 of the bias circuit, and the second copy potential input 22 of the follower circuit 20 is connected to the first potential output 11 of the bias circuit.

[0182] Specifically, see Figure 2 The positive ESD matching circuit 30 includes:

[0183] Positive ESD reverse bias potential input and positive ESD reverse bias current output;

[0184] The positive ESD reverse bias potential input is connected to the follower circuit 20, and the positive ESD reverse bias current output is connected to the first current mirror circuit 40.

[0185] The positive ESD matching circuit 30 controls the current of the first current mirror copy by outputting the positive ESD reverse bias current.

[0186] Specifically, see Figure 3 The positive ESD matching circuit 30 includes:

[0187] The cathode of the second diode D2 is connected to the positive power supply.

[0188] The anode of the second diode D2 is the positive ESD reverse bias potential input 31 and the positive ESD reverse bias current output of the positive ESD matching circuit 30;

[0189] The positive ESD reverse bias potential input 31 of the positive ESD matching circuit 30 is connected to the first clamp output 23 of the follower circuit 20.

[0190] Specifically, see Figure 3 The first current mirror circuit 40 includes:

[0191] The 30th MOSFET Q30, the 31st MOSFET Q31, the 40th MOSFET Q40, the 41st MOSFET Q41, and the 10th resistor R10;

[0192] The drain of the thirtieth MOSFET Q30 is connected to the second terminal of the tenth resistor R10, the source of the thirtieth MOSFET Q30 is connected to the drain of the thirtieth MOSFET Q31, and the gate of the thirtieth MOSFET Q30 is connected to the first terminal of the tenth resistor R10.

[0193] The gate of the thirty-first MOSFET Q31 is connected to the second terminal of the tenth resistor R10, and the source of the thirty-first MOSFET Q31 is connected to the negative power supply.

[0194] The source of the 40th MOSFET Q40 is connected to the drain of the 41st MOSFET Q41, and the gate of the 40th MOSFET Q40 is connected to the gate of the 30th MOSFET Q30.

[0195] The source of the forty-first MOSFET Q41 is connected to the negative power supply, and the gate of the forty-first MOSFET Q41 is connected to the gate of the thirty-first MOSFET Q31.

[0196] It should be noted that the first current mirror circuit in the embodiments of this specification includes a positive ESD reverse-biased leakage current input and a positive ESD reverse-biased leakage current copy output. The positive ESD reverse-biased leakage current input is connected to the positive ESD matching circuit, and the positive ESD reverse-biased leakage current copy output is connected to the ESD protection circuit.

[0197] Specifically, the first current mirror circuit 40 further includes:

[0198] The first terminal of the tenth resistor R10 is the positive ESD reverse bias leakage current input of the first current mirror circuit 40, and the drain of the fortieth MOS transistor Q40 is the positive ESD reverse bias leakage current copy output 42 of the first current mirror circuit 40.

[0199] The positive ESD reverse bias leakage current input 41 of the first current mirror circuit 40 is connected to the positive ESD reverse bias current output 31 of the positive ESD matching circuit 30.

[0200] It should be noted that, in the embodiments of this specification, the thirtieth MOS transistor, the thirty-first MOS transistor, the fortieth MOS transistor, and the forty-first MOS transistor are N-channel enhancement-mode MOS transistors; the width-to-length ratio of the thirtieth MOS transistor to the fortieth MOS transistor is 1:a2, and the width-to-length ratio of the thirty-first MOS transistor to the forty-first MOS transistor is 1:a2.

[0201] Specifically, see Figure 2 The second current mirror circuit 50 includes:

[0202] Negative ESD reverse bias leakage current input 51 and negative ESD reverse bias leakage current copy output 52;

[0203] The negative ESD reverse-biased leakage current input 51 is connected to the negative ESD matching circuit 60, specifically to the negative ESD reverse-biased current output 61 of the negative ESD matching circuit 60. The negative ESD reverse-biased leakage current output 52 is connected to the ESD protection circuit 70.

[0204] Specifically, see Figure 3 The second current mirror circuit 50 also includes:

[0205] The twenty-eighth MOSFET Q28, the twenty-ninth MOSFET Q29, the thirty-eighth MOSFET Q38, the thirty-ninth MOSFET Q39, and the sixth resistor R6;

[0206] The source of the 28th MOSFET Q28 is connected to the positive power supply, the drain of the 28th MOSFET Q28 is connected to the source of the 29th MOSFET Q29, and the gate of the 28th MOSFET Q28 is connected to the first terminal of the sixth resistor R6.

[0207] The drain of the 29th MOSFET Q29 is connected to the first terminal of the sixth resistor R6, and the gate of the 29th MOSFET Q29 is connected to the second terminal of the sixth resistor R6.

[0208] The source of the thirty-eighth MOSFET Q38 is connected to the positive power supply, the drain of the thirty-eighth MOSFET Q38 is connected to the source of the thirty-ninth MOSFET Q39, and the gate of the thirty-eighth MOSFET Q38 is connected to the gate of the twenty-eighth MOSFET Q28.

[0209] The gate of the 39th MOSFET Q39 is connected to the gate of the 29th MOSFET Q29.

[0210] The second current mirror circuit 50 further includes:

[0211] The second terminal of the sixth resistor R6 is the negative ESD reverse bias leakage current input 51 of the second current mirror circuit 50, and the drain of the thirty-ninth MOS transistor Q39 is the negative ESD reverse bias leakage current copy output 52 of the second current mirror circuit 50.

[0212] The negative ESD reverse bias leakage current input 51 of the second current mirror circuit 50 is connected to the negative ESD reverse bias current output 61 of the negative ESD matching circuit 60.

[0213] It should be noted that, in the embodiments of this specification, the 28th MOS transistor, the 29th MOS transistor, the 38th MOS transistor, and the 39th MOS transistor are P-channel enhancement-type MOS transistors; the width-to-length ratio of the 28th MOS transistor to the 38th MOS transistor is 1:a3, and the width-to-length ratio of the 29th MOS transistor to the 39th MOS transistor is 1:a3.

[0214] Specifically, see Figure 2The negative ESD matching circuit 60 includes:

[0215] Negative ESD reverse bias potential input 61 and negative ESD reverse bias current output;

[0216] The negative ESD reverse bias potential input 61 is connected to the follower circuit 20, specifically to the second clamping potential output 24 of the follower circuit 20. The negative ESD reverse bias current output is connected to the second current mirror circuit 50.

[0217] The negative ESD matching circuit 60 outputs a negative ESD reverse bias current to control the current copied by the second current mirror circuit 50.

[0218] Specifically, see Figure 3 The negative ESD matching circuit 60 further includes:

[0219] First diode D1; the anode of first diode D1 is connected to the negative power supply, and the cathode of first diode D1 is the negative ESD reverse bias potential input 61 and the negative ESD reverse bias current output of negative ESD matching circuit 60.

[0220] The negative ESD reverse bias potential input 61 of the negative ESD matching circuit 60 is connected to the second clamp output 24 of the follower circuit 20.

[0221] Specifically, see Figure 2 The ESD protection circuit 70 includes:

[0222] The circuit includes a potential output and a current input. The potential output is connected to the follower circuit 20 and the internal working circuit, while the current input is connected to the first current mirror circuit 40 and the second current mirror circuit 50.

[0223] Specifically, see Figure 3 The ESD protection circuit 70 further includes:

[0224] Third diode D3 and fourth diode D4;

[0225] The cathode of the third diode D3 is connected to the positive power supply, and the anode is connected to the cathode of the fourth diode D4; the anode of the fourth diode D4 is connected to the negative power supply.

[0226] The ESD protection circuit 70 further includes:

[0227] The anode of the third diode D3 serves as both the 70° potential output and current input for the ESD protection circuit.

[0228] The ESD protection circuit 70 potential output is connected to the follower circuit 20 clamping potential input 25;

[0229] The ESD protection circuit 70 is connected to the current input, the positive ESD reverse bias leakage current copy output 42 of the first current mirror circuit 40, the negative ESD reverse bias leakage current copy output 52 of the second current mirror circuit 50, and the internal circuit.

[0230] The detailed working process of the embodiments of this application will be described below with reference to the accompanying drawings.

[0231] See Figure 2 The detailed working process of this embodiment is as follows: When the overall circuit is powered on, the starting power-on structure of the bias circuit 10 starts working and pulls the reference current generation structure to generate a reference current. This reference current is then copied to the follower circuit 20 through the reference current copying structure, thereby driving the overall circuit to work. During operation, the bias circuit 10 ensures that the reverse bias voltage drop of the ESD protection diodes in the follower circuit 20 is consistent with that of the ESD protection circuit 70, the positive ESD matching circuit 30, and the negative ESD matching circuit 60. The first current mirror circuit 40 ensures that the positive ESD reverse bias current generated by the positive ESD matching circuit 30 is copied according to a set ratio, making the generated positive ESD reverse bias copy current consistent with the reverse bias current generated by the third ESD diode in the ESD protection circuit 70. Since the two currents are in the same direction, they complement each other. Similarly, the second current mirror circuit 50 ensures that the negative ESD reverse bias copy current is consistent with the reverse bias current generated by the fourth ESD diode in the ESD protection circuit 70, thus complementing each other. Since the ESD reverse bias currents are mutually complementary, no external circuitry is needed to provide the ESD reverse bias current, thus achieving low input bias current. Because the clamping effect of the follower circuit 20 is applicable under any common-mode voltage, low input bias current can be achieved across the entire common-mode voltage range.

[0232] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An ESD protection circuit with low input bias current across all common-mode voltages, characterized in that, include: Bias circuit (10), follower circuit (20), positive ESD matching circuit (30), first current mirror circuit (40), second current mirror circuit (50), negative ESD matching circuit (60), ESD protection circuit (70) and internal working circuit; The bias circuit (10) is connected to the follower circuit (20); the follower circuit (20) is connected to the positive ESD matching circuit (30), the first current mirror circuit (40), the second current mirror circuit (50) and the negative ESD matching circuit (60) respectively; the ESD protection circuit (70) is connected to the internal working circuit. The positive ESD matching circuit (30) is connected to the first current mirror circuit (40); the first current mirror circuit (40) is connected to the second current mirror circuit (50) and the ESD protection circuit (70); the second current mirror circuit (50) is connected to the negative ESD matching circuit (60).

2. The circuit according to claim 1, characterized in that, The bias circuit (10) includes: Power-on startup structure, reference current generation structure, and reference current copying structure; The output terminal of the power-on startup structure is connected to the input terminal of the reference current generation structure, and the output terminal of the reference current generation structure is connected to the reference current copy structure; the potential output of the bias circuit controls the potential input of the tail current source of the follower circuit.

3. The circuit according to claim 2, characterized in that, The power-on startup structure includes: The first MOSFET, the second MOSFET, the third MOSFET, the fourth MOSFET, the fifth MOSFET, the sixth MOSFET, the seventh MOSFET, the eighteenth MOSFET, the nineteenth MOSFET, the twenty-first MOSFET, and the first resistor R1; The source of the first MOSFET is connected to the positive power supply, the drain of the first MOSFET is connected to the source of the second MOSFET, and the gate of the first MOSFET is connected to the first terminal of the first resistor. The drain of the second MOSFET is connected to the source of the third and fourth MOSFETs, and the gate of the second MOSFET is connected to the first terminal of the first resistor; the second terminal of the first resistor is connected to the negative power supply. The drain of the third MOSFET is connected to the drain of the fifth MOSFET, and the gate of the third MOSFET is connected to the first terminal of the third resistor of the reference generation structure. The source of the fourth MOSFET is connected to the source of the third MOSFET, the drain of the fourth MOSFET is connected to the drain of the sixth MOSFET, and the gate of the fourth MOSFET is connected to the first terminal of the second resistor of the reference generation structure. The source of the fifth MOSFET is connected to the negative power supply, and the gate and drain of the fifth MOSFET are connected and connected to the gate of the sixth MOSFET. The source of the sixth MOSFET is connected to the negative power supply; the drain of the sixth MOSFET is connected to the drain of the seventh MOSFET; the source of the seventh MOSFET is connected to the negative power supply; the gate of the seventh MOSFET is connected to the drain and is also connected to the gate of the twenty-first MOSFET. The source of the 21st MOSFET is connected to the negative power supply, and the drain of the 21st MOSFET is connected to the source of the 18th MOSFET. The drain of the eighteenth MOSFET is connected to the drain of the nineteenth MOSFET, and the gate of the eighteenth MOSFET is connected to the positive power supply. The source of the nineteenth MOSFET is connected to the positive power supply. The drain of the nineteenth MOSFET is connected to the sources of the seventeenth and eighteenth MOSFETs respectively. The gate of the seventeenth MOSFET is connected to the gate of the eighteenth MOSFET and connected to the positive power supply.

4. The circuit according to claim 2, characterized in that, The reference current generation structure includes: The eighth MOSFET, the ninth MOSFET, the tenth MOSFET, the eleventh MOSFET, the twelfth MOSFET, the thirteenth MOSFET, the fourteenth MOSFET, the fifteenth MOSFET, the sixteenth MOSFET, the seventeenth MOSFET, the twentieth MOSFET, the second resistor R2 and the third resistor R3; The source of the eighth MOS transistor is connected to the positive power supply, the drain of the eighth MOS transistor is connected to the first end of the second resistor, and the gate of the eighth MOS transistor is connected to the gate of the ninth MOS transistor. The second terminal of the second resistor is connected to the first terminal of the third resistor; the second terminal of the third resistor is connected to the collector of the eleventh transistor. The base of the eleventh transistor is connected to the collector of the eleventh transistor, and the emitter of the eleventh transistor is connected to the negative power supply. The source of the ninth MOSFET is connected to the positive power supply, the drain of the ninth MOSFET is connected to the collector of the twelfth MOSFET, and the gate of the ninth MOSFET is connected to the gate of the tenth MOSFET; the base and collector of the twelfth MOSFET are connected, and the emitter of the twelfth MOSFET is connected to the negative power supply. The source of the tenth MOSFET is connected to the positive power supply, and the drain of the tenth MOSFET is connected to the sources of the thirteenth and fourteenth MOSFETs respectively. The gate of the thirteenth MOSFET is connected to the drain of the nineteenth MOSFET in the power-on startup structure. The drain of the thirteenth MOSFET is connected to the drain of the fifteenth MOSFET, and the gate of the thirteenth MOSFET is connected to the drain of the ninth MOSFET. The drain of the fourteenth MOSFET is connected to the drain of the sixteenth MOSFET, and the gate of the fourteenth MOSFET is connected to the first terminal of the third resistor. The drain of the fifteenth MOSFET is connected to the gate and also connected to the gate of the sixteenth MOSFET. The source of the fifteenth MOSFET is connected to the negative power supply. The gate of the sixteenth MOSFET is connected to the gate of the fifteenth MOSFET, the source of the sixteenth MOSFET is connected to the negative power supply, and the drain of the sixteenth MOSFET is also connected to the gate of the twentieth MOSFET. The drain of the seventeenth MOSFET is connected to the drain of the nineteenth MOSFET in the power-on structure, the source of the seventeenth MOSFET is connected to the drain of the twentieth MOSFET, the gate of the seventeenth MOSFET is connected to the positive power supply, and the source of the twentieth MOSFET is connected to the negative power supply.

5. The circuit according to claim 2, characterized in that, The reference current copy structure includes: The twenty-second MOSFET, the twenty-third MOSFET, the twenty-fourth transistor, the twenty-fifth MOSFET, the twenty-sixth MOSFET, the twenty-seventh MOSFET, the fourth resistor, and the fifth resistor; The source of the 22nd MOSFET is connected to the positive power supply, the drain of the 22nd MOSFET is connected to the drain of the 23rd MOSFET, and the gate of the 22nd MOSFET is connected to the drain of the 19th MOSFET in the power-on structure. The source of the 23rd MOSFET is connected to the emitter of the 24th MOSFET, and the gate and drain of the 23rd MOSFET are connected and connected to the gate of the 26th MOSFET; the base and collector of the 24th MOSFET are both connected to the negative power supply. The first terminal of the fourth resistor is connected to the positive power supply, and the second terminal of the fourth resistor is connected to the source of the twenty-fifth MOSFET. The drain of the 25th MOSFET is connected to the drain of the 26th MOSFET, and the gate of the 25th MOSFET is connected to the gate of the 22nd MOSFET. The source of the 26th MOSFET is connected to the drain of the 27th MOSFET, and the gate of the 26th MOSFET is connected to the gate of the 23rd MOSFET. The source of the 27th MOSFET is connected to the first terminal of the fifth resistor, and the gate and drain of the 27th MOSFET are connected; the second terminal of the fifth resistor is connected to the negative power supply. Among them, the gate of the 25th MOSFET is the first potential output of the bias circuit, and the gate of the 27th MOSFET is the second potential output of the bias circuit.

6. The circuit according to claim 1, characterized in that, The follower circuit (20) includes: Copy potential input, clamp potential input, and clamp potential output; The copy potential input is connected to the potential output of the bias circuit (10), the clamp potential input is connected to the ESD protection circuit (70), and the clamp potential output is connected to the positive ESD matching circuit (30) and the negative ESD matching circuit (60) respectively. The clamping voltage output of the follower circuit (20) controls the reverse bias voltage of the positive ESD matching circuit (30) and the negative ESD matching circuit (60), respectively.

7. The circuit according to claim 6, characterized in that, The follower circuit (20) includes: The 32nd MOSFET, the 33rd MOSFET, the 34th MOSFET, the 35th MOSFET, the 36th MOSFET, the 37th MOSFET, the 7th resistor, the 8th resistor, and the 9th resistor; The drain of the 32nd MOS transistor is connected to the positive power supply, the source of the 32nd MOS transistor is connected to the drain of the 34th MOS transistor, and the gate of the 32nd MOS transistor is connected to the positive terminal of the second diode of the positive ESD matching circuit (30). The source of the 34th MOSFET is connected to the first terminal of the 7th resistor, and the second terminal of the 7th resistor is connected to the negative power supply. The drain of the 33rd MOSFET is connected to the positive power supply, the source of the 33rd MOSFET is connected to the drain of the 34th MOSFET, and the gate of the 33rd MOSFET is connected to the negative terminal of the first diode in the negative ESD matching circuit (60). The drain of the 35th MOSFET is connected to the drain of the 34th MOSFET, the source of the 35th MOSFET is connected to the first terminal of the 8th resistor, and the gate of the 35th MOSFET is connected to the gate of the 34th MOSFET. The second terminal of the eighth resistor is connected to the negative power supply; the first terminal of the ninth resistor is connected to the positive power supply, and the second terminal is connected to the source of the thirty-sixth MOSFET; the drain of the thirty-sixth MOSFET is connected to the source of the thirty-seventh MOSFET; the drain of the thirty-seventh MOSFET is connected to the negative power supply, and the gate of the thirty-seventh MOSFET is connected to the source of the thirty-third MOSFET.

8. The circuit according to claim 7, characterized in that, The follower circuit (20) further includes: The gate of the thirty-second MOS transistor is the first clamping potential output of the follower circuit (20), and the gate of the thirty-third MOS transistor is the second clamping potential output of the follower circuit (20). The gate of the 34th MOS transistor is the first copy potential input of the follower circuit (20) and is connected to the second potential output of the bias circuit, i.e., the gate of the 27th MOS transistor; The gate of the thirty-sixth MOS transistor is the second copy potential input of the follower circuit and is connected to the first potential output of the bias circuit, which is the gate of the twenty-fifth MOS transistor. The thirty-seventh MOS transistor drain-follower circuit (20) clamps the potential input.

9. The circuit according to claim 1, characterized in that, The positive ESD matching circuit (30) includes: Positive ESD reverse bias potential input and positive ESD reverse bias current output; The positive ESD reverse bias potential input is connected to the follower circuit (20), and the positive ESD reverse bias current output is connected to the first current mirror circuit (40). The positive ESD matching circuit (30) controls the current of the first current mirror copy by outputting the positive ESD reverse bias current.

10. The circuit according to claim 9, characterized in that, The positive ESD matching circuit (30) includes: The second diode has its cathode connected to the positive power supply. The anode of the second diode is the positive ESD reverse bias potential input and positive ESD reverse bias current output of the positive ESD matching circuit (30); The positive ESD reverse bias potential input of the positive ESD matching circuit (30) is connected to the first clamp output of the follower circuit (20).

11. The circuit according to claim 1, characterized in that, The first current mirror circuit (40) includes: The 30th MOSFET, the 31st MOSFET, the 40th MOSFET, the 41st MOSFET, and the 10th resistor; The drain of the thirtieth MOS transistor is connected to the second terminal of the tenth resistor, the source of the thirtieth MOS transistor is connected to the drain of the thirty-first MOS transistor, and the gate of the thirtieth MOS transistor is connected to the first terminal of the tenth resistor. The gate of the thirty-first MOSFET is connected to the second terminal of the tenth resistor, and the source of the thirty-first MOSFET is connected to the negative power supply. The source of the 40th MOSFET is connected to the drain of the 41st MOSFET, and the gate of the 40th MOSFET is connected to the gate of the 30th MOSFET. The source of the forty-first MOSFET is connected to the negative power supply, and the gate of the forty-first MOSFET is connected to the gate of the thirty-first MOSFET.

12. The circuit according to claim 11, characterized in that, The first current mirror circuit (40) further includes: The first terminal of the tenth resistor is the positive ESD reverse bias leakage current input of the first current mirror circuit, and the drain of the fortieth MOS transistor is the positive ESD reverse bias leakage current copy output of the first current mirror circuit (40). The positive ESD reverse bias leakage current input of the first current mirror circuit (40) is connected to the positive ESD reverse bias current output of the positive ESD matching circuit (30).

13. The circuit according to claim 1, characterized in that, The second current mirror circuit (50) includes: Negative ESD reverse bias leakage current input and negative ESD reverse bias leakage current copy output; The negative ESD reverse-biased leakage current input is connected to the negative ESD matching circuit, and the negative ESD reverse-biased leakage current copy output is connected to the ESD protection circuit.

14. The circuit according to claim 13, characterized in that, The second current mirror circuit (50) also includes: The 28th MOSFET, the 29th MOSFET, the 38th MOSFET, the 39th MOSFET, and the 6th resistor; The source of the 28th MOSFET is connected to the positive power supply, the drain of the 28th MOSFET is connected to the source of the 29th MOSFET, and the gate of the 28th MOSFET is connected to the first terminal of the sixth resistor. The drain of the 29th MOSFET is connected to the first terminal of the 6th resistor, and the gate of the 29th MOSFET is connected to the second terminal of the 6th resistor. The source of the thirty-eighth MOS transistor is connected to the positive power supply, the drain of the thirty-eighth MOS transistor is connected to the source of the thirty-ninth MOS transistor, and the gate of the thirty-eighth MOS transistor is connected to the gate of the twenty-eighth MOS transistor. The gate of the 39th MOS transistor is connected to the gate of the 29th MOS transistor.

15. The circuit according to claim 14, characterized in that, The second current mirror circuit (50) also includes: The second terminal of the sixth resistor is the negative ESD reverse bias leakage current input of the second current mirror circuit, and the drain of the thirty-ninth MOS transistor is the negative ESD reverse bias leakage current copy output of the second current mirror circuit. The negative ESD reverse bias leakage current input of the second current mirror circuit (50) is connected to the negative ESD reverse bias current output of the negative ESD matching circuit (60).

16. The circuit according to claim 1, characterized in that, The negative ESD matching circuit (60) includes: Negative ESD reverse bias potential input and negative ESD reverse bias current output; The negative ESD reverse bias potential input is connected to the follower circuit (20), and the negative ESD reverse bias current output is connected to the second current mirror circuit (50); The negative ESD reverse bias current output of the negative ESD matching circuit (60) controls the current copied by the second current mirror circuit (50).

17. The circuit according to claim 16, characterized in that, The negative ESD matching circuit (60) also includes: First diode; the anode of the first diode is connected to the negative power supply, and the cathode of the first diode is the negative ESD reverse bias potential input and negative ESD reverse bias current output of the negative ESD matching circuit (60); The negative ESD reverse bias potential input of the negative ESD matching circuit (60) is connected to the second clamp output of the follower circuit (20).

18. The circuit according to claim 1, characterized in that, The ESD protection circuit (70) includes: Potential output and current input, the potential output is connected to the follower circuit (20) and the internal working circuit, and the current input is connected to the first current mirror circuit (40) and the second current mirror circuit (50).

19. The circuit according to claim 18, characterized in that, The ESD protection circuit (70) also includes: Third diode and fourth diode; The cathode of the third diode is connected to the positive power supply, and the anode is connected to the cathode of the fourth diode; the anode of the fourth diode is connected to the negative power supply.

20. The circuit according to claim 19, characterized in that, The ESD protection circuit (70) also includes: The anode of the third diode is the potential output and current input of the ESD protection circuit (70); The potential output of the ESD protection circuit (70) is connected to the clamping potential input of the follower circuit (20); The current input of the ESD protection circuit (70) is connected to the positive ESD reverse bias leakage current copy output of the first current mirror circuit (40) and the negative ESD reverse bias leakage current copy output of the second current mirror circuit (50).

Images