Method and apparatus for frequency control of central processing unit (CPU) core, and electronic device

Abstract

The application discloses a frequency control method and device of a CPU core and electronic equipment, and relates to the technical field of terminals. The specific technical scheme is as follows: the electronic equipment can acquire an interactive thread list; the interactive thread list comprises thread information, which is used for indicating an interactive thread for processing a user-perceptible event; and a frequency upper limit value of a first CPU core and at least one second CPU core is adjusted according to a first load parameter and a first power consumption threshold value; wherein a running queue of the first CPU core comprises the interactive thread; the first load parameter is a load parameter of the first CPU core running the interactive thread; the at least one second CPU core is a CPU core other than the first CPU core; and the first power consumption threshold value is a total power consumption upper limit value of the first CPU core and the at least one second CPU core.

Description

Technical Field

[0001] This application belongs to the field of terminal technology, specifically relating to a CPU core frequency control method, device, and electronic device. Background Technology

[0002] Currently, electronic devices are equipped with multiple preset temperature levels. Each preset temperature level is associated with a power consumption threshold and a ceiling frequency value for the central processing unit (CPU) core. In this way, the electronic device can select an appropriate temperature level based on its current temperature and limit the power consumption of each CPU core based on the power consumption threshold and ceiling frequency value associated with the selected temperature level, thereby preventing the electronic device from operating at high temperatures for a long time.

[0003] However, since the ceiling frequency value associated with the selected temperature setting of an electronic device may be inappropriate, this may result in some CPU cores running threads with lower efficiency, thus causing the electronic device to lag. Summary of the Invention

[0004] The purpose of this application is to provide a CPU core frequency control method, device, and electronic device that can make the upper limit of the CPU core running the interactive thread related to user interaction compatible with the load parameters of the interactive thread, and can avoid the total power consumption of the electronic device's CPU core being too high due to adjusting the CPU core, thereby improving the smoothness of the electronic device while reducing the power consumption of the electronic device.

[0005] In a first aspect, embodiments of this application provide a CPU core frequency control method, the method comprising: an electronic device acquiring an interactive thread list; the interactive thread list including thread information, the thread information indicating an interactive thread for processing user-perceptible events; and adjusting the upper limit of the frequency of a first CPU core and at least one second CPU core according to a first load parameter and a first power consumption threshold; wherein the running queue of the first CPU core includes interactive threads; the first load parameter is the load parameter of the first CPU core running interactive threads; the at least one second CPU core is a CPU core other than the first CPU core; and the first power consumption threshold is the upper limit of the total power consumption of the first CPU core and at least one second CPU core.

[0006] In some embodiments of this application, adjusting the upper frequency limit of the first CPU core and at least one second CPU core based on the first load parameter and the first power consumption threshold includes: the electronic device can determine the first upper frequency limit corresponding to the first load parameter; and increase the upper frequency limit of the first CPU core based on the first upper frequency limit, and determine a first remaining power consumption value based on the first upper frequency limit and the first power consumption threshold; the first remaining power consumption value is the maximum total remaining power consumption value of at least one second CPU core; and decrease the upper frequency limit of at least one second CPU core based on the first remaining power consumption value; wherein the adjustment range of the upper frequency limit of the first CPU core is positively correlated with the first upper frequency limit.

[0007] In some embodiments of this application, determining the first remaining power consumption value based on the first frequency upper limit and the first power consumption threshold includes: the electronic device can determine the maximum power consumption value corresponding to the first frequency upper limit based on the correspondence between the frequency upper limit and the remaining power consumption value; the maximum power consumption value is the maximum power consumption value available to the first CPU core; and the difference between the first power consumption threshold and the maximum power consumption value is determined as the first remaining power consumption value.

[0008] In some embodiments of this application, the above-mentioned reduction of the upper frequency limit of at least one second CPU core based on the first remaining power consumption value includes: the electronic device can construct at least one first function, each first function being used to characterize the rate of change of the energy efficiency ratio of a second CPU core with the frequency value; and solve each first function according to constraints to obtain the predicted frequency value of the second CPU core corresponding to each first function; the constraints include: the rate of change represented by each first function is the same, the first maximum power consumption value is greater than or equal to the total power consumption value of at least one second CPU core, and the difference between the first maximum power consumption value and the total power consumption value of at least one second CPU core is less than or equal to the difference threshold value; and the upper frequency limit of each second CPU core is reduced according to the predicted frequency value of each second CPU core; the adjustment range of the upper frequency limit of each second CPU core is positively correlated with the predicted frequency value of each second CPU core.

[0009] In some embodiments of this application, before adjusting the upper frequency limit of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold, the method further includes: the electronic device can determine a second load parameter; the second load parameter is the actual load parameter of the first CPU core running an interactive thread; and the product of the second load parameter and the first parameter value is determined as the first load parameter; wherein the parameter value of the second load parameter is greater than the parameter value of the first load parameter.

[0010] In some embodiments of this application, after adjusting the upper frequency limit of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold, the method further includes: the electronic device can adjust the upper frequency limit of the first CPU core and at least one second CPU core according to the first power consumption threshold, even if the run queue of the first CPU core does not include interactive threads.

[0011] In some embodiments of this application, the above-mentioned adjustment of the upper frequency limit of the first CPU core and at least one second CPU core includes: the electronic device can lower the upper frequency limit of the first CPU and raise the upper frequency limit of at least one second CPU core.

[0012] In some embodiments of this application, after adjusting the upper frequency limits of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold, the method further includes: when the electronic device migrates the interaction thread from the run queue of the first CPU core to the run queue of the third CPU core among the at least one second CPU core, the upper frequency limit of the third CPU core is adjusted to a second upper frequency limit, and the upper frequency limit of the first CPU core is adjusted to a third upper frequency limit; wherein the second upper frequency limit is the upper frequency limit of the first CPU core before the interaction thread migrates out of the run queue of the first CPU core; and the third upper frequency limit is the upper frequency limit of the third CPU core before the interaction thread migrates to the run queue of the third CPU core.

[0013] In some embodiments of this application, the above method further includes: when the power consumption threshold associated with the temperature setting of the electronic device changes from a first power consumption threshold to a second power consumption threshold, the electronic device adjusts the upper frequency limit of the first CPU core and at least one second CPU core according to the second power consumption threshold.

[0014] In some embodiments of this application, before obtaining the interaction thread list, the method further includes: the electronic device can add the thread information of the first application thread to the interaction thread list if the first application thread meets a first condition; wherein the first application thread is any application thread of the electronic device; wherein the first condition includes at least one of the following: the application thread is a thread of an application running in the foreground; the application thread is a thread for processing an image to be displayed; the application thread is a thread for processing audio data; the application thread is a thread for processing data transmission packets of an application running in the foreground.

[0015] In some embodiments of this application, after adding the thread information of the first application thread to the interactive thread list, the method further includes: the electronic device can delete the thread information of the first application thread from the interactive thread list if the first application thread does not meet the first condition.

[0016] Secondly, embodiments of this application provide a CPU core frequency control device, which includes an acquisition module and a processing module. The acquisition module is used to acquire an interactive thread list; the interactive thread list includes thread information, which indicates an interactive thread used to process user-perceptible events. The processing module is used to adjust the upper frequency limit of a first CPU core and at least one second CPU core according to a first load parameter and a first power consumption threshold; wherein the run queue of the first CPU core includes interactive threads; the first load parameter is the load parameter for the first CPU core to run interactive threads; the at least one second CPU core is a CPU core other than the first CPU core; and the first power consumption threshold is the upper limit of the total power consumption of the first CPU core and at least one second CPU core.

[0017] In some embodiments of this application, the above-mentioned processing module is specifically used to determine a first frequency upper limit value corresponding to the first load parameter; and according to the first frequency upper limit value, increase the frequency upper limit value of the first CPU core, and according to the first frequency upper limit value and the first power consumption threshold value, determine a first remaining power consumption value; the first remaining power consumption value is the maximum total power consumption value that at least one second CPU core can still use; and according to the first remaining power consumption value, decrease the frequency upper limit value of at least one second CPU core; wherein, the adjustment range of the frequency upper limit value of the first CPU core is positively correlated with the first frequency upper limit value.

[0018] In some embodiments of this application, the above-mentioned processing module is specifically used to determine a first maximum power consumption value corresponding to the first frequency upper limit value based on the correspondence between the frequency upper limit value and the power consumption value; the first maximum power consumption value is the maximum power consumption value available to the first CPU core; and the difference between the first power consumption threshold value and the maximum power consumption value is determined as the first remaining power consumption value.

[0019] In some embodiments of this application, the above-mentioned processing module is specifically used to construct at least one first function, each first function being used to characterize the rate of change of the energy efficiency ratio of a second CPU core with a frequency value; and to solve each first function according to constraints to obtain the predicted frequency value of the second CPU core corresponding to each first function; the constraints include: the rate of change represented by each first function is the same, the first remaining power consumption value is greater than or equal to the total power consumption value of at least one second CPU core, and the difference between the first remaining power consumption value and the total power consumption value of at least one second CPU core is less than or equal to a difference threshold value; and to lower the upper frequency limit value of each second CPU core according to the predicted frequency value of each second CPU core; the adjustment range of the upper frequency limit value of each second CPU core is positively correlated with the predicted frequency value of each second CPU core.

[0020] In some embodiments of this application, the above-described processing module is further configured to determine a second load parameter before adjusting the upper frequency limit of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold; the second load parameter is the actual load parameter of the first CPU core running the interactive thread; and the product of the second load parameter and the first parameter value is determined as the first load parameter; wherein the parameter value of the second load parameter is greater than the parameter value of the first load parameter.

[0021] In some embodiments of this application, the above-described processing module is further configured to, after adjusting the upper frequency limit of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold, adjust the upper frequency limit of the first CPU core and at least one second CPU core according to the first power consumption threshold when the run queue of the first CPU core does not include interactive threads.

[0022] In some embodiments of this application, the above-described processing module is specifically used to lower the upper frequency limit of the first CPU and raise the upper frequency limit of at least one second CPU core.

[0023] In some embodiments of this application, the processing module is further configured to, after adjusting the upper frequency limits of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold, adjust the upper frequency limit of the third CPU core to the second upper frequency limit and adjust the upper frequency limit of the first CPU core to the third upper frequency limit when the interaction thread is migrated from the run queue of the first CPU core to the run queue of the third CPU core among the at least one second CPU core; wherein, the second upper frequency limit is the upper frequency limit of the first CPU core before the interaction thread is migrated out of the run queue of the first CPU core; and the third upper frequency limit is the upper frequency limit of the third CPU core before the interaction thread is migrated to the run queue of the third CPU core.

[0024] In some embodiments of this application, the above-described processing module is further configured to adjust the upper frequency limit of the first CPU core and at least one second CPU core according to the second power consumption threshold value when the power consumption threshold value associated with the temperature setting of the CPU core frequency control device changes from the first power consumption threshold value to the second power consumption threshold value.

[0025] In some embodiments of this application, the processing module is further configured to add the thread information of the first application thread to the interactive thread list before the acquisition module acquires the interactive thread list, provided that the first application thread meets a first condition; wherein the first application thread is any application thread of the CPU core frequency control device; wherein the first condition includes at least one of the following: the first application thread is a thread of a foreground application; the first application thread is a thread for processing an image to be displayed; the first application thread is a thread for processing audio data; the first application thread is a thread for processing data transmission packets of a foreground application.

[0026] In some embodiments of this application, the above-described processing module is further configured to, after adding the thread information of the first application thread to the interactive thread list, delete the thread information of the first application thread from the interactive thread list if the first application thread does not meet the first condition.

[0027] Thirdly, embodiments of this application provide an electronic device including a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions implementing the steps of the method as described in the first aspect when executed by the processor.

[0028] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method as described in the first aspect.

[0029] Fifthly, embodiments of this application provide a chip including a processor and a communication interface coupled to the processor, the processor being used to run programs or instructions to implement the method as described in the first aspect.

[0030] In a sixth aspect, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the method as described in the first aspect.

[0031] In this embodiment, since the electronic device can obtain an interaction thread list, it can identify each interaction thread used to process user-perceptible events through the thread information included in the interaction thread list, i.e., identify the interaction threads related to whether the electronic device experiences lag. Thus, the electronic device can dynamically adjust the upper frequency limit of the first CPU core and at least one second CPU core (excluding the first CPU core) based on the first load parameter and the first power consumption threshold value for the interaction thread run by the first CPU core. Therefore, on the one hand, the upper frequency limit value of the first CPU core can be adapted to the first load parameter, thereby improving the efficiency of the electronic device in running interaction threads related to whether the electronic device experiences lag, and thus reducing the occurrence of lag. On the other hand, it can avoid the situation where adjusting the first CPU core causes the total power consumption of the first CPU core and at least one second CPU core to exceed the first power consumption threshold value, i.e., causing a large total power consumption of the first CPU core and at least one second CPU core, thus reducing the power consumption of the electronic device. In this way, the smoothness of the electronic device can be improved while reducing its power consumption. Attached Figure Description

[0032] Figure 1 This is a flowchart illustrating a CPU core frequency control method provided in some embodiments of this application;

[0033] Figure 2 This is a flowchart illustrating a CPU core frequency control method provided in some embodiments of this application;

[0034] Figure 3 This is a flowchart illustrating a CPU core frequency control method provided in some embodiments of this application;

[0035] Figure 4 This is a flowchart illustrating a CPU core frequency control method provided in some embodiments of this application;

[0036] Figure 5 This is a flowchart illustrating a CPU core frequency control method provided in some embodiments of this application;

[0037] Figure 6 This is a flowchart illustrating a CPU core frequency control method provided in some embodiments of this application;

[0038] Figure 7 This is a schematic diagram of the structure of a CPU core frequency control device provided in some embodiments of this application;

[0039] Figure 8 These are schematic diagrams of the hardware structure of electronic devices provided in some embodiments of this application;

[0040] Figure 9These are schematic diagrams of the hardware structure of electronic devices provided in some embodiments of this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0042] The following will explain the technical terms used in the embodiments of this application.

[0043] CPU energy efficiency ratio: Each CPU core has a corresponding computing power at different frequencies (Frequency, f). and power consumption At this point, the energy efficiency ratio of each CPU core is The overall energy efficiency ratio of this CPU is It can be approximated as a nonlinear function of frequency f. As f increases, the energy efficiency ratio decreases rapidly, exhibiting a strong marginal effect.

[0044] Ceiling frequency value: The upper limit of the CPU core frequency. In other words, the highest frequency value of the CPU core must be less than or equal to this upper limit frequency value.

[0045] Frequency limiting parameters: These are parameters used to limit the ceiling frequency value of CPU cores for specific scenarios or the entire system, generally for temperature control or power consumption considerations. These parameters may include, but are not limited to, the upper limit of computing power, the upper limit of power consumption, and the upper limit of energy efficiency ratio.

[0046] Utility: Utility is an integer from 0 to 1024, calculated by the electronic device based on the cumulative runtime of threads on the CPU core. A higher utility value indicates a heavier load on the CPU core for that thread, requiring more computing power. This utility changes linearly and is mapped to the CPU core frequency, ensuring that the computing power at the corresponding frequency can meet the load requirements. It's important to note that utility is not an absolute value; the utility of the same thread running on different CPU cores can vary.

[0047] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0048] The terms "at least one," "at least one of," etc., used in the specification and claims of this application refer to any one, any two, or a combination of two or more of the included items. For example, at least one of a, b, and c can mean: "a," "b," "c," "a and b," "a and c," "b and c," and "a, b, and c," where a, b, and c can be single or multiple. Similarly, "at least two" refers to two or more items, and its meaning is similar to that of "at least one."

[0049] Currently, electronic devices are equipped with multiple preset temperature levels, each associated with a power consumption threshold and a maximum CPU core frequency. This allows the device to select an appropriate temperature level based on its current temperature and limit the power consumption of each CPU core according to the associated power consumption threshold and maximum frequency, thus preventing the device from operating at excessively high temperatures for extended periods. However, it's possible that the selected temperature level might be misaligned with the chosen maximum frequency, potentially leading to lower efficiency for some CPU cores and causing lag or stuttering in the electronic device.

[0050] To address the aforementioned problems, embodiments of this application provide a CPU core frequency control method, apparatus, and electronic device. The following, in conjunction with the accompanying drawings, provides a detailed description of the CPU core frequency control method, apparatus, and electronic device provided in this application through specific embodiments and application scenarios.

[0051] It should be noted that the CPU core frequency control method provided in this application can be executed by electronic devices such as mobile phones, tablets, laptops, PDAs, and in-vehicle electronic devices. Some embodiments of this application use electronic devices as the executing entity to illustrate the CPU core frequency control method provided in this application.

[0052] The CPU core frequency control method provided in this application embodiment can be applied to scenarios where users use electronic devices.

[0053] One specific application scenario is when users use electronic devices in high-temperature environments, and another specific application scenario is when users use electronic devices to play games.

[0054] Figure 1 A flowchart illustrating the CPU core frequency control method provided in an embodiment of this application is shown. Figure 1 As shown, the CPU core frequency control method provided in this application embodiment may include the following steps 101 and 102.

[0055] Step 101: The electronic device obtains the list of interaction threads.

[0056] In some embodiments of this application, the above-mentioned list of interactive threads includes thread information that indicates an interactive thread for handling user-perceptible events.

[0057] In some embodiments of this application, the aforementioned thread information may include, but is not limited to, at least one of the following: thread ID, thread data, process ID of the process to which the thread belongs, and application ID of the application to which the thread belongs. The number of such thread information entries may be at least one. Each thread information entry may be used to indicate an interactive thread for handling user-perceptible events.

[0058] In some embodiments of this application, the aforementioned user-perceptible events may include, but are not limited to, at least one of the following: user input events, rendering events of image frames to be displayed on the interface, processing events of played audio, response events to user operations, and transmission events of messages generated by user interaction.

[0059] The aforementioned image frame to be displayed can be understood as the next image frame after the currently displayed image frame on the interface.

[0060] In some embodiments of this application, an important thread identification system and a temperature control frequency modulation system may be provided in the electronic device, so that the electronic device can generate an interactive thread list through the important thread identification system and obtain the interactive thread list from the important thread identification system through the temperature control frequency modulation system.

[0061] It is understandable that electronic devices can learn about the aforementioned interaction threads through the interaction thread list. These are the interaction threads used to process user-perceptible events, and also the threads that determine whether the electronic device is experiencing lag.

[0062] Step 102: The electronic device adjusts the upper frequency limit of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold.

[0063] In some embodiments of this application, the run queue of the first CPU core includes interactive threads; the first load parameter is the load parameter of the first CPU core running interactive threads; the at least one second CPU core is a CPU core other than the first CPU core; and the first power consumption threshold is the upper limit of the total power consumption of the first CPU core and at least one second CPU core.

[0064] It can be understood that the first CPU core mentioned above is the CPU core that runs the aforementioned interactive thread.

[0065] In some embodiments of this application, the first CPU core described above may be a small core or a large core in the CPU of an electronic device.

[0066] In some embodiments of this application, the aforementioned at least one second CPU core may be at least a portion of the CPU cores of an electronic device, excluding the first CPU core. The at least one second CPU core may include at least one of the following: a small core and a large core.

[0067] It is understandable that the at least one second CPU core can be entirely small cores, partially small cores, or entirely large cores.

[0068] In some embodiments of this application, the aforementioned first power consumption threshold can be a power consumption threshold associated with the current temperature setting of the electronic device. The current temperature setting can be one of a plurality of preset temperature settings that matches the temperature of the electronic device, and each of these preset temperature settings can be associated with a power consumption upper limit value. It can be understood that the aforementioned first power consumption threshold is the upper limit value of power consumption associated with the current temperature setting of the electronic device.

[0069] In some embodiments of this application, the aforementioned upper frequency limit can be the ceiling frequency value associated with the current temperature setting of the electronic device.

[0070] For example, adjusting the first CPU core in step 102 can be understood as adjusting the ceiling frequency value of the first CPU core associated with the current temperature setting of the electronic device, and adjusting at least one second CPU core can be understood as adjusting the ceiling frequency value of at least one second CPU core associated with the current temperature setting of the electronic device.

[0071] In some embodiments of this application, the electronic device can first detect the running queues of each CPU core of the CPU of the electronic device through a temperature control frequency modulation system, and determine the CPU core whose running queue includes the thread information of the above-mentioned interactive thread as the first CPU core, and determine at least some of the CPU cores of the CPU other than the first CPU core as at least one second CPU core, and then adjust the upper limit of the frequency of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold value of the first CPU core running the interactive thread.

[0072] It is understandable that, when the interactive thread is added to the running queue of the first CPU core, the electronic device can adjust the upper frequency limit of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold value of the interactive thread running on the first CPU core.

[0073] In some embodiments of this application, the electronic device can first calculate the first load parameter based on the running time of the first CPU core running the above-mentioned interactive thread through a temperature control frequency adjustment system, and determine the first power consumption threshold value associated with the current temperature level of the electronic device. Thus, the electronic device can adjust the upper frequency limit value of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold value.

[0074] It should be noted that the explanation of how the first load parameter is calculated based on the running time of the first CPU core running the above-mentioned interactive thread can be found in the specific descriptions in related technologies, and will not be repeated here in the embodiments of this application.

[0075] For example, assuming an electronic device has five preset temperature settings, Table 1 shows the upper limit of power consumption at different preset temperature settings. As shown in Table 1:

[0076] Table 1

[0077]

[0078] Among them, one of the five preset temperature settings corresponds to a temperature of 30℃ and an associated power consumption limit of 400W; another of the five preset temperature settings corresponds to a temperature of 35℃ and an associated power consumption limit of 300W; yet another of the five preset temperature settings corresponds to a temperature of 40℃ and an associated power consumption limit of 200W; yet another of the five preset temperature settings corresponds to a temperature of 45℃ and an associated power consumption limit of 100W; and the last of the five preset temperature settings corresponds to a temperature of 50℃ and an associated power consumption limit of 50W.

[0079] For example, in a specific application scenario, such as when a user uses an electronic device in a high-temperature environment, assuming the temperature of the electronic device is 44℃, the electronic device can select another preset temperature level from the above 5 preset temperature levels based on 44℃ through the temperature control frequency modulation system, and determine the upper limit of power consumption of 200W associated with the other preset temperature level as the first power consumption threshold value.

[0080] To illustrate further, in another specific application scenario, such as when a user is playing a game on an electronic device, assuming the temperature of the electronic device is 38°C, the electronic device can use a temperature control frequency modulation system to select another preset temperature level from the above 5 preset temperature levels based on 38°C, and determine the power consumption upper limit of 300W associated with that other preset temperature level as the power consumption threshold value.

[0081] In some embodiments of this application, the electronic device can first adjust the upper limit of the frequency of the first CPU core according to the first load parameters mentioned above through a temperature control frequency modulation system, and then adjust the upper limit of the frequency of at least one second CPU core according to the adjusted upper limit of the frequency of the first CPU core.

[0082] It is understood that the electronic device can increase or decrease the upper frequency limit of the first CPU core based on the aforementioned first load parameters. The electronic device can decrease the upper frequency limit of at least one second CPU core based on the adjusted upper frequency limit of the first CPU core, or increase the upper frequency limit of at least one second CPU core based on the adjusted upper frequency limit of the first CPU core.

[0083] The following example illustrates the specific solution of this application embodiment by taking an electronic device that increases the upper limit of the frequency of the first CPU core and decreases the upper limit of the frequency of at least one second CPU core.

[0084] In some examples, combined Figure 1 ,like Figure 2 As shown, step 102 can be implemented through steps 102a to 102c as described below.

[0085] Step 102a: The electronic device determines the upper limit value of the first frequency corresponding to the first load parameter.

[0086] Optionally, when the values ​​of the first load parameters are different, the value of the first frequency upper limit value will also be different.

[0087] Optionally, the electronic device may first determine the corresponding maximum computing power based on the first load parameter mentioned above, and then determine the first frequency upper limit value corresponding to the maximum computing power based on the maximum computing power.

[0088] The electronic device has multiple first correspondences set up, which are the correspondences between load parameters and computing power. The electronic device can determine the maximum computing power corresponding to the first load parameter according to these multiple first correspondences.

[0089] The electronic device has multiple second correspondences, which are the correspondences between preset temperature levels and frequency limiting parameters. The frequency limiting parameters include: the upper limit of CPU core frequency, the upper limit of CPU core computing power, the upper limit of CPU core power consumption, and the upper limit of CPU core energy efficiency ratio. Thus, the electronic device can determine the upper limit of the first frequency corresponding to the maximum computing power according to the multiple second correspondences.

[0090] For example, Table 2 shows the frequency limiting parameters for different preset temperature settings. As shown in Table 2:

[0091] Table 2

[0092]

[0093] Within each of the five preset temperature levels, the frequency limiting parameters for the large and small cores differ. For example, at one preset temperature level, the small core's maximum frequency is 100MHz, maximum computing power is 800MIPS, maximum power consumption is 1W, and maximum energy efficiency is 800MIPS / W. At another preset temperature level, the large core's maximum frequency is 200MHz, maximum computing power is 2400MIPS, maximum power consumption is 4W, and maximum energy efficiency is 600MIPS / W. At yet another preset temperature level, the small core's maximum frequency is 200MHz, maximum computing power is 160MIPS, and maximum computing power is 100MIPS / W. 0 MIPS, with a power consumption cap of 2W and an energy efficiency cap of 800 MIPS / W. Under another preset temperature setting, the large core's frequency cap is 400MHz, its computing power cap is 4800 MIPS, its power consumption cap is 10W, and its energy efficiency cap is 480 MIPS / W. Under yet another preset temperature setting, the small core's frequency cap is 300MHz, its computing power cap is 2400 MIPS, its power consumption cap is 4W, and its energy efficiency cap is 600 MIPS / W. Under one preset temperature setting, the maximum frequency of the large cores is 600MHz, the maximum computing power is 7200MIPS, the maximum power consumption is 20W, and the maximum energy efficiency ratio is 360MIPS / W. Under another preset temperature setting, the maximum frequency of the small cores is 400MHz, the maximum computing power is 3200MIPS, the maximum power consumption is 15W, and the maximum energy efficiency ratio is 213.3MIPS / W. Under yet another preset temperature setting, the maximum frequency of the large cores is 800MHz, and the maximum computing power is 960MIPS / W. 0 MIPS, with a power consumption cap of 60W and an energy efficiency cap of 160 MIPS / W; at the last preset temperature setting mentioned above, the small core's frequency cap is 500 MHz, the computing power cap is 4000 MIPS, the power consumption cap is 40W, and the energy efficiency cap is 100 MIPS / W. At the same time, the large core's frequency cap is 1000 MHz, the computing power cap is 12000 MIPS, the power consumption cap is 200W, and the energy efficiency cap is 60 MIPS / W.

[0094] For example, in the specific application scenario described above, assuming that the first CPU core is a large core and the first load parameter of the first CPU core running the above-mentioned interactive thread is 800, the electronic device can determine the maximum computing power corresponding to 800 according to the above-mentioned multiple first correspondences, such as 7800 MIPS, and then determine the first frequency upper limit value corresponding to 7800 MIPS, such as 700 MHz, according to the above-mentioned multiple second correspondences.

[0095] To illustrate further, in another specific application scenario, assuming the first CPU core is a large core and the first load parameter of the first CPU core running the above-mentioned interactive thread is 900, the electronic device can determine the maximum computing power corresponding to 900 according to the above-mentioned multiple first correspondences, such as 8000 MIPS, and then determine the first frequency upper limit value corresponding to 8000 MIPS according to the above-mentioned multiple second correspondences, such as 750 MHz.

[0096] Step 102b: The electronic device increases the upper limit of the frequency of the first CPU core according to the first upper limit of the frequency, and determines the first remaining power consumption value according to the first upper limit of the frequency and the first power consumption threshold.

[0097] In some embodiments of this application, the adjustment range of the upper frequency limit of the first CPU core is positively correlated with the upper frequency limit.

[0098] Optionally, in one example, if the first frequency upper limit is greater than the current frequency upper limit of the first CPU core, the electronic device can adjust the frequency upper limit of the first CPU core to the first frequency upper limit to increase the frequency upper limit of the first CPU core.

[0099] Alternatively, in another example, the electronic device can determine the new frequency upper limit value by the sum of the current frequency upper limit value of the first CPU core and the first frequency upper limit value, and adjust the current frequency upper limit value of the first CPU core to the new frequency upper limit value.

[0100] Optionally, if the first frequency upper limit is less than or equal to the current frequency upper limit of the first CPU core, the electronic device can jump to the end. That is, the electronic device can stop performing the subsequent steps of adjusting the frequency upper limit, i.e., the electronic device can choose not to lower the frequency upper limit of the first CPU core.

[0101] It is understandable that if the upper limit of the first frequency is less than or equal to the current upper limit of the first CPU core, the electronic device can be considered to be not experiencing any lag. Therefore, the electronic device can proceed to the end.

[0102] Optionally, the electronic device can apply the first frequency upper limit value to the frequency upper limit value of the first CPU core in the CPU hardware through a driver, so as to adjust the frequency upper limit value of the first CPU core to the first frequency upper limit value.

[0103] For example, in the specific application scenario described above, the upper limit of the frequency of the large core is 600MHz under another preset temperature setting, and the upper limit of the first frequency is 700MHz. That is, the upper limit of the first frequency is greater than the upper limit of the frequency of the large core under another preset temperature setting. Thus, the electronic device can apply 700MHz to the upper limit of the frequency of the first CPU core in the CPU hardware through the driver, thereby setting the upper limit of the frequency of the first CPU core to 700MHz.

[0104] For example, in another specific application scenario mentioned above, the upper limit of the frequency of the large core is 600MHz under another preset temperature setting, and the upper limit of the first frequency is 750MHz. That is, the upper limit of the first frequency is greater than the upper limit of the frequency of the large core under another preset temperature setting. Thus, the electronic device can apply 750MHz to the upper limit of the frequency of the first CPU core in the CPU hardware through the driver, so that the upper limit of the frequency of the first CPU core can be set to 750MHz.

[0105] In some embodiments of this application, the first remaining power consumption value is the maximum total power consumption value that at least one second CPU core can still use.

[0106] Optionally, combined Figure 2 ,like Figure 3 As shown, step 102b can be implemented through steps 102b1 and 102b2 as described below.

[0107] Step 102b1: The electronic device increases the upper limit of the frequency of the first CPU core according to the first upper limit of the frequency, and determines the first maximum power consumption value corresponding to the first upper limit of the frequency based on the correspondence between the upper limit of the frequency and the power consumption value.

[0108] In some embodiments of this application, the first maximum power consumption value is the maximum power consumption value available to the first CPU core.

[0109] The electronic device has multiple third correspondences, namely the correspondence between the upper limit of frequency and the remaining power consumption value. The electronic device can determine the first maximum power consumption value corresponding to the first upper limit of frequency according to these multiple third correspondences.

[0110] For example, in one of the specific application scenarios described above, the electronic device can determine the first maximum power consumption value corresponding to 700MHz, such as 12W, according to the aforementioned multiple third correspondences.

[0111] To illustrate further, in another specific application scenario, the electronic device can determine the first maximum power consumption value corresponding to 750MHz, such as 14W, according to the aforementioned multiple third correspondences.

[0112] Step 102b2: The electronic device determines the difference between the first power consumption threshold and the first maximum power consumption value as the first remaining power consumption value.

[0113] The aforementioned first remaining power consumption value can be understood as the maximum remaining usable power consumption value of the electronic device at its current temperature setting.

[0114] For example, in one of the specific application scenarios mentioned above, the maximum power consumption of the large core at another preset temperature setting is 20W. The electronic device can then determine the difference between 20W and 12W as the first remaining power consumption value, that is, 8W as the first remaining power consumption value.

[0115] To illustrate further, in another specific application scenario, if the maximum power consumption of the large core is 20W under another preset temperature setting, the electronic device can determine the difference between 20W and 14W as the first remaining power consumption value, that is, determine 6W as the first remaining power consumption value.

[0116] Thus, after the electronic device increases the upper limit of the frequency of the first CPU core according to the first upper limit of the frequency, it can also determine the maximum power consumption value available for the first CPU core under the first upper limit of the frequency. Therefore, the electronic device can accurately calculate the first remaining power consumption value of at least one second CPU core based on the difference between the first power consumption threshold and the first maximum power consumption value. In this way, the electronic device can accurately adjust the upper limit of the frequency of at least one second CPU core in subsequent steps.

[0117] Step 102c: The electronic device lowers the frequency limit of at least one second CPU core based on the first remaining power consumption value.

[0118] Optionally, the electronic device may first determine the minimum total power consumption value of at least one second CPU core, and if the first remaining power consumption value is greater than or equal to the minimum total power consumption value of the at least one second CPU core, reduce the upper limit of the frequency of the at least one second CPU core according to the first remaining power consumption value.

[0119] Each of the aforementioned preset temperature levels corresponds to the minimum power consumption value of a CPU core, thereby enabling the electronic device to determine the sum of the minimum power consumption values ​​of each second CPU core as the minimum total power consumption value of at least one second CPU core.

[0120] If the first remaining power consumption value is less than the minimum total power consumption value of the at least one second CPU core, the electronic device can terminate the process. In other words, the electronic device can skip the subsequent frequency upper limit adjustment operation.

[0121] It is understandable that if the first remaining power consumption value is less than the minimum total power consumption value of the at least one second CPU core, it can be assumed that after adjusting the upper limit of the frequency of the first CPU core, the predicted frequency of at least one second CPU core may be too low to continue adjustment. Therefore, the electronic device can terminate.

[0122] For example, in the specific application scenario mentioned above, assuming that the minimum power consumption of the large core is 1W under another preset temperature setting, and the number of at least one second CPU core is 4, the electronic device can first determine the minimum total power consumption of the 4 second CPU cores, that is, 4×1=4W. The first remaining power consumption value of 8W is greater than 4W, so the electronic device can adjust the upper limit of the frequency of the 4 second CPU cores according to 8W.

[0123] To illustrate further, in one specific application scenario, assuming the minimum power consumption of the large core is 1W under another preset temperature setting, and the number of at least one second CPU core is 4, the electronic device can first determine the minimum total power consumption of the 4 second CPU cores, i.e., 4×1=4W. The first remaining power consumption value of 6W is greater than 4W, so the electronic device can adjust the upper limit of the frequency of the 4 second CPU cores based on 6W.

[0124] Therefore, since the electronic device can determine the first frequency upper limit value corresponding to the first load parameter—that is, the first frequency upper limit value is adapted to the first load parameter—the electronic device can increase the frequency upper limit value of the first CPU core based on the first frequency upper limit value, so that the first CPU core can quickly run the aforementioned interactive thread, thereby improving the running efficiency of the interactive thread. Furthermore, the electronic device can determine the first remaining power consumption value of at least one second CPU core based on the first frequency upper limit value and the first power consumption threshold value, that is, the maximum remaining usable total power consumption value of the at least one second CPU core, and decrease the frequency upper limit value of at least one second CPU core based on the maximum remaining usable total power consumption value, so that each second CPU core can also run threads at an appropriate frequency, ensuring the running efficiency of other threads. Therefore, the probability of the electronic device experiencing stuttering can be reduced.

[0125] Optionally, combined Figure 2 ,like Figure 4 As shown, step 102c can be implemented through steps 102c1 to 102c3 as described below.

[0126] Step 102c1: The electronic device constructs at least one first function.

[0127] In some embodiments of this application, each of the at least one first function described above is used to characterize the rate of change of the energy efficiency ratio of a second CPU core as a function of frequency.

[0128] The electronic device has multiple fourth correspondences, which are the correspondences between the CPU core frequency, the CPU core computing power value and the CPU core power consumption value. The electronic device can determine each first function corresponding to each second CPU core based on these multiple fourth correspondences.

[0129] For example, the first function mentioned above can be:

[0130] (1)

[0131] Among them, ME j Let be the rate of change of the energy efficiency ratio of the j-th second CPU core as a function of frequency. This rate of change can also be called the marginal energy efficiency value. The frequency of the j-th second CPU core, For the j-th second CPU core at frequency The computing power value, P j For the j-th second CPU core at frequency The power consumption value.

[0132] Step 102c2: The electronic device solves each first function according to the constraints to obtain the predicted frequency value of the second CPU core corresponding to each first function.

[0133] In some embodiments of this application, the above constraints include: the rate of change represented by each first function is the same, the first remaining power consumption value is greater than or equal to the total power consumption value of at least one second CPU core, and the difference between the first remaining power consumption value and the total power consumption value of at least one second CPU core is less than or equal to a difference threshold value.

[0134] The rate of change represented by the first function can be called the marginal energy efficiency value. This marginal energy efficiency value is used to indicate the increase in the additional computing power value brought about by a unit of additional power consumption value. It can also be understood as the energy efficiency ratio benefit brought about by continuing to increase the frequency at a certain frequency.

[0135] The constraints mentioned above may also include other conditions, such as the frequency change value of some second CPU cores in at least one second CPU core being the same, the power consumption change value of such second CPU cores being the same, etc., which are not limited in this application embodiment.

[0136] The fact that each of the first functions described above represents the same rate of change can be understood as follows:

[0137] (2)

[0138] in, This represents the marginal energy efficiency value of the second CPU core.

[0139] It is understandable that to achieve the optimal energy efficiency ratio, the energy efficiency increment brought about by the small frequency change of each second CPU core should be equal, that is, the slope of the tangent line of the energy efficiency curve of each second CPU core is equal, that is, the rate of change of the energy efficiency ratio of each second CPU core with the frequency value is the same, that is, the marginal energy efficiency value of each second CPU core is the same.

[0140] The predicted frequency value can be understood as the frequency value that maximizes the energy efficiency of each second CPU core.

[0141] The electronic device can employ a first algorithm to solve each first function based on the constraints. This first algorithm may include, but is not limited to, a binary search algorithm. It is understood that since the power consumption of the second CPU core is a monotonically decreasing function of its marginal energy efficiency (i.e., when the marginal energy efficiency is 0, the power consumption is infinitely large), a binary search algorithm can be used to quickly calculate the predicted frequency value.

[0142] For example, an electronic device can take a maximum value. and a minimum value The highest value It can be a preset value, the minimum value. It can be 0, and the highest value will be... and minimum value As the entry point for the binary search algorithm, the predicted frequency value is calculated by substituting it into formula (2).

[0143] Among them, electronic devices can first set the highest value As the marginal energy efficiency value in formula (2) The initial frequency of each second CPU core is calculated separately. At each initial frequency, the marginal energy efficiency value of each second CPU core is the same. The initial power consumption value of each second CPU core at its initial frequency is also calculated. The sum of the initial power consumption values ​​of each second CPU core is determined as the initial total power consumption value of at least one second CPU core. The electronic device can then determine whether a first remaining power consumption value is greater than the initial total power consumption value of the at least one second CPU core, and whether the difference between the first remaining power consumption value and the initial total power consumption value of the at least one second CPU core is less than or equal to a difference threshold. If the first remaining power consumption value is less than or equal to the initial total power consumption value of the at least one second CPU core, the electronic device can then set the maximum power consumption value. The difference between the new value and the first preset value is determined as the new value. and again put the new As the marginal energy efficiency value in formula (2) Repeat the above steps. If the first remaining power consumption value is greater than the initial total power consumption value of the at least one second CPU core, and the difference between the first remaining power consumption value and the initial total power consumption value of the at least one second CPU core is greater than the difference threshold, then the electronic device can release the maximum power consumption value. The sum of the second preset value is determined as the new and again put the new As the marginal energy efficiency value in formula (2) Repeat the above steps.

[0144] Furthermore, electronic devices can first set the lowest value As the marginal energy efficiency value in formula (2) The initial frequency of each second CPU core is calculated separately. At each initial frequency, the marginal energy efficiency value of each second CPU core is the same. The initial power consumption value of each second CPU core at its initial frequency is also calculated. The sum of the initial power consumption values ​​of each second CPU core is determined as the initial total power consumption value of at least one second CPU core. The electronic device can then determine whether a first remaining power consumption value is greater than the initial total power consumption value of the at least one second CPU core, and whether the difference between the first remaining power consumption value and the initial total power consumption value of the at least one second CPU core is less than or equal to a difference threshold. If the first remaining power consumption value is less than or equal to the initial total power consumption value of the at least one second CPU core, the electronic device can set the minimum value... The difference between the new value and the third preset value is determined as the new value. and again put the new As the marginal energy efficiency value in formula (2) Repeat the above steps. If the first remaining power consumption value is greater than the initial total power consumption value of the at least one second CPU core, and the difference between the first remaining power consumption value and the initial total power consumption value of the at least one second CPU core is greater than the difference threshold, then the electronic device can reduce the power consumption to the minimum value. The sum of the fourth preset value is determined as the new and again put the new As the marginal energy efficiency value in formula (2) The above steps are repeated. Thus, the electronic device obtains at least one predicted frequency value by simultaneously calculating at least one first function, and this predicted frequency value corresponds one-to-one with the second CPU core.

[0145] The first preset value can be a positive number, for example, 100. The second preset value can be a positive number, for example, 100. The third preset value can be a positive number, for example, 100. The fourth preset value can be a positive number, for example, 100. The first, second, third, and fourth preset values ​​can all be the same, some can be the same, or all can be different.

[0146] For example, assuming the fourth correspondence mentioned above corresponds to the frequency limiting parameters under a preset temperature setting, the electronic device can construct a first function corresponding to the second CPU core based on this correspondence. This first function is used to calculate the rate of change of the energy efficiency ratio of the second CPU core with the frequency value, which can be understood as the marginal energy efficiency value. Table 3 shows the frequency limiting parameters and marginal energy efficiency values ​​under different preset temperature settings. As shown in Table 3:

[0147] Table 3

[0148]

[0149] Within each of the five preset temperature levels mentioned above, the frequency limiting parameters and marginal energy efficiency values ​​for the large and small cores differ. For example, at one preset temperature level, the small core's maximum frequency is 100MHz, maximum computing power is 800MIPS, maximum power consumption is 1W, maximum energy efficiency ratio is 800MIPS / W, and marginal energy efficiency is 800. At the same preset temperature level, the large core's maximum frequency is 200MHz, maximum computing power is 2400MIPS, maximum power consumption is 4W, maximum energy efficiency ratio is 600MIPS / W, and marginal energy efficiency is 400. At another preset temperature level, the small core's maximum frequency is 200MHz, and maximum computing power is 1600MIPS. S has a power consumption cap of 2W, an energy efficiency ratio cap of 800MIPS / W, and a marginal energy efficiency of 400. Under another preset temperature setting, the large core's frequency cap is 400MHz, its computing power cap is 4800MIPS, its power consumption cap is 10W, its energy efficiency ratio cap is 480MIPS / W, and its marginal energy efficiency is 240. Under yet another preset temperature setting, the small core's frequency cap is 300MHz, its computing power cap is 2400MIPS, its power consumption cap is 4W, its energy efficiency ratio cap is 600MIPS / W, and its marginal energy efficiency is 72.7. Under one preset temperature setting, the maximum frequency of the large cores is 600MHz, the maximum computing power is 7200MIPS, the maximum power consumption is 20W, the maximum energy efficiency ratio is 360MIPS / W, and the marginal energy efficiency is 60. Under another preset temperature setting, the maximum frequency of the small cores is 400MHz, the maximum computing power is 3200MIPS, the maximum power consumption is 15W, the maximum energy efficiency ratio is 213.3MIPS / W, and the marginal energy efficiency is 32.0. Under yet another preset temperature setting, the maximum frequency of the large cores is 800MHz, and the maximum computing power is 9600MIPS. PS, the maximum power consumption is 60W, the maximum energy efficiency ratio is 160MIPS / W, and the marginal energy efficiency is 17.1. Under the last preset temperature setting mentioned above, the maximum frequency of the small core is 500MHz, the maximum computing power is 4000MIPS, the maximum power consumption is 40W, the maximum energy efficiency ratio is 100MIPS / W, and the marginal energy efficiency is 0. Under the last preset temperature setting mentioned above, the maximum frequency of the large core is 1000MHz, the maximum computing power is 12000MIPS, the maximum power consumption is 200W, the maximum energy efficiency ratio is 60MIPS / W, and the marginal energy efficiency is 0.

[0150] Assuming the first remaining power consumption is 40W, and at least one second CPU core includes 6 small cores and 1 large core, the electronic device can solve for each of the above first functions based on the constraints. For example, the electronic device can first take the highest value. Starting with a binary search at 800, the initial frequency of each small core is calculated to be 100MHz, and the initial frequency of the large core is 200MHz. The total power consumption is 6×1+4=10W < 40W. The difference between 40W and the total power consumption of 10W is 30W, which is greater than the difference threshold of 5W. Therefore, the electronic device can use the binary search method to search downwards, taking the difference between 800 and the first preset value of 400 as the new... The system then solves each of the first functions again based on the aforementioned constraints. The calculated intermediate frequency for each small core is 200MHz, and the frequency for the large core is also 200MHz. The total power consumption is 6×2+4=16W < 40W. The difference between 40W and the total power consumption of 16W is 24W, which is greater than the difference threshold of 5W. Therefore, the electronic device can continue searching downwards, and so on. Ultimately, the electronic device can calculate at least one predicted frequency value. For example, the predicted frequency for 6 small cores is 300MHz, and the predicted frequency for 1 large core is 400MHz. At this point, the rate of change represented by each first function... It is 150.

[0151] Step 102c3: The electronic device lowers the upper frequency limit of each second CPU core according to the predicted frequency value of each second CPU core.

[0152] In some embodiments of this application, the adjustment range of the upper frequency limit of each second CPU core is positively correlated with the predicted frequency value of each second CPU core.

[0153] In one example, if the predicted frequency value of each second CPU core is less than the upper frequency limit of each second CPU core, the electronic device can adjust the upper frequency limit of each second CPU core to the predicted frequency value of each second CPU core, thereby lowering the upper frequency limit of each second CPU core.

[0154] The electronic device can apply each predicted frequency value to the upper frequency limit of the second CPU core corresponding to each predicted frequency value in the CPU hardware through a drive, so as to adjust the upper frequency limit of each second CPU core to the predicted frequency value corresponding to each second CPU core.

[0155] In another example, the electronic device can determine the difference between the current upper frequency limit of each second CPU core and the predicted frequency value of each second CPU core as the new upper frequency limit, and adjust the current upper frequency limit of each second CPU core to the new upper frequency limit.

[0156] For example, in one specific application scenario, assuming that the at least one second CPU core includes 6 small cores and 1 large core, and the electronic device determines that the predicted frequency value of the 6 small cores is 300MHz and the predicted frequency value of the 1 large core is 400MHz, then the electronic device can adjust the upper limit of the frequency of the 6 small cores to 300MHz and the upper limit of the frequency of the 1 large core to 400MHz through the driver.

[0157] To illustrate further, in another specific application scenario, assuming that the at least one second CPU core includes 6 small cores and 1 large core, and the electronic device determines that the predicted frequency value of the 6 small cores is 260MHz and the predicted frequency value of the 1 large core is 360MHz, then the electronic device can adjust the upper limit of the frequency of the 6 small cores to 260MHz and the upper limit of the frequency of the 1 large core to 360MHz through the driver.

[0158] It should be noted that the above two application scenarios are illustrated with the same upper frequency limit and energy efficiency ratio for all six small cores. In actual applications, electronic devices can determine the predicted frequency value for each second CPU core separately. Each predicted frequency value can be partially the same or different, so that the electronic device can adjust the upper frequency limit of each second CPU core according to each predicted frequency value.

[0159] Thus, since the electronic device can construct a rate of change of the energy efficiency ratio of each second CPU core as a function of frequency, and solve each first function according to the constraints to obtain the predicted frequency value of the second CPU core corresponding to each first function, that is, the frequency value when the frequency allocation of the second CPU core is optimal, the electronic device can accurately adjust the upper limit of the frequency of each second CPU core according to each predicted frequency value.

[0160] It should be noted that, for the description of lowering the upper frequency limit of the first CPU core and raising the upper frequency limit of at least one second CPU core in the electronic device, please refer to the specific description of raising the upper frequency limit of the first CPU core and lowering the upper frequency limit of at least one second CPU core in the above embodiment. The embodiments of this application will not repeat it here.

[0161] As can be seen from the above, compared with related technologies, the embodiments of this application can also dynamically adjust the upper limit of the frequency of multiple CPU cores of the electronic device's CPU according to the first load parameter of the first CPU core running the above-mentioned interactive thread. On the one hand, it can ensure the running efficiency of the above-mentioned interactive thread and reduce the phenomenon of electronic device lag. On the other hand, it can ensure that each CPU core can reasonably allocate computing resources.

[0162] This application provides a CPU core frequency control method. An electronic device can obtain an interactive thread list; the interactive thread list includes thread information indicating an interactive thread used to process user-perceptible events; and adjust the upper frequency limit of a first CPU core and at least one second CPU core according to a first load parameter and a first power consumption threshold; wherein the running queue of the first CPU core includes interactive threads; the first load parameter is the load parameter for the first CPU core running interactive threads; the at least one second CPU core is a CPU core other than the first CPU core; and the first power consumption threshold is the upper limit of the total power consumption of the first CPU core and at least one second CPU core. Because the electronic device can access a list of interaction threads, it can identify each interaction thread used to process user-perceptible events—that is, the interaction threads related to whether the electronic device is experiencing lag. This allows the electronic device to dynamically adjust the upper frequency limits of the first CPU core and at least one second CPU core (excluding the first CPU core) based on the first load parameter and the first power consumption threshold value for the interaction thread running on the first CPU core. Therefore, on the one hand, the upper frequency limit value of the first CPU core can be adapted to the first load parameter, thereby improving the efficiency of the electronic device in running interaction threads related to whether the device is experiencing lag, and thus reducing the occurrence of lag. On the other hand, it can avoid the situation where adjusting the first CPU core causes the total power consumption of the first CPU core and at least one second CPU core to exceed the first power consumption threshold value, resulting in a large total power consumption of the first CPU core and at least one second CPU core, thus reducing the power consumption of the electronic device. In this way, the smoothness of the electronic device can be improved while reducing its power consumption.

[0163] It is understandable that in the specific application scenarios mentioned above, such as food delivery in summer, factory work, video calls, etc., this application can provide sufficient computing power for the front-end application to ensure smooth user experience.

[0164] In another specific application scenario mentioned above, the game scenario relies more on single-core computing power (1-2 heavy-load threads to handle logic and rendering). Because frame drops in the game have a significant impact on the user experience, the rendering thread often has strong timeliness requirements. This application can dynamically adjust the computing power according to the game rendering load, stabilize the game frame rate, and reduce the overall power consumption.

[0165] In some embodiments of this application, combined with Figure 1 ,like Figure 5 As shown, prior to step 101 above, the CPU core frequency control method provided in this application embodiment may further include step 201 below.

[0166] Step 201: If the first application thread meets the first condition, the electronic device adds the thread information of the first application thread to the interaction thread list.

[0167] In some embodiments of this application, the first application thread can be any application thread of the electronic device.

[0168] In some examples, the first application thread mentioned above may include, but is not limited to, at least one of the following: a thread of a foreground application, a thread of a background application, or a thread of a system application.

[0169] In some embodiments of this application, the first condition described above includes at least one of the following:

[0170] The first application thread is the thread of the application running in the foreground;

[0171] The first application thread is used to process the image to be displayed;

[0172] The first application thread is used to process audio data;

[0173] The first application thread is used to process data packets transmitted by the application running in the foreground.

[0174] In some embodiments of this application, if the first application thread is a thread of an application running in the foreground, it can be assumed that the thread may be used to process user-perceptible events. Therefore, the electronic device can add the identifier of the thread to the list of interactive threads.

[0175] In some examples, the thread described above for handling the image to be displayed can be understood as: the thread for handling the rendering events of the image frames to be displayed on the interface. That is, the first application thread is rendering the image frames to be displayed on the interface.

[0176] In some embodiments of this application, if the first application thread is a thread used to process an image to be displayed, it can be assumed that the thread may be used to process user-perceptible events. Therefore, the electronic device can add the identifier of the thread to the list of interactive threads.

[0177] In some embodiments of this application, if the first application thread is a thread used to process audio data, it can be assumed that the thread may be used to process user-perceptible events. Therefore, the electronic device can add the identifier of the thread to the list of interactive threads.

[0178] In some embodiments of this application, the first application thread is a thread used to process data transmission packets of a foreground application. It can be assumed that this thread may be used to process user-perceptible events. Therefore, the electronic device can add the identifier of this thread to the list of interactive threads.

[0179] In some examples, the electronic device can determine whether a first application thread meets a first condition through an important thread identification system, and if the first application thread meets the preset condition, add the thread information of the first application thread to the interactive thread list.

[0180] Thus, it can be seen that since the electronic device can accurately determine whether the first application thread is an interactive thread by identifying at least one of the following: the first application thread is a thread of an application running in the foreground, the first application thread is a thread for processing images to be displayed, the first application thread is a thread for processing audio data, and the first application thread is a thread for processing data transmission packets of an application running in the foreground, and if the first application thread is an interactive thread, the thread information of the first application thread is added to the interactive thread list, the interactive thread list can be accurately located to the interactive thread, thereby enabling the electronic device to accurately identify the interactive thread and accurately adjust the upper frequency limit of the first CPU core and at least one second CPU core.

[0181] In some embodiments of this application, combined with Figure 5 ,like Figure 6 As shown, after step 201 above, the CPU core frequency control method provided in this application embodiment may further include step 202 below.

[0182] Step 202: If the first application thread does not meet the first condition, the electronic device deletes the thread information of the first application thread from the interaction thread list.

[0183] In some examples, an electronic device can use an important thread identification system to determine whether each thread indicated by the interactive thread list meets a first condition, and if it is determined that the first application thread does not meet the first condition, remove the thread information of the first application thread from the interactive thread list.

[0184] Therefore, since the electronic device can promptly remove the thread information of the first application thread from the interactive thread list when the first application thread no longer meets the first condition (i.e., when the first application thread is no longer used to process user-perceptible events), it can avoid the situation where the electronic device identifies a thread not used to process user-perceptible events as an interactive thread. This can prevent the electronic device from increasing the frequency limit of the CPU cores running threads not used to process user-perceptible events, thereby ensuring the reasonable allocation of computing resources of the electronic device's CPU cores and guaranteeing the running efficiency of each CPU core's threads. In this way, the smoothness of using the electronic device can be improved.

[0185] In some embodiments of this application, before step 102 above, the CPU core frequency control method provided in this application may further include the following steps 301 and 302.

[0186] Step 301: The electronic device determines the second load parameters.

[0187] In some embodiments of this application, the second load parameter is the actual load parameter of the first CPU core running the interactive thread.

[0188] In some examples, the electronic device can calculate the second load parameter based on the running time of the interactive thread on the first CPU core using a temperature control frequency modulation system.

[0189] It should be noted that the explanation of how the second load parameter is calculated based on the running time of the above-mentioned interactive thread on the first CPU core can be found in the specific description in the relevant technology, and will not be repeated here in the embodiments of this application.

[0190] Step 302: The electronic device determines the product of the second load parameter and the first parameter value as the first load parameter.

[0191] In some embodiments of this application, the parameter value of the second load parameter is greater than the parameter value of the first load parameter.

[0192] In some examples, the first parameter value can be a positive number greater than 1, for example, the first parameter value can be 120%.

[0193] Thus, it can be seen that, since the electronic device can determine the product of the second load parameter and the first parameter value as the first load parameter after calculating the second load parameter, that is, the electronic device can also determine the second load parameter, which is a multiple of the first parameter value, as the first load parameter used to adjust the first CPU core and at least one second CPU core. Therefore, it can avoid the situation where the load of the first CPU core running the interactive thread is so large that the load parameter after the surge is not compatible with the frequency limit value adjusted by the first CPU core. This can improve the efficiency of the electronic device in running the interactive thread related to whether the electronic device is stuttering, thereby reducing the phenomenon of stuttering in the electronic device and improving the smoothness of the electronic device.

[0194] In some embodiments of this application, the CPU core frequency control method provided in this application may further include the following step 401.

[0195] Step 401: When the power consumption threshold associated with the temperature setting of the electronic device changes from the first power consumption threshold to the second power consumption threshold, the upper frequency limit of the first CPU core and at least one second CPU core is adjusted according to the second power consumption threshold.

[0196] It should be noted that the execution order of step 401 is not limited in this embodiment. In one example, the electronic device may execute step 401 first, and then execute step 101. For example, when the preset temperature setting of the electronic device changes, the first power consumption threshold changes, thereby allowing the electronic device to adjust the upper frequency limit of the first CPU core and at least one second CPU core. In another example, the electronic device may execute step 102 first, and then execute step 401. For example, after adjusting the upper frequency limit of the first CPU core and at least one second CPU core in step 102, when the preset temperature setting of the electronic device changes, the first power consumption threshold changes, thereby allowing the electronic device to adjust the upper frequency limit of the first CPU core and at least one second CPU core. In yet another example, the electronic device may execute step 401 first, and then execute step 102.

[0197] In some examples, when the power consumption threshold associated with the temperature setting of the electronic device changes from a first power consumption threshold to a second power consumption threshold, the electronic device can adjust the upper frequency limit of the first CPU core and at least one second CPU core according to the second power consumption threshold.

[0198] In some examples, the electronic device can determine a second maximum power consumption value corresponding to a second power consumption threshold, which is the maximum total power consumption value of a first CPU core and at least one second CPU core. It then constructs at least two second functions, each representing the rate of change of the energy efficiency ratio (EER) of one of the first and at least one second CPU cores with respect to frequency. Each second function is solved according to new constraints to obtain the predicted frequency value of the CPU core corresponding to each second function. These new constraints include: each second function represents the same rate of change; the second maximum power consumption value is greater than or equal to the total power consumption value of the first and at least one second CPU core; the difference between the second maximum power consumption value and the total power consumption value of the first and at least one second CPU core is less than or equal to a difference threshold; and the upper frequency limit of each CPU core is adjusted to the predicted frequency value of each CPU core.

[0199] Therefore, since the electronic device can adjust the upper frequency limit of the first CPU core and at least one second CPU core according to the second power consumption threshold value when the power consumption threshold value associated with the temperature setting of the electronic device changes from the first power consumption threshold value to the second power consumption threshold value, instead of adjusting the upper frequency limit value of the first CPU core and at least one second CPU core according to the preset upper frequency limit value, it can reduce the situation where the adjusted upper frequency limit value of each CPU core is not compatible with the load parameters of the running thread of each CPU core due to the inappropriate preset upper frequency limit value. This can improve the efficiency of the running thread of each CPU core, thereby improving the smoothness of the electronic device.

[0200] In some embodiments of this application, after step 102 above, the CPU core frequency control method provided in this application embodiment may further include the following step 501.

[0201] Step 501: When the running queue of the first CPU core does not include interactive threads, the electronic device adjusts the upper frequency limit of the first CPU core and at least one second CPU core according to the first power consumption threshold.

[0202] In some examples, the electronic device can determine a third maximum power consumption value corresponding to a first power consumption threshold. This third maximum power consumption value is the maximum total power consumption value of a first CPU core and at least one second CPU core. Then, at least two second functions are constructed, each second function representing the rate of change of the energy efficiency ratio of one of the first CPU cores and at least one second CPU core with respect to a frequency value. Each second function is solved according to new constraints to obtain the predicted frequency value of the CPU core corresponding to each second function. The new constraints include: the rate of change represented by each second function is the same; the third maximum power consumption value is greater than or equal to the total power consumption value of the first CPU core and at least one second CPU core; and the difference between the third maximum power consumption value and the total power consumption value of the first CPU core and at least one second CPU core is less than or equal to a difference threshold value. Furthermore, the upper frequency limit value of each CPU core is adjusted to the predicted frequency value of each CPU core.

[0203] In some examples, the electronic device can adjust the upper frequency limit of the first CPU core and at least one second CPU core according to a first power consumption threshold, when the first CPU core's running queue does not include interactive threads, i.e., when interactive threads exit the first CPU core's running queue.

[0204] Thus, since the electronic device can adjust the upper frequency limit of the first CPU core and at least one second CPU core according to the first power consumption threshold, even when the interactive thread is not included in the running queue of the first CPU core, that is, when the interactive thread is paused, stopped, or completed, the efficiency of the running thread of at least one second CPU core can be reduced due to the first CPU core occupying more computing resources, thereby improving the smoothness of the electronic device.

[0205] In some examples, step 501 above can be specifically implemented by step 501a below.

[0206] Step 501a: If the running queue of the first CPU core does not include interactive threads, the electronic device lowers the upper limit of the frequency of the first CPU and raises the upper limit of the frequency of at least one second CPU core according to the first power consumption threshold.

[0207] It is understood that, in one possible manner, the electronic device may increase the upper limit of the frequency of the first CPU and decrease the upper limit of the frequency of at least one second CPU core in steps 102a to 102c above. Therefore, if the run queue of the first CPU core does not include interactive threads, the electronic device may decrease the upper limit of the frequency of the first CPU and increase the upper limit of the frequency of at least one second CPU core to restore the upper limit of the frequency of the first CPU and at least one second CPU core.

[0208] Thus, since the electronic device can lower the upper limit of the frequency of the first CPU and raise the upper limit of the frequency of at least one second CPU core according to the first power consumption threshold, even when the running queue of the first CPU core does not include the interactive thread, that is, when the interactive thread is paused, stopped, or completed, the efficiency of the running thread of at least one second CPU core can be reduced due to the first CPU core occupying more computing resources, thereby improving the smoothness of the electronic device.

[0209] In some embodiments of this application, after step 102 above, the CPU core frequency control method provided in this application embodiment may further include the following step 601.

[0210] Step 601: When the interactive thread is moved from the running queue of the first CPU core to the running queue of the third CPU core among the above-mentioned at least one second CPU core, the electronic device adjusts the upper limit of the frequency of the third CPU core to the second upper limit of the frequency, and adjusts the upper limit of the frequency of the first CPU core to the third upper limit of the frequency.

[0211] In some embodiments of this application, the second frequency upper limit is the frequency upper limit of the first CPU core before the interactive thread migrates out of the run queue of the first CPU core; the third frequency upper limit is the frequency upper limit of the third CPU core before the interactive thread migrates to the run queue of the third CPU core.

[0212] For example, if the electronic device does not adjust the upper frequency limit of the first CPU core and at least one second CPU core after step 102 above, then the second upper frequency limit can be the first upper frequency limit, and the third upper frequency limit can be the predicted frequency value.

[0213] Thus, it can be seen that since electronic devices can directly adjust the upper frequency limit of the third CPU core to the second upper frequency limit and the upper frequency limit of the first CPU core to the third upper frequency limit when the interaction thread is moved from the running queue of the first CPU core to the running queue of the third CPU core, without having to perform multiple calculations, the smoothness of electronic device use can be improved while saving the computing power resources of the electronic device.

[0214] The following will use a complete example to illustrate the specific scheme of the CPU core frequency control method provided in the embodiments of this application.

[0215] Assume the electronic device includes a temperature control frequency modulation system and an important task identification system, and that the electronic device is equipped with a 2-cluster 8-core CPU.

[0216] The CPU core frequency control method provided in this application embodiment may include the following steps:

[0217] Step 1: The electronic device generates a list of interactive threads through the important task identification system.

[0218] Specifically, this step is used to identify important tasks, namely interaction threads, and to maintain a list of interaction threads for temperature control frequency regulation, which is shared with the temperature control frequency regulation system.

[0219] Electronic devices can use a critical task identification system to monitor the status of key threads in the network, graphics, and audio subsystems via embedded data points. The identified key thread's thread ID is added to the interactive thread list, thus designating the key thread as an interactive thread. Here, the electronic device can add the key thread's thread ID to the interactive thread list while the key thread is running, and remove the thread ID from the list when the thread is destroyed or the application to which the thread belongs exits to the background. Finally, the interactive thread list is shared with the frequency modulation system.

[0220] For example: When an electronic device is in desktop standby mode and a video is downloading in the background, the video download task does not meet the aforementioned preset conditions, and the interaction thread list is empty. When the user opens a game, the game becomes a foreground task, and the system detects its rendering thread refreshing images. We add the game's rendering thread ID to the interaction thread list. When the game is moved to the background, we remove that thread ID from the interaction thread list.

[0221] Step 2: Adjust the initial frequency limit of each CPU core in the electronic device.

[0222] Specifically, electronic devices can adjust the initial frequency limit of each CPU core through a temperature-controlled frequency limiting adjustment system. This system is used to calculate and set the ceiling frequency value, i.e., the frequency limit value, for each CPU core.

[0223] Data structures involved:

[0224] Each preset temperature setting requires a corresponding preset total power consumption budget: Used to calculate the remaining power budget excluding the CPU core where the interactive thread resides: .

[0225] CPU collection The frequency of each CPU core is , … Its corresponding computing power is , … Its corresponding power consumption is , … .

[0226] First, similar to the temperature control strategies in related technologies, a set of ceiling frequency values ​​for the CPU cores is preset based on different preset temperature levels. This set of frequencies is allocated according to the optimal energy efficiency ratio and serves as the default parameter when there are no interactive threads. The specific calculation method can adopt the equal marginal efficiency algorithm described later, see step 6.

[0227] Next, temperature control frequency limiting adjustments will be triggered under several different conditions in steps 3, 4, and 5: when the system temperature changes, when interactive threads are enqueued or dequeued, and when interactive threads migrate. Each step will output constraints: (j represents the remaining energy-efficient CPU cores that need adjustment, excluding the first CPU core), and the remaining available power budget excluding the first CPU core. Used to calculate the optimal energy efficiency allocation of CPU cores in step 6.

[0228] Step 3: When the interactive thread enters and exits the running queue of the first CPU core, a temperature control frequency limiting adjustment needs to be triggered.

[0229] Specifically, for each CPU core, check whether the interactive threads indicated in the interactive thread list of step 1 enter or exit on the runqueue of the current core:

[0230] 1) When an interactive thread enters the runqueue of the first CPU core i:

[0231] a) Calculate its util value, and magnify this value by 20% (redundant value to prevent sudden load surges) as the load parameter for the final calculated frequency. Determine the ceiling frequency value fi required on this CPU core according to the frequency value of the CPU core mapped by the computing power required by its load parameter, and the power consumption is Pi.

[0232] b) If the ceiling frequency value f of the first CPU core i is ≥ fi, it means the computing power already meets the demand, then jump to the end. If the ceiling frequency value f of the current CPU core i < fi, obtain the remaining available power consumption Prem = Ptotal - Pi, and the remaining CPU set to be adjusted: C = cj, j ≠ i.

[0233] c) If Prem is less than the minimum power consumption of the set C, it means the other energy-efficient CPU cores cannot be adjusted, then jump to the end.

[0234] d) Otherwise, adjust the ceiling frequency value of the current core i to fi, and output the constraint conditions Prem and the set C to step 6.

[0235] 2) When an interactive thread exits the runqueue of the first CPU core i:

[0236] e) Put the first CPU core i into the set of CPU cores to be adjusted: C = cj + ci, and update the available power consumption Ptotal = Prem + Pi.

[0237] f) Output the constraint conditions Ptotal and the set C to step 6.

[0238] Illustrate with an example:

[0239] 1. Interactive Thread Enters First CPU Core: In the example of step 1, the user's phone board temperature is 45 degrees Celsius, in standby mode, and the total power consumption is constrained to 100W. At this time, the preset ceiling frequency values ​​are: small cores c1-c6 are 300MHz, and large cores c7-c8 are 600MHz. When the user opens the game, the game's rendering thread T1 is the interactive thread and is scheduled to CPU core c8. In step 1.a), the value of util on c8 after being amplified by 20% is obtained. In step 1.b), assuming that util in the previous step is 600, the mapped frequency f8 is 600MHz, which is less than or equal to the current ceiling frequency value of c8, and the process jumps directly to the end; if util is 800, the mapped large core frequency f8 is 800MHz. Proceeding to step 1.c), P8 power consumption is 60W, so Prem is 40W. Since the minimum power consumption of the remaining 7 CPU cores is 10W, Prem is greater than the sum of the minimum power consumption of the remaining CPU cores, proceeding to step 1.d). If the Prem calculated in the above steps is less than 10W, then jump directly to the end. In 1.d), record f8 = 800 MHz, and output Prem = 40W, CPU set C = cj, j ≠ 8 to step 6.

[0240] 2. Interactive thread exits the first CPU core's run queue: After the above steps, the user closes the game, and the rendering thread T1 exits the run queue of c8. At this time, Ptotal=100w is recalculated, and the CPU set C=cj,j=1…8 is output to step 6.

[0241] Step 4: If the interaction thread migrates, a temperature control frequency limit adjustment needs to be triggered.

[0242] Task migration definition: A thread is removed from the run queue of CPU core k and then enters the run queue of CPU core i. This is usually caused by a change in task load triggering load balancing or by a task being preempted and forced to migrate.

[0243] This step is equivalent to first executing the step in step 3 where the task exits CPU core k, and then executing the step where it enters CPU core i:

[0244] Exit CPU core k and proceed to step 3.2.a.

[0245] Enter CPU core i and execute step 3.1. If the execution fails, restore the preset ceiling frequency value and jump to the end.

[0246] If the execution is successful, the constraints will be... Output set C to step 6.

[0247] For example: In the example in step 3.1, the user adjusts the game's graphics settings, causing the rendering thread to... The load is reduced and migrated to the CPU core. Assuming that util becomes 1024 after the migration, the final calculation in step 3.1 is as follows. Required frequency =500, corresponding power consumption It's 40W. For 60W, collection .Will Output C to step 106.

[0248] Step 5: A change in temperature setting requires triggering a temperature control frequency limiting adjustment.

[0249] Total power consumption The changes, in the following steps:

[0250] If at this time, high computing power CPU core The total power consumption constraint is no longer met. Restore to the preset ceiling frequency value and jump to the end.

[0251] Otherwise, calculate the remaining available power consumption. = , constrain conditions Output set C to step 6.

[0252] For example: In the example in step 3.1, the user played games for a long time, causing the CPU temperature to rise and the board temperature to reach 50 degrees Celsius. It becomes 50W. =40W. In step 5.a), the minimum power consumption of the remaining CPU cores is 10W, which still meets the power consumption constraint, therefore... =10W, CPU Output to step 6, if step 5.a) is updated The power consumption has already fallen below the minimum power limit. Restore the upper frequency limit of all CPU cores to the preset ceiling frequency value and exit.

[0253] Step 6: Adjust the upper limit of CPU core frequency in the electronic device.

[0254] Specifically, this step is used to calculate the frequency allocation of the remaining available CPU cores to achieve optimal energy efficiency.

[0255] In the previous steps, we obtained the set of CPU cores that need to be adjusted. Remaining available power consumption That is, it is necessary to meet the power consumption conditions. To maximize overall energy efficiency: .

[0256] This is a dynamic programming problem. This application uses the principle of equal marginal energy efficiency to calculate the optimal energy efficiency allocation:

[0257] (1) Definition of marginal energy efficiency: The increase in computing power resulting from a unit increase in additional power consumption: ME = = (The derivative of computing power divided by the derivative of power consumption) can be understood as the energy efficiency gain of the CPU core continuing to operate at this frequency.

[0258] (2) To achieve the optimal energy efficiency ratio, the energy efficiency increment caused by a small frequency change of each CPU core should be equal, that is, the slope of the tangent line of the energy efficiency curve of all CPU cores should be equal, that is, the marginal energy efficiency of each CPU core should be equal:

[0259] = =…= =

[0260] (3) Because power consumption P is about The monotonically decreasing function ( The optimal solution can be quickly calculated using binary search. Value. We take the highest value. minimum value As the entry point for the bisection method, substituting it into the calculation... ... If power consumption < Then use binary search downwards, if > Then use a binary search method to search upwards, continuously narrowing the range until the final result is found. ≤ This is the optimal energy efficiency frequency. corresponding frequency ... Save it as the ceiling frequency value.

[0261] (4) Use caching for fast algorithm optimization: In step 6, we need to retain the frequency f of the last calculation and the marginal energy efficiency. To simplify subsequent calculations: if step 3 involves intra-cluster migration, simply use the previous calculation result and swap the upper frequency limit of the migrated CPU cores. Each time calculation 6 is entered, the previous result can be used. As a dichotomy The starting conditions can be adjusted to reduce the number of iterations.

[0262] (5) In some CPU architectures, CPU cores in the same cluster may change simultaneously, requiring additional constraints.

[0263] (6) The space complexity of this algorithm is O(n). The time complexity is n is the number of CPU cores, and the overhead is negligible.

[0264] The algorithm steps for step 6 are as follows:

[0265] start

[0266] Get the current state:

[0267] - CPU cores to be allocated

[0268] - Power consumption budget

[0269] Check if a recalculation is needed:

[0270] if migration within the task cluster

[0271] →Use a fast algorithm (step d)

[0272] else

[0273] → Complete recalculation (step ac)

[0274] Constraints , = =…= =

[0275] Binary search starting point ,

[0276] While - 0

[0277] + ) / 2, find , …

[0278] Checking power consumption feasibility

[0279] if

[0280] → Search downwards / / Power consumption is too low, increase frequency

[0281] else

[0282] → Search upwards / / Power consumption is too high, reduce frequency

[0283] The search yielded the one with the best energy efficiency ratio. , …

[0284] Cache results , … and corresponding

[0285] Step 7: This step applies the frequency calculated in the previous steps to the CPU hardware's maximum frequency value via a driver, thus completing the adjustment.

[0286] The high-performance CPU cores generated by the calculation and other energy-efficient CPU cores The frequency input is sent to the CPU temperature control frequency adjustment driver, which ultimately adjusts the CPU core's ceiling frequency to our calculated predicted frequency. Simultaneously, all frequencies are cached. and Power consumption Energy-efficient CPU core collection This is used for the next calculation.

[0287] In summary, this application can, based on the current stepped temperature control frequency limiting, calculate the optimal energy efficiency ratio frequency allocation of the CPU cores according to the total power consumption constraint at each preset temperature level using a dynamic programming algorithm, and use it as the preset default parameter. This parameter does not need to consider single-core performance and can reduce power consumption in the default scenario.

[0288] By monitoring subsystems related to user interaction, important tasks that are perceptible to the user can be identified, such as tasks that generate images and display them, tasks that provide audio data, and tasks that send and receive network packets in the foreground. A list of important tasks is maintained in real time.

[0289] Temperature-controlled frequency limiting is triggered when the system's preset temperature setting changes, when interactive threads enter or leave the CPU core's execution queue, or during migration. At each frequency adjustment point, the ceiling frequency of the CPU core running the interactive thread is dynamically adjusted based on its load, ensuring that single-core performance meets the thread's requirements. The CPU core running this interactive thread is designated as the high-performance CPU core. After eliminating the power consumption of the high-performance CPU core, a dynamic programming algorithm is used to allocate the ceiling frequency values ​​of the remaining CPU cores based on the remaining available power to achieve optimal energy efficiency. These CPU cores are designated as energy-efficient cores. Finally, the ceiling frequency values ​​of the high-performance and energy-efficient CPU cores are applied to the temperature-controlled frequency limiting.

[0290] The entire algorithm enables the CPU to achieve optimal energy efficiency while ensuring the performance of interactive threads.

[0291] It should be noted that each of the above method embodiments, or various possible implementations of each method embodiment, can be executed individually or in combination of any two or more. The specific implementation can be determined according to actual usage requirements, and this application embodiment does not impose any restrictions on this.

[0292] The CPU core frequency control method provided in this application can be executed by a CPU core frequency control device. This application uses the CPU core frequency control device executing the CPU core frequency control method as an example to illustrate the CPU core frequency control device provided in this application.

[0293] Figure 7 This is a schematic diagram of a CPU core frequency control device provided in an embodiment of this application. Figure 7 As shown, the CPU core frequency control device 700 may include an acquisition module 701 and a processing module 702.

[0294] The acquisition module 701 is used to acquire an interactive thread list; the interactive thread list includes thread information, which indicates an interactive thread used to process user-perceptible events. The processing module 702 is used to adjust the upper frequency limit of a first CPU core and at least one second CPU core according to a first load parameter and a first power consumption threshold; wherein the run queue of the first CPU core includes interactive threads; the first load parameter is the load parameter for the first CPU core to run interactive threads; the at least one second CPU core is a CPU core other than the first CPU core; and the first power consumption threshold is the upper limit of the total power consumption of the first CPU core and at least one second CPU core.

[0295] This application provides a CPU core frequency control device. Since the CPU core frequency control device can acquire an interactive thread list, it can identify each interactive thread used to process user-perceptible events through the thread information included in the interactive thread list, i.e., identify interactive threads related to whether the CPU core frequency control device experiences lag. Thus, the CPU core frequency control device can dynamically adjust the upper frequency limit of the first CPU core and at least one second CPU core (excluding the first CPU core) based on the first load parameter and the first power consumption threshold value of the first CPU core running the interactive thread. Therefore, on the one hand, the upper frequency limit value of the first CPU core can be adapted to the first load parameter, thereby improving the efficiency of the CPU core frequency control device in running interactive threads related to whether the CPU core frequency control device experiences lag, and thus reducing the occurrence of lag in the CPU core frequency control device. On the other hand, it can avoid the situation where adjusting the first CPU core causes the total power consumption of the first CPU core and at least one second CPU core to exceed the first power consumption threshold value, i.e., causing the total power consumption of the first CPU core and at least one second CPU core to be large. Therefore, the power consumption of the CPU core frequency control device can be reduced. In this way, the smoothness of the CPU core's frequency control device can be improved while the power consumption of the CPU core's frequency control device can be reduced.

[0296] In some embodiments of this application, the processing module 702 is specifically used to determine a first frequency upper limit value corresponding to the first load parameter; and according to the first frequency upper limit value, increase the frequency upper limit value of the first CPU core, and according to the first frequency upper limit value and the first power consumption threshold value, determine a first remaining power consumption value; the first remaining power consumption value is the maximum total power consumption value that at least one second CPU core can still use; and according to the first remaining power consumption value, decrease the frequency upper limit value of at least one second CPU core; wherein, the adjustment range of the frequency upper limit value of the first CPU core is positively correlated with the first frequency upper limit value.

[0297] In some embodiments of this application, the processing module 702 is specifically used to determine a first maximum power consumption value corresponding to the first frequency upper limit value based on the correspondence between the frequency upper limit value and the power consumption value; the first maximum power consumption value is the maximum power consumption value available to the first CPU core; and the difference between the first power consumption threshold value and the maximum power consumption value is determined as the first remaining power consumption value.

[0298] In some embodiments of this application, the processing module 702 is specifically configured to construct at least one first function, each first function representing the rate of change of the energy efficiency ratio of a second CPU core with respect to frequency; and to solve each first function according to constraints to obtain the predicted frequency value of the second CPU core corresponding to each first function; the constraints include: the rate of change represented by each first function is the same, the first remaining power consumption value is greater than or equal to the total power consumption value of at least one second CPU core, and the difference between the first remaining power consumption value and the total power consumption value of at least one second CPU core is less than or equal to the difference threshold value; and to lower the upper frequency limit value of each second CPU core according to the predicted frequency value of each second CPU core; the adjustment range of the upper frequency limit value of each second CPU core is positively correlated with the predicted frequency value of each second CPU core.

[0299] In some embodiments of this application, the processing module 702 is further configured to determine a second load parameter before adjusting the upper frequency limit of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold; the second load parameter is the actual load parameter of the first CPU core running the interactive thread; and the product of the second load parameter and the first parameter value is determined as the first load parameter; wherein the parameter value of the second load parameter is greater than the parameter value of the first load parameter.

[0300] In some embodiments of this application, the processing module 702 is further configured to, after adjusting the upper frequency limit of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold, adjust the upper frequency limit of the first CPU core and at least one second CPU core according to the first power consumption threshold when the run queue of the first CPU core does not include interactive threads.

[0301] In some embodiments of this application, the processing module 702 is specifically used to lower the upper frequency limit of the first CPU and raise the upper frequency limit of at least one second CPU core.

[0302] In some embodiments of this application, the processing module 702 is further configured to, after adjusting the upper frequency limits of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold, adjust the upper frequency limit of the third CPU core to the second upper frequency limit and adjust the upper frequency limit of the first CPU core to the third upper frequency limit when the interaction thread is migrated from the run queue of the first CPU core to the run queue of the third CPU core among the at least one second CPU core; wherein, the second upper frequency limit is the upper frequency limit of the first CPU core before the interaction thread is migrated out of the run queue of the first CPU core; and the third upper frequency limit is the upper frequency limit of the third CPU core before the interaction thread is migrated to the run queue of the third CPU core.

[0303] In some embodiments of this application, the processing module 702 is further configured to adjust the upper frequency limit of the first CPU core and at least one second CPU core according to the second power consumption threshold value when the power consumption threshold value associated with the temperature setting of the CPU core frequency control device 700 changes from the first power consumption threshold value to the second power consumption threshold value.

[0304] In some embodiments of this application, the processing module 702 is further configured to add the thread information of the first application thread to the interactive thread list before the acquisition module 701 acquires the interactive thread list, provided that the first application thread meets a first condition; wherein the first application thread is any application thread of the CPU core frequency control device 700; wherein the first condition includes at least one of the following: the first application thread is a thread of a foreground application; the first application thread is a thread for processing an image to be displayed; the first application thread is a thread for processing audio data; the first application thread is a thread for processing data transmission packets of a foreground application.

[0305] In some embodiments of this application, the processing module 702 is further configured to delete the thread information of the first application thread from the interactive thread list after adding the thread information of the first application thread to the interactive thread list, if the first application thread does not meet the first condition.

[0306] The CPU core frequency control device in this application embodiment can be an electronic device or a component in an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the scope of the device.

[0307] The CPU core frequency control device in this embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this embodiment does not specifically limit the specific operating system.

[0308] The CPU core frequency control device provided in this application embodiment can achieve… Figures 1 to 6 The various processes implemented in the method implementation examples will not be described again here to avoid repetition.

[0309] In some embodiments of this application, such as Figure 8 As shown, this application embodiment also provides an electronic device 800, including a processor 801 and a memory 802. The memory 802 stores a program or instructions that can run on the processor 801. When the program or instructions are executed by the processor 801, they implement the various steps of the CPU core frequency control method embodiment described above and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0310] It should be noted that the electronic devices in the embodiments of this application include the aforementioned mobile electronic devices and non-mobile electronic devices.

[0311] Figure 9 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0312] The electronic device 900 includes, but is not limited to, components such as: radio frequency unit 901, network module 902, audio output unit 903, input unit 904, sensor 905, display unit 906, user input unit 907, interface unit 908, memory 909, and processor 910.

[0313] Those skilled in the art will understand that the electronic device 900 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 910 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 9 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0314] The processor 910 is configured to acquire an interactive thread list, which includes thread information indicating an interactive thread for processing user-perceptible events; and adjust the upper frequency limit of the first CPU core and at least one second CPU core according to a first load parameter and a first power consumption threshold. The first CPU core's run queue includes interactive threads; the first load parameter is the load parameter for the first CPU core running interactive threads; the at least one second CPU core is a CPU core other than the first CPU core; and the first power consumption threshold is the upper limit of the total power consumption of the first CPU core and at least one second CPU core.

[0315] This application provides an electronic device that can acquire an interaction thread list. By using the thread information included in the interaction thread list, the device can identify each interaction thread used to process user-perceptible events, i.e., identify the interaction threads related to whether the electronic device experiences lag. In this way, the electronic device can dynamically adjust the upper frequency limits of the first CPU core and at least one second CPU core (excluding the first CPU core) based on the first load parameter and the first power consumption threshold value for the interaction thread run by the first CPU core. Therefore, on the one hand, the upper frequency limit value of the first CPU core can be adapted to the first load parameter, thereby improving the efficiency of the electronic device in running interaction threads related to whether the electronic device experiences lag, and thus reducing the occurrence of lag. On the other hand, it can avoid the situation where adjusting the first CPU core causes the total power consumption of the first CPU core and at least one second CPU core to exceed the first power consumption threshold value, i.e., resulting in a large total power consumption of the first CPU core and at least one second CPU core. Therefore, the power consumption of the electronic device can be reduced. Thus, the smoothness of the electronic device's operation can be improved while reducing its power consumption.

[0316] In some embodiments of this application, the processor 910 is specifically configured to determine a first frequency upper limit value corresponding to a first load parameter; and increase the frequency upper limit value of a first CPU core according to the first frequency upper limit value, and determine a first remaining power consumption value according to the first frequency upper limit value and a first power consumption threshold value; the first remaining power consumption value is the maximum total power consumption value remaining available for at least one second CPU core; and decrease the frequency upper limit value of at least one second CPU core according to the first remaining power consumption value; wherein the adjustment range of the frequency upper limit value of the first CPU core is positively correlated with the first frequency upper limit value.

[0317] In some embodiments of this application, the processor 910 is specifically used to determine the maximum power consumption value corresponding to the first frequency upper limit value based on the correspondence between the frequency upper limit value and the remaining power consumption value; the maximum power consumption value is the maximum power consumption value available to the first CPU core; and the difference between the first power consumption threshold value and the maximum power consumption value is determined as the first remaining power consumption value.

[0318] In some embodiments of this application, the processor 910 is specifically configured to construct at least one first function, each first function representing the rate of change of the energy efficiency ratio of a second CPU core with respect to frequency; and to solve each first function according to constraints to obtain the predicted frequency value of the second CPU core corresponding to each first function; the constraints include: the rate of change represented by each first function is the same, the first maximum power consumption value is greater than or equal to the total power consumption value of at least one second CPU core, and the difference between the first maximum power consumption value and the total power consumption value of at least one second CPU core is less than or equal to the difference threshold value; and to lower the upper frequency limit value of each second CPU core according to the predicted frequency value of each second CPU core; the adjustment range of the upper frequency limit value of each second CPU core is positively correlated with the predicted frequency value of each second CPU core.

[0319] In some embodiments of this application, the processor 910 is further configured to determine a second load parameter before adjusting the upper frequency limit of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold; the second load parameter is the actual load parameter of the first CPU core running the interactive thread; and the product of the second load parameter and the first parameter value is determined as the first load parameter; wherein the parameter value of the second load parameter is greater than the parameter value of the first load parameter.

[0320] In some embodiments of this application, the processor 910 is further configured to adjust the upper frequency limit of the first CPU core and at least one second CPU core according to the first power consumption threshold after adjusting the upper frequency limit of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold.

[0321] In some embodiments of this application, the processor 910 is specifically used to lower the upper frequency limit of the first CPU and raise the upper frequency limit of at least one second CPU core.

[0322] In some embodiments of this application, the processor 910 is further configured to, after adjusting the upper frequency limits of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold, adjust the upper frequency limit of the third CPU core to a second upper frequency limit and adjust the upper frequency limit of the first CPU core to a third upper frequency limit when the interaction thread is migrated from the run queue of the first CPU core to the run queue of the third CPU core among the at least one second CPU core; wherein the second upper frequency limit is the upper frequency limit of the first CPU core before the interaction thread is migrated out of the run queue of the first CPU core; and the third upper frequency limit is the upper frequency limit of the third CPU core before the interaction thread is migrated to the run queue of the third CPU core.

[0323] In some embodiments of this application, the processor 910 is further configured to adjust the upper frequency limit of the first CPU core and at least one second CPU core according to the second power consumption threshold value when the power consumption threshold value associated with the temperature setting of the electronic device changes from the first power consumption threshold value to the second power consumption threshold value.

[0324] In some embodiments of this application, the processor 910 is further configured to add the thread information of the first application thread to the interactive thread list before obtaining the interactive thread list, provided that the first application thread meets the first condition; wherein the first application thread is any application thread of the electronic device; wherein the first condition includes at least one of the following: the application thread is a thread of an application running in the foreground; the application thread is a thread for processing an image to be displayed; the application thread is a thread for processing audio data; the application thread is a thread for processing data transmission packets of an application running in the foreground.

[0325] In some embodiments of this application, the processor 910 is further configured to delete the thread information of the first application thread from the interactive thread list after the thread information of the first application thread has been added to the interactive thread list, if the first application thread does not meet the first condition.

[0326] It should be understood that, in this embodiment, the input unit 904 may include a graphics processing unit (GPU) 9041 and a microphone 9042. The GPU 9041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 906 may include a display panel 9061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 907 includes at least one of a touch panel 9071 and other input devices 9072. The touch panel 9071 is also called a touch screen. The touch panel 9071 may include a touch detection device and a touch controller. Other input devices 9072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0327] The memory 909 can be used to store software programs and various data. The memory 909 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 909 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 909 in the embodiments of this application includes, but is not limited to, these and any other suitable types of memory.

[0328] Processor 910 may include one or more processing units; optionally, processor 910 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 910.

[0329] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the CPU core frequency control method embodiment described above and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0330] The processor mentioned above is the processor in the electronic device described in the above embodiments. The readable storage medium mentioned above includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0331] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the CPU core frequency control method embodiment described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0332] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0333] This application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the various processes of the CPU core frequency control method embodiment described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0334] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0335] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0336] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A method for frequency control of a central processing unit (CPU) core, characterized in that, include: Obtain the list of interaction threads; the list of interaction threads includes thread information, which indicates an interaction thread used to handle user-perceptible events. Based on the first load parameters and the first power consumption threshold, adjust the upper frequency limit of the first CPU core and at least one second CPU core. Wherein, the run queue of the first CPU core includes the interactive thread; the first load parameter is the load parameter of the first CPU core running the interactive thread; the at least one second CPU core is a CPU core other than the first CPU core; The first power consumption threshold is the upper limit of the total power consumption of the first CPU core and the at least one second CPU core.

2. The method according to claim 1, characterized in that, The step of adjusting the upper frequency limit of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold includes: Determine the upper limit value of the first frequency corresponding to the first load parameter; Based on the first frequency upper limit value, the frequency upper limit value of the first CPU core is increased, and based on the first frequency upper limit value and the first power consumption threshold value, a first remaining power consumption value is determined; the first remaining power consumption value is the maximum total remaining power consumption value of the at least one second CPU core. Based on the first remaining power consumption value, the upper frequency limit of the at least one second CPU core is lowered; The adjustment range of the upper limit of the frequency of the first CPU core is positively correlated with the upper limit of the frequency.

3. The method according to claim 2, characterized in that, The step of determining the first remaining power consumption value based on the first frequency upper limit value and the first power consumption threshold value includes: Based on the correspondence between the upper limit of frequency and the power consumption value, a first maximum power consumption value corresponding to the first upper limit of frequency is determined; the first maximum power consumption value is the maximum power consumption value available to the first CPU core. The difference between the first power consumption threshold and the first maximum power consumption value is determined as the first remaining power consumption value.

4. The method according to claim 2 or 3, characterized in that, The step of lowering the frequency upper limit of the at least one second CPU core based on the first remaining power consumption value includes: Construct at least one first function, each first function being used to characterize the rate of change of the energy efficiency ratio of a second CPU core as a function of frequency; According to the constraints, each first function is solved to obtain the predicted frequency value of the second CPU core corresponding to each first function; the constraints include: the rate of change represented by each first function is the same, the first remaining power consumption value is greater than or equal to the total power consumption value of the at least one second CPU core, and the difference between the first remaining power consumption value and the total power consumption value of the at least one second CPU core is less than or equal to the difference threshold value. Based on the predicted frequency value of each second CPU core, the upper limit of the frequency of each second CPU core is lowered; the adjustment range of the upper limit of the frequency of each second CPU core is positively correlated with the predicted frequency value of each second CPU core.

5. The method according to claim 1, characterized in that, Before adjusting the upper frequency limit of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold, the method further includes: Determine the second load parameter; the second load parameter is the actual load parameter of the first CPU core running the interactive thread; The product of the second load parameter and the first parameter value is determined as the first load parameter; The value of the second load parameter is greater than the value of the first load parameter.

6. The method according to claim 1, characterized in that, After adjusting the upper frequency limits of the first CPU core and at least one second CPU core based on the first load parameter and the first power consumption threshold, the method further includes: If the interactive thread is not included in the run queue of the first CPU core, the upper frequency limit of the first CPU core and the at least one second CPU core is adjusted according to the first power consumption threshold.

7. The method according to claim 6, characterized in that, Adjusting the upper frequency limit of the first CPU core and the at least one second CPU core includes: Lower the upper limit of the frequency of the first CPU and raise the upper limit of the frequency of the at least one second CPU core.

8. The method according to claim 1, characterized in that, After adjusting the upper frequency limits of the first CPU core and at least one second CPU core based on the first load parameter and the first power consumption threshold, the method further includes: When the interaction thread is migrated from the run queue of the first CPU core to the run queue of the third CPU core among the at least one second CPU core, the upper frequency limit of the third CPU core is adjusted to the second upper frequency limit, and the upper frequency limit of the first CPU core is adjusted to the third upper frequency limit. Wherein, the second frequency upper limit value is the frequency upper limit value of the first CPU core before the interactive thread migrates out of the run queue of the first CPU core; the third frequency upper limit value is the frequency upper limit value of the third CPU core before the interactive thread migrates to the run queue of the third CPU core.

9. The method according to claim 1, characterized in that, The method further includes: When the power consumption threshold associated with the temperature setting of the electronic device changes from the first power consumption threshold to the second power consumption threshold, the upper frequency limit of the first CPU core and the at least one second CPU core is adjusted according to the second power consumption threshold.

10. The method according to claim 1, characterized in that, Before obtaining the list of interactive threads, the method further includes: If the first application thread meets the first condition, the thread information of the first application thread is added to the interactive thread list; wherein, the first application thread is any application thread of the electronic device; The first condition includes at least one of the following: The first application thread is the thread of the application running in the foreground; The first application thread is a thread used to process the image to be displayed; The first application thread is a thread used to process audio data; The first application thread is a thread used to process data packets transmitted by the application running in the foreground.

11. The method according to claim 10, characterized in that, After adding the thread information of the first application thread to the list of interactive threads, the method further includes: If the first application thread does not meet the first condition, the thread information of the first application thread is removed from the list of interaction threads.

12. A frequency control device for a central processing unit (CPU) core, characterized in that, include: An acquisition module is used to acquire a list of interactive threads; the list of interactive threads includes thread information, which indicates an interactive thread used to handle user-perceptible events. The processing module is used to adjust the upper frequency limit of the first CPU core and at least one second CPU core according to the first load parameter and the first power consumption threshold. Wherein, the run queue of the first CPU core includes the interactive thread; the first load parameter is the load parameter of the first CPU core running the interactive thread; the at least one second CPU core is a CPU core other than the first CPU core; The first power consumption threshold is the upper limit of the total power consumption of the first CPU core and the at least one second CPU core.

13. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor to implement the steps of the method as described in any one of claims 1 to 11.

Images