A method and system for improving the performance of an MCU by optimizing instruction set and cache prefetching

Abstract

This application provides a method and system for improving MCU performance through instruction set optimization and cache prefetching, relating to the field of microcontroller technology. The method includes: adding dedicated instructions for preset complex operations to the original instruction set of the MCU; the compiler identifies complex operation modes in the code and replaces them with corresponding dedicated instructions to generate optimized code; setting up multi-level caches between the MCU and main memory; the prefetch controller predicts and preloads target data based on the execution mode; synchronously monitoring the MCU load status and dynamically adjusting the CPU operating frequency accordingly. This solves the technical problems of low instruction execution efficiency, large memory access latency, and difficulty in balancing performance and power consumption in existing MCUs when performing complex operations. It achieves the technical effect of improving the execution efficiency and cache hit rate of the MCU, reducing memory access latency, and effectively reducing overall power consumption while ensuring performance by optimizing the instruction set, cache prefetching, and dynamic frequency adjustment.

Description

Technical Field

[0001] This invention relates to the field of microcontroller technology, and specifically to a method and system for improving MCU performance through instruction set optimization and cache prefetching. Background Technology

[0002] Microcontrollers (MCUs) are widely used in industrial control, smart home appliances, automotive electronics, IoT terminals, and embedded signal processing due to their low power consumption, low cost, and high integration. As application scenarios become increasingly complex, MCUs need to undertake more and more computationally intensive tasks, such as digital signal processing, matrix operations, encryption verification, and complex control algorithms, which places higher demands on their computing performance and energy efficiency.

[0003] Existing MCUs typically employ a general-purpose instruction set architecture, which often requires combining multiple basic instructions to perform complex operations. This results in long instruction execution cycles and low pipeline efficiency, limiting overall execution efficiency. Furthermore, due to the limited on-chip memory resources of the MCU, the CPU frequently accesses main memory during execution, leading to significant memory access latency and further restricting system performance.

[0004] To alleviate memory access bottlenecks, some MCUs have introduced cache structures or simple prefetching mechanisms. However, existing prefetching strategies are mostly based on fixed rules or linear address prediction, making it difficult to accurately predict complex instruction sequences and diverse data access patterns, resulting in limited improvement in cache hit rate. In addition, the dynamic frequency adjustment mechanisms of existing MCUs usually only make coarse-grained adjustments based on overall CPU utilization, failing to combine instruction type and actual power consumption characteristics for fine-grained control, which can easily lead to an imbalance between performance and power consumption. Summary of the Invention

[0005] This application provides a method and system for improving MCU performance through instruction set optimization and cache prefetching, which solves the technical problems of low instruction execution efficiency, large memory access latency, and difficulty in balancing performance and power consumption in existing MCUs when performing complex operations.

[0006] Firstly, this application provides a method for improving MCU performance through instruction set optimization and cache prefetching, the method comprising:

[0007] Based on the original instruction set of the MCU, special instructions for preset complex operations are added. These special instructions are implemented at the hardware level. The compiler identifies complex operation patterns in the code and replaces the complex operations with corresponding special instructions to generate optimized code. Multi-level caches are set between the MCU and the main memory. The prefetch controller predicts the target data that will be accessed in the future based on the program execution mode and loads the target data into the cache in advance when the CPU executes the optimized code. The load status of the MCU is monitored synchronously, and the CPU operating frequency is dynamically adjusted according to the load status.

[0008] Secondly, this application provides a system for improving MCU performance through instruction set optimization and cache prefetching, the system comprising: Specialized instruction addition component: Adds specialized instructions for preset complex operations to the original instruction set of the MCU. These specialized instructions are implemented at the hardware level. Code replacement component: The compiler identifies complex operation patterns in the code and replaces the complex operations with corresponding specialized instructions to generate optimized code. Data caching component: Sets up a multi-level cache between the MCU and the main memory. The prefetch controller predicts the target data that will be accessed in the future based on the program execution mode and loads the target data into the cache in advance when the CPU executes the optimized code. CPU adjustment component: Synchronously monitors the load status of the MCU and dynamically adjusts the CPU operating frequency according to the load status.

[0009] One or more technical solutions provided in this application have at least the following technical effects or advantages: This application provides a method and system for improving MCU performance through instruction set optimization and cache prefetching, which relates to the field of microcontroller technology. It solves the technical problems of low instruction execution efficiency, large memory access latency, and difficulty in balancing performance and power consumption in existing MCUs when performing complex operations. It achieves the technical effect of improving MCU execution efficiency and cache hit rate, reducing memory access latency, and effectively reducing overall power consumption while ensuring performance by optimizing the instruction set, cache prefetching, and dynamic frequency adjustment. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart illustrating a method for improving MCU performance through instruction set optimization and cache prefetching, as described in this application.

[0012] Figure 2 This is a schematic diagram of the MCU performance improvement system based on instruction set optimization and cache prefetching, as described in this application.

[0013] Explanation of reference numerals in the attached diagram: Component 11 for adding special instructions, Component 12 for code replacement, Component 13 for data caching, and Component 14 for CPU tuning. Detailed Implementation

[0014] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0015] Example 1, as Figure 1 As shown, this application provides a method for improving MCU performance through instruction set optimization and cache prefetching, the method comprising: Based on the original instruction set of the MCU, special instructions for preset complex operations are added, and these special instructions are implemented at the hardware level.

[0016] Specifically, without changing the existing general instruction set of the MCU, such as basic instructions like arithmetic logic, memory access, branching, and shifting, several opcodes and their extended fields are reserved or added in the instruction encoding space to define a set of special instructions for specific complex operations. These complex operations are operation patterns that occur frequently in the target application, are repeatedly spliced ​​together from multiple basic instructions, and are time-consuming, such as matrix multiplication and addition, FFT butterfly operation, CRC check iteration, FIR / IIR filtering, etc. To ensure that dedicated instructions can be executed by hardware, an execution unit or microstructure corresponding to each dedicated instruction is added to the MCU core. This includes instruction decoding and extension logic, dedicated arithmetic data paths, and necessary control logic and register interfaces. The instruction decoding and extension logic identifies the new opcode and parses fields such as registers, immediate values, and lengths. The dedicated arithmetic data paths can be parallel multiply-accumulate arrays, butterfly computation units, CRC linear feedback shift registers (LFSRs), saturated arithmetic and fixed-point scaling units, etc. The control logic and register interfaces are used to read source operands from the general-purpose register file, write results back to the target register, and support updating flag bits or exception states. When the CPU fetches and decodes the dedicated instruction, it no longer executes the basic instruction sequence expanded by the compiler in the traditional way. Instead, the decoding control logic directly triggers the dedicated execution unit to complete the corresponding complex operation within one or more defined clock cycles and writes the result back to the specified register or memory address. To ensure executability and reproducibility, the input and output operand formats, memory access semantics, timing semantics, and exception handling rules are specified for each dedicated instruction. In this way, complex operations are transformed from software concatenation of multiple basic instructions to hardware acceleration triggered by a single instruction. This significantly reduces the number of instructions and execution cycle at the same clock frequency, reduces instruction fetching and decoding overhead, and improves the MCU's processing efficiency for high-frequency complex computing tasks.

[0017] Furthermore, the special instructions include at least one of matrix operation instructions, fast Fourier transform instructions, cyclic redundancy check instructions, and digital signal processing instructions.

[0018] Specifically, based on the complex computational types that frequently occur in the target application scenarios of the MCU, typical computational processes are summarized and abstracted, and corresponding dedicated instruction categories are defined. Taking the Arm Cortex-M7 core instruction set architecture as an example, without disrupting the original Thumb-2 instruction encoding system and instruction execution timing, by expanding the opcode space and introducing dedicated instruction recognition logic in the instruction decoding stage, several new dedicated instructions for complex high-frequency computational scenarios are added, such as at least one of matrix operation instructions, fast Fourier transform instructions, cyclic redundancy check instructions, and digital signal processing instructions, to replace complex operations traditionally completed by combining multiple basic instructions. Among them, the matrix operation instruction is the MATMUL instruction, which is used to trigger a dedicated matrix operation unit to complete a 4×4 matrix multiplication operation within a single instruction cycle. During execution, the MATMUL instruction reads two 4×4 matrix data from the general-purpose register set or on-chip memory at once, and completes the parallel calculation of matrix elements through a hardware parallel multiply-accumulate array. The calculation result is written back to the target register or memory address within a predetermined cycle, thereby avoiding the instruction redundancy and control overhead caused by the traditional element-by-element multiply-accumulate instruction loop. The Fast Fourier Transform (FFT) instruction performs a 16-point Fast Fourier Transform operation. After decoding, the FFT instruction directly drives the built-in butterfly operation hardware unit to perform complex number addition, subtraction, multiplication, and data rearrangement operations according to the preset transform series and rotation factor order. This achieves frequency domain transformation of the input sequence, reducing multi-level loops and multiple memory accesses. The Cyclic Redundancy Check (CRC32) instruction performs a 32-bit CRC check on the input data stream. During execution, the CRC32 instruction loads the input data and a preset generator polynomial into the hardware CRC calculation unit. A linear feedback shift register structure completes the full check value update within one or a few clock cycles, significantly improving check efficiency compared to software bit-by-bit or byte-by-byte calculation methods. The digital signal processing instructions are FIR instructions, which are used to perform 8th-order finite impulse response filtering operations. FIR instructions integrate multi-channel multiply-accumulate units at the hardware level, enabling parallel multiplication, accumulation, and processing of input sampled data and filter coefficients under a single instruction trigger. They also support fixed-point saturation, rounding, and result scaling, making them suitable for audio processing, sensor signal filtering, and other scenarios. Through this instruction set extension method, complex operations such as matrix operations, fast Fourier transforms, cyclic redundancy checks, and digital signal processing are solidified into dedicated instructions that can be directly executed by the hardware. This allows the MCU to complete calculations with fewer instructions and shorter execution cycles when performing related tasks, thus providing a clear instruction-level foundation for subsequent compiler replacement, cache prefetching, and power consumption adjustment.

[0019] The compiler identifies complex operation patterns in the code and replaces these complex operations with corresponding dedicated instructions to generate optimized code.

[0020] Specifically, the compiler is an embedded compiler built on the LLVM framework. The identification and replacement of complex operations are completed in the compiler's intermediate representation (IR) layer to avoid affecting the semantics of the source code and ensure cross-language versatility. After completing front-end syntax analysis and generating LLVM intermediate code, the compiler performs instruction-level data flow analysis and control flow analysis on the intermediate code to identify high computational complexity operation patterns that recur in the program. Then, the compiler identifies complex operation fragments that meet the replacement conditions by matching the complex operation pattern library with the LLVM intermediate code, thereby replacing the complex operations with corresponding dedicated instructions, such as replacing matrix operations in loops with MATMUL instructions, and FFT calculations with FFT instructions, etc. The complex operation pattern library is used to describe the operational features that can be replaced by dedicated instructions, including but not limited to multi-layer nested multiply-add sequences in matrix multiplication, butterfly operation structures in fast Fourier transform, and shift and XOR iteration patterns in cyclic redundancy check, etc. After completing the complex operation replacement, the compiler continues to execute the regular register allocation, instruction scheduling, and code generation process, mapping dedicated instruction nodes to the instruction encoding format supported by the target MCU architecture, and generating optimized target code containing dedicated instructions. Through the above process, complex operations that originally required multiple basic instructions and multiple loops are compressed into dedicated instructions that can be directly executed by the hardware. This significantly reduces the number of instructions and execution cycle while ensuring the equivalence of program functions, improves code execution efficiency, and provides more explicit execution characteristics for subsequent cache prefetching and power consumption adjustment.

[0021] Furthermore, the compiler identifies complex operation patterns in the code and replaces these complex operations with corresponding dedicated instructions, generating optimized code, including: The compiler is an LLVM-based compiler. The compiler adds data dependency analysis and loop nesting depth detection to the LLVM intermediate code layer to identify complex operation variants not covered by traditional rules and obtain the complex operation. The complex operation is replaced with the corresponding special instructions, and the compiler generates the optimized code and embeds data range markers.

[0022] Specifically, the compiler is built on the LLVM compiler framework and introduces enhanced analysis and instruction substitution mechanisms for complex operations during the intermediate code (LLVM IR) optimization phase. After completing front-end syntax analysis and generating LLVM IR, the compiler inserts a dedicated complex operation identification pass before or during the regular optimization process to perform multi-dimensional analysis of the intermediate code. First, the complex operation identification pass performs data dependency analysis at the LLVM IR layer, constructing a read-write dependency graph between instructions to determine whether there are cross-iteration dependencies, loop-carried dependencies, or memory alias conflicts between different operation instructions. Simultaneously, it parses the loop structure in the program, detecting loop nesting depth, loop boundaries, and iteration steps to obtain the structural features of the operation patterns within the loops. Through the combination of data dependency analysis and loop nesting depth detection, it can identify complex operation variants that are difficult to cover using traditional simple pattern matching rules, such as operation sequences rearranged, expanded, or merged by the compiler. Based on this, the compiler matches the analyzed operation structure with predefined complex operation feature templates. When a continuous multiply-accumulate instruction sequence is detected in a nested loop, and the data access pattern conforms to the row and column access characteristics of a fixed-dimensional matrix, it is determined to be a complex matrix operation, and the operation segment is marked as replaceable by the MATMUL instruction. When an operation sequence containing butterfly structure, twitch factor access, and hierarchical loop characteristics is detected, it is determined to be a Fast Fourier Transform calculation, and is marked as replaceable by the FFT instruction. When an operation sequence with shift or XOR as its core and updating the accumulated check value by byte or word is detected, it is determined to be a Cyclic Redundancy Check calculation, and is marked as replaceable by the CRC32 instruction. When an operation sequence performing sliding window multiply-accumulate in a loop and having a fixed-order coefficient access pattern is detected, it is determined to be a Finite Impulse Response (FIR) filter operation, and is marked as replaceable by the FIR instruction.

[0023] After identifying complex operations, the compiler performs a validity check on the complex operation fragments, confirming that their data types, data alignment, access ranges, and loop boundaries meet the hardware execution constraints of the corresponding dedicated instructions. When the check passes, the compiler deletes the original arithmetic code segment consisting of multiple basic instructions and loop structures, and inserts a dedicated instruction node corresponding to the complex operation into the LLVM IR. Simultaneously, a data range marker is embedded in the instruction node to describe the starting address, data length, and step size of the data that the dedicated instruction may access during execution. Finally, the compiler continues with subsequent register allocation, instruction scheduling, and target code generation processes, mapping the dedicated instruction node to machine instruction encoding supported by the target MCU architecture, generating optimized code containing at least one of the following: MATMUL, FFT, CRC32, and FIR instructions. Through this process, the compiler can automatically identify and replace various complex operation variants at the LLVM intermediate code layer, achieving efficient utilization of dedicated instructions and providing precise data access range information for subsequent cache prefetch control.

[0024] Furthermore, replacing the complex operation with corresponding dedicated instructions also includes: Configure a performance detection module. When the performance detection module reports a cache hit rate greater than a preset probability, enable dedicated instruction replacement; otherwise, maintain the basic instruction sequence.

[0025] Specifically, the performance detection module is used to collaboratively evaluate whether the execution environment of complex operations on the target MCU is suitable for enabling dedicated instruction replacement during the compilation and runtime phases. During the compilation phase, after the compiler identifies a complex operation segment that can be replaced by dedicated instructions, it does not immediately perform instruction replacement. Instead, it marks the complex operation segment as a candidate replacement region and inserts a performance detection marker in the intermediate code. This performance detection module evaluates the cache hit rate that the complex operation may generate at runtime based on the cache structure parameters of the target MCU, such as cache level, capacity, line size, and replacement strategy, combined with the memory access address pattern, data access span, and number of loop accesses of the candidate complex operation. This evaluation can be performed by combining static analysis and historical runtime statistics. Static analysis is used to determine whether the access exhibits a continuous, regular, or predictable pattern, while historical runtime statistics are used to introduce cache hit records of the same or similar code segments in previous runs, thereby obtaining a more accurate cache hit rate feedback value. When the cache hit rate reported by the performance detection module is greater than a preset probability, it is determined that the current complex operation is suitable for execution by a dedicated instruction. In this case, the compiler activates the dedicated instruction replacement process, deleting the basic instruction sequence corresponding to the complex operation fragment and replacing it with a dedicated instruction corresponding to the complex operation, while retaining relevant data range markers and execution constraint information. Conversely, when the cache hit rate reported by the performance detection module is less than or equal to the preset probability, it is determined that enabling a dedicated instruction under the current cache conditions may not achieve the expected performance improvement, and may even introduce additional memory access overhead or pipeline blocking. In this case, the compiler does not perform dedicated instruction replacement, but maintains the original instruction sequence composed of basic instructions to ensure the stability and compatibility of the program on the target hardware platform. Through the above performance detection and conditional replacement mechanism, adaptive control of dedicated instruction activation is achieved, ensuring that dedicated instructions are only used when cache conditions and memory access behavior meet the expected performance benefits, thereby avoiding performance fluctuations caused by blind replacement and improving overall code execution efficiency and system robustness.

[0026] A multi-level cache is set up between the MCU and the main memory. The prefetch controller predicts the target data that will be accessed in the future based on the program execution mode, and loads the target data into the cache in advance when the CPU executes the optimized code.

[0027] Specifically, a multi-level cache structure is set up between the MCU core and main memory to reduce the average latency of CPU access to main memory. This multi-level cache includes at least a Level 1 cache (L1) and a Level 2 cache (L2). The L1 cache is tightly coupled to the CPU core to provide low-latency instruction and data access. The L2 cache, as a unified cache, is located between the MCU internal bus and main memory to cache data from main memory and provide L2 cache hit support for the L1 cache. A prefetch controller is set up in the multi-level cache structure. This prefetch controller is equipped with an instruction type awareness unit to sense instruction execution characteristics during program execution and predict future data access needs. It extracts data access characteristics, prefetch addresses, etc., to locate the target data that will be accessed in the future. Then, with the cooperation of the cache control logic, the prefetch controller loads the target data from main memory into the L2 cache through idle bus cycles or low-priority memory access channels without affecting the normal instruction execution of the CPU. If necessary, it further loads the data into the L1 data cache. When the CPU actually accesses the target data during subsequent instruction execution, the data is already resident in the cache, thereby significantly reducing the waiting cycles caused by accessing main memory. By working together with the above-mentioned multi-level caching and prefetch control, the prefetch behavior is matched with the execution characteristics of the optimized code, thus enabling advance preparation for future data access, effectively improving cache hit rate, reducing memory access latency, and further amplifying the performance improvement brought about by dedicated instructions and compiler optimizations.

[0028] Furthermore, the multi-level cache includes an L1 cache and an L2 cache; wherein the L1 cache is divided into an instruction cache and a data cache; and the L2 cache is a unified cache.

[0029] Specifically, to improve the instruction fetching and data access efficiency of the MCU when executing optimized code, a multi-level cache system is built between the MCU core and main memory. This multi-level cache includes a Level 1 cache (L1 cache) and a Level 2 cache (L2 cache), which are connected to the main memory sequentially via an on-chip bus. The L1 cache is located inside the MCU core or in a location tightly coupled to the core to provide the shortest access latency. To avoid contention between instruction fetching and data access on the same cache resources, the L1 cache adopts a separate structure, divided into an instruction cache and a data cache. The instruction cache stores the instruction code that the CPU is about to execute, including basic instructions and special instructions; the data cache stores operands, intermediate calculation results, and target data that the CPU frequently accesses during instruction execution. The instruction cache and data cache are configured with independent cache lines, replacement policies, and access ports, enabling instruction fetching and data read / write operations to be performed in parallel, thereby improving pipeline execution efficiency. The L2 cache is located between the MCU's internal bus and main memory, serving as the next level down from the L1 cache. It employs a unified cache structure to simultaneously cache instruction data and data information. This unified structure allows the L2 cache to dynamically allocate cache space based on actual access needs, improving overall cache utilization for different types of data. When the CPU misses an instruction cache or data cache access, the request is first forwarded to the L2 cache. If the L2 cache hits, the corresponding cache line is backfilled into the L1 cache. If the L2 cache misses, the L2 cache control logic then initiates an access request to the main memory. During this multi-level cache operation, the L1 instruction cache, L1 data cache, and L2 unified cache work collaboratively through consistency control and state management mechanisms to ensure the consistency and correctness of instructions and data across different cache levels. Simultaneously, the L2 unified cache provides a unified data preloading entry point for the prefetch controller, facilitating the priority loading of predicted target data into the L2 cache, followed by selective backfilling into the L1 data cache based on access urgency. This further reduces overall memory access latency while ensuring system stability.

[0030] Furthermore, a multi-level cache is set up between the MCU and the main memory, and the prefetch controller predicts the target data that will need to be accessed in the future based on the program execution mode, including: An instruction type awareness unit is configured in the prefetch controller. The instruction type awareness unit parses the data access characteristics of the special instruction to be executed. The data access characteristics are analyzed based on historical access patterns to generate a prefetch address. Based on the prefetch address, the prefetch controller is guided to locate the target data according to the data range marker embedded in the optimized code.

[0031] Specifically, the prefetch controller is internally configured with an instruction type awareness unit. This unit identifies the type of the instruction to be executed in real time during the CPU's execution of optimized code and parses the corresponding data access characteristics. This instruction type awareness unit is connected to the instruction decoding unit. When it detects that the instruction to be executed is a special-purpose instruction, it reads the opcode, operand field, and extended control field of the special-purpose instruction to determine whether the instruction belongs to a matrix operation, fast Fourier transform, cyclic redundancy check, or digital signal processing operation. After completing instruction type identification, the instruction type awareness unit parses the corresponding data access characteristics of the special-purpose instruction during execution based on a pre-established instruction memory access characteristic description table. These data access characteristics include at least the data start address, access data length, access step size, access order (sequential access, step-by-step access, or block access), and whether the access exhibits periodicity or repetition. This characteristic description table can be preset during system initialization or dynamically updated during operation based on statistical results. Subsequently, the prefetch controller analyzes the data access characteristics based on historical access patterns. Specifically, the prefetch controller maintains a historical memory access record buffer to record the actual memory access address sequence, cache hit status, and access interval of the same type of special instructions during previous executions. Through statistical analysis of historical memory access records, the prefetch controller can determine whether the data access pattern is stable and predict the range of data block addresses that may be accessed in the next stage, i.e., blocks whose access frequency exceeds a threshold in the statistics. After prediction, the prefetch controller generates one or more prefetch addresses based on the current execution context to represent the memory addresses where the target data that needs to be preloaded resides.

[0032] After generating the prefetch address, the prefetch controller constrains and verifies the prefetch address by combining the data range marker embedded in the optimized code by the compiler. This data range marker describes the data boundaries that a special instruction is allowed to access within the current execution cycle, including the legal start address, end address, and maximum access span. The prefetch controller compares the prefetch address with the data range marker, filters out prediction results that exceed the legal range, and finally determines the target data address for prefetching. After locating the target data address, the prefetch controller submits the prefetch address to the cache control logic. Without affecting the normal instruction execution of the CPU, the corresponding target data is preloaded from main memory into the L2 cache or L1 data cache, thereby improving the cache hit rate and reducing access latency when subsequent special instructions or related basic instructions actually access the target data.

[0033] The CPU operating frequency is dynamically adjusted based on the load status of the MCU.

[0034] Specifically, a load monitoring module and a dynamic frequency adjustment module are set up inside the MCU to sense the MCU's operating load in real time during program execution and adaptively adjust the CPU operating frequency. The load monitoring module is connected to the CPU core, instruction scheduling unit, and cache control logic, and periodically collects various operating parameters reflecting the MCU's load status. Specifically, within a preset monitoring period, the load monitoring module counts the CPU's effective execution time and idle time, calculates CPU utilization, and, combined with the type of instruction being executed, distinguishes the execution ratio of basic instructions and special instructions, and counts indicators such as instruction issue rate, pipeline occupancy, and cache misses, forming a comprehensive load status description for the current operating cycle. After obtaining the comprehensive load status, the dynamic frequency adjustment module evaluates the current operating state based on a pre-established power consumption model, and, combined with the power consumption weight of special instructions, performs a weighted calculation of the execution load of different types of instructions, thereby obtaining a load evaluation result that more accurately reflects actual power consumption characteristics. When the evaluation indicates a low load, the dynamic frequency adjustment module sends a down-frequency command to the clock control unit, reducing the CPU operating frequency to the corresponding low-frequency level to minimize unnecessary power consumption. Conversely, when the evaluation indicates a high load or the execution of numerous computationally intensive dedicated instructions, the dynamic frequency adjustment module sends an up-frequency command to the clock control unit, increasing the CPU operating frequency to meet real-time computing demands. During frequency adjustment, the dynamic frequency adjustment module smoothly switches the CPU operating frequency using a phase-locked loop or a programmable clock divider, and resynchronizes the timing sequence after the switch to ensure the continuity of instruction execution and system stability. Through this synchronous monitoring and dynamic adjustment mechanism, the MCU can adaptively balance performance and power consumption based on the actual operating load, thereby effectively reducing overall energy consumption while ensuring execution efficiency.

[0035] Furthermore, it synchronously monitors the MCU's load status and dynamically adjusts the CPU's operating frequency based on the load status, including: A real-time power consumption model is established for each type of dedicated instruction; a weighted power consumption value based on the instruction sequence is calculated based on the real-time power consumption model; and the CPU operating frequency is dynamically adjusted based on the weighted power consumption value.

[0036] Specifically, to achieve fine-grained adjustment of the CPU operating frequency, a real-time power consumption model is established in the dynamic frequency adjustment module within the MCU for different types of dedicated instructions. These real-time power consumption models describe the power consumption characteristics of each type of dedicated instruction per unit time or unit number of executions. The model parameters include at least the hardware resource occupancy weights corresponding to matrix operation instructions, Fast Fourier Transform instructions, Cyclic Redundancy Check instructions, and Digital Signal Processing instructions. During program execution, the load monitoring module acquires the currently executing instruction sequence information in real time. Based on the instruction sequence, the dynamic power consumption evaluation module calls the corresponding real-time power consumption model to calculate the power consumption contribution of each type of dedicated instruction and performs a weighted sum of the power consumption values ​​for different instruction types, thereby obtaining a weighted power consumption value reflecting the current execution load intensity. This weighted power consumption value comprehensively reflects multiple factors such as instruction execution intensity, hardware unit activation level, and memory access behavior. After obtaining the weighted power consumption value, the dynamic frequency adjustment module compares it with a pre-set power consumption threshold range and selects the corresponding CPU operating frequency level based on the comparison result, enabling the MCU to balance performance improvement and energy consumption optimization in different computing scenarios.

[0037] Furthermore, the dynamic frequency adjustment operates within a frequency range of 100MHz to 400MHz, with a load monitoring cycle of 1ms.

[0038] Specifically, the CPU's dynamic frequency adjustment operates within a preset operating frequency range, limited to 100MHz to 400MHz, to balance the MCU's real-time performance requirements with power consumption control. The load monitoring module samples the MCU's operating status at a fixed monitoring period of 1ms. Within each monitoring period, the load monitoring module collects the CPU's operating parameters in real time and generates a corresponding load assessment result at the end of the current monitoring period. After each 1ms load monitoring period, the dynamic frequency adjustment module adjusts the CPU's operating frequency towards 100MHz or 400MHz based on the load assessment result. During frequency adjustment, the dynamic frequency adjustment module uses a graded or gradual frequency switching strategy through the clock control unit to smoothly transition between adjacent frequency levels, so as to avoid frequent jumps affecting system stability and timing reliability. At the same time, after the frequency switching is completed, the load monitoring module enters the next 1ms monitoring cycle to continue to evaluate the new operating state, thus forming a closed-loop control process of "monitoring-evaluation-adjustment". This enables the MCU to respond quickly to load changes on a millisecond time scale, reduce power consumption in low load scenarios, and improve performance in high load or real-time computing scenarios, thereby achieving a dynamic balance between performance and power consumption.

[0039] Furthermore, dynamically adjusting the CPU operating frequency based on the weighted power consumption value includes: When CPU utilization is below 20%, the frequency is adjusted to 100MHz; when CPU utilization is between 20% and 60%, the frequency is adjusted to 200MHz; when CPU utilization is between 60% and 80%, the frequency is adjusted to 300MHz; and when CPU utilization is above 80%, the frequency is adjusted to 400MHz.

[0040] Specifically, the dynamic frequency adjustment module performs tiered control of the CPU operating frequency based on CPU utilization to achieve a balance between performance and power consumption. CPU utilization represents the percentage of time the CPU actually spends executing instructions within a unit monitoring cycle, and is statistically calculated by the load monitoring module in each preset load monitoring cycle. Within each load monitoring cycle, the load monitoring module calculates the effective execution time and total monitoring time of the CPU, and calculates the current CPU utilization based on their ratio. When the CPU utilization is below 20%, it indicates that the current operating load is low, and the CPU is in a long-term idle or light-load state. At this time, the dynamic frequency adjustment module sends a frequency reduction control signal to the clock control unit, adjusting the CPU operating frequency to 100MHz to reduce dynamic and static power consumption. When the CPU utilization is between 20% and 60%, it indicates that the CPU is executing a certain number of routine tasks, but has not yet reached the level of computationally intensive load. At this time, the dynamic frequency adjustment module adjusts the CPU operating frequency to 200MHz to control power consumption growth while ensuring basic performance requirements. When CPU utilization is between 60% and 80%, it indicates a further increase in CPU load and a greater demand for computation or dedicated instruction execution. In this case, the dynamic frequency adjustment module adjusts the CPU operating frequency to 300MHz to improve instruction throughput and meet higher real-time requirements. When CPU utilization exceeds 80%, it indicates that the CPU is operating under high or near-full load, typically corresponding to computationally intensive tasks or applications with high response time requirements. In this case, the dynamic frequency adjustment module adjusts the CPU operating frequency to 400MHz to maximize processing performance and ensure system stability and real-time performance. During the frequency adjustment process, the dynamic frequency adjustment module uses a sequential switching method between adjacent frequency levels and waits at least one load monitoring cycle after each frequency switch before making the next adjustment to avoid frequent jitter. This hierarchical frequency control mechanism allows the MCU to dynamically select the appropriate operating frequency based on actual load changes, achieving adaptive optimization of performance and power consumption.

[0041] In summary, the MCU performance improvement method based on instruction set optimization and cache prefetching provided in this application embodiment has at least the following technical effects: by optimizing the instruction set, cache prefetching, and dynamic frequency adjustment, the execution efficiency and cache hit rate of the MCU are improved, memory access latency is reduced, and overall power consumption is effectively reduced while ensuring performance.

[0042] Example 2 is based on the same inventive concept as the MCU performance improvement method of instruction set optimization and cache prefetching in the foregoing examples, such as... Figure 2 As shown, this application provides a system for improving MCU performance through instruction set optimization and cache prefetching. The system includes: Specialized instruction addition component 11: Adds specialized instructions for preset complex operations to the original instruction set of the MCU. The specialized instructions are implemented at the hardware level. Code replacement component 12: The compiler identifies complex operation patterns in the code and replaces the complex operations with corresponding specialized instructions to generate optimized code. Data caching component 13: Sets up a multi-level cache between the MCU and the main memory. The prefetch controller predicts the target data that will need to be accessed in the future based on the program execution mode and loads the target data into the cache in advance when the CPU executes the optimized code. CPU adjustment component 14: Synchronously monitors the load status of the MCU and dynamically adjusts the CPU operating frequency according to the load status.

[0043] Furthermore, the dedicated instruction addition component 11 includes: The special instructions include at least one of matrix operation instructions, fast Fourier transform instructions, cyclic redundancy check instructions, and digital signal processing instructions.

[0044] Furthermore, the code replacement component 12 includes: The compiler is an LLVM-based compiler. The compiler adds data dependency analysis and loop nesting depth detection to the LLVM intermediate code layer to identify complex operation variants not covered by traditional rules and obtain the complex operation. The complex operation is replaced with the corresponding special instructions, and the compiler generates the optimized code and embeds data range markers.

[0045] Furthermore, the code replacement component 12 includes: Configure a performance detection module. When the performance detection module reports a cache hit rate greater than a preset probability, enable dedicated instruction replacement; otherwise, maintain the basic instruction sequence.

[0046] Furthermore, the data caching component 13 includes: The multi-level cache includes an L1 cache and an L2 cache; wherein, the L1 cache is divided into an instruction cache and a data cache; and the L2 cache is a unified cache.

[0047] Furthermore, the data caching component 13 includes: An instruction type awareness unit is configured in the prefetch controller. The instruction type awareness unit parses the data access characteristics of the special instruction to be executed. The data access characteristics are analyzed based on historical access patterns to generate a prefetch address. Based on the prefetch address, the prefetch controller is guided to locate the target data according to the data range marker embedded in the optimized code.

[0048] Furthermore, the CPU tuning component 14 includes: A real-time power consumption model is established for each type of dedicated instruction; a weighted power consumption value based on the instruction sequence is calculated based on the real-time power consumption model; and the CPU operating frequency is dynamically adjusted based on the weighted power consumption value.

[0049] Furthermore, the CPU tuning component 14 includes: The dynamic frequency adjustment operates within a frequency range of 100MHz to 400MHz, with a load monitoring cycle of 1ms.

[0050] Furthermore, the CPU tuning component 14 includes: When CPU utilization is below 20%, the frequency is adjusted to 100MHz; when CPU utilization is between 20% and 60%, the frequency is adjusted to 200MHz; when CPU utilization is between 60% and 80%, the frequency is adjusted to 300MHz; and when CPU utilization is above 80%, the frequency is adjusted to 400MHz.

[0051] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0052] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of this application and its equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for improving MCU performance through instruction set optimization and cache prefetching, characterized in that, include: On the basis of the original instruction set of the MCU, special instructions for preset complex operations are added, and the special instructions are implemented at the hardware level; The compiler identifies complex operation patterns in the code and replaces these complex operations with corresponding dedicated instructions to generate optimized code. A multi-level cache is set up between the MCU and the main memory. The prefetch controller predicts the target data that will be accessed in the future based on the program execution mode, and loads the target data into the cache in advance when the CPU executes the optimized code. The CPU operating frequency is dynamically adjusted based on the load status of the MCU.

2. The MCU performance improvement method based on instruction set optimization and cache prefetching as described in claim 1, characterized in that, The special instructions include at least one of matrix operation instructions, fast Fourier transform instructions, cyclic redundancy check instructions, and digital signal processing instructions.

3. The MCU performance improvement method based on instruction set optimization and cache prefetching as described in claim 1, characterized in that, The compiler identifies complex operation patterns in the code and replaces these complex operations with corresponding dedicated instructions, generating optimized code, including: The compiler is an LLVM-based compiler. The compiler adds data dependency analysis and loop nesting depth detection to the LLVM intermediate code layer to identify complex operation variants not covered by traditional rules and obtain the complex operation. The complex operation is replaced with the corresponding dedicated instructions, the optimized code is generated by the compiler, and data range markers are embedded.

4. The MCU performance improvement method based on instruction set optimization and cache prefetching as described in claim 3, characterized in that, Replacing the complex operation with corresponding dedicated instructions also includes: Configure a performance detection module. When the performance detection module reports that the cache hit rate is greater than a preset probability, enable a dedicated instruction to replace it. Otherwise, maintain the basic instruction sequence.

5. The MCU performance improvement method based on instruction set optimization and cache prefetching as described in claim 1, characterized in that, The multi-level cache includes L1 cache and L2 cache; The L1 cache is divided into an instruction cache and a data cache. The L2 cache is a unified cache.

6. The MCU performance improvement method based on instruction set optimization and cache prefetching as described in claim 1, characterized in that, A multi-level cache is set up between the MCU and the main memory. The prefetch controller predicts the target data that will need to be accessed in the future based on the program execution mode, including: An instruction type awareness unit is configured in the prefetch controller, and the data access characteristics of the special instruction to be executed are parsed through the instruction type awareness unit. Based on the analysis of historical access patterns, the data access characteristics are generated to generate a prefetch address; Based on the prefetch address, the prefetch controller is guided to locate the target data according to the data range marker embedded in the optimized code.

7. The MCU performance improvement method based on instruction set optimization and cache prefetching as described in claim 1, characterized in that, Synchronously monitor the MCU's load status and dynamically adjust the CPU's operating frequency based on the load status, including: Establish a real-time power consumption model for each type of dedicated instruction; The CPU operating frequency is dynamically adjusted based on the weighted power consumption value calculated according to the instruction sequence based on the real-time power consumption model.

8. The MCU performance improvement method based on instruction set optimization and cache prefetching as described in claim 7, characterized in that, The dynamic frequency adjustment operates within a frequency range of 100MHz to 400MHz, with a load monitoring cycle of 1ms.

9. The MCU performance improvement method based on instruction set optimization and cache prefetching as described in claim 8, characterized in that, Dynamically adjusting the CPU operating frequency based on the weighted power consumption value includes: When CPU utilization is below 20%, the frequency is adjusted to 100MHz; When CPU utilization is between 20% and 60%, the frequency is adjusted to 200MHz; When CPU utilization is between 60% and 80%, the frequency is adjusted to 300MHz; When CPU utilization is above 80%, the frequency is adjusted to 400MHz.

10. A system for improving MCU performance through instruction set optimization and cache prefetching, characterized in that, A method for improving MCU performance by instruction set optimization and cache prefetching as described in any one of claims 1-9 includes: Specialized instruction addition component: Based on the original instruction set of the MCU, specialized instructions for preset complex operations are added, and the specialized instructions are implemented at the hardware level; Code replacement component: The compiler identifies complex operation patterns in the code and replaces the complex operations with corresponding special instructions to generate optimized code; Data caching component: A multi-level cache is set up between the MCU and the main memory. The prefetch controller predicts the target data that will be accessed in the future based on the program execution mode, and loads the target data into the cache in advance when the CPU executes the optimized code; CPU adjustment component: Synchronously monitors the MCU's load status and dynamically adjusts the CPU's operating frequency based on the load status.

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