First core particle, first core chip, core particle intercommunication method, and electronic device

Abstract

The present disclosure relates to the technical field of integrated circuits, and proposes a first core particle, a first chip, a core particle intercommunication method and an electronic device. The first core particle comprises a first host, a first network on chip, M second networks on chip, a communication module and N storage units, the i-th second network on chip is connected with the first network on chip, the communication module and the j-th storage unit; the first network on chip is used for communication between the first host and the M second networks on chip; the communication module is used for communication between the first core particle and a second core particle; the i-th second network on chip is used for communication between the j-th storage unit and the first network on chip, communication between the j-th storage unit and the communication module, and communication between the first network on chip and the communication module. The routing path of the network on chip of the first core particle is short, the delay is low, and the power consumption is small, thereby being capable of improving cross-core particle access performance and meeting high-performance computing requirements.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a first chip, a first chip, a chip-to-chip communication method, and an electronic device. Background Technology

[0002] Graphics Processing Units (GPUs), Artificial Intelligence (AI) accelerators, and large-scale heterogeneous computing systems often employ multi-die packaging structures. Each die typically interconnects multiple functional modules, such as compute units, memory controllers, and die-to-die (D2D) interfaces, via a network-on-chip (NoC) connection. Cross-die access is achieved between different dies through the D2D interface.

[0003] Existing on-chip networks suffer from drawbacks such as long routing paths, high latency, and high power consumption, which reduce cross-chip access performance and make it difficult to meet the needs of high-performance computing. Summary of the Invention

[0004] In view of this, this disclosure proposes a first chip, a first chip, an inter-chip communication method, and an electronic device. The on-chip network of the first chip has a short routing path, low latency, and low power consumption, thereby improving cross-chip access performance and meeting the needs of high-performance computing.

[0005] According to one aspect of this disclosure, a first chip is provided, the first chip including a first host, a first on-chip network, M second on-chip networks, a communication module, and N storage units, where M and N are positive integers; the i-th second on-chip network connects the first on-chip network, the communication module, and the j-th storage unit; i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N; the first on-chip network is used for communication between the first host and the M second on-chip networks; the communication module is used for communication between the first chip and the second chips; the i-th second on-chip network is used for communication between the j-th storage unit and the first on-chip network, and for communication between the j-th storage unit and the communication module, and for communication between the first on-chip network and the communication module.

[0006] In one possible implementation, the communication module is configured to output a first access request for the j-th storage unit generated by the second host on the second chip to the i-th second on-chip network; the i-th second on-chip network is configured to output the first access request to the j-th storage unit.

[0007] In one possible implementation, the communication module includes M communication units, the i-th second on-chip network is connected to the i-th communication unit, and the i-th communication unit is used to output a first access request for the j-th storage unit generated by the second host on the second chip to the i-th second on-chip network.

[0008] In one possible implementation, the communication module on the first chip is connected to the communication module on the second chip, and the communication module on the second chip and the q-th storage unit on the second chip are connected to the p-th second on-chip network on the second chip, where p and q are positive integers; the first on-chip network is used to output the second access request to the i-th second on-chip network when the first host generates a second access request for the q-th storage unit; the i-th second on-chip network is used to output the second access request to the communication module on the first chip; the communication module on the first chip is used to output the second access request to the communication module on the second chip; the second access request is output to the q-th storage unit via the communication module on the second chip and the p-th second on-chip network.

[0009] In one possible implementation, the communication module on the first chip includes M communication units, the i-th second on-chip network is connected to the i-th communication unit, the communication module on the second chip includes W communication units, where W is an integer greater than or equal to p; the i-th communication unit is connected to the p-th communication unit on the second chip, the p-th communication unit on the second chip and the q-th storage unit on the second chip are connected to the p-th second on-chip network on the second chip, where p and q are positive integers; the i-th second on-chip network is used to output the second access request to the i-th communication unit; the i-th communication unit is used to output the second access request to the p-th communication unit; on the second chip, the second access request is output to the q-th storage unit via the p-th communication unit and the p-th second on-chip network.

[0010] In one possible implementation, the first on-chip network is configured to output the third access request to the i-th second on-chip network when the first host generates a third access request for the j-th storage unit; the i-th second on-chip network is configured to output the third access request to the j-th storage unit.

[0011] In one possible implementation, the i-th second on-chip network includes: a first interface for connecting to the first on-chip network; a second interface for connecting to the j-th storage unit; a third interface and a fourth interface for connecting to the communication module, wherein the third interface is used for uplink transmission and the fourth interface is used for downlink transmission; and a routing module for interconnecting the first interface, the second interface, the third interface, and the fourth interface.

[0012] In one possible implementation, the first chip further includes a first conversion module connected between the first host and the first on-chip network; the first on-chip network includes M fifth interfaces, the i-th fifth interface being connected to the i-th second on-chip network; the first conversion module is used to convert the first physical address carried in the access request generated by the first host into a second physical address recognizable by the first on-chip network, and then output the access request to the first on-chip network; the second physical address includes the identifier of the storage unit corresponding to the first physical address; the first on-chip network is used to determine one of the M fifth interfaces corresponding to the access request by identifying the second physical address, and output the access request through the determined fifth interface.

[0013] In one possible implementation, the communication module on the first chip includes M communication units, the i-th second on-chip network is connected to the i-th communication unit, and when the first physical address corresponds to a storage unit on the second chip, the second physical address also includes the identifier of the communication unit on the first chip used to transmit the access request; the first on-chip network is used to determine that the access request corresponds to the i-th fifth interface when it recognizes that the second physical address includes the identifier of the j-th storage unit or the identifier of the i-th communication unit.

[0014] In one possible implementation, the i-th second on-chip network is configured to: output the received access request to the j-th storage unit when the second physical address in the received access request includes the identifier of the j-th storage unit; and output the received access request to the i-th communication unit when the second physical address in the received access request includes the identifier of the i-th communication unit.

[0015] According to another aspect of this disclosure, a first chip is provided, comprising the first chip and the second chip as described in any of the preceding claims.

[0016] According to another aspect of this disclosure, an electronic device is provided, including the first chip described above.

[0017] According to another aspect of this disclosure, an inter-chip communication method is provided, the method being applied to a first chip, the first chip including a first host, a first on-chip network, M second on-chip networks, a communication module, and N storage units, where M and N are positive integers; the i-th second on-chip network connects the first on-chip network, the communication module, and the j-th storage unit; i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N; the method includes: using the first on-chip network to implement communication between the first host and the M second on-chip networks; using the communication module to implement communication between the first chip and the second chips; using the i-th second on-chip network to implement communication between the j-th storage unit and the first on-chip network, communication between the j-th storage unit and the communication module, and communication between the first on-chip network and the communication module.

[0018] In one possible implementation, the method further includes: using the communication module to output a first access request for the j-th storage unit generated by a second host on the second chip to the i-th second on-chip network; the step of using the i-th second on-chip network to realize communication between the j-th storage unit and the first on-chip network, communication between the j-th storage unit and the communication module, and communication between the first on-chip network and the communication module includes: using the i-th second on-chip network to output the first access request to the j-th storage unit.

[0019] In one possible implementation, the communication module includes M communication units, the i-th second on-chip network is connected to the i-th communication unit, and the step of using the communication module to output the first access request for the j-th storage unit generated by the second host on the second chip to the i-th second on-chip network includes: using the i-th communication unit to output the first access request for the j-th storage unit generated by the second host on the second chip to the i-th second on-chip network.

[0020] In one possible implementation, the communication module on the first chip is connected to the communication module on the second chip, and the communication module on the second chip and the q-th storage unit on the second chip are connected to the p-th second on-chip network on the second chip, where p and q are positive integers; the step of using the first on-chip network to implement communication between the first host and the M second on-chip networks includes: using the first on-chip network, when the first host generates a second access request for the q-th storage unit, outputting the second access request to the i-th second on-chip network; the step of using the i-th second on-chip network to implement communication between the j-th storage unit and the first host includes: using the first on-chip network, when the first host generates a second access request for the q-th storage unit, outputting the second access request to the i-th second on-chip network; The communication between the unit and the first on-chip network, the communication between the j-th storage unit and the communication module, and the communication between the first on-chip network and the communication module include: using the i-th second on-chip network to output the second access request to the communication module on the first chip; the communication module is used to realize the communication between the first chip and the second chip, which includes: using the communication module on the first chip to output the second access request to the communication module on the second chip; the second access request is output to the q-th storage unit via the communication module on the second chip and the p-th second on-chip network.

[0021] In one possible implementation, the communication module on the first chip includes M communication units, the i-th second on-chip network is connected to the i-th communication unit, the communication module on the second chip includes W communication units, where W is an integer greater than or equal to p; the i-th communication unit is connected to the p-th communication unit on the second chip, the p-th communication unit on the second chip and the q-th storage unit on the second chip are connected to the p-th second on-chip network on the second chip, where p and q are positive integers; the step of using the i-th second on-chip network to output the second access request to the communication module on the first chip includes: using the i-th second on-chip network to output the second access request to the i-th communication unit; the step of using the communication module on the first chip to output the second access request to the communication module on the second chip includes: using the i-th communication unit to output the second access request to the p-th communication unit; on the second chip, the second access request is output to the q-th storage unit via the p-th communication unit and the p-th second on-chip network.

[0022] In one possible implementation, the step of using the first on-chip network to implement communication between the first host and the M second on-chip networks includes: using the first on-chip network, when the first host generates a third access request for the j-th storage unit, outputting the third access request to the i-th second on-chip network; the step of using the i-th second on-chip network to implement communication between the j-th storage unit and the first on-chip network, as well as communication between the j-th storage unit and the communication module, and communication between the first on-chip network and the communication module includes: using the i-th second on-chip network to output the third access request to the j-th storage unit.

[0023] In one possible implementation, the i-th second on-chip network includes: a first interface for connecting to the first on-chip network; a second interface for connecting to the j-th storage unit; a third interface and a fourth interface for connecting to the communication module, wherein the third interface is used for uplink transmission and the fourth interface is used for downlink transmission; and a routing module for interconnecting the first interface, the second interface, the third interface, and the fourth interface.

[0024] In one possible implementation, the first chip further includes a first conversion module connected between the first host and the first on-chip network; the first on-chip network includes M fifth interfaces, the i-th fifth interface being connected to the i-th second on-chip network; the method further includes: the first conversion module converting a first physical address carried in an access request generated by the first host into a second physical address recognizable by the first on-chip network, and then outputting the access request to the first on-chip network; the second physical address includes an identifier of the storage unit corresponding to the first physical address; using the first on-chip network to realize communication between the first host and the M second on-chip networks includes: the first on-chip network determining a fifth interface among the M fifth interfaces corresponding to the access request by recognizing the second physical address, and outputting the access request through the determined fifth interface.

[0025] In one possible implementation, the communication module on the first chip includes M communication units, and the i-th second on-chip network is connected to the i-th communication unit. When the first physical address corresponds to a storage unit on the second chip, the second physical address also includes the identifier of the communication unit on the first chip used to transmit the access request. The first on-chip network determines one of the M fifth interfaces corresponding to the access request by identifying the second physical address, including: when the first on-chip network identifies that the second physical address includes the identifier of the j-th storage unit or the identifier of the i-th communication unit, it determines that the access request corresponds to the i-th fifth interface.

[0026] In one possible implementation, the communication between the j-th storage unit and the first on-chip network, the communication between the j-th storage unit and the communication module, and the communication between the first on-chip network and the communication module are implemented using the i-th second on-chip network, including: when the second physical address in the received access request includes the identifier of the j-th storage unit, the received access request is output to the j-th storage unit; when the second physical address in the received access request includes the identifier of the i-th communication unit, the received access request is output to the i-th communication unit.

[0027] According to an embodiment of this disclosure, the first chip includes a first host, a first on-chip network, M second on-chip networks, a communication module, and N storage units, where M and N are positive integers. The i-th second on-chip network connects the first on-chip network, the communication module, and the j-th storage unit; i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N. The first on-chip network is used for communication between the first host and the M second on-chip networks. The communication module is used for communication between the first chip and the second chips. The i-th second on-chip network is used for communication between the j-th storage unit and the first on-chip network, as well as communication between the j-th storage unit and the communication module, and communication between the first on-chip network and the communication module. In the first chip, the first on-chip network handles the routing between the host and the first on-chip network, while the second on-chip networks are only responsible for routing between the connected storage units, the first on-chip network, and the communication module. Compared to the complete routing of the main NoC in the prior art, the second on-chip network provides local routing, resulting in shorter routing paths, reduced routing complexity, lower latency, and lower power consumption. In cross-chip access, when the first chip is used as the destination chip and the second chip as the source chip, compared with existing cross-chip access schemes, the embodiments of this disclosure can shorten the internal path of the destination chip, reduce the latency of the internal path of the destination chip, and save power consumption. Furthermore, since the on-chip network latency of the second chip is lower, the data access latency of the first host on the first chip to the storage unit of the first chip is less affected, resulting in higher efficiency for large-scale computing chips composed of multiple chips. In summary, the first chip can improve the communication performance between chips and meet the needs of high-performance computing.

[0028] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0029] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0030] Figure 1 This diagram illustrates cross-chip access in a prior art on-chip network.

[0031] Figure 2 An exemplary application scenario of the first chip according to an embodiment of this disclosure is shown.

[0032] Figure 3 A schematic diagram showing the structure of a first core according to an embodiment of the present disclosure is provided.

[0033] Figure 4a A schematic diagram of the routing path for a first access request according to an embodiment of this disclosure is shown.

[0034] Figure 4bA schematic diagram of the routing path for a first access request according to an embodiment of this disclosure is shown.

[0035] Figure 5a A schematic diagram of the routing path for a second access request according to an embodiment of this disclosure is shown.

[0036] Figure 5b A schematic diagram of the routing path for a second access request according to an embodiment of this disclosure is shown.

[0037] Figure 6 A schematic diagram of the routing path for a third access request according to an embodiment of this disclosure is shown.

[0038] Figure 7 A schematic diagram showing the structure of a second on-chip network according to an embodiment of the present disclosure is provided.

[0039] Figure 8 A schematic diagram showing the structure of a first core according to an embodiment of the present disclosure is provided.

[0040] Figure 9 A schematic diagram illustrating the flow of the first conversion module according to an embodiment of the present disclosure is shown.

[0041] Figure 10 A schematic diagram illustrating a second physical address according to an embodiment of this disclosure is shown.

[0042] Figure 11 A schematic diagram illustrating the flow of an inter-chip communication method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0043] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0044] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0045] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0046] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0047] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0048] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0049] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0050] Figure 1 This diagram illustrates cross-chip access in a prior art on-chip network.

[0051] like Figure 1 As shown, in the prior art, when the host on the source chip (such as the computing unit mentioned above) needs to access the storage unit on the destination chip, the access path is usually as follows:

[0052] Source Core Internal Path (L1): The host initiating the access request first sends the access request through the Main NoC (MainNoC) inside the source core. The access request goes through multiple levels of routing in the Main NoC before reaching the D2D interface connected to the Main NoC.

[0053] Cross-core transmission path (L2): The access request is transmitted to the D2D interface of the destination core according to a predetermined transmission protocol through the D2D interface of the source core.

[0054] Destination core internal path (L3): After the access request arrives at the D2D interface of the destination core, it is routed to the memory controller (not shown) via the main NoC of the destination core.

[0055] Storage access path (L4): The memory controller routes access requests to off-chip memory (not shown) or on-chip memory.

[0056] Therefore, the total latency for cross-core access in the existing technology is T_total = L1 + L2 + L3 + L4.

[0057] With the increase in computing power and scale of large-scale GPUs or System on Chip (SoC), the bandwidth requirements and number of interfaces of NoCs within the chip also increase. This greatly increases the routing hierarchy and complexity of NoCs within the chip, making the transmission performance of the source chip internal path (L1) and the destination chip internal path (L3) have a greater impact on cross-chip access performance.

[0058] In existing technologies for cross-core access, the D2D interface is used only as an external communication port, while the access request still needs to go through the complete routing path of the main NoC to be routed to the corresponding memory controller. This leads to the following disadvantages:

[0059] 1. High latency of cross-chip access: When an access request is transmitted from the source chip to the destination chip, it still needs to go through multiple levels of routing and arbitration by the main NoC of the destination chip to reach the port connected to the memory controller in the main NoC of the destination chip. That is, the internal path (L3) of the destination chip is long and the access latency is high.

[0060] 2. Path duplication and resource waste: Even if the access to the on-chip storage unit of the destination chip is independent of the host of the destination chip, the access request must go through the main NoC of the destination chip to complete the complete routing and arbitration process, which will increase the power consumption and congestion of the main NoC.

[0061] 3. Inability to meet the low-latency requirements of high-performance computing: For data-intensive computing units such as GPUs, the latency between the computing core and memory is a key factor affecting overall system performance. Traditional cross-core access must pass through the main NoC of two cores, resulting in a long routing path. This makes it difficult to meet the low-latency requirements of Non-Uniform Memory Access (NUMA) in multi-core architectures, thus limiting the performance expansion of multi-core GPUs.

[0062] In view of this, this disclosure proposes a first chip, a first chip, an inter-chip communication method, and an electronic device. The on-chip network of the first chip has a short routing path, low latency, and low power consumption, thereby improving cross-chip access performance and meeting the needs of high-performance computing.

[0063] Figure 2 An exemplary application scenario of the first chip according to an embodiment of this disclosure is shown.

[0064] like Figure 2 As shown, the first chip can be a high-performance GPU or an AI chip. The first chip includes interconnected first and second chips.

[0065] When the second chip acts as the source chip and the first chip acts as the destination chip, the second chip can generate a first access request for a memory cell (not shown) on the first chip. The second chip can transmit the first access request to the first chip, and the first chip, in response to the first access request, returns first response data to the second chip.

[0066] When the first memory chip is the source memory chip and the second memory chip is the destination memory chip, the first memory chip can generate a second access request for a memory cell (not shown) on the second memory chip. The first memory chip can transmit the second access request to the second memory chip, and the second memory chip responds to the second access request by returning second response data to the first memory chip.

[0067] Those skilled in the art will understand that the first chip may include multiple pairs of interconnected chips, and the first chip and the second chip may be any pair of interconnected chips included in the first chip.

[0068] Figure 3 A schematic diagram showing the structure of a first core according to an embodiment of the present disclosure is provided.

[0069] like Figure 3 As shown, in one possible implementation, the first chip includes a first host, a first on-chip network, M second on-chip networks, a communication module, and N storage units, where M and N are positive integers.

[0070] The i-th second on-chip network connects the first on-chip network, the communication module, and the j-th storage unit; i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N.

[0071] The first on-chip network is used for communication between the first host and M second on-chip networks.

[0072] The communication module is used for communication between the first core and the second core.

[0073] The i-th second on-chip network is used for communication between the j-th storage unit and the first on-chip network, as well as communication between the j-th storage unit and the communication module, and communication between the first on-chip network and the communication module.

[0074] For example, the first core may include a first host, which may be a computing unit such as a processor core. In practical applications, the first core may include multiple hosts, each of which can serve as the first host. This disclosure does not limit the number or type of hosts in the first core.

[0075] The first chip may include a first on-chip network for communication between a first host and M second on-chip networks. Each access request generated by the first host may be transmitted via the first on-chip network to one of the M second on-chip networks. Response data for access requests generated by the first host received by the second on-chip networks may be transmitted via the first on-chip network to the first host.

[0076] The first chip may include M second on-chip networks, a communication module, and N memory cells. The i-th second on-chip network connects to the first on-chip network, the communication module, and the j-th memory cell.

[0077] The communication module is used for communication between the first chip and the second chip. It can convert the access request / response data of the first chip into a physical layer-transmittable signal according to a preset protocol (such as Universal Chiplet Interconnect Express (UCIe)) and transmit it to the second chip. The second chip may also include a communication module (not shown). Before using the first chip for cross-chip access, the connection relationship between the communication modules of the first chip and the second chip can be preset, and the communication modules of the first chip and the second chip can be connected according to the preset connection relationship. For example, the communication module on the first chip can be directly connected or connected to the communication module on the second chip through a simplified routing. The embodiments of this disclosure do not limit the specific method by which the communication module of the first chip implements communication between the first chip and the second chip.

[0078] Since the i-th second on-chip network connects the communication module and the j-th storage unit, the i-th second on-chip network can be used for communication between the j-th storage unit and the communication module. Since the i-th second on-chip network connects the first on-chip network and the j-th storage unit, the i-th second on-chip network can be used for communication between the j-th storage unit and the first on-chip network. Since the i-th second on-chip network connects the first on-chip network and the communication module, the i-th second on-chip network can be used for communication between the first on-chip network and the communication module.

[0079] In summary, in the first chip, the first on-chip network is responsible for routing between the host and the first on-chip network, while the second on-chip network is only responsible for routing between the connected storage unit and the first on-chip network, as well as between the connected storage unit and the connected communication module, and between the first on-chip network and the communication module connected to the second on-chip network. Compared with the large-area complete routing of the main NoC in the prior art, the second on-chip network is a small-area local routing, which shortens the routing path, reduces routing complexity, reduces latency, and reduces power consumption.

[0080] In cross-chip access, if the second chip needs to output an access request to a memory cell on the first chip, the access request does not need to pass through the first on-chip network when transmitted on the first chip. It only needs to pass through the second on-chip network connected to the memory cell and the communication module connected to the second on-chip network. For example, when the second chip outputs an access request to the j-th memory cell on the first chip, it only needs to pass through the communication module on the first chip and the i-th second on-chip network to reach the j-th memory cell on the first chip. That is, when the first chip is the destination chip and the second chip is the source chip, compared with the cross-chip access scheme of the prior art, the embodiments of this disclosure can shorten the internal path (L3) of the destination chip and reduce the latency of the internal path of the destination chip. Since the path is shortened, power consumption can be saved.

[0081] Those skilled in the art should understand that the structure of the second core may be the same as or different from that of the first core, and the embodiments disclosed herein do not limit the specific structure of the second core.

[0082] According to an embodiment of this disclosure, the first chip includes a first host, a first on-chip network, M second on-chip networks, a communication module, and N storage units, where M and N are positive integers. The i-th second on-chip network connects the first on-chip network, the communication module, and the j-th storage unit; i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N. The first on-chip network is used for communication between the first host and the M second on-chip networks. The communication module is used for communication between the first chip and the second chips. The i-th second on-chip network is used for communication between the j-th storage unit and the first on-chip network, as well as communication between the j-th storage unit and the communication module, and communication between the first on-chip network and the communication module. In the first chip, the first on-chip network handles the routing between the host and the first on-chip network, while the second on-chip networks are only responsible for routing between the connected storage units, the first on-chip network, and the communication module. Compared to the complete routing of the main NoC in the prior art, the second on-chip network provides local routing, resulting in shorter routing paths, reduced routing complexity, lower latency, and lower power consumption. In cross-chip access, when the first chip is used as the destination chip and the second chip as the source chip, compared with existing cross-chip access schemes, the embodiments of this disclosure can shorten the internal path of the destination chip, reduce the latency of the internal path of the destination chip, and save power consumption. Furthermore, since the latency of the second on-chip network is lower, the data access latency of the first host on the first chip to the memory unit of the first chip is less affected, resulting in higher efficiency for large-scale computing chips composed of multiple chips. In summary, the first chip can improve the communication performance between chips and meet the needs of high-performance computing. When the first chip is applied to a multi-chip chip, it significantly optimizes the latency performance of communication paths (especially cross-chip memory access paths) while maintaining high bandwidth and high interconnectivity of the on-chip network.

[0083] The following section uses the transmission of access requests as an example to describe the communication process of the first core in a cross-core access scenario, as well as the communication process of the first core in a local access scenario. The transmission of response data is a mirror image of the transmission of access requests, and will not be described again in this embodiment.

[0084] The following describes the transmission method of the access request on the first core when the first core is used as the target core in the cross-core access scenario.

[0085] In one possible implementation, the communication module is used to output the first access request for the j-th storage unit generated by the second host on the second chip to the i-th second on-chip network.

[0086] The i-th second on-chip network is used to output the first access request to the j-th storage unit.

[0087] For example, the second core may include a second host. The second host may be a computing unit such as a processor core. In practical applications, the second core may include multiple hosts, each of which can serve as a second host. This disclosure does not limit the number or type of hosts in the second core.

[0088] In a cross-chip access scenario, a second host can generate a first access request for the j-th storage unit on the first chip. In one example, the connection relationships between the second on-chip network, communication module, and storage unit on the first chip are known to the second chip. Therefore, after the second chip determines that the second host has generated a first access request for the j-th storage unit on the first chip, it can determine, based on the connection relationships between the second on-chip network, communication module, and storage unit on the first chip, that the i-th second on-chip network on the first chip is used for communication between the j-th storage unit and the communication module, and output the first access request to the communication module on the first chip.

[0089] On the first chip, when the communication module receives an access request, it can arbitrate which second on-chip network to output the access request to. For example, if the first access request is for the j-th memory cell, the arbitrated second on-chip network can be the i-th second on-chip network. Based on this, the communication module can output the first access request to the i-th second on-chip network. The i-th second on-chip network is responsible for outputting the first access request to the j-th memory cell.

[0090] In one example, the first access request output by the second chip can directly carry the identifiers of the i-th second on-chip network and the j-th memory cell. The communication module arbitrates based on the identifiers carried in the first access request, and the i-th second on-chip network can directly output the first access request to the j-th memory cell based on the identifiers carried in the first access request.

[0091] Figure 4a A schematic diagram of the routing path for a first access request according to an embodiment of this disclosure is shown.

[0092] like Figure 4a As shown, for the first access request, the cross-chip transmission path (L2) is from the communication module of the second chip (not shown) to the communication module of the first chip. The destination chip intra-path (L3) is from the communication module of the first chip to the i-th second on-chip network. The storage access path (L4) is from the i-th second on-chip network to the j-th storage cell. It can be seen that the destination chip intra-path (L3) is significantly shortened.

[0093] In this way, when the first core is used as the target core in a cross-core access scenario, the access request can be transmitted quickly on the first core.

[0094] In one possible implementation, the communication module includes M communication units, with the i-th second on-chip network connected to the i-th communication unit. The i-th communication unit is used to output the first access request for the j-th storage unit generated by the second host on the second chip to the i-th second on-chip network.

[0095] Figure 4b A schematic diagram of the routing path for a first access request according to an embodiment of this disclosure is shown.

[0096] like Figure 4b As shown, the communication module on the first chip can be further divided into M communication units, so that the i-th second on-chip network is connected to the i-th communication unit. Each communication unit can be a D2D interface or an interface using other communication protocols, and this embodiment of the present disclosure is not limited thereto. At this time, the i-th second on-chip network is used for communication between the j-th storage unit and the first on-chip network, as well as communication between the j-th storage unit and the i-th communication unit, and communication between the first on-chip network and the i-th communication unit.

[0097] In one example, the connections between the second on-chip network, communication unit, and storage unit on the first chip are known to the second chip. After the second chip determines that the second host generates a first access request for the j-th storage unit on the first chip, it can determine, based on the connections between the second on-chip network, communication unit, and storage unit on the first chip, that the i-th second on-chip network on the first chip is used for communication between the j-th storage unit and the i-th communication unit, and output the first access request to the i-th communication unit on the first chip. The i-th communication unit does not need to determine which second on-chip network the first access request should be output to; it directly outputs the first access request to the i-th second on-chip network.

[0098] This method eliminates the arbitration step of the communication module, further reducing the routing complexity and latency of the first access request on the first chip, and improving routing efficiency.

[0099] The following describes the transmission method of the access request on the first core when the first core is used as the source core and the second core is used as the target core in the cross-core access scenario.

[0100] In one possible implementation, the communication module on the first chip is connected to the communication module on the second chip, and the communication module on the second chip and the q-th storage unit on the second chip are connected to the p-th second on-chip network on the second chip, where p and q are positive integers.

[0101] The first on-chip network is used to output the second access request to the i-th second on-chip network when the first host generates a second access request for the q-th storage unit.

[0102] The i-th second on-chip network is used to output the second access request to the communication module on the first chip;

[0103] The communication module on the first core is used to output the second access request to the communication module on the second core.

[0104] The second access request is output to the qth memory cell via the communication module on the second chip and the p-th second on-chip network.

[0105] Figure 5a A schematic diagram of the routing path for a second access request according to an embodiment of this disclosure is shown.

[0106] For example, the structure of the second chip can be the same as that of the first chip. The second chip may include a second host, a first on-chip network, W second on-chip networks, a communication module, and N storage units. Figure 5a As shown, on the second chip, the p-th second on-chip network connects to the first on-chip network, the communication module, and the q-th memory unit. The communication module on the first chip can be connected to the communication module on the second chip.

[0107] In a cross-chip access scenario, a first host can generate a second access request to the q-th storage unit on a second chip. In one example, the connection relationships between the second on-chip network, communication module, and storage unit on the second chip are known to the first chip. Therefore, after the first chip determines that the first host has generated a second access request to the q-th storage unit on the second chip, it can determine, based on the connection relationships between the second on-chip network, communication module, and storage unit on the second chip, that the p-th second on-chip network on the second chip is used for communication between the q-th storage unit and the communication module. Since the communication module on the second chip is connected to the communication module on the first chip, and the communication module on the first chip is connected to the i-th second on-chip network on the first chip, the routing path for the second access request is: first host (first chip), first on-chip network (first chip), i-th second on-chip network (first chip), communication module (first chip), communication module (second chip), p-th second on-chip network (second chip), q-th storage unit (second chip).

[0108] Therefore, on the first chip, the first on-chip network is used to output the second access request to the i-th second on-chip network on the first chip when the first host generates a second access request for the q-th memory cell. The i-th second on-chip network on the first chip is used to output the second access request to the communication module on the first chip. The communication module on the first chip is used to output the second access request to the communication module on the second chip. On the second chip, the second access request is output to the q-th memory cell via the communication module and the p-th second on-chip network.

[0109] When the communication module on the second chip receives an access request, it can arbitrate which second on-chip network to output the access request to. For example, if the second access request is for the q-th memory cell on the second chip, the arbitrated second on-chip network can be the p-th second on-chip network. Based on this, the communication module on the second chip can output the second access request to the p-th second on-chip network. The p-th second on-chip network is responsible for outputting the second access request to the q-th memory cell.

[0110] In one example, the second access request can directly carry the identifiers of the p-th second on-chip network and the q-th memory cell. The communication module on the second chip performs arbitration based on the identifiers carried in the second access request, and the p-th second on-chip network can directly output the second access request to the q-th memory cell based on the identifiers carried in the second access request.

[0111] For the second access request, the source chip's internal path (L1) is from the first host to the communication module. The cross-chip transmission path (L2) is from the communication module of the first chip to the communication module of the second chip. The destination chip's internal path (L3) is from the communication module of the second chip to the p-th second on-chip network. The storage access path (L4) is from the p-th second on-chip network to the q-th storage unit. It can be seen that the destination chip's internal path (L3) is significantly shortened.

[0112] In one example, the first on-chip network can parse the second physical address carried in the received second access request to obtain the routing information of the second access request. Based on the routing information, the first on-chip network can directly output the second access request to the i-th second on-chip network. Examples of the second physical address and the parsing of the second physical address are given later.

[0113] In this way, when the first core is used as the source core in a cross-core access scenario, the access request can be transmitted quickly in the second core.

[0114] In one possible implementation, the communication module on the first chip includes M communication units, the i-th second on-chip network connects to the i-th communication unit, and the communication module on the second chip includes W communication units, where W is an integer greater than or equal to p.

[0115] The i-th communication unit is connected to the p-th communication unit on the second chip, and the p-th communication unit on the second chip and the q-th storage unit on the second chip are connected to the p-th second on-chip network on the second chip, where p and q are positive integers;

[0116] The i-th second on-chip network is used to output the second access request to the i-th communication unit;

[0117] The i-th communication unit is used to output the second access request to the p-th communication unit;

[0118] On the second chip, the second access request is output to the q-th memory cell via the p-th communication unit and the p-th second on-chip network.

[0119] Figure 5b A schematic diagram of the routing path for a second access request according to an embodiment of this disclosure is shown.

[0120] like Figure 5b As shown, the communication module on the first chip can be further divided into M communication units, so that the i-th second on-chip network is connected to the i-th communication unit. At this time, on the first chip, the i-th second on-chip network is used for communication between the j-th storage unit and the first on-chip network, as well as communication between the j-th storage unit and the i-th communication unit, and communication between the first on-chip network and the i-th communication unit.

[0121] The second chip includes W second on-chip networks, which can further divide the communication modules on the second chip into W communication units, such that the p-th second on-chip network is connected to the p-th communication unit. In this case, the p-th second on-chip network on the second chip is used for communication between the q-th storage unit and the first on-chip network, as well as communication between the q-th storage unit and the p-th communication unit, and communication between the first on-chip network and the p-th communication unit.

[0122] The i-th communication unit of the first core is connected to the q-th communication unit of the second core. Each communication unit can be a D2D interface or an interface using other communication protocols, and this disclosure does not limit this.

[0123] In one example, the connections between the second on-chip network, communication unit, and storage unit on the first chip are known to the second chip. After the first chip determines that the first host generates a second access request for the q-th storage unit on the second chip, it can determine, based on the connections between the second on-chip network, communication unit, and storage unit on the second chip, that the p-th second on-chip network on the second chip is used for communication between the q-th storage unit and the p-th communication unit. Since the p-th communication unit on the second chip is connected to the i-th communication unit on the first chip, and the i-th communication unit on the first chip is connected to the i-th second on-chip network on the first chip, the routing path for the second access request is: first host (first chip), first on-chip network (first chip), i-th second on-chip network (first chip), i-th communication unit (first chip), p-th communication unit (second chip), p-th second on-chip network (second chip), q-th storage unit (second chip).

[0124] Therefore, on the first chip, the first on-chip network is used to output the second access request to the i-th second on-chip network on the first chip when the first host generates a second access request for the q-th memory unit. The i-th second on-chip network on the first chip is used to output the second access request to the i-th communication unit on the first chip. The i-th communication unit on the first chip is used to output the second access request to p communication units on the second chip. On the second chip, the second access request is output to the q-th memory unit via the p-th communication unit and the p-th second on-chip network.

[0125] This method eliminates the arbitration step of the communication module on the second core, further reducing the routing complexity and latency of the second access request on the second core, and improving routing efficiency.

[0126] As described above, the first chip may include M second on-chip networks and N storage units. The communication module may include M communication units, with the i-th second on-chip network connected to the i-th communication unit. Assuming M=N and i=j, then the M communication units are bound one-to-one with the N storage units, and the i-th communication unit is bound to the j-th storage unit. In this case, regardless of which storage unit the first access request wants to access on the first chip, the routing path for the first access request on the first chip is the shortest. If the application scenario requires maximizing routing efficiency, this configuration of the first chip can be chosen.

[0127] The above describes the transmission method of access requests on the first core in different cross-core access scenarios where the source and destination cores are the same core. The following describes the transmission method of access requests on the core in local access scenarios where the source and destination cores are the same core.

[0128] In one possible implementation, the first on-chip network is used to output the third access request to the i-th second on-chip network when the first host generates a third access request for the j-th memory unit.

[0129] The i-th second on-chip network is used to output the third access request to the j-th storage unit.

[0130] For example, in a local access scenario, the first host can generate a third access request for the j-th storage unit on the first chip. In one example, the connection relationships between the second on-chip network, communication module, and storage unit on the first chip are known to the first chip. Therefore, after the first chip determines that the first host has generated a third access request for the j-th storage unit on the first chip, it can determine, based on the connection relationships between the second on-chip network, communication module, and storage unit on the first chip, that the i-th second on-chip network on the first chip is used for communication between the j-th storage unit and the first on-chip network, and output the third access request to the i-th second on-chip network through the first on-chip network.

[0131] The i-th second-on-chip network is responsible for outputting the third access request to the j-th storage unit. In one example, the third access request received by the i-th second-on-chip network can directly carry the identifier of the j-th storage unit, and the i-th second-on-chip network can directly output the third access request to the j-th storage unit based on the identifier carried in the third access request.

[0132] Figure 6 A schematic diagram of the routing path for a third access request according to an embodiment of this disclosure is shown.

[0133] like Figure 6As shown, for the third access request, the source chip internal path (L1) is from the first host to the i-th second on-chip network. The storage access path (L4) is from the i-th second on-chip network to the j-th storage unit.

[0134] In this way, access requests generated by the first host of the first chip in a local access scenario can be quickly transmitted to the storage unit to be accessed within the first chip.

[0135] Figure 7 A schematic diagram showing the structure of a second on-chip network according to an embodiment of the present disclosure is provided.

[0136] like Figure 7 As shown, in one possible implementation, the i-th second on-chip network includes:

[0137] The first interface is used to connect to the first on-chip network;

[0138] The second interface is used to connect to the j-th storage unit;

[0139] The third and fourth interfaces are used to connect the communication module. The third interface is used for uplink transmission, and the fourth interface is used for downlink transmission.

[0140] The routing module is used for interconnection between the first interface, the second interface, the third interface, and the fourth interface.

[0141] In this scenario, communication between the first on-chip network and the j-th storage unit can be achieved through the first and second interfaces in a local access scenario; communication between the first on-chip network and the communication module can be achieved through the first, third, and fourth interfaces in a cross-chip access scenario; and communication between the j-th storage unit and the communication module can be achieved through the second, third, and fourth interfaces in a cross-chip access scenario.

[0142] Furthermore, when the communication module includes multiple communication units and the i-th second on-chip network is connected to the i-th communication unit, the third interface and the fourth interface can be used to connect the i-th communication unit in the communication module.

[0143] Since the second chip-on-network has only four interfaces, its routing complexity is very low, the routing path is short, and low-latency data transmission can be performed within the second chip-on-network.

[0144] It should be understood that the more second on-chip networks (NICs) on the first chip, the greater the area overhead of the first chip. The more storage units a single second on-chip network connects, the longer the routing path and the higher the latency. Therefore, while meeting application requirements in terms of latency, the second on-chip network can connect to more storage units to reduce the number of second on-chip networks on the first chip, thus saving area costs. In this case, the i-th second on-chip network may include multiple second interfaces for connecting to multiple storage units respectively. This disclosure does not limit the number of storage units connected to each second on-chip network or the number of interfaces it includes.

[0145] The embodiments disclosed herein do not impose any restrictions on the structure of the second on-chip network, as long as the i-th second on-chip network can enable communication between the j-th storage unit and the first on-chip network, as well as communication between the j-th storage unit and the communication module.

[0146] Figure 8 A schematic diagram showing the structure of a first core according to an embodiment of the present disclosure is provided.

[0147] like Figure 8 As shown, in one possible implementation,

[0148] The first chip also includes a first conversion module, which is connected between the first host and the first on-chip network.

[0149] The first on-chip network includes M fifth interfaces, and the i-th fifth interface is connected to the i-th second on-chip network;

[0150] The first conversion module is used to convert the first physical address carried in the access request generated by the first host into a second physical address that can be recognized by the first on-chip network, and then output the access request to the first on-chip network; the second physical address includes the identifier of the storage unit corresponding to the first physical address;

[0151] The first on-chip network is used to identify the fifth interface corresponding to the access request among M fifth interfaces by recognizing the second physical address, and to output the access request through the determined fifth interface.

[0152] For example, the first chip also includes a first conversion module connected between the first host and the first on-chip network.

[0153] The first on-chip network includes M fifth interfaces, with the i-th fifth interface connecting to the i-th second on-chip network. Correspondingly, the first on-chip network may also include an IP interface for connecting to the first host. This disclosure does not limit the specific structure of the first on-chip network. It is acceptable as long as the first on-chip network enables communication between the first host and the M second on-chip networks.

[0154] The first conversion module is used to convert the first physical address carried in the access request generated by the first host into a second physical address, and then output the access request to the first on-chip network.

[0155] Figure 9 A schematic diagram illustrating the flow of the first conversion module according to an embodiment of the present disclosure is shown.

[0156] like Figure 9 As shown, the access request generated by the host carries a first physical address. After receiving the access request, the first conversion module performs interleaving, hashing and other existing technology algorithms on the first physical address to convert it into a second physical address that can be recognized by the first on-chip network.

[0157] The second physical address includes at least the identifier of the memory cell corresponding to the first physical address. In one example, the communication path between the second on-chip network and the memory cell is known to the first on-chip network. Furthermore, the first on-chip network knows that its i-th fifth interface connects to the i-th second on-chip network of its respective chip. In this case, the first on-chip network can determine the fifth interface to which the access request should be routed based on the identifier of the memory cell included in the second physical address, and output the access request to the second on-chip network through the determined fifth interface.

[0158] For example, if the first on-chip network on the first chip identifies that the second physical address includes the identifier of storage unit 1 on the first chip, and the first on-chip network on the first chip knows that storage unit 1 is connected to the first second on-chip network on the first chip, then the first on-chip network can determine that the access request should be routed to the first fifth interface.

[0159] For example, if the first on-chip network on the first chip identifies that the second physical address includes the identifier of the storage unit 2 on the second chip, and the first on-chip network on the first chip knows that the storage unit 2 is connected to the first second on-chip network on the first chip through the storage module of the second chip and the storage module of the first chip, then the first on-chip network can determine that the access request should be routed to the first fifth interface.

[0160] In this embodiment, the first conversion module supports configurable address translation modes. During power-on initialization of the first chip, different configuration modes are used depending on the chip's form factor. For example, the first chip can be configured as an independent chip mode or a multi-chip interconnect mode. The configuration mode settings can be implemented based on existing technologies and will not be elaborated here. In each mode, the storage units of the chip can be accessed by the host on the chip. That is, in independent chip mode, there is a routing path from the host of this chip to the storage unit of this chip; in multi-chip interconnect mode, there is a routing path from the host of this chip to the storage unit of a remote chip.

[0161] In one possible implementation, the communication module on the first chip includes M communication units, and the i-th on-chip network of the second chip connects to the i-th communication unit.

[0162] When the first physical address corresponds to a storage cell on the second chip, the second physical address also includes the identifier of the communication cell on the first chip used to transmit access requests;

[0163] The first on-chip network is used to determine that the access request corresponds to the i-th fifth interface when it is recognized that the second physical address includes the identifier of the j-th storage unit or the identifier of the i-th communication unit.

[0164] As described above, the communication module on the first chip includes M communication units, and the i-th second on-chip network connects to the i-th communication unit. Furthermore, when the first physical address corresponds to a storage unit on the second chip, the second physical address also includes the identifier of the communication unit on the first chip used to transmit the access request.

[0165] In this case, the first on-chip network only needs to know the connection path between the memory cell on its own chip, the second on-chip network, and the communication unit to complete the transmission of the access request.

[0166] For example, if the first on-chip network on the first chip identifies that the second physical address includes the identifier of storage unit 1 on the first chip, and the first on-chip network on the first chip knows that storage unit 1 is connected to the first second on-chip network on the first chip, then the first on-chip network can determine that the access request should be routed to the first fifth interface.

[0167] For example, if the first on-chip network on the first chip identifies that the second physical address includes the identifier of communication unit 1 on the second chip, and the first on-chip network on the first chip knows that communication unit 1 is connected to the first second on-chip network on the first chip, then the first on-chip network can determine that the access request should be routed to the first fifth interface.

[0168] Figure 10 A schematic diagram illustrating a second physical address according to an embodiment of this disclosure is shown.

[0169] like Figure 10 As shown, the second physical address may include three address segments, where the first address segment is the identifier of the communication unit, the second address segment is the identifier of the storage unit, and the third address segment is the address offset within the storage unit.

[0170] Assume that the physical address of the memory cell on the first chip is greater than 0xf00000000, and the physical address of the memory cell on the second chip is less than 0xf00000000.

[0171] Suppose that access request 1 generated by the first host carries a physical address of 0x000000180. After conversion using existing algorithms such as interleaving and hashing, it becomes 0xf00000080. Since 0xf00000080 is greater than 0xf00000000, it indicates that the access request should be sent to a storage unit on the first chip. The access request is not transmitted through the communication unit; therefore, the second physical address only needs to carry the identifier of the target storage unit, not the identifier of the communication unit. An invalid identifier F can be filled into the first address segment. In one example, each storage unit on the first chip corresponds to an address segment, and 0xf00000080 can only fall within one address segment. Therefore, when 0xf00000080 falls into the address segment corresponding to the j-th storage unit, the target storage unit is the j-th storage unit, and the identifier j of the j-th storage unit can be filled into the second address segment. The offset (e.g., x1) between 0xf00000080 and the starting address of the address segment corresponding to the j-th storage unit can be filled into the third address segment. At this point, the second physical address can be obtained.

[0172] Suppose that access request 2 generated by the first host carries a physical address of 0x000000280. After conversion using existing algorithms such as interleaving and hashing, it becomes 0x000000080. Since 0x000000080 is less than 0xf00000000, this indicates that the access request should be sent to a storage unit on the second chip. The access request is transmitted through a communication unit; therefore, the second physical address needs to carry the identifier of the target storage unit and the identifier of the communication unit traversed on the first chip. In one example, each storage unit on the second chip corresponds to an address segment, and 0x000000080 can only fall within one address segment. Therefore, when 0x000000080 falls within the address segment corresponding to the q-th storage unit, the target storage unit is the q-th storage unit, and the identifier q of the q-th storage unit can be filled into the second address segment. The routing path from the first chip to the q-th memory cell of the second chip is: the i-th second on-chip network (first chip), the i-th communication unit (first chip), the p-th communication unit (second chip), the p-th second on-chip network (second chip), and the q-th memory cell (second chip). The identifier i of the i-th communication unit can be filled into the first address segment. The offset (e.g., x2) between 0x000000080 and the starting address of the address segment corresponding to the q-th memory cell can be filled into the third address segment. At this point, the second physical address can be obtained.

[0173] In one example, the IP interface of the first on-chip network may include a protocol conversion layer for converting the protocol of the access request sent by the first host (such as the AXI protocol) into the transport protocol internal to the first on-chip network. Here, the protocol conversion layer will parse the on-chip network's internal routing information (slave_id) based on the first physical address. The parsed routing information can be implemented based on existing technology, which will not be elaborated here. In this embodiment of the disclosure, since the first chip may have a large number of hosts and storage units, the first on-chip network will have multi-level routing nodes. There is a correspondence between slave_id and the fifth interface. After obtaining the slave_id, the first on-chip network can send the access request to the corresponding fifth interface according to the slave_id.

[0174] In one possible implementation, the i-th second on-chip network is configured to output the received access request to the j-th storage unit when the second physical address in the received access request includes the identifier of the j-th storage unit; and to output the received access request to the i-th communication unit when the second physical address in the received access request includes the identifier of the i-th communication unit.

[0175] As mentioned above, the first conversion module has added the identifier of the communication unit to the second physical address. Therefore, for the second on-chip network, when the second physical address in the received access request includes the identifier of the i-th communication unit, no additional judgment is required, and the received access request can be directly output to the i-th communication unit.

[0176] This embodiment of the disclosure designs a matching routing method for the first on-chip network based on the routing method of the second on-chip network, enabling the first on-chip network to send access requests to a corresponding fifth interface. The fifth interface can access either a storage unit within the current chip or a corresponding storage unit in a remote chip. Matching address translation logic is designed based on the routing methods of the first and second on-chip networks, allowing the first on-chip network to route access requests to a specific fifth interface based on the translated second physical address. This reduces the routing complexity of access requests.

[0177] This disclosure does not limit the specific content of the routing information, as long as the routing information can indicate the above content.

[0178] In this way, the efficiency of the first on-chip network can be improved.

[0179] This disclosure also proposes an inter-chip communication method. Figure 11 A schematic diagram illustrating the flow of an inter-chip communication method according to an embodiment of the present disclosure is shown.

[0180] like Figure 11As shown, in one possible implementation, the method is applied to a first chip, which includes a first host, a first on-chip network, M second on-chip networks, a communication module, and N storage units, where M and N are positive integers; the i-th second on-chip network connects the first on-chip network, the communication module, and the j-th storage unit; i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N;

[0181] The method includes:

[0182] Step S11: Use the first on-chip network to realize communication between the first host and M second on-chip networks;

[0183] Step S21: Use a communication module to realize communication between the first core and the second core;

[0184] Step S31: Use the i-th second on-chip network to realize communication between the j-th storage unit and the first on-chip network, as well as communication between the j-th storage unit and the communication module, and communication between the first on-chip network and the communication module.

[0185] In one possible implementation, the method further includes: using the communication module to output a first access request for the j-th storage unit generated by a second host on the second chip to the i-th second on-chip network; the step of using the i-th second on-chip network to realize communication between the j-th storage unit and the first on-chip network, communication between the j-th storage unit and the communication module, and communication between the first on-chip network and the communication module includes: using the i-th second on-chip network to output the first access request to the j-th storage unit.

[0186] In one possible implementation, the communication module includes M communication units, the i-th second on-chip network is connected to the i-th communication unit, and the step of using the communication module to output the first access request for the j-th storage unit generated by the second host on the second chip to the i-th second on-chip network includes: using the i-th communication unit to output the first access request for the j-th storage unit generated by the second host on the second chip to the i-th second on-chip network.

[0187] In one possible implementation, the communication module on the first chip is connected to the communication module on the second chip, and the communication module on the second chip and the q-th storage unit on the second chip are connected to the p-th second on-chip network on the second chip, where p and q are positive integers; the step of using the first on-chip network to implement communication between the first host and the M second on-chip networks includes: using the first on-chip network, when the first host generates a second access request for the q-th storage unit, outputting the second access request to the i-th second on-chip network; the step of using the i-th second on-chip network to implement communication between the j-th storage unit and the first host includes: using the first on-chip network, when the first host generates a second access request for the q-th storage unit, outputting the second access request to the i-th second on-chip network; The communication between the unit and the first on-chip network, the communication between the j-th storage unit and the communication module, and the communication between the first on-chip network and the communication module include: using the i-th second on-chip network to output the second access request to the communication module on the first chip; the communication module is used to realize the communication between the first chip and the second chip, which includes: using the communication module on the first chip to output the second access request to the communication module on the second chip; the second access request is output to the q-th storage unit via the communication module on the second chip and the p-th second on-chip network.

[0188] In one possible implementation, the communication module on the first chip includes M communication units, the i-th second on-chip network is connected to the i-th communication unit, the communication module on the second chip includes W communication units, where W is an integer greater than or equal to p; the i-th communication unit is connected to the p-th communication unit on the second chip, the p-th communication unit on the second chip and the q-th storage unit on the second chip are connected to the p-th second on-chip network on the second chip, where p and q are positive integers; the step of using the i-th second on-chip network to output the second access request to the communication module on the first chip includes: using the i-th second on-chip network to output the second access request to the i-th communication unit; the step of using the communication module on the first chip to output the second access request to the communication module on the second chip includes: using the i-th communication unit to output the second access request to the p-th communication unit; on the second chip, the second access request is output to the q-th storage unit via the p-th communication unit and the p-th second on-chip network.

[0189] In one possible implementation, the step of using the first on-chip network to implement communication between the first host and the M second on-chip networks includes: using the first on-chip network, when the first host generates a third access request for the j-th storage unit, outputting the third access request to the i-th second on-chip network; the step of using the i-th second on-chip network to implement communication between the j-th storage unit and the first on-chip network, as well as communication between the j-th storage unit and the communication module, and communication between the first on-chip network and the communication module includes: using the i-th second on-chip network to output the third access request to the j-th storage unit.

[0190] In one possible implementation, the i-th second on-chip network includes: a first interface for connecting to the first on-chip network; a second interface for connecting to the j-th storage unit; a third interface and a fourth interface for connecting to the communication module, wherein the third interface is used for uplink transmission and the fourth interface is used for downlink transmission; and a routing module for interconnecting the first interface, the second interface, the third interface, and the fourth interface.

[0191] In one possible implementation, the first chip further includes a first conversion module connected between the first host and the first on-chip network; the first on-chip network includes M fifth interfaces, the i-th fifth interface being connected to the i-th second on-chip network; the method further includes: the first conversion module converting a first physical address carried in an access request generated by the first host into a second physical address recognizable by the first on-chip network, and then outputting the access request to the first on-chip network; the second physical address includes an identifier of the storage unit corresponding to the first physical address; using the first on-chip network to realize communication between the first host and the M second on-chip networks includes: the first on-chip network determining a fifth interface among the M fifth interfaces corresponding to the access request by recognizing the second physical address, and outputting the access request through the determined fifth interface.

[0192] In one possible implementation, the communication module on the first chip includes M communication units, and the i-th second on-chip network is connected to the i-th communication unit. When the first physical address corresponds to a storage unit on the second chip, the second physical address also includes the identifier of the communication unit on the first chip used to transmit the access request. The first on-chip network determines one of the M fifth interfaces corresponding to the access request by identifying the second physical address, including: when the first on-chip network identifies that the second physical address includes the identifier of the j-th storage unit or the identifier of the i-th communication unit, it determines that the access request corresponds to the i-th fifth interface.

[0193] In one possible implementation, the communication between the j-th storage unit and the first on-chip network, the communication between the j-th storage unit and the communication module, and the communication between the first on-chip network and the communication module are implemented using the i-th second on-chip network, including: when the second physical address in the received access request includes the identifier of the j-th storage unit, the received access request is output to the j-th storage unit; when the second physical address in the received access request includes the identifier of the i-th communication unit, the received access request is output to the i-th communication unit.

[0194] This disclosure also proposes a first chip, including the first chip and the second chip described above. Examples of the type and structure of the first chip can be found in [reference needed]. Figure 2 The relevant description is as follows. The structure of the second chip can be the same as that of the first chip, or it can use the structure of existing technology. The embodiments of this disclosure do not limit the specific structure of the second chip in the first chip.

[0195] This disclosure also proposes an electronic device including the first chip described above. The electronic device may be a terminal device or a server; this disclosure does not limit the specific type of electronic device.

[0196] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0197] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A first core element, characterized in that, The first chip includes a first host, a first on-chip network, M second on-chip networks, a communication module, and N storage units, where M and N are positive integers; the i-th second on-chip network connects the first on-chip network, the communication module, and the j-th storage unit; i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N; The first on-chip network is used for communication between the first host and the M second on-chip networks; The communication module is used for communication between the first core and the second core; The i-th second on-chip network is used for communication between the j-th storage unit and the first on-chip network, communication between the j-th storage unit and the communication module, and communication between the first on-chip network and the communication module.

2. The first core according to claim 1, characterized in that, The communication module is used to output the first access request for the j-th storage unit generated by the second host on the second chip to the i-th second on-chip network; The i-th second on-chip network is used to output the first access request to the j-th storage unit.

3. The first core particle according to claim 2, characterized in that, The communication module includes M communication units, and the i-th second on-chip network is connected to the i-th communication unit. The i-th communication unit is used to output the first access request for the j-th storage unit generated by the second host on the second chip to the i-th second on-chip network.

4. The first core according to claim 1, characterized in that, The communication module on the first chip is connected to the communication module on the second chip, and the communication module on the second chip and the qth memory unit on the second chip are connected to the pth second on-chip network on the second chip, where p and q are positive integers. The first on-chip network is used to output the second access request to the i-th second on-chip network when the first host generates a second access request for the q-th storage unit; The i-th second on-chip network is used to output the second access request to the communication module on the first chip; The communication module on the first core is used to output the second access request to the communication module on the second core; The second access request is output to the qth storage unit via the communication module on the second chip and the p-th second on-chip network.

5. The first core according to claim 4, characterized in that, The communication module on the first chip includes M communication units, and the i-th second on-chip network is connected to the i-th communication unit. The communication module on the second chip includes W communication units, where W is an integer greater than or equal to p. The i-th communication unit is connected to the p-th communication unit on the second chip, and the p-th communication unit and the q-th storage unit on the second chip are connected to the p-th second on-chip network on the second chip, where p and q are positive integers; The i-th second on-chip network is used to output the second access request to the i-th communication unit; The i-th communication unit is used to output the second access request to the p-th communication unit; On the second chip, the second access request is output to the q-th storage unit via the p-th communication unit and the p-th second on-chip network.

6. The first core according to claim 1, characterized in that, The first on-chip network is used to output the third access request to the i-th second on-chip network when the first host generates a third access request for the j-th storage unit; The i-th second on-chip network is used to output the third access request to the j-th storage unit.

7. The first core according to claim 1, characterized in that, The i-th second on-chip network includes: The first interface is used to connect to the first on-chip network; The second interface is used to connect to the j-th storage unit; The third interface and the fourth interface are used to connect the communication module. The third interface is used for uplink transmission, and the fourth interface is used for downlink transmission. The routing module is used for interconnection between the first interface, the second interface, the third interface, and the fourth interface.

8. The first core according to claim 1, characterized in that, The first chip also includes a first conversion module, which is connected between the first host and the first on-chip network; The first on-chip network includes M fifth interfaces, and the i-th fifth interface is connected to the i-th second on-chip network; The first conversion module is used to convert the first physical address carried in the access request generated by the first host into a second physical address that can be recognized by the first on-chip network, and then output the access request to the first on-chip network; the second physical address includes the identifier of the storage unit corresponding to the first physical address; The first on-chip network is used to identify one of the M fifth interfaces corresponding to the access request by recognizing the second physical address, and to output the access request through the determined fifth interface.

9. The first core according to claim 8, characterized in that, The communication module on the first chip includes M communication units, and the i-th on-chip network is connected to the i-th communication unit. When the first physical address corresponds to a storage cell on the second chip, the second physical address also includes an identifier of a communication cell on the first chip used to transmit the access request; The first on-chip network is used to determine that the access request corresponds to the i-th fifth interface when it is recognized that the second physical address includes the identifier of the j-th storage unit or the identifier of the i-th communication unit.

10. The first core according to claim 9, characterized in that, The i-th second on-chip network is used for, When the second physical address in the received access request includes the identifier of the j-th storage unit, the received access request is output to the j-th storage unit; When the second physical address in the received access request includes the identifier of the i-th communication unit, the received access request is output to the i-th communication unit.

11. A first chip, characterized in that, It includes the first core and the second core as described in any one of claims 1-10.

12. An electronic device, characterized in that, Includes the first chip as described in claim 11.

13. A chip-to-chip communication method, characterized in that, The method is applied to a first chip, which includes a first host, a first on-chip network, M second on-chip networks, a communication module, and N storage units, where M and N are positive integers; the i-th second on-chip network connects the first on-chip network, the communication module, and the j-th storage unit. i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N; the method includes: The first on-chip network is used to realize communication between the first host and the M second on-chip networks; The communication module is used to realize communication between the first core and the second core. The i-th second on-chip network is used to realize communication between the j-th storage unit and the first on-chip network, communication between the j-th storage unit and the communication module, and communication between the first on-chip network and the communication module.

14. The method according to claim 13, characterized in that, The method further includes: using the communication module to output the first access request for the j-th storage unit generated by the second host on the second chip to the i-th second on-chip network; The method of using the i-th second on-chip network to realize communication between the j-th storage unit and the first on-chip network, communication between the j-th storage unit and the communication module, and communication between the first on-chip network and the communication module includes: using the i-th second on-chip network to output the first access request to the j-th storage unit.

15. The method according to claim 14, characterized in that, The communication module includes M communication units, and the i-th second on-chip network is connected to the i-th communication unit. The step of using the communication module to output the first access request for the j-th storage unit generated by the second host on the second chip to the i-th second on-chip network includes: using the i-th communication unit to output the first access request for the j-th storage unit generated by the second host on the second chip to the i-th second on-chip network.

16. The method according to claim 13, characterized in that, The communication module on the first chip is connected to the communication module on the second chip, and the communication module on the second chip and the qth memory unit on the second chip are connected to the pth second on-chip network on the second chip, where p and q are positive integers. The method of using the first on-chip network to realize communication between the first host and the M second on-chip networks includes: using the first on-chip network, when the first host generates a second access request for the q-th storage unit, outputting the second access request to the i-th second on-chip network; The method of using the i-th second on-chip network to realize communication between the j-th storage unit and the first on-chip network, communication between the j-th storage unit and the communication module, and communication between the first on-chip network and the communication module includes: using the i-th second on-chip network to output the second access request to the communication module on the first chip; The step of using the communication module to realize communication between the first core and the second core includes: using the communication module on the first core to output the second access request to the communication module on the second core; The second access request is output to the qth storage unit via the communication module on the second chip and the p-th second on-chip network.

17. The method according to claim 16, characterized in that, The communication module on the first chip includes M communication units, and the i-th second on-chip network is connected to the i-th communication unit. The communication module on the second chip includes W communication units, where W is an integer greater than or equal to p. The i-th communication unit is connected to the p-th communication unit on the second chip, and the p-th communication unit and the q-th storage unit on the second chip are connected to the p-th second on-chip network on the second chip, where p and q are positive integers; The step of using the i-th second on-chip network to output the second access request to the communication module on the first chip includes: using the i-th second on-chip network to output the second access request to the i-th communication unit; The step of using the communication module on the first chip to output the second access request to the communication module on the second chip includes: using the i-th communication unit to output the second access request to the p-th communication unit; On the second chip, the second access request is output to the q-th storage unit via the p-th communication unit and the p-th second on-chip network.

18. The method according to claim 13, characterized in that, The method of using the first on-chip network to realize communication between the first host and the M second on-chip networks includes: using the first on-chip network, when the first host generates a third access request for the j-th storage unit, outputting the third access request to the i-th second on-chip network; The method of using the i-th second on-chip network to realize communication between the j-th storage unit and the first on-chip network, communication between the j-th storage unit and the communication module, and communication between the first on-chip network and the communication module includes: using the i-th second on-chip network to output the third access request to the j-th storage unit.

19. The method according to claim 13, characterized in that, The i-th second on-chip network includes: The first interface is used to connect to the first on-chip network; The second interface is used to connect to the j-th storage unit; The third interface and the fourth interface are used to connect the communication module. The third interface is used for uplink transmission, and the fourth interface is used for downlink transmission. The routing module is used for interconnection between the first interface, the second interface, the third interface, and the fourth interface.

20. The method according to claim 13, characterized in that, The first chip also includes a first conversion module, which is connected between the first host and the first on-chip network; The first on-chip network includes M fifth interfaces, and the i-th fifth interface is connected to the i-th second on-chip network; The method further includes: the first conversion module converts the first physical address carried in the access request generated by the first host into a second physical address that can be recognized by the first on-chip network, and then outputs the access request to the first on-chip network; the second physical address includes the identifier of the storage unit corresponding to the first physical address; Using the first on-chip network to realize communication between the first host and the M second on-chip networks includes: the first on-chip network determining a fifth interface among the M fifth interfaces corresponding to the access request by identifying the second physical address, and outputting the access request through the determined fifth interface.

21. The method according to claim 20, characterized in that, The communication module on the first chip includes M communication units, and the i-th on-chip network is connected to the i-th communication unit. When the first physical address corresponds to a storage cell on the second chip, the second physical address also includes an identifier of a communication cell on the first chip used to transmit the access request; The first on-chip network determines one of the M fifth interfaces corresponding to the access request by identifying the second physical address, including: when the first on-chip network identifies that the second physical address includes the identifier of the j-th storage unit or the identifier of the ith communication unit, it determines that the access request corresponds to the ith fifth interface.

22. The method according to claim 21, characterized in that, The communication between the j-th storage unit and the first on-chip network, the communication between the j-th storage unit and the communication module, and the communication between the first on-chip network and the communication module are implemented using the i-th second on-chip network, including: When the second physical address in the received access request includes the identifier of the j-th storage unit, the received access request is output to the j-th storage unit; When the second physical address in the received access request includes the identifier of the i-th communication unit, the received access request is output to the i-th communication unit.

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