Die, integrated circuit, integrated circuit design method, server, and storage medium

Abstract

This application provides a die, integrated circuit, integrated circuit design method, server, and storage medium, applicable to the field of computer technology. The die includes at least one cache module, and the cache module includes a control module and a storage module. The control module is configured with a first memory access port and a second memory access port, and the storage module is configured with a second storage port and a second storage port. When the die is independently packaged, the first memory access port of the control module is connected to the first storage port of the storage module in the same cache module, ensuring that the independently packaged die can use the cache module normally. When the die is packaged with other dies, the control module is connected to the storage module of other dies through the second memory access port, and the storage module is connected to the control module of other dies through the second storage port, so that each die has a corresponding cache module available, effectively improving die utilization, shortening the design cycle, and improving tape-out efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a die, integrated circuit, integrated circuit design method, server, and storage medium. Background Technology

[0002] With the advent of the post-Moore's Law era, 3D chip technology has become one of the important directions for further improving chip performance. In existing technologies, 3D chips integrate two dies, which are stacked sequentially in the vertical direction, thereby increasing the number of transistors integrated per unit area.

[0003] However, the inventors discovered that in existing 3D chips, the two dies share a cache module, which means that the entire chip can only operate when the two dies are packaged together. A single die cannot be packaged as an independent chip. This not only results in low die utilization, but also makes the overall process complex and time-consuming, and leads to low tape-out efficiency because the layout design of the two dies needs to be carried out simultaneously during the 3D chip design process. Summary of the Invention

[0004] In view of this, this application aims to provide a bare die, integrated circuit, integrated circuit design method, server and storage medium, so that the bare die can be packaged and used alone or packaged into a 3D chip, thereby improving the utilization rate of the bare die, shortening the design cycle and improving the tape-out efficiency.

[0005] In a first aspect, this application provides a bare die, comprising: at least one cache module, the cache module including a control module and a storage module, wherein,

[0006] The control module is configured with a first memory access port and a second memory access port, and the storage module is configured with a first storage port and a second storage port;

[0007] In the case of independent die packaging, the first memory access port of the control module is connected to the first storage port of the storage module in the same cache module;

[0008] When the die is packaged with other dies, the control module communicates with the storage module of the other die through the second memory access port, and the storage module communicates with the control module of the other die through the second storage port.

[0009] In one optional implementation, the storage module includes a gating module and a storage submodule, wherein,

[0010] The storage submodule is used to store data;

[0011] The gating module is configured with a first storage port, a second storage port, and a data exchange port. The gating module is connected to the storage submodule through the data exchange port.

[0012] The gating module connects the first storage port and the data interaction port in response to a first control signal, or connects the second storage port and the data interaction port in response to a second control port.

[0013] In one optional implementation, the gating module includes a multiplexer, which is configured with a first input terminal, a second input terminal, an output terminal, and a control terminal, wherein...

[0014] The first input terminal serves as the first storage port of the gating module, the second input terminal serves as the second storage port of the gating module, and the output terminal serves as the data interaction port.

[0015] The control terminal is used to receive the first control signal or the second control signal.

[0016] In one alternative implementation, each of the cache modules is located on the top layer of the bare die.

[0017] In one optional implementation, the first memory access port is connected to the first storage port of the storage module in the same cache module via a metal wire.

[0018] The second memory access port is connected to the second memory port of the memory module of the other die via a through-silicon via (TSV).

[0019] In one optional implementation, the die provided in the first aspect of this application further includes: at least one processor core, wherein,

[0020] Each processor core corresponds to one cache module;

[0021] The control module of the cache module is also connected to the corresponding processor core.

[0022] Secondly, this application provides an integrated circuit, comprising: a first die and a second die, wherein...

[0023] The first wafer includes a wafer as described in any of the first aspects of this application;

[0024] The second bare film includes the bare film as described in any of the first aspects of this application;

[0025] The first and second dies are stacked vertically.

[0026] In one alternative implementation, the first die and the second die are stacked vertically back-to-back.

[0027] In one alternative implementation, each cache module in the first die corresponds vertically to a cache module in the second die;

[0028] The control module of any cache module in the first die is connected to the storage module of the corresponding cache module in the second die;

[0029] The storage module of any cache module in the first die is connected to the control module of the corresponding cache module in the second die.

[0030] In one optional embodiment, the integrated circuit provided in the second aspect of this application further includes a first packaging substrate and a second packaging substrate, wherein...

[0031] The first die is connected to the first packaging substrate by wire bonding;

[0032] The second die is connected to the second packaging substrate by wire bonding.

[0033] In one optional embodiment, the integrated circuit provided in the second aspect of this application further includes a first PCB board and a second PCB board, wherein...

[0034] The first PCB board shown is connected to the first packaging substrate, and the second PCB board is connected to the second packaging substrate.

[0035] In one optional embodiment, the integrated circuit provided in the second aspect of this application further includes a first packaging substrate, wherein...

[0036] The first die is connected to the first packaging substrate via flip-chip packaging, and the second die is connected to the first packaging substrate via wire bonding.

[0037] In one optional embodiment, the integrated circuit provided in the second aspect of this application further includes a first PCB board, wherein...

[0038] The first PCB board is connected to the first packaging substrate.

[0039] Thirdly, this application provides an integrated circuit design method, wherein the integrated circuit includes one or two dies, and the dies include at least one cache module, the method comprising:

[0040] Obtain the cache module netlist of the cache module;

[0041] The cache module netlist is divided into a control module netlist and a storage module netlist;

[0042] Create a first memory access port and a second memory access port in the control module netlist, and create a first storage port and a second storage port in the storage module netlist;

[0043] In the case of an independent die package, the first memory access port of the control module is connected to the first storage port of the storage module in the same cache module;

[0044] In the case of two die stacked together, the control module of one die is connected to the second memory port of the memory module of the other die through the second memory access port.

[0045] In one optional implementation, creating a first storage port and a second storage port in the storage module netlist includes:

[0046] Create a gating module netlist in the storage module netlist;

[0047] A first storage port, a second storage port, and a data interaction port are created in the gating module netlist. The data interaction port is used to connect to the storage module netlist.

[0048] In an optional implementation, the integrated circuit design method provided in the third aspect of this application further includes:

[0049] In the case of two bare dies stacked in a package, the layout and routing are performed based on the control module netlist and storage module netlist corresponding to each cache module to obtain the first layout result;

[0050] Extract the TSV (Through Silicon Via) layout diagram and target data from the first layout result;

[0051] Based on the target data and the top-level netlist of the die, the top-level layout and routing of the die are performed to obtain the second layout result;

[0052] The integrated circuit is packaged based on the TSV layout diagram and the second layout result.

[0053] In one optional implementation, the integrated circuit is packaged based on the TSV layout diagram and the second layout result, including:

[0054] In a die-in-package configuration, the integrated circuit is packaged based on the second layout result;

[0055] Alternatively, in the case of two said die stacked packages, the integrated circuit is packaged based on the TSV layout diagram and the second layout result.

[0056] In an optional implementation, before packaging the integrated circuit based on the TSV layout diagram and the second layout result, the method further includes:

[0057] In the case of a die-in-package configuration, static timing verification is performed on the data path formed by the first memory access port and the first memory port.

[0058] In the case of two die stacked packages, static timing verification is performed on the data path formed by the second memory access port and the second memory port.

[0059] Fourthly, this application provides a server including a memory, a processor, and a computer program stored on the memory and executed by the processor, wherein the processor executes the computer program to implement the steps of the integrated circuit design method as described in any of the third aspects of this application.

[0060] Fifthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the integrated circuit design method as described in any of the third aspects of this application.

[0061] Based on the above, the die provided in this application includes at least one cache module, and the cache module includes a control module and a storage module. The control module is configured with a first memory access port and a second memory access port, and the storage module is configured with a second storage port and a second storage port. When the die is independently packaged, the first memory access port of the control module is connected to the first storage port of the storage module in the same cache module, ensuring that the independently packaged die can use the cache module normally. Furthermore, when the die is stacked and packaged with other dies, the control module is connected to the storage module of other dies through the second memory access port, and the storage module is connected to the control module of other dies through the second storage port, so that each die has a corresponding cache module available. It can be seen that the die provided in this application can be independently packaged or stacked with other dies to build a 3D chip, effectively improving die utilization, shortening the design cycle, and improving tape-out efficiency. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1 This is a schematic diagram of the layout of a bare die in the prior art.

[0064] Figure 2 This is a schematic diagram of the layout of a bare die provided in this application.

[0065] Figure 3 This is a structural block diagram of a cache module provided in this application.

[0066] Figure 4 This is a schematic diagram illustrating the connection relationship between cache modules when two bare dies are stacked.

[0067] Figure 5 This is a structural block diagram of a storage module provided in this application.

[0068] Figure 6 This is a schematic diagram of the structure of an integrated circuit provided in this application.

[0069] Figure 7 This is a schematic diagram of another integrated circuit structure provided in this application.

[0070] Figure 8 This is a schematic diagram of another integrated circuit structure provided in this application.

[0071] Figure 9 This application provides a schematic diagram of the structure of an integrated circuit.

[0072] Figure 10 This is a flowchart of an integrated circuit design method provided in this application.

[0073] Figure 11 This is a flowchart of another integrated circuit design method provided in this application.

[0074] Figure 12 This is a TSV layout diagram provided in this application.

[0075] Figure 13 This is a schematic diagram of a power supply network provided in this application.

[0076] Figure 14 This is a schematic diagram of the structure of a server provided in this application. Detailed Implementation

[0077] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0078] To address the issues in existing 3D chip technologies where the entire chip can only function when two dies are packaged together, and a single die cannot be packaged as an independent chip, resulting in low die utilization, long design cycles, and low tape-out efficiency, this application provides a die that ensures the independent packaged die can use the cache module normally. Furthermore, when the die is stacked with other dies, each die has a corresponding cache module available, thereby effectively improving die utilization, shortening the design cycle, and increasing tape-out efficiency.

[0079] In practical applications, a bare die includes multiple functional modules for implementing preset functions. During the design phase, the overall layout of these functional modules needs to be considered to maximize space utilization. See [link / reference]. Figure 1 As shown, the functional modules involved in the bare die may include: at least one PCIe (Peripheral Component Interconnect express) communication module. Figure 1 The chip includes PCIe0 and PCIe1, GPIO (General-Purpose Input / Output) modules, DDR (Double Data Rate) memory modules, and four processor cores, namely core0 to core3. Of course, the die may also include other functional modules, which will not be listed here; please refer to relevant technologies for details.

[0080] Combination Figure 1 As shown, during the actual die design and layout process, the shapes of some functional modules cannot be made optimal, resulting in a large amount of unused area on the top layer of the die. For example... Figure 1 The free area is indicated by a dashed box.

[0081] Based on the above, this application provides a Figure 2 The bare die shown, based on the foregoing, includes at least one cache module, and each cache module is configured with a control module and a storage module.

[0082] Specifically, in one optional implementation, the cache module operates as the processor core's L3 cache (also known as the last level cache). Therefore, the cache module is configured in a one-to-one correspondence with the processor core. Based on this, in the die provided in this embodiment, the number of cache modules can be the same as the number of processor cores. Figure 2The cache modules 0 through 3 are shown in the diagram. Each cache module is located in a free area on the top layer of the die, and each cache module is communicatively connected to a processor core. It is understood that, as a preferred implementation, the cache module preferentially communicates with the nearest processor core, thereby reducing the time required for the processor core to access the cache module.

[0083] In related technologies, the control logic and storage logic of the cache module are not clearly separated, and all logic implementations are intertwined. This intertwining is particularly severe in the design of 3D chips, resulting in the entire chip only functioning when two dies are packaged together; a single die cannot be packaged as an independent chip. In contrast to related technologies, the die provided in this application separates the control logic and storage logic of the cache module into two independent parts. The control logic serves as the control module of the cache module, and the corresponding storage logic serves as the storage module of the cache module. The control module responds to data access instructions, reading data from or writing data to the storage module, while the storage module stores the data. Furthermore, the control module provided in this application is configured with a first memory access port and a second memory access port, and the storage module is configured with a first storage port and a second storage port. In order to achieve communication with the corresponding processor core, the control module is also connected to the corresponding processor core. In an optional embodiment, the control module also includes a communication port, through which it receives instructions from the processor core or feeds back data to the processor core. In practical applications, the communication port of the control module may include clock lines and signal lines. Of course, it may also include other connecting lines, which will not be detailed here. For specific implementation, please refer to relevant technologies.

[0084] Combination Figure 3 As shown, taking core0 and cache module0 as an example, control module0 is configured with a first memory access port A1, a second memory access port A2, and a communication port A3, while storage module0 is configured with a first storage port B1 and a second storage port B2. Based on this, in the case of independent die packaging, the first memory access port A1 of control module0 in cache module0 is connected to the first storage port B1 of storage module0 in the same cache module (i.e., cache module0), ensuring that control module0 can establish an effective communication connection with storage module0, thereby realizing complete data caching functionality. Furthermore, control module0 is also connected to core0 through communication port A3, completing data storage or data retrieval for storage module0 according to data access instructions provided by core0.

[0085] It is understandable that when the die is packaged independently, the second memory access port of the control module and the second memory port of the storage module are both in an idle state. Based on this, if it can be determined that the die will be packaged independently into the corresponding chip product, the implementation logic of the corresponding port can be deleted during the die design stage.

[0086] Since the connection between the control module and the storage module within the same cache module is a connection within the same die when the bare die is independently packaged, as a preferred embodiment, the connection between the first memory access port of the control module and the first storage port of the storage module in the same cache module can be implemented by a metal stripe.

[0087] Furthermore, in the case of stacked packaging of two dies, the control module is connected to the storage module of the other die through the second memory access port, and correspondingly, the storage module is connected to the control module of the other die through the second storage port. It should be noted that, as mentioned above, the dies in the prior art do not divide the cache module into independent control and storage modules. This means that the dies in the prior art cannot be combined with the dies provided in this application to obtain a 3D chip. Based on this, the other dies mentioned in the various embodiments of this application all refer to the dies provided in accordance with the core idea of ​​this application. In other words, in the case of stacked packaging of two dies, both dies involved are the dies provided in this application.

[0088] In practical applications, there are two ways to stack bare dies in the vertical direction: face-to-face stacking and back-to-back stacking. Considering that face-to-face stacking introduces additional bumps, which in turn affects the arrangement of the bumps on the top layer of the bare die, this application samples the back-to-back stacking method.

[0089] To clearly illustrate the connection relationship between the control module and the storage module when two bare dies are stacked, Figure 4This diagram illustrates the connection relationship when the upper die is translated so that the two dies are on the same horizontal plane. In one optional implementation, the two dies inside the 3D chip have completely identical functions. That is, in the case of the cache module provided in this application, the functions and layouts of other functional modules within the two dies are also completely identical. In this case, only one die needs to be designed. After the die is completed, the other die can be obtained by copying it. Furthermore, in order to stack the two dies back to back, one of the dies needs to be flipped 180°. At this time, the cache module 3 in the upper die is located directly above the cache module 0 in the lower die. Specifically, the storage module 3 in the upper die cache module 3 corresponds to the control module 0 in the lower die cache module 0. The two can be combined into a complete cache module. Correspondingly, the control module 3 in the upper die cache module 3 corresponds to the storage module 0 in the lower die cache module 0. The two can be combined into another complete cache module. At the same time, since the connection relationship between the processor core and the control module has not changed, each processor core can still access the corresponding storage module through the control module. Similarly, the correspondence of other cache modules is not listed here, but can be implemented with reference to the content here.

[0090] In the case of two die stacked packages, the connection between the control module and the memory module is a connection between different dies. Therefore, as a preferred embodiment, the connection between the second memory access port of the control module and the second memory port of the corresponding memory module in the other die can be achieved through TSV (Through Silicon Via).

[0091] It is understood that in the bare die provided in this application, any storage module corresponds to two data transmission paths, namely a first storage port and a second storage port. Referring to the foregoing, when the bare die is independently packaged, the storage module interacts with data through the first storage port. When two bare dies are stacked and packaged, the storage module interacts with data through the second storage port. To meet this data interaction requirement, this application provides an optional implementation method for the storage module.

[0092] See Figure 5 As shown, the storage module provided in this embodiment includes a gating module and a storage submodule. The storage submodule is used to store data. In practical applications, it can be implemented based on SRAM (Static Random-Access Memory). Of course, it can also be other storage media that can meet the fast data access requirements of the processor core. This application does not make any specific limitations on this.

[0093] As an optional implementation, the gating module can be selected as a multiplexer (MUX), combined with... Figure 5 As shown, the multiplexer includes a first input terminal, a second input terminal, an output terminal, and a control terminal. The first input terminal of the multiplexer serves as the first storage port B1 of the gating module, the second input terminal of the multiplexer serves as the second storage port B2 of the gating module, the output terminal of the multiplexer serves as the data interaction port C1 of the gating module, and the control terminal of the multiplexer serves as the control terminal C2 of the gating module, receiving a first control signal or a second control signal.

[0094] Based on the above, the gating module is connected to the storage submodule via data exchange port C1. Responding to the first control signal, the gating module connects the first storage port B1 and the data exchange port C1 to establish a first data transmission path. Alternatively, in response to the second control port, the gating module connects the second storage port B2 and the data exchange port C1 to establish a second data transmission path. In practical applications, by providing either the first or second control signal, the selection of different data transmission paths can be achieved, thereby meeting the different data interaction requirements in both single-die independent packaging and two-die stacked packaging scenarios.

[0095] In one alternative implementation, the aforementioned first control signal and second control signal are provided by each control module. Of course, they can also be provided by other control modules inside the 3D chip, which will not be listed here. As long as they do not exceed the core idea of ​​this application, they also fall within the scope of protection of this application.

[0096] In summary, the die provided in this application, when the die is independently packaged, has its first memory access port of the control module connected to the first storage port of the storage module in the same cache module, ensuring that the independently packaged die can use the cache module normally. When the die is stacked and packaged with other dies, the control module is connected to the storage module of other dies through the second memory access port, and the storage module is connected to the control module of other dies through the second storage port, so that each die has a corresponding cache module available. Therefore, the die provided in this application can be independently packaged or stacked with other dies to build a 3D chip, effectively improving die utilization, shortening the design cycle, and improving tape-out efficiency.

[0097] See Figure 6 As shown, this application also provides an integrated circuit, including a first die 0 and a second die 1. It should be noted that both the first die 0 and the second die 1 are die provided in the foregoing embodiments of this application.

[0098] Combination Figure 6As shown, the first die 0 and the second die 1 are stacked vertically, with the first die 0 located above the second die 1, and the first die 0 and the second die 1 are connected via a TSV. It should be noted that... Figure 6 In the integrated circuit provided in the illustrated embodiment, the first die 0 and the second die 1 are connected in the aforementioned back-to-back manner.

[0099] Furthermore, based on the aforementioned content, since the first die 0 and the second die 1 have identical functional module layouts, when stacked back-to-back, each cache module in the first die 0 corresponds vertically to a cache module in the second die 1. Correspondingly, the control module of any cache module in the first die 0 is connected to the storage module of the corresponding cache module in the second die 1, and the storage module of any cache module in the first die 0 is connected to the control module of the corresponding cache module in the second die 1. This allows the vertically opposite control modules and storage modules in different dies to form corresponding cache modules, enabling the sharing of cache modules between the first die 0 and the second die 1. For the connection relationship between the control module and storage module in the cache modules of each die, please refer to... Figure 4 As shown, it will not be repeated here.

[0100] It should be noted that, Figure 6 And the FEOL shown in the following figures, which stands for the Front-End-Of-Line, and the corresponding BEOL, which stands for the Back-End-Of-Line, are not improved in this application. For details, please refer to the relevant technologies.

[0101] In one alternative implementation, Figure 6 The integrated circuit provided in the illustrated embodiment may further include a first packaging substrate, a second packaging substrate, a first PCB board, and a second PCB board.

[0102] See Figure 7 As shown, the first die 0 is connected to the first package substrate 0 via wire bonding, and the first package substrate 0 is connected to the first PCB board pcb0 via wire bonding. Correspondingly, the second die 1 is connected to the second package substrate 1 via wire bonding, and the second package substrate 1 is connected to the second PCB board pcb1 via wire bonding.

[0103] Understandably, when adopting Figure 7When performing dual-die stacked packaging as shown, the use of two packaging substrates can effectively reduce the wiring density of the packaging substrates compared to the single packaging substrate method. Using two external PCBs also helps to reduce the volume of the PCB board.

[0104] In another alternative implementation, Figure 6 The integrated circuit provided in the illustrated embodiment may further include a first packaging substrate and a first PCB board.

[0105] See Figure 8 As shown, the first die 0 is connected to the first package substrate 0 via flip chip packaging, the second die 1 is connected to the first package substrate 0 via wire bonding, and the first package substrate 0 is further connected to the first PCB board pcb0 via wire bonding.

[0106] Compared to Figure 7 The embodiment shown, Figure 8 The packaging method shown can reduce the use of packaging substrate and PCB board, resulting in lower cost.

[0107] As mentioned above, the bare die provided in this application can also be independently packaged into a corresponding chip. Based on this, when packaging a bare die provided in this application, the following methods can be used: Figure 9 The structure is shown. For the specific implementation of a single die package, please refer to relevant technologies; details will not be elaborated here.

[0108] It should be noted that the packaging methods provided in the above embodiments are only for describing the relevant improvements of this application. For the parts of the above content that are described in detail, they can be implemented with reference to relevant technologies.

[0109] Furthermore, this application also provides an integrated circuit design method applied to an electronic device, which may be a personal computer (PC), a laptop computer, or any other electronic device capable of running the software corresponding to the integrated circuit design method provided in this application. In some cases, it may also be applied to a network-side server.

[0110] See Figure 10 As shown, the integrated circuit design method provided in this application includes the following steps.

[0111] S100, Obtain the cache module netlist of the cache module.

[0112] First, it should be noted that the integrated circuit design method provided in this embodiment is used to design the integrated circuit provided in any of the foregoing embodiments. Depending on the packaging, the integrated circuit may include one die provided in the foregoing embodiments, or it may include two dies provided in the foregoing embodiments. That is, the design method provided in this embodiment can design an integrated circuit including one die or an integrated circuit including two dies. Furthermore, the die mentioned in this embodiment includes at least one cache module.

[0113] Based on the existing phase divisions of the integrated circuit design process, the integrated circuit design method provided in this application belongs to the physical design phase of integrated circuits. Physical design, also known as back-end design, is one of the key design phases in the integrated circuit design process. Physical design takes the netlist of the integrated circuit, which is the final output of the logic design (also known as front-end design), as input, and the layout information (GDS file) that can be used by the factory for mask fabrication as the final output. Of course, there is no strict division of labor between logic design and physical design. In the subsequent embodiments provided in this application, obtaining the netlist of the integrated circuit is taken as the starting point of the physical design work.

[0114] A netlist is used to describe the interconnections between circuit components, and is typically a text file that follows a relatively simple syntax. Conversely, a gate-level netlist refers to a netlist that describes circuit components that are primarily at the gate level or equivalent.

[0115] Based on the above, it can be seen that the integrated circuit netlist includes the netlists of all functional modules included in the integrated circuit. Therefore, after obtaining the integrated circuit netlist, the netlists corresponding to each cache module within the integrated circuit, i.e., the cache module netlists, can be further extracted from it. The specific process of obtaining the integrated circuit netlist can be found in relevant documentation and will not be detailed here.

[0116] S110. Divide the cache module netlist into the control module netlist and the storage module netlist.

[0117] As mentioned earlier, related technologies do not clearly separate the control logic and storage logic of the cache module, resulting in all logic implementations being intertwined. This is a key factor preventing multiple bare dies sharing a cache module from being independently packaged and used in related technologies. Therefore, after obtaining the cache module netlist, this application splits the cache module netlist into a control module netlist and a storage module netlist, so that the control module and storage module can be treated as independent physical implementations in subsequent design processes. In practical applications, the splitting of the control module netlist and the storage module netlist mainly depends on the overall functionality of each related content within the netlist in the cache module netlist. Netlist content related to control functionality is included as part of the control module netlist, and correspondingly, netlist content related to the storage module is included as part of the storage module netlist, thus obtaining the control module netlist and the storage module netlist.

[0118] S120. Create a first memory access port and a second memory access port in the control module netlist, and create a first storage port and a second storage port in the storage module netlist.

[0119] To enable the bare die to be packaged and used independently or stacked with other bare dies, this method further creates a first memory access port and a second memory access port in the control module netlist, and correspondingly creates a first memory port and a second memory port in the memory module netlist. The specific way these ports are recorded in their respective netlists can be referenced from related technologies, and this application does not limit this.

[0120] Based on the foregoing, by creating the aforementioned ports, the die provided in this application can be packaged and used independently or stacked with other dies. In the case of an independent die package, the first memory access port of the control module is connected to the first memory port of the storage module in the same cache module, enabling the integrated circuit to independently use the corresponding control module and storage module. Correspondingly, in the case of two dies stacked and packaged, the control module of any die is connected to the second memory port of the storage module of the other die through the second memory access port, so that the two dies can share the corresponding cache module.

[0121] In one alternative implementation, in order to create a first storage port and a second storage port in the storage module netlist, a gating module netlist is first created in the storage module netlist. In practical applications, the gating module can be a multiplexer (MUX), i.e., a multiplexer netlist is created. Further, a first storage port, a second storage port, and a data interaction port are created in the gating module netlist. The data interaction port is used to connect to the storage module netlist. Thus, the creation of the first storage port and the second storage port in the storage module netlist is completed.

[0122] As mentioned earlier, in the case of a single die package, the first memory access port of the control module is connected to the first memory port of the memory module in the same cache module. This connection is considered an intra-die connection. Therefore, the connection between the first memory access port and the second memory port can be achieved through metal lines. Based on this, the first memory access port can be brought out on the M4 layer. Similarly, in the case of two stacked dies, the control module of any die is connected to the second memory port of the memory module of the other die through its second memory access port. This connection is considered an inter-die connection, which can be implemented using TSVs during the design process. Furthermore, when routing these ports, they can be staggered across different metal layers to reduce crosstalk between signal lines on the same layer, while effectively utilizing the integrated circuit design area.

[0123] In summary, the integrated circuit design method provided in this embodiment splits the cache module netlist into a control module netlist and a storage module netlist, and creates a first memory access port and a second memory access port in the control module netlist, and a first storage port and a second storage port in the storage module netlist. In the case of an independent die package, the first memory access port of the control module is connected to the first storage port of the storage module in the same cache module, so that the integrated circuit can independently use the corresponding control module and storage module. Correspondingly, in the case of two dies stacked and packaged, the control module of any die is connected to the second storage port of the storage module of the other die through the second memory access port, so that the two dies can share the corresponding cache module. Based on this, the integrated circuit provided by the integrated circuit design method of this application can independently package a single die, or it can be stacked with other dies to build a 3D chip, effectively improving die utilization, shortening the design cycle, and improving tape-out efficiency.

[0124] Furthermore, this application also provides another integrated circuit design method, see [link to relevant documentation]. Figure 11 As shown, in Figure 10 Based on the illustrated embodiment, the integrated circuit design method provided in this embodiment may further include the following steps.

[0125] S130. In the case of two bare dies stacked in a package, the layout and routing are performed based on the control module netlist and storage module netlist corresponding to each cache module to obtain the first layout result.

[0126] To meet the requirement that both standalone die packages and stacked packages are available, automatic placement and routing (APR) based on netlists needs to be performed in a scenario with two stacked die packages (i.e., a 3D scenario).

[0127] As mentioned earlier, the cache module is located at the top layer of the bare die. Therefore, the top layer includes the entire storage module body. When planning the location of these storage modules, it's important to avoid excessively close proximity and to reserve space for TSV configuration. Simultaneously, the TSV locations should be planned appropriately, taking into account… Figure 12 As shown, by avoiding placing TSVs in the area where the storage module is located and ensuring that the TSVs are as evenly distributed as possible, the corresponding TSV layout diagram can be obtained. In practical applications, since the storage module needs to directly interact with the processor core, in order to meet the requirements of fast data read response, the storage module can be implemented based on SRAM.

[0128] For the design of power supply networks, you can refer to... Figure 13 As shown, horizontal metal strips are laid out on even-numbered layers and vertical metal strips are laid out on odd-numbered layers. Metal vias are used to connect the intersections. Power bumps can be evenly distributed. As for the specific design process of the power supply network, you can refer to relevant technologies for implementation, which will not be described in detail here.

[0129] Furthermore, since the cache module interacts with other functional modules in the integrated circuit via timing signals, it is necessary to perform automatic placement and routing between these communication interfaces according to the layout of the corresponding communication interfaces. It is important to note that during the automatic placement and routing process, it is necessary to ensure that placement blockage is added in the TSV region to prevent the standard cells of the integrated circuit from being placed in the TSV region.

[0130] For the layout and routing processes not mentioned or elaborated in detail above, relevant technologies can be referenced for implementation, and they will not be described in detail here.

[0131] In one optional implementation, after obtaining the first layout result, static timing analysis (STA) and physical verification (PV) and other related verification measures can be performed on the obtained first layout result. If the first layout result fails any verification, the layout and routing need to be redone until the obtained first layout result passes the verification. The specific verification process can also be implemented with reference to relevant technologies, which will not be described in detail here.

[0132] S140. Extract the TSV layout diagram and target data from the first layout result.

[0133] The TSV layout diagram can be found here. Figure 12As shown, the target data includes, but is not limited to, physical library files, physical data used to describe cell size and metal layer information, and timing data used to describe timing delays, transition times, etc. In practical applications, it may also include other information related to subsequent steps of integrated circuit design, which will not be listed here. As long as it does not exceed the core idea of ​​this application, it also falls within the scope of protection of this application.

[0134] S150. Based on the target data and the top-level netlist of the die, perform top-level placement and routing of the die to obtain the second placement result.

[0135] Having completed the aforementioned steps, we have obtained the layout results of each cache module and related layout information, such as the TSV layout diagram. Based on this, we can continue with the layout planning and design of the top layer of the integrated circuit, that is, perform the top layer layout and routing of the die based on the target data and the top layer netlist of the die, and obtain the second layout result. It should be noted that the top layer of the die includes not only the aforementioned cache modules, but also other modules that can be set at the top layer. Therefore, the top layer netlist mentioned in this step mainly includes the netlists of other modules besides the cache module netlist.

[0136] When performing this step, the actual application scenario of the two stacked dies needs to be considered to ensure the correspondence between the control module and the storage module between different dies. The layout should ensure central symmetry. After final issuance, the resulting second layout can be found in [reference needed]. Figure 2 As shown, the overall layout result of the bare die is obtained.

[0137] In an optional implementation, the second layout result can also be verified by referring to the verification process of the first layout result to obtain a second layout result that meets the corresponding verification requirements. It should be emphasized that the cache module provided in this application includes two data paths. During timing analysis, both data paths must meet timing requirements. Therefore, it is necessary to verify the two cases separately: in the case of a single die independently packaged, static timing verification is performed on the data path formed by the first memory access port and the first storage port; correspondingly, in the case of two dies stacked and packaged, static timing verification is performed on the data path formed by the second memory access port and the second storage port. It is understood that the verification process in this step requires setting two timing constraints (Synopsys Design Constraints, SDC).

[0138] In practical applications, the second layout result can be recorded in the form of a GDS file. Based on this, the final output of this step is the GDS file of a single die.

[0139] S160, based on the TSV layout diagram and the second layout result, packaged integrated circuit.

[0140] In the case of a single die-in-package (i.e., operating with a single die), simply removing all TSV-related information from the GDS file allows the die to be packaged based on the second layout result, yielding the corresponding integrated circuit. Conversely, in the case of a stacked die package, the dies are connected via TSVs; therefore, the integrated circuit needs to be packaged using both the TSV layout diagram and the second layout result. The specific form of the resulting integrated circuit can be found in the aforementioned content and illustrations, and will not be repeated here.

[0141] In summary, the integrated circuit design method provided in this application can complete the design of an integrated circuit that can be independently packaged from a single die, or it can complete the design of an integrated circuit that can be stacked and packaged from two dies. The resulting dies can be used independently or stacked and packaged with other dies, effectively improving die utilization, shortening the design cycle, and increasing tape-out efficiency.

[0142] Below, for reference Figure 14 The server provided in this embodiment of the invention may include: at least one processor 100, at least one communication interface 200, at least one memory 300 and at least one communication bus 400.

[0143] In this embodiment of the invention, the number of processor 100, communication interface 200, memory 300, and communication bus 400 is at least one, and the processor 100, communication interface 200, and memory 300 communicate with each other through communication bus 400; obviously, Figure 14 The communication connections shown for the processor 100, communication interface 200, memory 300, and communication bus 400 are optional.

[0144] Optionally, the communication interface 200 can be an interface of a communication module, such as the interface of a GSM module; the processor 100 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.

[0145] The memory 300 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0146] Specifically, the processor 100 is used to execute the application program in the memory to implement the steps of the integrated circuit design method described above.

[0147] In some embodiments, this embodiment also provides a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc., in which one or more instructions implementing the above steps are stored. When these one or more instructions are executed by one or more processors, the processors perform the integrated circuit design method described above. For specific implementation details, please refer to the foregoing description; further elaboration is not provided here.

[0148] In addition to the methods and apparatus described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the integrated circuit design methods according to various embodiments of this application as described above.

[0149] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0150] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.

[0151] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.

[0152] This disclosure uses flowcharts to illustrate the steps of a method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes.

[0153] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This disclosure is not limited to any particular combination of hardware and software.

[0154] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0155] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A bare wafer, characterized in that, include: At least one cache module, the cache module comprising a control module and a storage module, wherein, The control module is configured with a first memory access port and a second memory access port, and the storage module is configured with a first storage port and a second storage port; In the case of independent die packaging, the first memory access port of the control module is connected to the first storage port of the storage module in the same cache module; When the die is packaged with other dies, the control module communicates with the storage module of the other die through the second memory access port, and the storage module communicates with the control module of the other die through the second storage port.

2. The bare wafer according to claim 1, characterized in that, The storage module includes a gating module and a storage submodule, wherein, The storage submodule is used to store data; The gating module is configured with a first storage port, a second storage port, and a data exchange port. The gating module is connected to the storage submodule through the data exchange port. The gating module connects the first storage port and the data interaction port in response to a first control signal, or connects the second storage port and the data interaction port in response to a second control port.

3. The bare wafer according to claim 2, characterized in that, The selection module includes a multiplexer, which is configured with a first input terminal, a second input terminal, an output terminal, and a control terminal. The first input terminal serves as the first storage port of the gating module, the second input terminal serves as the second storage port of the gating module, and the output terminal serves as the data interaction port. The control terminal is used to receive the first control signal or the second control signal.

4. The bare die according to claim 1, characterized in that, Each of the aforementioned cache modules is located at the top layer of the bare die.

5. The bare die according to claim 1, characterized in that, The first memory access port is connected to the first storage port of the storage module in the same cache module via a metal wire; The second memory access port is connected to the second memory port of the memory module of the other die via a through-silicon via (TSV).

6. The bare die according to any one of claims 1 to 5, characterized in that, Also includes: At least one processor core, wherein, Each processor core corresponds to one cache module; The control module of the cache module is also connected to the corresponding processor core.

7. An integrated circuit, characterized in that, include: The first nude film and the second nude film, among which... The first die includes the die as described in any one of claims 1 to 5; The second die includes the die as described in any one of claims 1 to 5; The first and second dies are stacked vertically.

8. The integrated circuit according to claim 7, characterized in that, The first and second bare wafers are stacked vertically with their backs to back.

9. The integrated circuit according to claim 8, characterized in that, Each cache module in the first die corresponds vertically to one cache module in the second die; The control module of any cache module in the first die is connected to the storage module of the corresponding cache module in the second die; The storage module of any cache module in the first die is connected to the control module of the corresponding cache module in the second die.

10. The integrated circuit according to claim 8, characterized in that, It also includes a first packaging substrate and a second packaging substrate, wherein, The first die is connected to the first packaging substrate by wire bonding; The second die is connected to the second packaging substrate by wire bonding.

11. The integrated circuit according to claim 10, characterized in that, It also includes a first PCB board and a second PCB board, wherein The first PCB board shown is connected to the first packaging substrate, and the second PCB board is connected to the second packaging substrate.

12. The integrated circuit according to claim 8, characterized in that, It also includes a first packaging substrate, wherein, The first die is connected to the first packaging substrate via flip-chip packaging, and the second die is connected to the first packaging substrate via wire bonding.

13. The integrated circuit according to claim 12, characterized in that, It also includes the first PCB board, in which, The first PCB board is connected to the first packaging substrate.

14. An integrated circuit design method, characterized in that, The integrated circuit includes one or two dies, each die including at least one cache module, and the method includes: Obtain the cache module netlist of the cache module; The cache module netlist is divided into a control module netlist and a storage module netlist; Create a first memory access port and a second memory access port in the control module netlist, and create a first storage port and a second storage port in the storage module netlist; In the case of a single die being independently packaged, the first memory access port of the control module is connected to the first storage port of the storage module in the same cache module; In the case of two die stacked together, the control module of one die is connected to the second memory port of the memory module of the other die through the second memory access port.

15. The integrated circuit design method according to claim 14, characterized in that, Creating a first storage port and a second storage port in the storage module netlist includes: Create a gating module netlist in the storage module netlist; A first storage port, a second storage port, and a data interaction port are created in the gating module netlist. The data interaction port is used to connect to the storage module netlist.

16. The integrated circuit design method according to claim 14, characterized in that, Also includes: In the case of two bare dies stacked in a package, placement and routing are performed based on the control module netlist and storage module netlist corresponding to each cache module to obtain a first placement result; Extract the silicon through-silicon via (TSV) layout diagram and target data from the first layout result; Based on the target data and the top-level netlist of the die, the top-level layout and routing of the die are performed to obtain the second layout result; The integrated circuit is packaged based on the TSV layout diagram and the second layout result.

17. The integrated circuit design method according to claim 16, characterized in that, The integrated circuit is packaged based on the TSV layout diagram and the second layout result, including: In a die-in-package configuration, the integrated circuit is packaged based on the second layout result; Alternatively, in the case of two said die stacked packages, the integrated circuit is packaged based on the TSV layout diagram and the second layout result.

18. The integrated circuit design method according to claim 16, characterized in that, Before packaging the integrated circuit based on the TSV layout diagram and the second layout result, the method further includes: In the case of a die-in-package configuration, static timing verification is performed on the data path formed by the first memory access port and the first memory port. In the case of two die stacked packages, static timing verification is performed on the data path formed by the second memory access port and the second memory port.

19. A server comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, characterized in that, When the processor executes the computer program, it implements the steps of the integrated circuit design method as described in any one of claims 14 to 18.

20. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the integrated circuit design method as described in any one of claims 14 to 18.

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