A heterogeneous computing platform for underwater acoustic signal processing

Abstract

This invention discloses a heterogeneous computing platform for underwater acoustic signal processing, belonging to the field of sensor architecture technology. The platform includes a VPX-standard-based chassis, backplane, and various functional boards plugged into it, including power boards, CPU boards, cache boards, switching boards, and three types of heterogeneous computing boards (A, B, and C). The platform adopts a dual-bus switching architecture of Ethernet and SRIO, and integrates a message middleware compliant with the DDSI-RTPS standard to realize data publishing and subscription between heterogeneous boards, shielding underlying hardware differences. Each board integrates a domestically produced chassis management and monitoring chip, supports the IPMI 2.0 standard, and has hot-swappable, remote monitoring, and dynamic reconfiguration capabilities. This invention achieves intelligent allocation and efficient utilization of computing resources, improves the modularity, intelligent algorithm compatibility, and system scalability of the underwater acoustic signal processing platform, and is suitable for various underwater acoustic detection and intelligent processing tasks.

Description

Technical Field

[0001] This invention relates to the field of sensor architecture technology, and more specifically to a heterogeneous computing platform for underwater acoustic signal processing. Background Technology

[0002] Existing underwater acoustic signal processing platforms are mainly divided into two categories: general-purpose processing platforms based on CPUs and dedicated processing platforms based on FPGAs and DSPs. In the early stages of underwater acoustic system development, the computational requirements were relatively low because only basic target information such as range and azimuth needed to be acquired. However, with the increasing demands for detection accuracy in modern combat environments, underwater acoustic systems need to acquire increasingly refined target feature information, expanding from traditional positional information to multi-dimensional information such as target micro-motion characteristics and imaging features. This directly leads to an exponential increase in the complexity of signal processing algorithms, and the amount of data processed has jumped from megabytes to terabytes. Modern underwater acoustic systems have evolved into integrated detection systems containing multiple transceiver units and large arrays. Standardized and modular system architectures are commonly used at both the transducer array and signal processing platform levels. This development trend has placed unprecedented demands on signal processing platforms for high performance, strong real-time capabilities, and loose coupling.

[0003] Currently, the field of underwater acoustic signal processing faces three major technical bottlenecks: First, while traditional dedicated processing platforms based on FPGAs and DSPs have advantages in certain specific computing tasks, their hardware scale is large, development and debugging are difficult, and they especially require professional hardware design capabilities, which seriously restricts the rapid iteration and upgrade maintenance of the system. Second, the hardware description language used by FPGAs has a serious ecological disconnect from the current mainstream intelligent algorithm frameworks such as TensorFlow and PyTorch, making it significantly lagging behind GPU architecture in supporting new intelligent algorithms such as deep learning. Third, although general-purpose processing platforms based on CPUs have advantages in system versatility and development flexibility, they have obvious computing power bottlenecks when handling large-scale parallel computing tasks, making it difficult to meet the real-time processing needs of massive amounts of data. Summary of the Invention

[0004] This invention provides a heterogeneous computing platform for underwater acoustic signal processing to address the problems of low modularity, poor compatibility of intelligent algorithm ecosystems, and rigid computing power configuration faced by current underwater acoustic signal processing platforms.

[0005] This invention provides a heterogeneous computing platform for underwater acoustic signal processing, comprising: A chassis based on the VPX standard with an integrated backplate, which has multiple slots compliant with the VITA46 standard. Several functional boards plugged into the slots include power boards, CPU boards, cache boards, switching boards, and at least one heterogeneous computing board; The heterogeneous computing boards include type A boards, type B boards and type C boards, which use different combinations of CPU and GPU chips to form a tiered computing power system. The platform also includes a dual-bus switching architecture, including Ethernet and SRIO dual buses, for data transmission between boards, between chassis, and at the chip level; The platform also includes an encapsulated message middleware that conforms to the DDSI-RTPS standard, used to build a global data space and enable data publishing and subscription between heterogeneous boards.

[0006] In some instances, the Type A board includes one CPU processor chip and two GPU processor chips interconnected via a PCIe 4.0 bus; The CPU processor has no fewer than 8 cores, a clock speed of no less than 2.0 GHz, and a floating-point processing power of no less than 256 GFlops; Each GPU processor has a clock speed of no less than 1GHz and a floating-point processing capability of no less than 16 TFlops; the Type A board is suitable for scenarios where multiple applications run in parallel and require physical isolation.

[0007] In some instances, the Type B board includes a CPU processor chip and a GPU processor chip interconnected via a PCIe 4.0 bus; Its CPU processor chip is the same as that of the Type A board, and its GPU processor has a main frequency of no less than 1.5GHz and a floating-point processing power of no less than 32TFlops; The Type B board is suitable for scenarios where a single application is running and high GPU computing power is required.

[0008] In some instances, the Type-C board includes a CPU processor chip and a GPU processor chip interconnected via a PCIe 4.0 bus; Its GPU processor chip is the same as that of the Type B board, and its CPU processor has no less than 32 cores, a main frequency of no less than 2.5GHz, and a floating-point processing power of no less than 1.2 TFlops; The C-type board is suitable for scenarios requiring high-complexity logic processing capabilities.

[0009] In some instances, the dual-bus switching architecture includes Ethernet interfaces with speeds of 1Gbps, 10Gbps, and 40Gbps. Each board provides at least two 1Gbps interfaces for IPMI management, four 10Gbps interfaces for medium-to-high-speed data transmission, and one 40Gbps interface for chassis interconnection; The SRIO interface conforms to the SRIO 2.0 specification, with at least two channels configured on each board, and a transmission bandwidth of no less than 20Gbps, for low-latency data transmission between boards.

[0010] In some instances, the message middleware constructs a global data space through topics, data objects, publishers, and subscribers; Applications on each board communicate by subscribing to and publishing data objects, without needing to be aware of the underlying hardware differences; The middleware supports QoS policy control of data transmission behavior and supports data writers, data readers, send queues, and historical caching mechanisms.

[0011] In some instances, the CPU board includes a high-performance CPU processor and an Ethernet controller, providing at least one 40Gbps communication interface; The cache board includes a high-performance CPU processor and a high-speed NVMe storage module with two XMC interfaces; The power supply board supports +12V and +3.3V AUX DC input and has surge current suppression function.

[0012] In some instances, each functional board integrates a domestically produced chassis management and monitoring chip, supports the IPMI 2.0 standard protocol, and complies with the VITA 46.11 standard; The monitoring chip provides peripheral interfaces such as USART, UART, I²C, I²S, SPI, and CAN, and supports IPMB bus and Ethernet data interface; It is used to monitor the voltage, current and temperature of the board in real time, and provides overvoltage, overcurrent and overtemperature power-off protection.

[0013] In some instances, all functional boards support hot-swapping; The platform supports dynamic system reconfiguration and functional expansion by adjusting the number and slot positions of Type A, Type B, and Type C boards. After the board is replaced, the message middleware automatically discovers the new node and establishes communication, without requiring any modifications to the application.

[0014] In some instances, when the platform is applied to underwater acoustic signal processing tasks, it supports the following data processing flow: The CPU board receives the collected data via a 40G Ethernet interface; The data is processed in parallel using Algorithm A via the Type A board; The processing results are transmitted to the C-type or B-type board to execute Algorithm 2, Algorithm 3, and Algorithm 4 in sequence; The final result is transmitted to the cache board for storage or graphical display; The algorithms are executed in parallel on different boards, forming a pipelined processing architecture; The IPMI management system monitors the system status in real time.

[0015] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects: This invention platform fully leverages the advantages of CPUs in complex logic control, task scheduling, and system management, while utilizing the high efficiency of GPUs in large-scale parallel computing and deep learning inference, achieving intelligent allocation and efficient utilization of computing resources. Particularly in supporting intelligent algorithms, the platform is directly compatible with mainstream deep learning frameworks, significantly improving system performance in intelligent processing tasks such as target recognition, interference suppression, and adaptive beamforming. By employing fully domestically produced hardware components and independently developed middleware software, it provides reliable technical support for the development of next-generation underwater acoustic systems while ensuring information security, effectively promoting the transformation and upgrading of underwater acoustic signal processing technology towards intelligence and software-based solutions. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a typical configuration of the VPX chassis and boards for the underwater acoustic signal processing heterogeneous computing platform provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the heterogeneous computing board principle of the underwater acoustic signal processing heterogeneous computing platform provided in this embodiment of the invention; Figure 3 This is a schematic diagram of the message middleware principle of the heterogeneous computing platform for underwater acoustic signal processing provided in an embodiment of the present invention; Figure 4 This is a typical data flow diagram of the heterogeneous computing platform for underwater acoustic signal processing provided in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] In the following description, specific embodiments of the invention will be illustrated with reference to steps and symbols performed by one or more computers, unless otherwise stated. Therefore, these steps and operations will be referred to several times as being performed by a computer, and computer execution as referred to herein includes operations by a computer processing unit representing electronic signals of data in a structured format. This operation transforms the data or maintains it at a location in the computer's memory system, which can be reconfigured or otherwise alter the operation of the computer in a manner well known to those skilled in the art. The data structure maintained by the data is the physical location of the memory, which has specific characteristics defined by the data format. However, the principles of the invention described above are not intended to be limiting, and those skilled in the art will understand that many of the following steps and operations can also be implemented in hardware.

[0020] The terms "module" or "unit" as used herein can be considered as software objects executing on the computing system. Different components, modules, engines, and services described herein can be considered as implementations on the computing system. The apparatus and methods described herein are preferably implemented in software, but can also be implemented in hardware, both of which are within the scope of this invention.

[0021] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0022] This invention provides a heterogeneous computing platform for underwater acoustic signal processing, which mainly addresses the following issues: (1) To address the contradiction between existing underwater acoustic signal processing platforms and the application of intelligent algorithms, a tiered computing power system was constructed by designing three heterogeneous computing boards (Type A, Type B, and Type C) using different models of CPU and GPU chips. Each type of board has a differentiated configuration in terms of power consumption and computing performance, which can not only complete general signal processing tasks, but also support the training and inference of intelligent models based on deep learning, thus meeting the evolution requirements of underwater acoustic systems from traditional processing to intelligent applications. (2) To address the issues of insufficient interface bandwidth and limited link selection in traditional underwater acoustic signal processing platforms, we designed and integrated multiple high-speed interfaces, including Ethernet, SRIO, and PCIe, to establish a high-bandwidth, low-latency data transmission channel and provide a reliable link foundation for large-scale data interaction. (3) To address the issues of closed ecosystems and poor versatility in existing underwater acoustic signal processing platforms, a unified specification covering hardware architecture, electrical characteristics, structural design, and interface standards is established to ensure the compatibility and interchangeability of various types of boards. The platform supports hot-swapping of boards and remote management and monitoring functions, allowing for flexible configuration of different numbers of various types of boards in the VPX chassis. At the same time, based on standardized network communication, SRIO interfaces, and message middleware software, flexible data scheduling, rapid fault migration, and dynamic system reconfiguration are achieved, effectively meeting the decoupling requirements of modular equipment and significantly improving system availability, openness, and upgradeability.

[0023] This invention provides a heterogeneous computing platform for underwater acoustic signal processing, the specific method of which is as follows: (1) System integration is achieved by adopting a unified VPX bus architecture.

[0024] Multiple functional boards are configured within a VPX-based chassis. These boards interconnect with the chassis backplane via VPX connectors compliant with the VITA46 standard. The backplane employs a hybrid architecture design, compatible with multiple standard interface slots, ensuring backward compatibility with existing boards during system upgrades and evolution. The system includes VPX boards covering power supply boards, CPU boards, cache boards, switch boards, and three types of heterogeneous computing boards (A, B, and C). Each board possesses the following technical characteristics: 1) The power supply board adopts +12V and +3.3V AUX DC input and has the function of suppressing surge current when powered on; 2) The CPU board contains a high-performance CPU processor chip and an Ethernet controller chip, providing one 40Gbps communication interface to the outside world; 3) The cache board includes a high-performance CPU processor chip and two high-speed NVMe storage modules with XMC interfaces, providing large-capacity data storage; 4) Each board contains a domestic chassis management and monitoring chip, which can provide a variety of peripheral resources such as USART, UART, I2C, I2S, SPI, CAN and other interfaces, support the IPMI2.0 standard protocol, comply with the VPX VITA46.11 standard, support IPMB bus and Ethernet data interface, monitor the voltage, current and temperature of each key node of the VPX chassis and provide overvoltage, overcurrent and overtemperature power-off protection.

[0025] 5) The number and slot positions of A, B, and C boards can be adjusted according to different application scenarios and requirements, or other boards that conform to the VPX architecture can be added; 6) All VPX cards support hot-swapping.

[0026] (2) The three types of heterogeneous computing boards, A, B, and C, need to have the core computing capabilities to handle typical underwater acoustic signal processing workloads, and reserve sufficient computing power expansion space through modular heterogeneous architecture design to meet the growing computing resource requirements of future intelligent underwater acoustic signal processing algorithms. The three types of boards have the following technical features: 1) Class A boards contain a CPU processor chip and two GPU processor chips, interconnected via PCIe 4.0, with a transmission bandwidth of up to 72Gbps between the CPU and GPU processors. The CPU processor has at least 8 cores, a clock speed of at least 2.0GHz, a floating-point processing power (FP32) of at least 256GFlops, and a typical power consumption of 43W; each GPU processor has a clock speed of at least 1GHz, a floating-point processing power (FP32) of at least 16TFlops, and an average power consumption of 75W. Class A boards are suitable for application scenarios where multiple applications run simultaneously on a single board and require physical isolation.

[0027] 2) Class B boards contain a CPU processor chip and a GPU processor chip, interconnected via PCIe 4.0, with a transmission bandwidth of up to 26Gbps between the CPU and GPU processors. The CPU chip is the same as that of Class A boards. The GPU processor has a minimum clock speed of 1.5GHz, a minimum floating-point processing power (FP32) of 32TFLOPS, and an average power consumption of 150W. Compared to the GPU chip in Class A boards, the GPU processor in Class B boards has higher power consumption but also higher performance, supporting higher clock speeds and computing power, making it suitable for applications requiring higher GPU computing power for single-application operation.

[0028] 3) Class C boards contain a CPU processor chip and a GPU processor chip, interconnected via PCIe 4.0, with a transmission bandwidth of up to 28Gbps between the CPU and GPU. Its GPU chip is the same as that of Class B boards. The CPU processor has at least 32 cores, a clock speed of at least 2.5GHz, a floating-point processing power (FP32) of at least 1.2 TFlops, and a typical power consumption of 87W. Compared to the CPU chips in Class A / B boards, Class C boards have higher power consumption and higher performance, supporting higher clock speeds, more cores, and greater computing power, providing superior low latency and complex logic processing capabilities.

[0029] (3) The system data transmission is realized by adopting a dual-bus switching architecture consisting of standard Ethernet and SRIO (Serial RapidIO) interconnection.

[0030] Each VPX board is equipped with a domestically produced Ethernet controller and a domestically produced SRIO bridge chip, which are interconnected with the processor and VPX connector respectively through PCIe bridging chips. The Ethernet controller supports multiple interface configurations such as 1Gbps, 10Gbps and 40Gbps, and the SRIO bridge chip provides 20Gbps transmission bandwidth. The two interfaces can be used independently or in combination to build a multi-level data transmission channel covering chassis, board, and chip levels.

[0031] The network communication interfaces strictly adhere to the VPX backplane Ethernet standard, with each board providing two 1Gbps interfaces, four 10Gbps interfaces, and one 40Gbps interface. The 1Gbps interfaces are dedicated to IPMI health management and debugging functions, the 10Gbps interfaces handle medium-to-high-speed data transmission, and the 40Gbps interface is designed for high-volume data transmission scenarios such as chassis interconnects.

[0032] The SRIO communication interface fully complies with the SRIO 2.0 specification and is specifically optimized for high-bandwidth, low-latency transmission requirements. Each board provides at least two SRIO interfaces, primarily serving high-speed data exchange between boards within the chassis, ensuring deterministic data transmission for real-time signal processing tasks.

[0033] (4) Encapsulated message middleware software realizes unified distribution of system data and communication management.

[0034] The message middleware conforms to the DDSI-RTPS (Data Distribution Service Interoperability Real-Time Publish-Subscribe Protocol) standard, supports QoS-driven data distribution, and can communicate across platforms and components.

[0035] The message middleware organizes all participating boards into a global data space, containing topics, data objects, data publishers, and data subscribers. It automatically establishes publisher-subscriber connections and controls data transmission behavior. Within this data space, each board's computing resources are organized into data objects, publisher nodes, and subscriber nodes. Applications on each node do not communicate directly but interact by subscribing to and publishing data objects. First, publisher and subscriber applications establish communication by joining a data space through a specific topic. Then, the publisher places data objects into a data writer, which, according to the data transmission behavior strategy, places the data into a sending queue or history cache. Subscribers receive data objects from a data reader, which similarly places the data into a receiving queue or history cache according to the same strategy. Subscriber applications perform calculations or processing on the received data objects and transmit the results as new data objects to the new subscriber in another publisher-subscriber pair. Through the transmission and processing of data objects across multiple publisher-subscriber pairs, the entire signal processing algorithm's chain-like flow is completed.

[0036] Although the three types of heterogeneous computing boards (A, B, and C) differ in hardware architecture and resource configuration, this middleware effectively shields the underlying hardware heterogeneity by introducing logical entities such as topics, data objects, data publishers, and data subscribers. Through a standardized data transmission control mechanism, a chain-like pipeline for processing data objects can be built across multiple heterogeneous boards. When the type or number of computing boards in the system changes, this architecture maintains the stability of the application architecture, enabling flexible configuration of hardware resources and smooth expansion of system functions.

[0037] This invention addresses the problems of low modularity, poor compatibility of intelligent algorithm ecosystems, and rigid computing power configuration faced by current underwater acoustic signal processing platforms. It proposes a heterogeneous computing platform for underwater acoustic signal processing, the advantages of which are: (1) Through the flexible combination of three types of heterogeneous computing boards, A, B and C, the platform can adapt to the needs of all scenarios from traditional underwater acoustic signal processing to intelligent algorithm applications without changing the hardware architecture. This modular design not only ensures that the platform has the training and reasoning capabilities of intelligent algorithms such as deep reinforcement learning, but also realizes the on-demand configuration of computing resources, which significantly improves the adaptability and scalability of the platform for different underwater acoustic signal processing tasks.

[0038] (2) Based on the standardized network architecture, SRIO communication interface and message middleware software, a complete hardware and software decoupling system was constructed. This design realizes flexible scheduling of data resources, rapid migration and dynamic reconstruction of platform failures, and greatly improves the replaceability of hardware and the reusability of software. Through the modular equipment decoupling scheme, the platform maintains high performance while significantly reducing maintenance complexity, providing reliable technical support for the continuous evolution of equipment.

[0039] In another embodiment of the present invention, a specific implementation method is described using a signal processing platform as an example.

[0040] like Figure 1 As shown, this configuration includes 10 boards: two power supply boards are installed in slots DY1 and DY2, one CPU computing board is installed in slot 1 (X1), one Type A board is installed in slot 2 (X2), two Type C boards are installed in slots 3 (X3) and 11 (X11), one SRIO switch board is installed in slot 6 (X5), one Ethernet switch board is installed in slot 7 (X5), and two Type B boards are installed in slots 9 (X9) and 10 (X10).

[0041] The SRIO switch board provides SRIO communication between the chassis and the external environment, while the Ethernet switch board provides network communication between the chassis and the external environment, as well as IPMI management functionality. All boards are equipped with 40G / 10G / 1G Ethernet interfaces, RapidIO interfaces, and management and monitoring interfaces to enable network communication, SRIO communication, and IPMI management between boards.

[0042] Figure 2 The schematic diagram applies to Type A, Type B, and Type C boards. The differences between the three types of computing boards lie in the specifications / number of GPU chips connected to the CPU chip and the number / capacity of onboard DDR memory chips. Each CPU+GPU heterogeneous computing board contains one CPU processor and one or two GPU processors, with each GPU interconnected to the CPU via a PCIe 4.0 bus. The CPU processor is also connected via the PCIe bus to an Ethernet chip, an SRIO bridge, DDR memory chips of varying capacities, a management and monitoring BMC chip, and other PCIe peripheral chips. The software running on all three types of computing boards includes standardized networking, a standardized SRIO communication interface, and message middleware.

[0043] The message middleware utilizes standardized Ethernet and SRIO links to organize all participating computing boards into a global data space. The computing resources of each board are organized into data objects, publisher nodes, and subscriber nodes, interacting through subscribing to and publishing data objects. Although Type A, Type B, and Type C boards have different architectures and hardware resources, the message middleware masks these hardware differences and establishes a chained process for processing data objects across multiple heterogeneous computing boards by controlling the data transmission behavior between them. Even if the type and / or number of computing boards changes, the message middleware maintains the chained process unit of topics, data objects, data publishers, and data subscribers, and the publisher and subscriber applications at each node in the chained process do not need to be aware of the hardware differences between the computing boards.

[0044] Changes in the type and / or number of computing boards may alter the topology of nodes in the global data space organized by the message middleware (e.g., due to changes in the number of publisher / subscriber nodes). However, within each publisher / subscriber node, the data objects they receive, process, and send remain the same, thus requiring no changes to the publisher and subscriber applications. The underlying libraries used by the publisher and subscriber applications to adapt to CPU / GPU may need to be replaced accordingly, but the application's processing procedures and software architecture remain unchanged.

[0045] The schematic diagram of the message middleware principle of this invention is as follows: Figure 3 As shown, the global data space comprises multiple data spaces (data space 1, data space 2, data space 3, and data space 4 are shown). Within each data space, publisher nodes and subscriber nodes communicate through specific topics. A data space can contain any number of publisher and subscriber nodes. Publisher / subscriber nodes can be CPU processors running message middleware, or publisher / subscriber applications running on them. The same CPU processor can act as both a publisher node and a subscriber node.

[0046] like Figure 3 As shown in the lower left part, the communication process of a pair of publisher-subscriber nodes in the data space is as follows: First, the publisher node / application and the subscriber node / application establish communication by each joining a specific data space by publishing a specific topic and subscribing to the same topic. Then, the publisher sends a data object, which can only be obtained by subscribers who have joined the specific topic. The data object is processed to obtain the data result, and finally the data result is sent as the data object of the next publisher node.

[0047] exist Figure 3In the example, the data processing chain involving multiple boards is as follows: The CPU computing board and the Type A board are added to data space 1. The CPU computing board, as publisher node 10, sends data objects, and the Type A board, as subscriber node 11, receives the data objects. The results are obtained through two GPU processors and sent back to the CPU processor. The Type A board is added to data space 2 and, as publisher node 20, sends the results (data objects). Two Type B boards are added to data space 2 and, as subscriber nodes 21 and 22 respectively, receive the data objects. The results are obtained through the GPU processors and sent back to the CPU processor. Two Type B boards are added to data space 3 and, as publisher nodes 30 and 31 respectively, send the results (data objects). The Type C board is added to data space 3 and, as subscriber node 32, receives the data objects. The results are obtained through the GPU processors and sent back to the CPU processor. The Type C board is added to data space 4 and, as publisher node 40, sends the results. The interactive board is added to data space 4 and, as subscriber node 41, receives the data. Although there are different types of computing boards, these boards communicate based on the same publisher-subscriber model. Programs running on the boards that perform signal processing tasks do not need to be aware of the hardware differences between the computing boards, and can form a chain process to collaboratively complete complex signal processing tasks.

[0048] The data flow of a typical signal processing task is as follows: Figure 4 As shown, the VPX chassis first receives the acquired data, which has a bandwidth of 36Gbps and needs to be received through the chassis's external 40Gbps network interface. Then, data preprocessing is performed, rearranging or compensating the data according to the array spatial position; this processing is suitable for CPU computing boards. Next, calculations are performed using Algorithms 1, 2, and up to Algorithm 4, which include logical operations and parallel computing; this processing is suitable for CPU+GPU heterogeneous boards. Finally, the processing results are obtained, and the results are graphically displayed and stored through a human-machine interface; this processing is suitable for cache boards. Communication between all boards within the chassis is based on a 10Gbps network and message middleware, while communication between the CPU and GPU processors within the computing boards is based on the PCIe bus. The specific signal processing flow is as follows: Step 1: The CPU computing board located in the first slot (X1) receives the collected data through the rear 40G Ethernet interface, processes the data, and then transmits the data to the A-type board in the second slot (X2) through the four 10G Ethernet interfaces in the VPX chassis. Step 2: In the Type A card of the second slot (X2), the amount of data is large at this time. The CPU processor splits the received data into two parts and transmits the data to the two GPU processors through the PCIe bus for Algorithm 1 calculation. After the GPU processor completes the calculation, it sends the result back to the CPU processor. At this time, the amount of data remains the same and still requires 40G bandwidth. In order to meet the bandwidth requirements, the CPU processor transmits the data to the Type C card of the third slot (X3) through the four 10G Ethernet aggregated into a 40G bandwidth network interface in the VPX chassis. Step 3: Algorithm 2, performed on the C-type card in the third slot (X3), is a traditional general algorithm with low complexity. Calculations show that the C-type card can meet the task cycle requirements. Similarly, the CPU transmits data to the GPU via the PCIe bus for computation. After completing Algorithm 2, the GPU returns the result to the CPU, reducing the amount of output data. The CPU can then transmit data to the calculation card for Algorithm 3 via a single 10G Ethernet interface.

[0049] Step Four: In the Type-B board of the ninth slot (X9), a relatively complex Algorithm Three needs to be performed. Calculations show that to meet the system's cycle time requirements, two Type-B boards' GPU processors are needed for computational support. Therefore, each of the two Type-B boards completes a portion of the Algorithm Three task and collaborates to complete all the calculations required for Algorithm Three. Data is calculated in the Type-B boards of the ninth slot (X9) and the tenth slot (X10), respectively, and the calculation results are sent back to the CPU processor. Subsequently, the CPU processors of the two Type-B boards transmit the data to the Type-C board of the eleventh slot (X11) via 10G Ethernet. At this point, the computational power required for Algorithm Four only needs to be met by one Type-C board. After the calculation is completed, the CPU processor of the Type-C board transmits the data to the cache board of the twelfth slot (X12) via 10G Ethernet and displays the algorithm processing results graphically.

[0050] In Algorithm 1, after the data is collected at the wet end, the preprocessed data is filtered, noise suppressed, and signal enhanced. Algorithm 2 corresponds to the preprocessed beamforming process; Algorithm 3 is feature extraction. After beamforming, feature extraction is performed. Feature extraction has a high computational dimension, so two CPUs are used and two CPUs are controlled separately. Algorithm 4 is relatively simple. It is for target recognition or target tracking and only requires logical operations, so it only requires one CPU + GPU.

[0051] The system continuously executes steps one through four, processing and graphically displaying the collected data. Simultaneously, the IPMI management system monitors key statuses of the entire chassis in real time, including temperature, voltage, and current. Algorithms one through four are processed in parallel on various computing boards, achieving a pipelined processing flow. Subsequent algorithms can begin processing without waiting for the results of previous algorithms on the same data, maximizing data processing efficiency.

[0052] In the signal processing of the above scenario, one Type A board, two Type B boards, and two Type C boards were used. In another application scenario, due to optimization of the processing algorithm, the method of Algorithm 2 running in the Type C board in the third slot (X3) was improved. Accordingly, a higher-precision Algorithm 5 was needed to replace the current Algorithm 2 to achieve a higher target signal-to-noise ratio. However, the increased computational complexity of Algorithm 5 resulted in insufficient computing power for the Type C board. Calculations showed that one Type B board could meet the cycle time requirements of Algorithm 5 in this system.

[0053] Therefore, after deploying the Algorithm 5 application software on a new Type B board, Figure 1 The C-type card in the third slot (X3) of the VPX chassis is removed and replaced with this new B-type card. After the B-type card is powered on and begins normal operation, it runs the Algorithm 5 application software, creating new middleware publisher and subscriber nodes. The middleware data space immediately detects this new participant and automatically establishes a connection. The subsequent signal processing flow is as follows: Step 1: The CPU computing board located in the first slot (X1) receives the data collected by the wet end through the rear 40G Ethernet interface, processes the data, and then transmits the data to the A-type board in the second slot (X2). Step 2: In the Type A card of the second slot (X2), the CPU processor splits the received data into two parts and transmits the data to the two GPU processors through the PCIe bus for Algorithm 1 calculation. After the GPU processor completes the calculation, it sends the result back to the CPU processor, and the CPU processor then transmits the data to the Type B card of the third slot (X3). Step 3: The result data of Algorithm 1 will be received by the new Type B board subscriber in the third slot (X3). In this board, the CPU processor transmits the received data to the GPU processor for calculation via the PCIe bus. After the GPU processor completes the calculation of Algorithm 5, it sends the result back to the CPU processor. The CPU processor then transmits the data to the calculation board of Algorithm 3 via 10G Ethernet.

[0054] Step 4: Execute Algorithm 3 on the Type B boards in slots 9 (X9) and 10 (X10). Each Type B board completes a portion of the Algorithm 3 task and collaborates to complete all the calculations required for Algorithm 3. Data is calculated on the Type B boards in slots 9 (X9) and 10 (X10) respectively, and the calculation results are sent back to the CPU processor. Subsequently, the CPU processors of the two Type B boards transmit the data to the Type C board in slot 8 (X8) via 10G Ethernet. At this point, the computing power required for Algorithm 4 only needs to be met by one Type C board. After the calculation is completed, the CPU processor of the Type C board transmits the data to the cache board in slot 12 (X12) via 10G Ethernet and displays the algorithm processing results graphically.

[0055] The system continues to execute steps one through four. Simultaneously, the IPMI management system monitors the critical status of the entire chassis in real time, including temperature, voltage, and current.

[0056] The above provides a detailed description of a heterogeneous computing platform for underwater acoustic signal processing provided by embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A heterogeneous computing platform for underwater acoustic signal processing, characterized in that, include: A chassis based on the VPX standard with an integrated backplate, which has multiple slots compliant with the VITA46 standard. Several functional boards plugged into the slots include power boards, CPU boards, cache boards, switching boards, and at least one heterogeneous computing board; The heterogeneous computing boards include type A boards, type B boards and type C boards, which use different combinations of CPU and GPU chips to form a tiered computing power system. The platform also includes a dual-bus switching architecture, including Ethernet and SRIO dual buses, for data transmission between boards, between chassis, and at the chip level; The platform also includes an encapsulated message middleware that conforms to the DDSI-RTPS standard, used to build a global data space and enable data publishing and subscription between heterogeneous boards.

2. The platform according to claim 1, characterized in that, The Type A board includes one CPU processor chip and two GPU processor chips, interconnected via a PCIe 4.0 bus; The CPU processor has no fewer than 8 cores, a clock speed of no less than 2.0 GHz, and a floating-point processing power of no less than 256 GFlops; Each GPU processor has a clock speed of no less than 1GHz and a floating-point processing capability of no less than 16 TFlops; the Type A board is suitable for scenarios where multiple applications run in parallel and require physical isolation.

3. The platform according to claim 1, characterized in that, The Type B board includes a CPU processor chip and a GPU processor chip, which are interconnected via a PCIe 4.0 bus; Its CPU processor chip is the same as that of the Type A board, and its GPU processor has a main frequency of no less than 1.5GHz and a floating-point processing power of no less than 32TFlops; The Type B board is suitable for scenarios where a single application is running and high GPU computing power is required.

4. The platform according to claim 1, characterized in that, The C-type board includes a CPU processor chip and a GPU processor chip, which are interconnected via a PCIe 4.0 bus; Its GPU processor chip is the same as that of the Type B board, and its CPU processor has no less than 32 cores, a main frequency of no less than 2.5GHz, and a floating-point processing power of no less than 1.2 TFlops; The C-type board is suitable for scenarios requiring high-complexity logic processing capabilities.

5. The platform according to any one of claims 1 to 4, characterized in that, In the dual-bus switching architecture, the Ethernet interface includes three speed configurations: 1Gbps, 10Gbps, and 40Gbps. Each board provides at least two 1Gbps interfaces for IPMI management, four 10Gbps interfaces for medium-to-high-speed data transmission, and one 40Gbps interface for chassis interconnection; The SRIO interface conforms to the SRIO 2.0 specification, with at least two channels configured on each board, and a transmission bandwidth of no less than 20Gbps, for low-latency data transmission between boards.

6. The platform according to claim 5, characterized in that, The message middleware constructs a global data space through topics, data objects, publishers, and subscribers; Applications on each board communicate by subscribing to and publishing data objects, without needing to be aware of the underlying hardware differences; The middleware supports QoS policy control of data transmission behavior and supports data writers, data readers, send queues, and historical caching mechanisms.

7. The platform according to claim 6, characterized in that, The CPU board includes a high-performance CPU processor and an Ethernet controller, providing at least one 40Gbps communication interface; The cache board includes a high-performance CPU processor and a high-speed NVMe storage module with two XMC interfaces; The power supply board supports +12V and +3.3V AUX DC input and has surge current suppression function.

8. The platform according to claim 7, characterized in that, Each functional board integrates a domestically produced chassis management and monitoring chip, supports the IPMI 2.0 standard protocol, and complies with the VITA46.11 standard; The monitoring chip provides USART, UART, I²C, I²S, SPI, and CAN peripheral interfaces, and supports IPMB bus and Ethernet data interface; It is used to monitor the voltage, current and temperature of the board in real time, and provides overvoltage, overcurrent and overtemperature power-off protection.

9. The platform according to claim 8, characterized in that, All functional boards support hot-swapping; The platform supports dynamic system reconfiguration and functional expansion by adjusting the number and slot positions of Type A, Type B, and Type C boards. After the board is replaced, the message middleware automatically discovers the new node and establishes communication, without requiring any modifications to the application.

10. The platform according to claim 9, characterized in that, When the platform is used for underwater acoustic signal processing tasks, it supports the following data processing flow: The CPU board receives the collected data via a 40G Ethernet interface; The data is processed in parallel using Algorithm A via the Type A board; The processing results are transmitted to the C-type or B-type board to execute Algorithm 2, Algorithm 3, and Algorithm 4 in sequence; The final result is transmitted to the cache board for storage or graphical display; The algorithms are executed in parallel on different boards, forming a pipelined processing architecture; The IPMI management system monitors the system status in real time.

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