A semiconductor yield analysis optimization method, system, device and medium based on multi-module cooperation

Abstract

The present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor yield analysis optimization method, system, device and medium based on multi-module cooperation; first, a data collection and integration module is used to collect multi-type data of the whole process of semiconductor manufacturing, and cleaning, standardization and integration processing are performed; second, based on the integrated data, a comprehensive yield analysis model is constructed through historical data statistical analysis and physical model simulation, and the key factors affecting yield are located; then, the analysis results and the expected yield are verified through design rule checking, electrical rule checking and yield prediction verification based on the model; finally, based on the verified analysis results, process parameter optimization and design optimization schemes are formulated and executed, and through a feedback iteration mechanism, continuous optimization is carried out to improve yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically, to a semiconductor yield analysis and optimization method, system, device, and medium based on multi-module collaboration. Background Technology

[0002] In semiconductor manufacturing, yield is a core indicator for measuring production efficiency and product quality, directly impacting a company's economic benefits and market competitiveness. Semiconductor manufacturing is complex, involving hundreds of processes such as photolithography, etching, deposition, and doping. The process parameters, equipment status, raw material properties, and environmental factors at each process can all lead to wafer defects, thus affecting yield.

[0003] Existing semiconductor manufacturing yield analysis and optimization technologies have several shortcomings: First, data is scattered and inconsistently formatted, with data from different processes and equipment stored in independent systems, lacking an effective integration mechanism and resulting in low data utilization. Second, yield analysis models are often singular, relying heavily on either statistical analysis or physical simulation, making it difficult to comprehensively cover the complex influencing factors in the semiconductor manufacturing process, leading to insufficient accuracy of the analysis results. Third, the yield verification process is disconnected from the analysis and optimization processes, with verification results failing to be promptly fed back to the analysis and optimization workflow, resulting in weak targeting of optimization solutions. Fourth, the optimization process lacks a closed-loop iterative mechanism, making it difficult to dynamically adjust optimization strategies based on actual production results, resulting in poor optimization efficiency and effectiveness.

[0004] Therefore, there is an urgent need for a semiconductor yield analysis and optimization system and method that can achieve efficient data integration, multi-dimensional accurate analysis, comprehensive verification, and closed-loop iterative optimization to solve the problems existing in the current technology. Summary of the Invention

[0005] This invention addresses the shortcomings of existing yield analysis methods, such as inefficient integration, multi-dimensional accurate analysis, comprehensive verification, and closed-loop iterative optimization. It proposes a semiconductor yield analysis and optimization method, system, equipment, and medium based on multi-module collaboration. By comprehensively integrating chip design and manufacturing process parameter data, and conducting in-depth analysis, verification, and optimization, it can identify potential manufacturing problems in chip design in advance and make timely adjustments, thereby improving chip manufacturability, reducing design changes and problems in the production process, and lowering production costs and product launch cycles.

[0006] The specific implementation details of this invention are as follows: A semiconductor yield analysis and optimization method based on multi-module collaboration specifically includes the following steps: Step S1: Collect various types of data from the entire semiconductor manufacturing process and integrate them to obtain integrated data; Step S2: Construct a multi-dimensional comprehensive yield analysis model based on the integrated data to generate a combination of process parameters that can guide mass production; Step S3: Calculate the predicted chip yield based on the combination of process parameters, and calculate the yield deviation, taking the design parameters and process parameters that have a significant impact on the yield as key factors; Step S4: Optimize semiconductor yield based on design parameters and process parameters.

[0007] To better realize the present invention, the specific operation of step S1 is as follows: to obtain the chip design data and process parameters in the production process, and to integrate them to obtain integrated data.

[0008] To better realize the present invention, step S2 further includes the following steps: Step S21: Obtain and analyze historical production data to obtain the correlation between key factors and parameters affecting chip yield, and determine the quantitative relationship between exposure dose and chip yield in the photolithography process through regression analysis; Step S22: Combining semiconductor physics principles, construct a physical model of the chip manufacturing process, call computer simulation technology to simulate the chip manufacturing process, and predict the chip performance and yield under different process conditions; Step S23: Combine the statistical analysis results based on historical data with the physical model and simulation results to establish a comprehensive yield analysis model; Step S24: Compare the key parameters output by the simulation with the test bonding data of the actual production in the wafer fab, and adjust the uncertain parameters in the model through sensitivity analysis to generate a combination of process parameters that can guide mass production.

[0009] To better realize the present invention, step S24 further includes the following steps: Step S241: Construct a sensitivity function based on the key parameters output by the simulation and the test bonding data from the actual production of the wafer fab; Step S242: Calculate the key parameters for the current combination based on the sensitivity function and the set learning rate; Step S243: Obtain the combination of process parameters based on the key parameters.

[0010] To better realize the present invention, step S3 further includes the following steps: Step S31: Based on the combination of process parameters and the comprehensive yield analysis model, obtain the predicted yield; Step S32: Calculate the yield deviation based on the predicted yield and the target yield; Step S33: If the yield deviation is greater than or equal to 0, then the current process parameters are considered reasonable; if the yield deviation is less than 0, calculate the sensitivity of the design parameters and process parameters to the yield, and take the parameters with larger absolute values ​​of sensitivity as the key factors affecting the yield.

[0011] To better realize the present invention, the specific operation of step S4 is as follows: optimize the production process parameters according to key factors, and determine the optimal value based on simulation to improve the process window and yield, and generate yield optimization suggestions.

[0012] Based on the aforementioned semiconductor yield analysis and optimization method based on multi-module collaboration, in order to better realize the present invention, a semiconductor yield analysis and optimization system based on multi-module collaboration is further proposed to execute the aforementioned semiconductor yield analysis and optimization method based on multi-module collaboration; including a data collection and integration module, a yield analysis model construction module, a yield verification module, and a yield optimization module; The data collection and integration module is used to collect multiple types of data from the entire semiconductor manufacturing process and integrate them to obtain integrated data. The yield analysis model construction module is used to construct a multi-dimensional comprehensive yield analysis model based on integrated data, and generate a combination of process parameters that can guide mass production. The yield verification module is used to calculate and predict chip yield based on the combination of process parameters, and to calculate yield deviation, taking design parameters and process parameters that have a significant impact on yield as key factors. The yield optimization module is used to optimize semiconductor yield based on design parameters and process parameters.

[0013] Based on the aforementioned semiconductor yield analysis and optimization method based on multi-module collaboration, in order to better realize the present invention, an electronic device is further proposed, including a memory and a processor; the memory stores a computer program; when the computer program is executed on the processor, the aforementioned semiconductor yield analysis and optimization method based on multi-module collaboration is implemented.

[0014] Based on the aforementioned semiconductor yield analysis and optimization method based on multi-module collaboration, in order to better realize the present invention, a computer-readable storage medium is further proposed, wherein computer instructions are stored on the computer-readable storage medium; when the computer instructions are executed on the aforementioned electronic device, the aforementioned semiconductor yield analysis and optimization method based on multi-module collaboration is realized.

[0015] The present invention has the following beneficial effects: (1) By comprehensively integrating chip design and manufacturing process parameter data, this invention can conduct in-depth analysis, verification and optimization, which can identify potential manufacturing problems in chip design in advance and make timely adjustments, thereby improving chip manufacturability, reducing design changes and problems in the production process, and reducing production costs and product launch cycle.

[0016] (2) The present invention is based on a yield analysis model of physical model and simulation, which can accurately predict the performance and yield of chip under different process conditions. By optimizing process parameters and design suggestions, it can ensure that the chip can achieve the expected performance and quality standards in actual production, thereby improving the yield and reliability of the chip.

[0017] (3) The feedback and iterative optimization mechanism of this invention enables the chip manufacturing process to be continuously improved and optimized. With the continuous accumulation of production data and the continuous improvement of analysis models, the manufacturability, performance and quality of chips can be continuously improved, thereby enhancing the competitiveness of enterprises. Attached Figure Description

[0018] Figure 1 This is a schematic flowchart of the semiconductor yield analysis and optimization method based on multi-module collaboration provided by the present invention. Detailed Implementation

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments, and therefore should not be regarded as a limitation on the scope of protection. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0021] Example 1: This embodiment proposes a semiconductor yield analysis and optimization method based on multi-module collaboration, which specifically includes the following steps: Step S1: Collect various types of data from the entire semiconductor manufacturing process and integrate them to obtain integrated data; The specific operation of step S1 is as follows: obtain the chip design data and process parameters during the production process, and integrate them to obtain integrated data.

[0022] Step S2: Construct a multi-dimensional comprehensive yield analysis model based on the integrated data to generate a combination of process parameters that can guide mass production; Step S2 specifically includes the following steps: Step S21: Obtain and analyze historical production data to obtain the correlation between key factors and parameters affecting chip yield, and determine the quantitative relationship between exposure dose and chip yield in the photolithography process through regression analysis; Step S22: Combining semiconductor physics principles, construct a physical model of the chip manufacturing process, call computer simulation technology to simulate the chip manufacturing process, and predict the chip performance and yield under different process conditions; Step S23: Combine the statistical analysis results based on historical data with the physical model and simulation results to establish a comprehensive yield analysis model; Step S24: Compare the key parameters output by the simulation with the test bonding data of the actual production in the wafer fab, and adjust the uncertain parameters in the model through sensitivity analysis to generate a combination of process parameters that can guide mass production.

[0023] Step S24 specifically includes the following steps: Step S241: Construct a sensitivity function based on the key parameters output by the simulation and the test bonding data from the actual production of the wafer fab; Step S242: Calculate the key parameters for the current combination based on the sensitivity function and the set learning rate; Step S243: Obtain the combination of process parameters based on the key parameters.

[0024] Step S3: Calculate the predicted chip yield based on the combination of process parameters, and calculate the yield deviation, taking the design parameters and process parameters that have a significant impact on the yield as key factors; Step S3 specifically includes the following steps: Step S31: Based on the combination of process parameters and the comprehensive yield analysis model, obtain the predicted yield; Step S32: Calculate the yield deviation based on the predicted yield and the target yield; Step S33: If the yield deviation is greater than or equal to 0, then the current process parameters are considered reasonable; if the yield deviation is less than 0, calculate the sensitivity of the design parameters and process parameters to the yield, and take the parameters with larger absolute values ​​of sensitivity as the key factors affecting the yield.

[0025] Step S4: Optimize semiconductor yield based on design parameters and process parameters.

[0026] The specific operation of step S4 is as follows: optimize the production process parameters based on key factors, and determine the optimal value based on simulation to improve the process window and yield, and generate yield optimization suggestions.

[0027] Working principle: This embodiment first collects various types of data from the entire semiconductor manufacturing process through a data collection and integration module, and then cleans, standardizes, and integrates the data. Secondly, based on the integrated data, a comprehensive yield analysis model is constructed through historical data statistical analysis and physical model simulation to identify key factors affecting yield. Then, the analysis results and expected yield are verified through design rule checks, electrical rule checks, and model-based yield prediction verification. Finally, based on the verified analysis results, process parameter optimization and design optimization schemes are formulated and implemented, and continuous optimization is achieved through a feedback iteration mechanism to improve yield.

[0028] Example 2: This embodiment is based on the above embodiment 1, such as... Figure 1 As shown, a specific embodiment will be used for illustration.

[0029] Step S1: Data collection and integration.

[0030] This module is used to collect various types of data throughout the entire semiconductor manufacturing process, and to clean, standardize, and integrate the collected data to provide high-quality data support for subsequent yield analysis, verification, and optimization. It can interface with various equipment in the semiconductor manufacturing process (such as lithography machines, etching machines, deposition equipment, etc.), testing equipment (such as defect detection equipment, electrical performance testing equipment, etc.), and production management systems to achieve real-time data acquisition and batch import. The types of data collected include, but are not limited to: process parameter data (such as lithography dose, etching time, deposition temperature, etc.), equipment status data (such as equipment operating power, pressure, speed, etc.), raw material parameter data (such as wafer material, photoresist viscosity, etc.), defect data (such as defect location, type, size, etc.), electrical performance data (such as resistance, capacitance, leakage current, etc.), and production environment data (such as workshop temperature, humidity, cleanliness, etc.).

[0031] Chip design data collection. This involves collecting the chip's circuit design data, including transistor-level schematics and logic gate-level netlists. This data details the chip's functionality and logic structure. Simultaneously, it includes collecting the chip's layout design data, such as GDSII files, which contain the chip's physical layer placement and routing information, including the location and shape of each component and the routing of metal interconnects.

[0032] Production process parameter collection. This involves acquiring various process parameters during production, such as exposure dose and focal length in photolithography, etching rate and etch selectivity in etching, and implantation energy and implantation dose in ion implantation. These process parameters directly affect the quality and precision of each stage of chip manufacturing.

[0033] Integrate multi-source data. Integrate collected chip design data and manufacturing process parameter data to establish a unified data model. Through data mapping and correlation, each element in the design data is correlated with its corresponding manufacturing process parameter, providing a comprehensive and accurate data foundation for subsequent analysis and verification.

[0034] Step S2: Construction of yield analysis model.

[0035] Based on the integrated data output from the data collection and integration module, a multi-dimensional comprehensive yield analysis model is constructed to accurately pinpoint key factors and weak links affecting semiconductor yield. This module improves the comprehensiveness and accuracy of yield analysis by integrating various analytical methods such as historical data statistical analysis and physical model simulation. Specifically, this includes: conducting statistical analysis based on historical production data to uncover the correlation between various parameters and yield; constructing physical models of key semiconductor manufacturing processes to simulate the process effects under different parameter combinations; and combining the statistical analysis results with the physical simulation results to establish a comprehensive yield analysis model, enabling quantitative analysis and precise positioning of factors affecting yield.

[0036] Statistical analysis based on historical data. A large amount of historical production data was collected, including chip design parameters, actual manufacturing process parameters, and corresponding chip yield data. Statistical methods were used to analyze this data to identify key factors affecting chip yield and the correlations between parameters. Regression analysis was used to determine the quantitative relationship between exposure dose in the photolithography process and chip yield.

[0037] Physical Modeling and Simulation. A physical model of the chip manufacturing process is constructed based on semiconductor physics principles. Computer simulation technology is used to simulate the chip manufacturing process and predict chip performance and yield under different process conditions.

[0038] A comprehensive yield analysis model was established. This model combines statistical analysis results based on historical data with physical model and simulation results to create a comprehensive yield analysis model. This model reflects the complex relationship between chip design, manufacturing process parameters, and chip yield.

[0039] Adjust the model's uncertainty parameters. Compare key parameters from the simulation output (such as linewidth deviation and etching depth uniformity) with test bond data from actual wafer fab production. Adjust the uncertainty parameters in the model through sensitivity analysis (SA). The specific process is as follows: 1. Define the sensitivity function Let the simulation model be ,in To output the key parameter vector, This represents the model parameter vector. Sensitivity function. It can be defined as: in, It is the first One key parameter, It is the first Each model parameter. Calculated... It can quantify the degree of influence of each parameter on key output parameters, thereby identifying uncertain parameters that need to be adjusted.

[0040] 2. Parameter Adjustment Strategy Based on the sensitivity analysis results, the gradient descent method is used to iteratively update the parameters: in, It is the first The first iteration Parameter values, For learning rate, For the target key parameter value, It is the output of the model at the k-th iteration. Key parameter values.

[0041] A multi-parameter collaborative optimization algorithm is established to automatically iterate the process window for yield targets, generating process parameter combinations that can guide mass production. The algorithm input is the initial process parameter combination. Yield target Parameter adjustment range The algorithm outputs the optimal combination of process parameters. The specific algorithm flow is as follows: Initialization: Let Yield obtained through simulation or pilot production Iterative optimization: Calculate the key parameters under the current parameter combination. Based on sensitivity analysis, parameters are adjusted to obtain candidate parameter combinations. right Perform boundary checks, if Then calculate the yield rate under this combination. like ,but Otherwise, keep , Termination condition judgment: If If the maximum number of iterations Kmax is reached, then the iteration stops. Otherwise, k = k + 1, return to step 2; By using the aforementioned sensitivity analysis method and multi-parameter collaborative optimization algorithm, precise adjustment of model parameters and optimization of process parameter combinations are achieved, ultimately generating process parameter combinations that can guide mass production.

[0042] Step S3: Yield verification.

[0043] Design Rule Check (DRC) checks the physical rules of the layout, such as linewidth and spacing, based on chip design rules and manufacturing process requirements to ensure that it meets the feasibility of manufacturing processes. Electrical Rule Check (ERC) verifies the correctness of connections and signal integrity in circuit design, and checks for problems such as short circuits and signal delays. Model-based yield prediction verification uses yield analysis models to predict the yield of chip design and manufacturing process parameters, compares it with the target yield to verify its rationality, and further analyzes potential problems if the prediction does not meet the target.

[0044] Design Rule Check (DRC). Based on chip design rules and manufacturing process requirements, the chip layout design is checked. The check includes physical rules such as linewidth, spacing, and overlap to ensure the layout design meets manufacturing process feasibility. For example, it checks whether the minimum linewidth of metal interconnects meets the resolution requirements of the photolithography process, and whether the spacing between different layers meets the precision requirements of the etching process.

[0045] Electrical compliance check (ERC). This involves performing an electrical compliance check on the chip's circuit design to verify the correctness of circuit connections and signal integrity. The check includes verifying for short circuits, open circuits, signal transmission delays, noise, and other issues. For example, circuit simulation tools can be used to check whether signal delays on critical signal paths are within the design's acceptable range.

[0046] Model-based yield prediction verification. Using the established yield analysis model, yield predictions are made for chip design and current manufacturing process parameters. The predicted results are compared with the target yield in actual production to verify the rationality of the chip design and manufacturing process parameters. If the predicted yield is lower than the target yield, the reasons are further analyzed to identify potential problems.

[0047] (1) Define the model inputs, outputs, and variables. Assume the chip design parameter vector is... The production process parameter vector is The comprehensive yield analysis model is ,in To predict chip yield, This is a nonlinear mapping function trained based on historical data (which can be constructed using machine learning algorithms such as neural networks and random forests). The target yield is denoted as... .

[0048] (2) Predict chip yield. This involves analyzing the chip's design parameters. and current production process parameters The data is input into the yield analysis model, which calculates and outputs the predicted chip yield using the formula described above. Then, the predicted chip yield will be... Compared with the target yield in actual production Compare them. If This indicates that the current chip design and manufacturing process parameters are reasonable; if Then, we further analyze the model output results to verify the algorithm process: Step 1: Data Input: Input the chip design parameters and production process parameters As input to the model.

[0049] Step 2: Yield Prediction: Predict the yield rate using the model. This calculation process can be based on the parameter matrix and activation function (such as the weight matrix in a neural network) obtained from model training. and bias ,calculate ,in (The activation function).

[0050] Step 3: Comparison and Verification: Calculate the yield deviation .

[0051] like If so, then the current parameters are reasonable; like Sensitivity analysis algorithms, such as backpropagation in gradient descent, are used to calculate the gradient of parameters with respect to yield. Identify the design parameters that have a significant impact on yield. and process parameters As a key factor, potential problem points can also be located through the intermediate layer features of the model output, such as the output of the hidden layer of the neural network.

[0052] Calculate the sensitivity of each design parameter and process parameter to yield, identify parameters with larger absolute values ​​of sensitivity as key factors affecting yield, locate potential problem points, and provide a basis for subsequent yield optimization.

[0053] Step S4: Yield optimization.

[0054] Based on yield analysis results, production process parameters are optimized. For example, for key parameters such as exposure dose in the photolithography process, the optimal values ​​are determined through experiments and simulations to improve the process window and yield. At the same time, optimization suggestions are provided for chip design, such as adjusting the layout of compact areas in the layout, increasing spacing, or optimizing wiring to improve manufacturability. The yield optimization results are then fed back to chip design and manufacturing processes. Through continuous feedback and iteration of models and data, the manufacturability, performance, and quality of chips are continuously improved, achieving a continuous improvement in yield.

[0055] Process parameter optimization. Based on the results of yield analysis and verification, production process parameters are optimized. By adjusting process parameters, the process window in chip manufacturing is improved, thereby increasing chip yield. For example, if it is found that the exposure dose in the photolithography process has a significant impact on yield, and the current exposure dose is at the edge of the process window, the optimal exposure dose value is found through experiments and simulations to improve the photolithography quality and yield of the chip.

[0056] Design optimization recommendations. Provide optimization suggestions for chip design to improve manufacturability and yield. For example, if certain areas in the layout design are found to be too compact, making them prone to process defects during manufacturing, it is recommended to adjust the layout of these areas, increasing appropriate spacing or optimizing the routing method.

[0057] Feedback and Iterative Optimization. The results of yield optimization are fed back into chip design and manufacturing processes for a new round of design and production. Through continuous feedback and iterative optimization of models and data, the manufacturability, performance, and quality of chips are gradually improved, achieving a continuous increase in chip yield.

[0058] The above optimization process can be performed by modeling and optimizing as follows: 1. Manufacturing data modeling; The yield optimization results are fed back into chip design and manufacturing processes for a new round of design and production. During this new production cycle, chip design data continues to be collected. Production process parameters And chip yield data Y, the actual chip yield is The yield predicted by the yield analysis model is The design data set is SD, the production process parameter set is SP, and the yield data set is SY. These data are then fed back to the data collection and integration module and the yield analysis model construction module.

[0059] 2. Construct a yield analysis model; The gradient descent algorithm is used to optimize the yield analysis model. Assume the yield analysis model is... ,in These are the model parameters.

[0060] 3. Define the loss function; The mean squared error (MSE) is used as the loss function to measure the difference between the predicted yield and the actual yield. , in, For the number of data samples, The first The design parameters, manufacturing process parameters, and actual yield of each sample.

[0061] 4. Optimization Algorithm (Gradient Descent); The model parameters θ are updated using the gradient descent algorithm, with the iterative formula as follows: in, For learning rate, For the loss function in The gradient at that point.

[0062] 5. Optimization of manufacturing process parameters and chip design; Based on the updated model parameters The optimal production process parameters are found through optimization algorithms (such as genetic algorithms and particle swarm optimization algorithms). and chip design parameters This makes it possible to predict yield. maximize:

[0063] 6. Iterative optimization process; (1) Incremental data collection. In the new round of production, new design data is collected. Production process parameters and yield data Update the dataset .

[0064] (2) Model update. The yield analysis model is retrained using the updated dataset, and the model parameters are updated using the gradient descent algorithm. .

[0065] (3) Parameter optimization. Based on the updated model parameters Recalculate the optimal production process parameters and chip design parameters .

[0066] (4) Iterative process. Repeat the above steps of data collection, model update and parameter optimization to continuously optimize the manufacturing process and chip design and improve chip yield.

[0067] By analyzing and processing new data, we continuously improve the yield analysis model and further optimize production process parameters and chip design. Through a continuous feedback and iterative optimization mechanism from both model and data perspectives, we continuously improve the manufacturability, performance, and quality of chips, thereby achieving a continuous increase in chip yield.

[0068] The other parts of this embodiment are the same as those in Embodiment 1 above, so they will not be described again.

[0069] Example 3: This embodiment, based on any one of Embodiments 1-2 above, takes the data collection and integration implementation in a chip manufacturing project as an example for detailed explanation.

[0070] Step S1: Data collection and integration; First, professional design tools are used to obtain the chip's circuit design files and layout design files. For the circuit design files, circuit design software is used to read and parse the transistor-level circuit schematic and the logic gate-level netlist file to extract information such as circuit structure and device parameters. For the layout design files, the GDSII file is loaded using layout design software to obtain the chip's physical layout and routing information, including the position coordinates, shape and size of each device, and the paths of metal interconnects.

[0071] Simultaneously, process parameters during production are collected in real time through the monitoring system and data acquisition interface of the production equipment. For example, lithography equipment uses sensors to collect parameters such as exposure dose and focal length in real time and transmits this data to the data collection server. Etching equipment, ion implantation equipment, and other equipment also use similar methods to transmit their respective process parameters to the data collection server.

[0072] During the data integration process, this module employs pre-defined data mapping rules to convert data from different sources and formats (such as CSV, JSON, and XML) into a unified format. It also uses data cleaning algorithms to remove outlier data (such as data exceeding reasonable limits, duplicate data, and data lacking key information), while appropriately completing missing data (based on statistical characteristics of similar data or machine learning prediction models). Finally, the integrated data is stored in a distributed database, supporting fast querying and retrieval.

[0073] On the data collection server, data integration software is used to integrate the collected chip design data and manufacturing process parameter data. First, based on the device identifiers and their positions in the chip layout, the design data is associated with the corresponding manufacturing process parameters. Then, according to a predefined data model, the integrated data is stored in a database to provide data support for subsequent analysis and verification.

[0074] Step S2: Construction of yield analysis model; By integrating various analytical methods such as historical data statistical analysis and physical model simulation, the comprehensiveness and accuracy of yield analysis are improved. Specifically, this includes: conducting statistical analysis based on historical production data to uncover the correlation between various parameters and yield; constructing physical models of key semiconductor manufacturing processes to simulate the process effects under different parameter combinations; and combining statistical analysis results with physical simulation results to establish a comprehensive yield analysis model, enabling quantitative analysis and precise identification of factors affecting yield.

[0075] Step S21: Statistical analysis based on historical data; Production data from the past 100 batches of this chip manufacturing project were collected. The data was cleaned and preprocessed using Python's Pandas library and R's dplyr package to remove missing and outlier values. Statistical analysis was then performed using SPSS or MATLAB. Taking photolithography as an example, linear regression analysis revealed that chip yield is higher when the exposure dose is in the range of [180mJ / cm², 220mJ / cm²], reaching over 92% within this range. Specific details are as follows: Step S211: Referring to Step A, collect production data from the past 100 batches of this chip manufacturing project, covering the design parameters of each batch, such as transistor size and number of circuit layers, actual production process parameters (parameters for photolithography, etching, deposition, etc.), and the corresponding chip yield. In engineering implementation, the raw data is first cleaned and preprocessed using Python's Pandas library and R's dplyr package to remove missing and outlier values, ensuring data integrity and accuracy.

[0076] Step S212: Perform in-depth data analysis using SPSS statistical analysis software or MATLAB. Taking the optimization of exposure dose parameters in photolithography as an example, the specific implementation process is as follows: (1) Data modeling. The exposure dose was set as the independent variable and the chip yield was set as the dependent variable to construct a univariate linear regression model.

[0077] (2) Parameter setting. During the analysis, the scanning range of the exposure dose was set to 150-250 mJ / cm², with a step value of 5 mJ / cm², to ensure that the data covered the critical process window.

[0078] (3) Analysis Results. Regression analysis revealed a significant positive correlation between chip yield and exposure dose in the range of [180 mJ / cm², 220 mJ / cm²]. When the exposure dose was within this range, the chip yield could reach over 92%; however, when the exposure dose was below 180 mJ / cm², the yield dropped to around 85%; and when the exposure dose was above 220 mJ / cm², the yield was below 88%, mainly due to overexposure leading to pattern distortion or photoresist residue.

[0079] B2 physical model and simulation; Using specialized semiconductor device simulation software, a physical model of the chip manufacturing process is constructed based on the chip's design and manufacturing process parameters. For example, when simulating photolithography, the physical processes such as the exposure characteristics of the photoresist, light propagation, and scattering are considered, and the exposure pattern of the photoresist during photolithography is simulated through numerical calculations. When simulating etching, the physical processes such as the chemical reactions of etching gases and ion bombardment are considered, and the chip structure after etching is simulated. By simulating these physical processes, the chip's performance and yield under different process conditions are predicted. The operation process includes everything from selecting software tools and setting parameters to building and verifying the model, with each step refined to meet actual production requirements.

[0080] Step S221: Simulation software selection and parameter configuration; The mainstream semiconductor device simulation software, namely the TCAD tool suite, is selected. Based on the GDSII layout, device size parameters, and key parameters in the process manual output during the chip design stage, such as photoresist type and etching gas ratio, the process parameter library is customized in the software environment.

[0081] Step S222: Physical model construction and solution; (1) Photolithography process simulation. The vector lithography model is used to parameterize the exposure dose-development relationship (EDR curve) of the photoresist and construct the light field propagation equation in combination with Fresnel diffraction theory. The exposure process is numerically solved by the finite difference method (FDM) or the finite element method (FEM) to generate the three-dimensional contour data of the latent image after the photoresist exposure.

[0082] (2) Etching process simulation. Based on the reactive ion etching (RIE) mechanism, a chemical vapor phase reaction kinetic model and an ion bombardment energy transfer model are established. The Monte Carlo method (MC) is used to simulate the collision process between ions and the material surface, and the removal rate of the etching products is calculated by the molecular dynamics (MD) algorithm. Finally, the three-dimensional structure model of the etched chip is output.

[0083] Step S223: Verification and optimization of simulation results; Key parameters such as linewidth deviation and etching depth uniformity from the simulation output are compared with test key data from actual wafer fab production. Sensitivity analysis (SA) is used to adjust uncertain parameters in the model. A multi-parameter collaborative optimization algorithm is established to automatically iterate the process window for yield targets, generating process parameter combinations that can guide mass production.

[0084] Step S23: Establish a comprehensive yield analysis model; By combining statistical analysis results based on historical data with physical models and simulation results, a comprehensive yield analysis model is established. This model considers the impact of multiple design parameters and manufacturing process parameters on chip yield, and describes the relationships between them using mathematical formulas and algorithms. For example, parameters such as exposure dose and focal length in the photolithography process, and etching rate and etching selectivity in the etching process are used as input variables, with chip yield as the output variable. Multiple linear regression models or neural network models are then established to accurately predict chip yield under different process conditions.

[0085] Step S231: Data Acquisition and Preprocessing; (1) Build an automated data acquisition system with the help of step A to acquire process parameter data such as exposure dose and focal length in the lithography process and etching rate and etching selectivity in the etching process from wafer manufacturing equipment such as lithography machine and etching machine in real time, and record the corresponding chip yield detection results at the same time.

[0086] (2) Data cleaning algorithms are used to remove outliers and missing values. Missing data are processed by interpolation or mean filling techniques to ensure data quality.

[0087] Step S232: Model construction and algorithm implementation; (1) Construction of multiple linear regression model In a Python environment, a multiple linear regression model is built using the Scikit-learn library. First, the original process parameter data is cleaned, outliers are removed, and missing values ​​are imputed. Z-score normalization is used to scale the data to a uniform scale, avoiding the impact of feature scale differences on model performance. The preprocessed process parameter data is used as the feature matrix X, and the chip yield data is used as the target vector y. The model is trained using the `fit` method of the `LinearRegression` class. During training, the model automatically calculates the regression coefficients for each process parameter, establishing a linear relationship of the form y = β0 + β1x1 + β2x2 + ... + βnxn. For example, when process parameters include multiple variables such as lithography exposure time, etching rate, and temperature, the model can quantify the impact of each parameter on chip yield.

[0088] We selected 1,000 batches of 8-inch wafer manufacturing data from a wafer fab in 2023, focusing on photolithography and etching processes. We substituted actual data into the algorithm process and demonstrated the yield prediction method through multiple linear regression and neural network models.

[0089] From the 2023 production data of a wafer manufacturing plant, 1000 batches of 8-inch wafer manufacturing data were randomly selected as a sample. The photolithography process had an exposure dose range of 180-220 mJ / cm², with focal length fluctuations within ±0.5 μm; the etching process had an etching rate of 500-700 Å / min, with etching selectivity of 3:1-5:1. These parameters were used as input variables, and chip yield as the output variable.

[0090] (2) Parameter modeling process of multiple linear regression model By fitting the data using the least squares method, the yield prediction formula was obtained as Y = 0.65 + 0.002X1 - 0.05X2 + 0.001X3 - 0.02X4 (where X1 is the exposure dose, X2 is the focal length, X3 is the etching rate, and X4 is the etching selectivity). Validated on the test set, the model's average prediction error was 4.2%. For example, when the exposure dose was 200 mJ / cm², the focal length was 0.3 μm, the etching rate was 600 Å / min, and the etching selectivity was 4:1, the model predicted a yield of 88.5%, while the actual yield was 87.8%.

[0091] A multilayer perceptron (MLP) neural network is built using TensorFlow or PyTorch frameworks. In terms of architecture design, the number of hidden layers (e.g., 2-3 layers) and the number of neurons are appropriately set based on the number and complexity of process parameters (usually determined using empirical formulas or cross-validation). The ReLU activation function is chosen, as it effectively alleviates the vanishing gradient problem and improves the network's learning efficiency. The mean squared error (MSE) loss function is used, which measures the squared error between the predicted and true values, providing direction for model optimization. The Adam optimizer is selected, combining the advantages of AdaGrad and RMSProp, enabling adaptive adjustment of the learning rate and accelerating model convergence. Process parameters are used as input layer data. The forward propagation algorithm calculates the predicted values, and the backpropagation algorithm calculates the gradient of the loss function with respect to the network weights, thereby adjusting the network weights to fit the complex nonlinear relationship between process parameters and chip yield.

[0092] (3) Neural network model construction process A three-layer fully connected neural network was employed, with four neurons in the input layer corresponding to four process parameters, ten neurons in the hidden layer, and one neuron in the output layer representing yield. Using the Adam optimizer with mean squared error as the loss function, after 500 iterations of training, the model's prediction error on the test set was reduced to 2.8%. For example, under a new combination of process parameters (exposure dose 195 mJ / cm², focal length -0.2 μm, etch rate 550 Å / min, etch selectivity 3.5:1), the neural network predicted a yield of 90.2%, while the actual production yield was 90.1%. These real-world data demonstrate how the comprehensive yield analysis model can accurately predict chip yield using algorithms.

[0093] B33 Model Validation and Optimization (1) The collected historical data is divided into training and test sets in an 8:2 ratio. To ensure the scientific nature and stability of the division, stratified sampling can be used to ensure that the training and test sets have similar data distributions. The trained model is validated using the test set. The prediction accuracy of the model is evaluated by calculating the mean squared error (MSE), coefficient of determination (R2), and mean absolute error (MAE). Among them, MSE reflects the square mean of the error between the predicted value and the true value. The smaller the value, the more accurate the model prediction. R2 is used to measure the goodness of fit of the model to the data. The value ranges from 0 to 1. The closer it is to 1, the better the model fit. MAE represents the mean absolute value of the error between the predicted value and the true value, which can intuitively reflect the average size of the prediction error.

[0094] (2) To address the issue of large prediction errors in the model, multiple optimization strategies were employed. On one hand, model parameters were adjusted, such as increasing or decreasing the number of hidden layers in the neural network, adjusting the number of neurons, or changing the activation function type. On the other hand, data preprocessing methods were optimized, different standardization methods were tried, or feature engineering was added, such as combining features of process parameters and extracting higher-order features. Through multiple iterations of training, combined with cross-validation, the accuracy of the model in predicting chip yield under different process conditions was comprehensively evaluated, ultimately yielding the best-performing prediction model.

[0095] Step S3: Yield verification.

[0096] Step S31: Design Rule Check (DRC); When performing Design Rule Check (DRC) checks on chip layout designs using specialized layout verification tools, these tools are typically based on a hierarchical data processing architecture and employ distributed storage and parallel computing technologies to improve processing efficiency. The tool decomposes the chip layout into geometric units and, combined with manufacturing process parameters such as photolithography, etching, and deposition stored in the process file, constructs a three-dimensional virtual manufacturing environment.

[0097] During the inspection process, the tool uses vector graphics algorithms to examine the physical rules of the layout, such as line width, spacing, and overlap. Specifically, it employs polygon intersection algorithms to accurately calculate the distances and coverage relationships between geometric shapes, and combines Monte Carlo simulation methods to assess the impact of process deviations on design rules. For example, when checking the minimum line width of metal interconnects, it not only verifies whether it is greater than or equal to the minimum line width achievable by the photolithography process, but also simulates line width variations under different process windows based on the photoresist exposure dose distribution model. When verifying the spacing between different layers, it comprehensively considers factors such as etching rate fluctuations and sidewall angle errors to determine whether the etching process accuracy requirements are met.

[0098] The tool's built-in AI algorithm can intelligently reason about complex rules. When a potential violation is detected, it automatically links to relevant design rule documents and historical case libraries, providing optimization suggestions. If a violation of design rules is found in the layout design, the tool will automatically locate the problem through a visual marking system, distinguishing the violation type with different colors and icons on the layout interface, and outputting detailed error information including coordinates, the violation rule clause number, and an impact analysis in the log file. Simultaneously, the tool supports data interaction with Electronic Design Automation (EDA) platforms, directly synchronizing issues to the designer's work interface for targeted modifications and verification.

[0099] From an engineering implementation perspective, it is necessary to clarify the specific implementation methods, system architecture, and data interaction processes for each stage. First, the integrated architecture of the layout verification tool will be introduced, followed by a detailed description of the implementation of the inspection process, including specific engineering details such as data input, rule matching, and error handling.

[0100] Step S311: Integration architecture of layout verification tools; Employing a modular design, the layout verification tool is deeply integrated with the chip design platform, enabling data interaction through standardized API interfaces. The core modules of the tool include a DRC rule engine, a layout data parser, and an error report generator. The layout data parser supports mainstream layout data formats such as GDSII and OASIS, ensuring accurate reading of chip layout information.

[0101] Step S312: DRC check implementation process; (1) Data preprocessing. After importing the chip layout design data into the verification tool, the data is converted and cleaned to establish an efficient layout data index structure, thereby improving the efficiency of subsequent inspections.

[0102] (2) Rule base loading and matching. Pre-built chip design rules and manufacturing process requirements are stored in the DRC rule base in the form of structured data. During inspection, the rule engine automatically matches the corresponding rules according to the layout element type (such as metal interconnects, vias, etc.). For example, for metal interconnects, the minimum linewidth parameter corresponding to the photolithography process is retrieved from the rule base, the linewidth of the metal interconnects in the layout is accurately measured by a geometric algorithm, and compared with the rule parameters; for the spacing check between different layers, the actual distance between the patterns of each layer is calculated using a spatial topology analysis algorithm to determine whether the etching process accuracy requirements are met.

[0103] (3) Error detection and marking. Once a violation of design rules is detected, the error detection module will mark the coordinates of the violation location in the layout data and record detailed information such as the violation type, the relevant rule clauses, and the specific error value in the error log. At the same time, the problem area will be highlighted in the visualization interface in a prominent way, such as highlighting and flashing, to facilitate the designer's location.

[0104] (4) Error Report Generation. The error report generator automatically generates structured error reports based on the error logs, supporting output in multiple formats such as HTML and PDF. The report not only includes the location of the problem and error information, but also provides rule explanations, historical solutions to similar problems, and other content to help designers quickly understand the problem and make modifications.

[0105] Step S32: Electrical Rule Check (ERC); Use circuit simulation tools to perform ERC checks on the chip's circuit design. During the check, import the circuit design file into the simulation tool and set appropriate simulation parameters, such as power supply voltage and signal frequency. Then, use the simulation tool to analyze the circuit, checking for electrical connection problems such as short circuits and open circuits, as well as signal transmission delays and noise. For example, when checking signal delay on critical signal paths, by setting the input waveform and transmission path parameters, the simulation tool can calculate the signal delay time on that path and compare it with the design-allowed delay time. If the signal delay exceeds the design-allowed range, the simulation tool will provide corresponding prompts so that designers can optimize the circuit.

[0106] Step S321: Tool integration and environment configuration; In engineering practice, circuit design files (such as .sch format schematic files) can be automatically imported into circuit simulation tools through script interfaces (such as Python scripts combined with simulation tool APIs), establishing project file association paths and enabling rapid loading of design files.

[0107] Configure the simulation parameter management module, which allows for quick access to standard parameters corresponding to different process nodes (such as power supply voltage 1.2V±5% and signal frequency range 1-5GHz under 14nm process) through the parameter template library, and supports batch import and version management of user-defined parameters.

[0108] Step S322: Automated simulation process; Construct an ERC inspection pipeline: Use Makefiles or scripting languages ​​to write automated scripts that sequentially execute steps such as circuit netlist extraction, simulation initialization, and simulation analysis. Implement unattended batch inspection tasks through the simulation tool's command-line interface (CLI), supporting multi-threaded parallel processing of multiple circuit modules.

[0109] Critical signal path identification: Based on design annotation information (such as timing constraints in SDF files), critical paths are automatically selected, the signal transmission path topology is extracted through the path tracing function of the tool, and the actual transmission line parameters are obtained by combining parasitic parameter extraction tools (such as StarRC) to achieve accurate simulation.

[0110] Step S323 Problem diagnosis and feedback mechanism; Establish a problem classification and coding system to standardize the coding of electrical connection problems such as short circuits and open circuits (error codes EC-001 to EC-010) and timing / signal integrity problems such as signal delays and noise (error codes SI-001 to SI-010) to facilitate subsequent problem statistics and analysis.

[0111] Develop a visualization report generation module that automatically converts the prompts output by simulation tools, such as excessive signal delay, into HTML / Excel format reports. The reports use color coding (red for serious problems and yellow for warnings) and hyperlinks (clicking the problem description directly jumps to the corresponding location in the design file) to help designers quickly locate and optimize circuits.

[0112] Step S33: Validation of model-based yield prediction; Using an established comprehensive yield analysis model, yield prediction is performed based on current chip design and manufacturing process parameters. The chip's design parameters and current manufacturing process parameters are input into the yield analysis model, which then calculates and outputs a predicted chip yield. The predicted yield is then compared with the target yield in actual production. If the predicted yield is higher than or equal to the target yield, it indicates that the current chip design and manufacturing process parameters are reasonable. If the predicted yield is lower than the target yield, the model output is further analyzed to identify key factors affecting yield and potential problems, providing a basis for subsequent yield optimization.

[0113] Step S331: Construction of the comprehensive yield analysis model; A comprehensive yield analysis model is constructed by integrating historical production data (including chip design parameters, process parameters, actual yield, and other multi-dimensional data) based on machine learning algorithms (such as random forests and support vector machines) and mathematical statistics. During the model training phase, a cross-validation strategy is used to optimize parameters, ensuring that the model has high prediction accuracy and generalization ability on both the training and test sets.

[0114] The model structure adopts a layered architecture design. The bottom layer is the data preprocessing layer, which normalizes the input data, fills in missing values, and detects outliers. The middle layer is the feature extraction layer, which uses methods such as principal component analysis (PCA) to mine key influencing factors. The top layer is the prediction and decision layer, which outputs the chip yield prediction results.

[0115] Step S332: Yield prediction execution process; Data Acquisition and Integration: By interfacing with Electronic Design Automation (EDA) systems and Manufacturing Execution Systems (MES), chip design parameters (such as circuit architecture, wiring rules, device dimensions, etc.) and current production process parameters (such as photolithography exposure dose, etching rate, thin film deposition thickness, etc.) are collected in real time and then standardized and integrated according to the model input format.

[0116] Predictive calculation: The integrated data is input into the trained yield analysis model. The model uses its built-in mathematical calculation engine and algorithm logic to perform feature mapping and nonlinear fitting on the input parameters, and finally outputs the predicted chip yield value.

[0117] Step S333: Yield Comparison and Decision-Making Mechanism; Comparative analysis: The predicted chip yield is numerically compared with the pre-set target yield (determined based on market demand, production costs, and industry standards), and the difference is quantified using a dual evaluation method of difference calculation and percentage deviation.

[0118] Decision-making and judgment: If the predicted yield is greater than or equal to the target yield, the system will automatically generate an analysis report stating that "the combination of design and process parameters is reasonable" and synchronize the results to the production scheduling system to support continuous production of the current plan.

[0119] If the predicted yield is less than the target yield, the system will initiate a deep analysis program: Key factor identification: Using the model’s feature importance assessment module, the model output is deconstructed, and sensitivity analysis is used to determine the key design and process parameters (such as lithography resolution, doping concentration, etc.) that affect yield.

[0120] Potential problem identification: By combining historical failure data with fault tree analysis (FTA), key factors are correlated with abnormal events in the production process to identify potential problem points (such as equipment parameter drift, environmental temperature and humidity fluctuations, etc.).

[0121] Step S334 yield optimization support; The system outputs a detailed yield optimization report, including the adjustment direction of key influencing factors, such as suggesting to increase the exposure dose of a certain photolithography layer by 5%, and solutions to potential problems, such as increasing the monitoring frequency of temperature and humidity sensors. It also displays the simulated yield improvement effect after parameter adjustment through a visual interface, providing process engineers and design teams with a scientific basis for optimization.

[0122] Step S4: Yield optimization; Step S41: Optimize process parameters; Based on the results from the yield verification module, it was found that the exposure dose in the current photolithography process was at the edge of the process window. Furthermore, the yield analysis model predicted that appropriately increasing the exposure dose could improve chip yield. Therefore, a series of experiments were conducted on the production line, gradually increasing the exposure dose, and the chips were inspected after each experiment to statistically analyze the chip yield. The experiments showed that when the exposure dose was increased to X3, the chip yield significantly improved. Therefore, the exposure dose in the photolithography process was adjusted to X3, and this optimized process parameter was applied to subsequent production.

[0123] Step S411: Yield Data Acquisition and Analysis. Sensors deployed on the wafer fabrication equipment collect exposure dose data in real time during the photolithography process, simultaneously gathering detection data from the chip manufacturing process. The yield verification module analyzes the collected data using a preset algorithm, calculating the deviation between actual production data and the theoretical value of the process window to determine if the current exposure dose is at the edge of the process window.

[0124] Step S412: Yield Prediction Modeling. Based on historical production data and process parameters, a yield analysis model incorporating multiple influencing factors is constructed. Machine learning algorithms are used to train the model, enabling it to predict chip yield trends based on changes in the input exposure dose parameter. The model prediction reveals that appropriately increasing the exposure dose can improve chip yield.

[0125] Step S413 Experimental Verification and Parameter Optimization (1) Set up an experimental environment on the production line and adopt a progressive experimental method. Set the initial exposure dose increment as ΔX and adjust the exposure dose to X1 (X1=current dose+ΔX), X2 (X2=X1+ΔX), and X3 (X3=X2+ΔX) in sequence.

[0126] (2) After each adjustment of the exposure dose, a batch of chips was produced as the experimental group, while chips produced under the same process conditions with the original exposure dose were retained as the control group.

[0127] (3) Automated testing equipment was used to conduct comprehensive testing on the chips of the experimental and control groups, including key dimension measurement and defect detection. The test results were processed using statistical analysis software to calculate the chip yield under different exposure doses.

[0128] Step S414: Process Parameter Update and Application. After experiments confirm that X3 significantly improves chip yield, X3 is entered as the new exposure dose value for the lithography process into the Manufacturing Execution System (MES). The MES system automatically sends the parameter to the lithography equipment's control system and sets up a parameter verification mechanism to ensure the equipment accurately executes the new exposure dose parameter in subsequent production. Simultaneously, a process parameter monitoring process is established to monitor the production process under the new parameters in real time and collect feedback data for continuous process optimization.

[0129] Step S415 refers to steps S411-S414 above. The actual calculation process is as follows: According to the detection data from the yield verification module, the current exposure dose in the photolithography process is 85 mJ / cm², which is at the upper edge of the critical position within this process window (75 mJ / cm²-95 mJ / cm²). Using a deep learning-based yield analysis model for simulation prediction, when the exposure dose is increased to 92 mJ / cm², the chip yield is expected to increase from the current 82.3% to 88.5%.

[0130] Based on the above predictions, a process optimization experiment was conducted on a 300mm wafer production line: the exposure dose was gradually increased in seven increments of 1 mJ / cm², with 100 wafers produced in each experiment. The chip critical dimension (CD) was inspected using an optical microscope, and functional testing was performed using automated test equipment (ATE). The chip yield under different exposure doses was statistically analyzed. Specific experimental data are shown in Table 1 below.

[0131] Table 1 Comparison of Experimental Data

[0132] Experimental results show that when the exposure dose is increased to 92 mJ / cm² (i.e., the X3 setting), the chip yield improves by 8.7 percentage points compared to the initial state, achieving a significant optimization effect. Therefore, the exposure dose in the photolithography process is officially adjusted to 92 mJ / cm², and all production equipment parameters are updated synchronously through the process control system to ensure the stable application of this optimized process in subsequent large-scale production. Simultaneously, a process monitoring mechanism is established to control the exposure dose fluctuation range within 91.5 mJ / cm²-92.5 mJ / cm² to ensure process stability.

[0133] Step S42: Design optimization suggestions; During yield verification, it was discovered that certain areas in the chip layout design, due to overly compact placement, were prone to incomplete etching during manufacturing, thus affecting chip yield. Based on this issue, optimization suggestions were provided to the chip design team, recommending adjustments to the layout of these areas and increasing appropriate spacing to improve the etching process. Following these suggestions, the design team modified the chip layout, re-performed DRC and ERC checks, and used a yield analysis model to predict the yield of the modified layout. The prediction results showed that the modified layout is expected to improve chip yield under current manufacturing process conditions.

[0134] During yield verification, the following engineering implementation techniques are used to solve chip layout design problems: Step S421: Defect Detection and Analysis. Microscopic imaging of the wafer surface is performed using an optical microscope (OM) and a scanning electron microscope (SEM). Combined with electron beam inspection (E-beam inspection) technology, incomplete etching areas are precisely located. Using a defect classification algorithm, the analysis concludes that the compact layout hinders etchant diffusion.

[0135] Step S422: Layout optimization implementation. Use professional layout design tools (such as Cadence Virtuoso, Synopsys IC Compiler) to interactively edit the problem areas. Use automated scripts to batch adjust the spacing of transistors and interconnects to ensure that the minimum spacing requirements of photolithography and etching processes are met (e.g., increasing the metal layer spacing from 0.18μm to 0.22μm).

[0136] Step S423: Design Rules and Electrical Verification. Based on the PDK (Process Design Kit) provided by the foundry, configure the DRC (Design Rule Check) rule file, focusing on checking whether the newly added spacing conforms to the process specifications. Simultaneously, use the ERC (Electrical Rule Check) tool to perform circuit connectivity and short / open circuit checks on the modified layout, shortening the verification time through incremental verification algorithms.

[0137] Step S424: Yield Prediction Modeling. Construct a machine learning-based yield analysis model. Input geometric parameters (e.g., linewidth, spacing, area), process parameters (e.g., etching time, temperature, gas flow rate), and historical yield data before and after layout modification. Train the model using a random forest or neural network algorithm. Use this model to perform Monte Carlo simulations on the modified layout, simulating 1000 production cycles, and predicting that the yield will improve to the target value (e.g., from 82% to 88%).

[0138] Step S43: Feedback and Iterative Optimization; The results of yield optimization are fed back into chip design and manufacturing processes for a new round of design and production. During this new production cycle, chip design data, manufacturing process parameters, and chip yield data continue to be collected and fed back into the data collection and integration module and the yield analysis model building module. Through the analysis and processing of this new data, the yield analysis model is continuously improved, further optimizing manufacturing process parameters and chip design. This feedback and iterative optimization mechanism, combining both model and data, continuously improves chip manufacturability, performance, and quality, achieving a continuous increase in chip yield.

[0139] (1) Establish a closed-loop feedback mechanism. Feedback the yield optimization results to the chip design end and the manufacturing process end respectively. At the chip design end, the design parameters such as chip architecture, circuit layout, and transistor size are adjusted using the yield analysis results; at the manufacturing process end, the process parameters (such as exposure dose, etching time, temperature, pressure, etc.) of core processes such as photolithography, etching, and deposition are optimized to start a new round of chip design and manufacturing process.

[0140] (2) Real-time data acquisition and bidirectional transmission. In the new round of production, high-precision sensors and data acquisition equipment are deployed to collect chip design data (including but not limited to layout files, logic design parameters, power network structure, etc.), production process parameters (such as lithography machine overlay accuracy, etching rate uniformity, thin film thickness consistency, etc.), and chip yield data (number of good products per batch, failure modes, etc., by process step). This data is encrypted and transmitted to the central data server via industrial Ethernet or fiber optic network. A message queue, Kafka, is used to ensure reliable reception and buffering of high-concurrency data, while simultaneously transmitting it to the data collection and integration module and the yield analysis model construction module.

[0141] (3) Model Iteration Optimization and Algorithm Upgrade. In the data collection and integration module, data cleaning algorithms are used to remove outliers and noisy data, data standardization is used to unify the data format, and time series correlation analysis is used to establish a correspondence between design data, process parameters, and yield data. Based on the integrated data, the yield analysis model construction module uses machine learning algorithms (such as random forests, neural networks, etc.) to train and optimize the model. By comparing the predicted results with the actual yield data, the model parameters and algorithm structure are continuously adjusted to improve the accuracy of the model in predicting factors affecting yield.

[0142] Working principle: This embodiment first uses the ETL tool Apache NiFi to clean, transform, and standardize the raw data, eliminating outliers and noisy data. The processed data is then stored in a distributed database to establish a multi-dimensional data warehouse containing design versions, process batches, yield indicators, etc. Data traceability is ensured through data lineage tracing technology.

[0143] Secondly, based on Python and the TensorFlow / PyTorch framework, a deep learning yield prediction model, such as a convolutional neural network or an LSTM network, is built and trained using historical data. The model performance is evaluated in real time using the MLflow model monitoring platform. When the prediction error exceeds a threshold, an incremental learning mechanism is automatically triggered, adding new data to the training set to retrain the model and optimize its parameters and structure.

[0144] Furthermore, based on the updated yield analysis model, a multi-objective optimization algorithm is used to collaboratively optimize manufacturing process parameters and chip design parameters. For example, the simulated annealing algorithm is used to find the optimal combination of exposure dose and development time in the photolithography process, while simultaneously combining it with redundant circuit design in chip design to balance manufacturing costs and yield improvement requirements. The optimized parameters are then fed back to the production execution system and electronic design automation tools to guide the next round of production and design improvements.

[0145] The yield analysis results are then pushed to the chip design department's EDA tools and manufacturing process control system via the Enterprise Service Bus (ESB) in the form of a standardized interface (RESTful API). Based on the analysis results, the design department optimizes the circuit structure, layout and routing using automated design tools (such as Cadence Virtuoso); the manufacturing department automatically adjusts process parameters through programmable logic controllers (PLCs) and distributed control systems (DCS) to achieve closed-loop control.

[0146] Finally, a real-time monitoring platform is established to visualize and provide early warnings for key parameters and yield indicators during the production process. When yield fluctuations or process parameter deviations are detected, the system automatically triggers a data analysis process to quickly locate the root cause of the problem and proposes adjustment suggestions based on the optimized yield analysis model. This achieves dynamic closed-loop control of the chip manufacturing process, continuously improving chip manufacturability, performance, and quality, and driving a step-by-step increase in chip yield. A version management system, such as Git or SVN, is established to control the versioning of design documents and process parameters, generating a new design version and process recipe after each optimization. The entire production process is monitored through a Manufacturing Execution System (MES). After the completion of a new round of production, a data collection and analysis process is automatically triggered, forming a continuous improvement cycle of "data collection - model optimization - parameter adjustment - production verification," gradually improving chip yield and manufacturing quality.

[0147] The other parts of this embodiment are the same as any one of the above embodiments 1-2, so they will not be described again.

[0148] Example 4: Based on any one of Embodiments 1-3 above, this embodiment proposes a semiconductor yield analysis and optimization system based on multi-module collaboration, used to execute the above-mentioned semiconductor yield analysis and optimization method based on multi-module collaboration; including a data collection and integration module, a yield analysis model construction module, a yield verification module, and a yield optimization module; The data collection and integration module is used to collect multiple types of data from the entire semiconductor manufacturing process and integrate them to obtain integrated data. The yield analysis model construction module is used to construct a multi-dimensional comprehensive yield analysis model based on integrated data, and generate a combination of process parameters that can guide mass production. The yield verification module is used to calculate and predict chip yield based on the combination of process parameters, and to calculate yield deviation, taking design parameters and process parameters that have a significant impact on yield as key factors. The yield optimization module is used to optimize semiconductor yield based on design parameters and process parameters.

[0149] This embodiment also proposes an electronic device, including a memory and a processor; the memory stores a computer program; when the computer program is executed on the processor, it implements the above-mentioned semiconductor yield analysis and optimization method based on multi-module collaboration.

[0150] This embodiment also proposes a computer-readable storage medium, on which computer instructions are stored; when the computer instructions are executed on the aforementioned electronic device, the aforementioned semiconductor yield analysis and optimization method based on multi-module collaboration is implemented.

[0151] The other parts of this embodiment are the same as any one of the embodiments 1-3 above, so they will not be described again.

[0152] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the present invention.

Claims

1. A semiconductor yield analysis and optimization method based on multi-module collaboration, characterized in that, Specifically, the following steps are included: Step S1: Collect various types of data from the entire semiconductor manufacturing process and integrate them to obtain integrated data; Step S2: Construct a multi-dimensional comprehensive yield analysis model based on the integrated data to generate a combination of process parameters that can guide mass production; Step S3: Calculate the predicted chip yield based on the combination of process parameters, and calculate the yield deviation, taking the design parameters and process parameters that have a significant impact on the yield as key factors; Step S4: Optimize semiconductor yield based on design parameters and process parameters.

2. The semiconductor yield analysis and optimization method based on multi-module collaboration according to claim 1, characterized in that, The specific operation of step S1 is as follows: obtain the chip design data and process parameters during the production process, and integrate them to obtain integrated data.

3. The semiconductor yield analysis and optimization method based on multi-module collaboration according to claim 1, characterized in that, Step S2 specifically includes the following steps: Step S21: Obtain and analyze historical production data to obtain the correlation between key factors and parameters affecting chip yield, and determine the quantitative relationship between exposure dose and chip yield in the photolithography process through regression analysis; Step S22: Combining semiconductor physics principles, construct a physical model of the chip manufacturing process, call computer simulation technology to simulate the chip manufacturing process, and predict the chip performance and yield under different process conditions; Step S23: Combine the statistical analysis results based on historical data with the physical model and simulation results to establish a comprehensive yield analysis model; Step S24: Compare the key parameters output by the simulation with the test bonding data of the actual production in the wafer fab, and adjust the uncertain parameters in the model through sensitivity analysis to generate a combination of process parameters that can guide mass production.

4. The semiconductor yield analysis and optimization method based on multi-module collaboration according to claim 3, characterized in that, Step S24 specifically includes the following steps: Step S241: Construct a sensitivity function based on the key parameters output by the simulation and the test bonding data from the actual production of the wafer fab; Step S242: Calculate the key parameters for the current combination based on the sensitivity function and the set learning rate; Step S243: Obtain the combination of process parameters based on the key parameters.

5. The semiconductor yield analysis and optimization method based on multi-module collaboration according to claim 1, characterized in that, Step S3 specifically includes the following steps: Step S31: Based on the combination of process parameters and the comprehensive yield analysis model, obtain the predicted yield; Step S32: Calculate the yield deviation based on the predicted yield and the target yield; Step S33: If the yield deviation is greater than or equal to 0, then the current process parameters are considered reasonable; if the yield deviation is less than 0, calculate the sensitivity of the design parameters and process parameters to the yield, and take the parameters with larger absolute values ​​of sensitivity as the key factors affecting the yield.

6. The semiconductor yield analysis and optimization method based on multi-module collaboration according to claim 1, characterized in that, The specific operation of step S4 is as follows: optimize the production process parameters based on key factors, and determine the optimal value based on simulation to improve the process window and yield, and generate yield optimization suggestions.

7. A semiconductor yield analysis and optimization system based on multi-module collaboration, used to execute the semiconductor yield analysis and optimization method based on multi-module collaboration as described in claim 1; characterized in that, It includes a data collection and integration module, a yield analysis model construction module, a yield verification module, and a yield optimization module; The data collection and integration module is used to collect multiple types of data from the entire semiconductor manufacturing process and integrate them to obtain integrated data. The yield analysis model construction module is used to construct a multi-dimensional comprehensive yield analysis model based on integrated data, and generate a combination of process parameters that can guide mass production. The yield verification module is used to calculate and predict chip yield based on the combination of process parameters, and to calculate yield deviation, taking design parameters and process parameters that have a significant impact on yield as key factors. The yield optimization module is used to optimize semiconductor yield based on design parameters and process parameters.

8. An electronic device, characterized in that, It includes a memory and a processor; the memory stores a computer program; when the computer program is executed on the processor, it implements the semiconductor yield analysis and optimization method based on multi-module collaboration as described in any one of claims 1-6.

9. A computationally readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions; when the computer instructions are executed on the electronic device as described in claim 8, they implement the semiconductor yield analysis and optimization method based on multi-module collaboration as described in any one of claims 1-6.

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