A power consumption simulation method of a system on chip

Abstract

This application provides a power consumption simulation method for a system-on-a-chip (SoC). The method includes: acquiring a preset case for the SoC, the operating state of each intellectual property core (IP core) of the SoC when running the preset case, and operating parameters of the SoC, wherein the operating state indicates whether the IP core participates in running the preset case; simulating a periodic waveform file of the SoC running the preset case based on the preset case, the operating state of each IP core, and the operating parameters; and performing power consumption simulation on the periodic waveform file using a power consumption simulation tool according to the operating state and operating parameters of each IP core to obtain a periodic simulated power consumption waveform.

Description

Technical Field

[0001] This application relates to the field of system-on-a-chip (SoC) technology, and in particular to a method for simulating the power consumption of a SoC. Background Technology

[0002] With the continuous advancement of semiconductor technology, the integration and complexity of System-on-Chip (SoC) are constantly increasing. To reduce the complexity of board-level power supply design, some motherboards typically divide a single power rail into multiple power domains (independent power supply areas for the chip) to power multiple intellectual property (IP) cores within the SoC. This poses challenges to power consumption analysis and optimization on the silicon chip, necessitating the use of simulation tools for tile-level simulation. To ensure the accuracy of simulation data, it is necessary to fit it to the data from the silicon chip, gradually converging the error between the simulation and measured values. Therefore, the selection of test cases and the alignment of the actual test and simulation environments and conditions are particularly important. It is necessary to ensure complete coverage of cells in the power domain while minimizing the number of introduced variables to reduce the workload of the simulation.

[0003] In existing technologies, selecting a test case and capturing the corresponding waveform file for power consumption simulation requires simultaneous simulation of each unit involved in each power domain. The simulation results of each power domain are then summed to obtain the power consumption simulation result of the system-on-a-chip. This results in high time costs, high server resource utilization, and difficulty in analyzing the reasons for large discrepancies between simulation results and actual test results when simulation calibration is difficult. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide at least one method for power consumption simulation of a system-on-a-chip, which solves the technical problem in the prior art that the power consumption simulation of all units involved in each power domain leads to inaccurate results, thereby improving the accuracy of power consumption simulation.

[0005] This application mainly includes the following aspects: In a first aspect, embodiments of this application provide a power consumption simulation method for a system-on-a-chip (SoC). The method includes: acquiring a preset case for the SoC, the operating state of each intellectual property core (IP core) of the SoC when running the preset case, and operating parameters of the SoC, wherein the operating state is used to indicate whether the IP core participates in running the preset case; simulating a periodic waveform file of the SoC running the preset case based on the preset case, the operating state of each IP core, and the operating parameters; and performing power consumption simulation on the periodic waveform file according to the operating state and operating parameters of each IP core using a power consumption simulation tool to obtain a periodic simulated power consumption waveform.

[0006] Optionally, the method further includes: determining the actual periodic power consumption waveform of the system-on-a-chip when running the preset case; performing error analysis on the actual periodic power consumption waveform and the simulated periodic power consumption waveform; and when the error analysis result does not meet the preset error conditions, re-determining the periodic waveform file, or re-determining the working state of each intellectual property core, or calibrating the power consumption simulation tool.

[0007] Optionally, the operating parameters include chip voltage. The actual power consumption waveform of the system-on-a-chip during the operation of the preset case is determined by: obtaining the measured voltage and current values ​​of the chip within the time window corresponding to the periodic waveform file using a post-silicon test board; calculating the target chip voltage using a preset voltage correction coefficient and the measured voltage value, wherein the preset voltage correction coefficient is used to reduce the difference between the measured voltage value and the chip voltage; and determining the actual power consumption waveform based on the target chip voltage and the measured current value.

[0008] Optionally, the operating states include a participating state, a cut-off state, and a reset state, wherein the participating state is used to indicate that the intellectual property core participates in the operation of the preset case, the cut-off state is used to indicate that the intellectual property core does not participate in the operation of the preset case and sets power gating, and the reset state is used to indicate that the intellectual property core does not participate in the operation of the preset case and does not set power gating and pulls a reset signal high.

[0009] Optionally, the operating parameters include chip voltage and chip temperature, and the periodic simulation power consumption waveform is obtained by: converting the periodic waveform file into a target format corresponding to the simulation accelerator; inputting the target format periodic waveform file, the chip voltage, and the chip temperature into a power consumption simulation tool to perform power consumption simulation, so as to obtain the periodic simulation power consumption waveform of the system-on-a-chip.

[0010] Optionally, the operating parameters include the chip frequency. The system-on-a-chip (SoC) obtains a periodic waveform file when running the preset case by simulating the following: inputting the preset case, the operating state of each intellectual property core, and the chip frequency to a simulation accelerator to simulate the preset waveform file generated when the SoC cycles through the preset case; and extracting a periodic waveform file for one operating cycle from the preset waveform file.

[0011] Optionally, an operating cycle can be determined by: reading the bandwidth utilization on the Advanced Scalable Interface bus while simulating the system-on-a-chip and running the preset case cyclically; and determining an operating cycle for the entire time period of the preset waveform file based on the changes in the bandwidth utilization.

[0012] Optionally, the method further includes: acquiring the actual power consumption waveform of the system-on-a-chip when running the preset case, so as to calibrate the running cycle through the actual power consumption waveform.

[0013] Secondly, embodiments of this application also provide an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory through the bus. The machine-readable instructions are executed by the processor to perform the steps of the system-on-a-chip power consumption simulation method described in the first aspect or any possible implementation of the first aspect.

[0014] Thirdly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the power consumption simulation method for a system-on-a-chip described in the first aspect or any possible implementation of the first aspect.

[0015] This application provides a method for power consumption simulation of a system-on-a-chip (SoC). The method includes: acquiring a preset case for the SoC, the operating state of each intellectual property core (IP core) of the SoC when running the preset case, and the operating parameters of the SoC, wherein the operating state is used to indicate whether the IP core participates in running the preset case; simulating a periodic waveform file of the SoC running the preset case based on the preset case, the operating state of each IP core, and the operating parameters; and performing power consumption simulation on the periodic waveform file according to the operating state and operating parameters of each IP core using a power consumption simulation tool to obtain a periodic simulated power consumption waveform. This application solves the technical problem in the prior art that the power simulation results are inaccurate because all units involved in each power domain are simulated. It sets a preset case and determines the working state of each intellectual property core and the operating parameters of the system-on-a-chip when the preset case is run. Then, it simulates the power consumption of the periodic waveform file according to the working state and operating parameters of each intellectual property core using a power consumption simulation tool to obtain the periodic simulated power consumption waveform.

[0016] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart of a power consumption simulation method for a system-on-a-chip provided in an embodiment of this application is shown.

[0019] Figure 2 A flowchart of another system-on-a-chip power consumption simulation method provided in an embodiment of this application is shown.

[0020] Figure 3 This paper illustrates a functional block diagram of a system-on-a-chip power consumption simulation device provided in an embodiment of this application.

[0021] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0023] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0024] In existing technologies, power consumption simulation of a system-on-a-chip (SoC) requires performing power consumption simulation for each power domain individually, and then summing the power consumption results of each power domain to obtain the simulated power consumption of the SoC. Specifically, simulating each power domain requires performing power consumption simulation for each individual unit within that power domain, and then summing the simulated power consumption of each unit to obtain the simulated power consumption of the power domain. Consequently, this method results in long simulation times, high server resource utilization, and difficulty in analyzing the specific reasons when the power correlation calibration results are poor.

[0025] Based on this, this application provides a power consumption simulation method for a system-on-a-chip (SoC). By setting a preset case and determining the operating state of each intellectual property core and the operating parameters of the SoC when running the preset case, a periodic waveform file is simulated according to the preset case and the SoC's operating parameters. Then, power consumption simulation is performed on the periodic waveform file using a power consumption simulation tool according to the operating state and operating parameters of each intellectual property core to obtain a periodic simulated power consumption waveform. This solves the technical problem in the prior art where power consumption simulation is performed on all units involved in each power domain, leading to inaccurate results, and achieves the technical effect of improving the accuracy of power consumption simulation. Specifically, as follows: Please see Figure 1 , Figure 1 This is a flowchart illustrating a power consumption simulation method for a system-on-a-chip (SoC) provided in an embodiment of this application. Figure 1 As shown in the embodiments of this application, the power consumption simulation method for a system-on-a-chip includes the following steps: S101: Obtain a preset case for the system-on-a-chip, the working status of each intellectual property core of the system-on-a-chip when running the preset case, and the operating parameters of the system-on-a-chip.

[0026] Specifically, the preset case describes the application scenario of the system-on-a-chip (SoC), or in other words, the preset case refers to the computer running a preset application. For example, the preset case could refer to the computer running the SoC performing image processing using minimum cost flow. Furthermore, in this application, the SoC corresponds to the same preset case during both power consumption simulation and actual testing to align the application scenarios in simulation and actual testing, thus avoiding affecting the accuracy of simulation calibration.

[0027] The operating status is used to indicate whether the intellectual property core participates in running the preset case. In other words, the operating status reflects whether each intellectual property core participates in the operation of the preset case when the system-on-a-chip runs.

[0028] The operating parameters are used to reflect the internal parameters of the system-on-a-chip (SoC) during power consumption simulation. These parameters should be consistent with the internal parameters of the SoC during actual testing. The operating parameters include the SoC's chip temperature, chip voltage, and chip frequency. The chip temperature is typically set to room temperature (25 degrees Celsius), the chip voltage is the SoC's internal voltage, and the chip frequency is the SoC's internal clock frequency.

[0029] Specifically, the working states include a participating state, a cut-off state, and a reset state. The participating state indicates that the intellectual property core is participating in the operation of the preset case. The cut-off state indicates that the intellectual property core is not participating in the operation of the preset case and a power gating is set. The reset state indicates that the intellectual property core is not participating in the operation of the preset case and a power gating is not set, and a reset signal is pulled high.

[0030] Whether each intellectual property core participates in the operation of the system-on-a-chip (SoC) during the execution of preset cases can be set by the experience of technical personnel and by the preset cases run by the SoC. Due to the chip structure and space constraints within the SoC, some intellectual property cores may not have power gating. Therefore, intellectual property cores without power gating and not participating in the execution of preset cases are set to a reset state. The power generated by the intellectual property core in the reset state during operation is leakage power. Furthermore, the simulated power of the intellectual property core in the reset state can be obtained by simulating leakage power, thus improving simulation accuracy.

[0031] In other words, for each intellectual property core (IPC) of the system-on-a-chip (SoC), it is determined whether the IPC participates in the operation of a preset case during SoC operation. If the IPC participates in the operation, its working state is determined to be "participating in operation," and the IPC will inevitably generate power consumption, which is related to the signal fluctuations corresponding to the IPC in the waveform file. If the IPC does not participate in the operation, it is determined whether the IPC is correspondingly set to a power gating. If the IPC is correspondingly set to a power gating, its working state is determined to be "off state," and the power gating of the IPC can be directly controlled to disconnect, so that the IPC is cut off from its corresponding power domain. In the power consumption simulation process, there is no need to perform power consumption simulation on the IPC. If the IPC is not correspondingly set to a power gating, its working state is determined to be "reset state," and the IPC is set to be in the reset state. The waveform of the IPC in the reset state can be obtained from the waveform file, and leakage power consumption simulation is performed on the IPC based on the waveform.

[0032] Furthermore, by analyzing the different operating states of each intellectual property core, the power consumption simulation for each core can be determined according to different strategies. For intellectual property cores in the operational state, power consumption simulation is performed directly based on waveform files. For intellectual property cores in the off state, they are considered not to be operational and no power consumption simulation is performed. For intellectual property cores in the reset state, their leakage power consumption is simulated. In other words, the power consumption of an intellectual property core in the reset state can be approximated by the power consumption generated by leakage. Therefore, the power consumption of the intellectual property core can be obtained by simulating the leakage power consumption of the intellectual property core in the reset state.

[0033] Furthermore, since there is no need to perform power consumption simulation on the intellectual property cores in the off state, this application reduces the number of intellectual property cores involved in power consumption simulation by setting the operating state of each intellectual property core, thereby reducing the simulation time. Moreover, by distinguishing intellectual property cores in different operating states, power consumption simulation can be performed on each intellectual property core in more detail, improving the accuracy of power consumption simulation. Furthermore, when a significant difference is found between the simulated power consumption and the measured power consumption, the cause can be analyzed by confirming whether the operating state of each intellectual property core is correct, thus improving the calibration capability of the simulation.

[0034] S102: Based on the preset case, the working state of each intellectual property core, and the operating parameters, simulate the periodic waveform file of the system-on-a-chip when running the preset case; Specifically, the operating parameters include the chip frequency. The system-on-a-chip (SoC) obtains the periodic waveform file when running the preset case by simulating the following method: inputting the preset case, the operating state of each intellectual property core, and the chip frequency into a simulation accelerator to simulate the preset waveform file generated when the SoC cycles through the preset case; and extracting the periodic waveform file located in one operating cycle from the preset waveform file.

[0035] In other words, a simulation accelerator (EMU) is used to simulate the system-on-a-chip (SoC) running preset cases cyclically at the chip frequency in the operating state corresponding to each intellectual property core. Since the SoC cyclically runs the preset cases during simulation, the target waveforms related to the preset case execution in the preset waveform file exhibit periodicity; one running cycle reflects one execution of the preset case by the SoC simulation. Therefore, the periodic waveform file representing one execution of the preset case by the SoC simulation can be extracted based on the periodicity of the target waveforms in the preset waveform file.

[0036] For example, an operating cycle is determined by reading the bandwidth utilization on the Advanced Scalable Interface bus while the system-on-a-chip is simulating the preset case; and determining an operating cycle for the entire time period of the preset waveform file based on the changes in the bandwidth utilization.

[0037] To improve the accuracy of the runtime cycle, the real-time bandwidth utilization of the Advanced eXtensible Interface (AXI) bus was simulated during the cyclic execution of a preset case of the simulated system-on-a-chip (SoC). Since bandwidth utilization is positively correlated with the power consumption of the SoC's DDR (Double Data Rate Synchronous Dynamic Random-Access Memory), a higher bandwidth utilization indicates higher DDR power consumption. Since DDR power consumption primarily depends on data read and write operations, and the bandwidth utilization of the AXI bus reflects the frequency of these operations, the power consumption of the DDR bus can be inferred by simulating the bandwidth utilization of the AXI bus.

[0038] Furthermore, since the DDR power consumption generated by the system-on-a-chip (SoC) during the cyclic operation of the preset case is periodic, the bandwidth utilization is obviously also periodic. That is, the bandwidth utilization waveform of each operating cycle should be consistent. Therefore, the time window of an operating cycle can be determined by the periodicity of the bandwidth utilization obtained from simulation. Then, the time window of an operating cycle determined by the bandwidth utilization is used to determine an operating cycle in the preset waveform file obtained from simulation, so that the periodic waveform file of an operating cycle can be extracted.

[0039] For example, during the process of simulating a system-on-a-chip running a preset case, the simulation accelerator can obtain the bandwidth utilization obtained from the simulation, as well as the counter value of the simulation's performance monitoring unit (PMU) or activity monitoring unit (AMU). The power consumption changes can be reflected by the counter value of the performance monitoring unit or the activity monitoring unit to correct the time window of the running cycle. That is, both the counter value of the performance monitoring unit and the counter value of the activity monitoring unit are periodic.

[0040] Specifically, the method further includes: acquiring the actual power consumption waveform of the system-on-a-chip when running the preset case, so as to calibrate the running cycle through the actual power consumption waveform.

[0041] For example, during the actual operation of a preset case of a system-on-a-chip (SoC), the voltage and current values ​​of the SoC are collected in real time to infer the actual power consumption of the SoC and form an actual power consumption waveform. The operating cycle obtained by the periodicity of bandwidth utilization is calibrated according to the periodicity of the actual power consumption waveform to improve the accuracy of the operating cycle. The periodic waveform file can be extracted and replaced.

[0042] S103: Use a power consumption simulation tool to perform power consumption simulation on the periodic waveform file according to the working state and operating parameters of each intellectual property core, so as to obtain the periodic simulated power consumption waveform.

[0043] Specifically, the operating parameters include chip voltage and chip temperature. The periodic simulation power consumption waveform is obtained by: converting the periodic waveform file into the target format corresponding to the simulation accelerator; inputting the target format periodic waveform file, the chip voltage, and the chip temperature into a power consumption simulation tool to perform power consumption simulation, so as to obtain the periodic simulation power consumption waveform of the system-on-a-chip.

[0044] The periodic waveform file obtained through the simulation accelerator is in the STW format, which is the original waveform format output by the simulation accelerator. Therefore, the STW format is converted into the FSDB (Fast Signal Database) format, that is, the target format is the waveform file format supported by the power consumption simulation tool.

[0045] The periodic waveform file includes at least the operating waveform of the intellectual property core participating in the operating state and the leakage waveform of the intellectual property core in the reset state. Furthermore, the power consumption simulation tool uses the operating waveform, chip voltage, and chip temperature to perform power consumption simulation, obtaining the simulated power consumption of the intellectual property core participating in the operating state. Similarly, the power consumption simulation tool uses the leakage waveform, chip voltage, and chip temperature to perform power consumption simulation, obtaining the simulated power consumption of the intellectual property core in the reset state. Thus, the sum of the simulated power consumption of the intellectual property cores participating in the operating state and / or the intellectual property cores in the reset state within each tile of the system-on-a-chip (SoC) yields the unit simulated power consumption of each tile. Finally, the sum of the unit simulated power consumption of each tile of the SoC yields the SoC's overall simulated power consumption.

[0046] In other words, it is not necessary to perform power consumption simulation for every intellectual property core of the system-on-a-chip during the power consumption simulation process. This reduces the number of intellectual property cores to be simulated, thereby improving power consumption simulation efficiency and reducing time costs.

[0047] Please see Figure 2 , Figure 2This is a flowchart illustrating another system-on-a-chip power consumption simulation method provided in an embodiment of this application. For example... Figure 2 As shown in the embodiments of this application, the power consumption simulation method for a system-on-a-chip includes the following steps: S201: Determine the actual power consumption waveform of the system-on-a-chip during the operation of the preset case.

[0048] Specifically, the operating parameters include chip voltage. The actual power consumption waveform of the system-on-a-chip during the operation of the preset case is determined by the following method: obtaining the measured voltage and current values ​​of the chip within the time window corresponding to the periodic waveform file through a post-silicon test board; calculating the target chip voltage using a preset voltage correction coefficient and the measured voltage value, wherein the preset voltage correction coefficient is used to reduce the difference between the measured voltage value and the chip voltage; and determining the actual power consumption waveform based on the target chip voltage and the measured current value.

[0049] In other words, during the actual operation of the pre-set case of the system-on-a-chip (SoC) produced in actual production, the voltage and current values ​​of the SoC are collected in real time through the SoC test board. The measured voltage value is extracted from the real-time collected voltage value of the SoC according to the time window corresponding to the periodic waveform file, and the measured current value is extracted from the real-time collected current value of the SoC according to the time window corresponding to the periodic waveform file.

[0050] Furthermore, the time windows for the measured voltage and current values ​​are the same as the time windows corresponding to the periodic waveform files. The time windows for the measured voltage and current values ​​also correspond to one operating cycle of the system-on-a-chip's actual operating preset case, so as to compare the simulated power consumption and the actual power consumption of the system-on-a-chip.

[0051] The real-time voltage and current values ​​of the system-on-a-chip (SoC) are collected from sampling points (balls or bumps) on the actual manufactured SoC. In other words, the collected voltage and current values ​​are the external sampling points of the SoC. Furthermore, due to the voltage drop within the SoC, the actual collected SoC voltage value should be greater than the internal chip voltage. Therefore, to reduce the difference between the measured voltage value and the actual chip voltage caused by the internal voltage drop, the measured voltage value can be multiplied by a preset voltage correction factor to calculate the target chip voltage. That is, the target chip voltage can be understood as the internal chip voltage of the SoC derived from the measured voltage value.

[0052] For example, since the measured voltage value is greater than the chip voltage, the preset voltage correction factor should be a decimal less than 1. The preset voltage correction factor can be an empirical value, or it can be calculated by simulating the power distribution network of the package using simulation tools to calculate the voltage drop between the voltage at the sampling point and the internal cell voltage. Alternatively, the preset voltage correction factor can be obtained directly from the packaging manufacturer. This application does not limit the method of obtaining the preset voltage correction factor.

[0053] S202: Perform error analysis on the actual power consumption waveform and the simulated power consumption waveform of the period.

[0054] S203: If the error analysis results do not meet the preset error conditions, redetermine the periodic waveform file, or redetermine the working state of each intellectual property core, or calibrate the power consumption simulation tool.

[0055] Furthermore, the target chip voltage is obtained by multiplying the measured voltage value by a preset voltage correction coefficient. Then, the product of the target chip voltage and the measured current value is calculated to obtain the actual power consumption waveform over time. This allows for error analysis of the actual power consumption waveform and the simulated power consumption waveform over time. For example, the power consumption difference at each moment in the actual and simulated power consumption waveforms can be calculated, and it can be determined whether the power consumption difference at each moment falls within a preset difference range to determine if the error analysis result meets the preset error conditions. Alternatively, the power consumption difference at each moment can be averaged, and it can be determined whether the average value falls within a preset difference range to determine if the error analysis result meets the preset error conditions. This application does not impose any limitations on this approach.

[0056] For example, when the power consumption difference at each moment falls within the preset difference range, the error analysis result is considered to meet the preset error condition period, and the actual power consumption waveform and the periodic simulated power consumption waveform are approximately the same. That is, the simulated power consumption obtained by the power consumption simulation tool is approximately the measured power consumption of the system-on-a-chip. In this case, the power consumption simulation tool does not need calibration, the time window of the running cycle is accurate, and the working status of each intellectual property core is accurate when running the preset case. When the power consumption difference at at least one moment does not fall within the preset difference range, the error analysis result is considered to not meet the preset error condition period, and there is a difference between the periodic actual power consumption waveform and the periodic simulated power consumption waveform. That is, there is a difference between the simulated power consumption obtained by the power consumption simulation tool and the measured power consumption of the system-on-a-chip. In this case, it is necessary to consider whether the simulated power consumption calculation of the power consumption simulation tool is inaccurate, or the time window of the running cycle is not accurately found, or the working status of each intellectual property core is inaccurate when running the preset case.

[0057] Furthermore, after recalibrating the time window of the running cycle and / or the working status of each intellectual property core when running the preset case, power consumption simulation is performed again. If there is still a difference between the periodic simulated power consumption waveform obtained by the modified power consumption simulation and the actual periodic power consumption waveform, then the power consumption simulation tool is considered to need calibration, that is, the model parameters involved in the power consumption simulation tool are modified in order to improve the simulation capability of the power consumption simulation tool.

[0058] Furthermore, this application simplifies the simulation environment and reduces the number of intellectual property cores to be simulated by setting the working state of each intellectual property core when the system-on-a-chip (SoC) runs a preset case and simulating the periodic waveform file accordingly. This reduces the simulation workload and the difficulty of analyzing errors. By weighting the voltage values ​​of the SoC actually acquired, the difference between the measured power consumption and the simulated power consumption is reduced, thereby improving simulation accuracy and simplifying the simulation process. Moreover, the bandwidth utilization simulated by the accelerator can be used to characterize power consumption changes, improving the accuracy of the time window of the running cycle. More accurate periodic waveform files can be extracted from the waveform file to eliminate test errors in advance and reduce power consumption calibration time.

[0059] Based on the same application concept, this application also provides a system-on-a-chip power consumption simulation device corresponding to the system-on-a-chip power consumption simulation method provided in the above embodiments. Since the principle of the device in this application is similar to the system-on-a-chip power consumption simulation method in the above embodiments of this application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0060] For example, Figure 3 This application provides a functional block diagram of a system-on-a-chip (SoC) power consumption simulation device 10. The SoC power consumption simulation device 10 includes: an acquisition module 101, used to acquire a preset case for the SoC, the operating status of each intellectual property core (IP core) of the SoC when running the preset case, and operating parameters of the SoC, wherein the operating status indicates whether the IP core participates in running the preset case; a waveform simulation module 102, used to simulate a periodic waveform file of the SoC running the preset case based on the preset case, the operating status of each IP core, and the operating parameters; and a power consumption simulation module 103, used to perform power consumption simulation on the periodic waveform file according to the operating status and operating parameters of each IP core using a power consumption simulation tool to obtain a periodic simulated power consumption waveform.

[0061] Based on the same application concept, see [link / reference] Figure 4The diagram shown is a structural schematic of an electronic device provided in an embodiment of this application. The electronic device 20 includes a processor 201, a memory 202, and a bus 203. The memory 202 stores machine-readable instructions that can be executed by the processor 201. When the electronic device 20 is running, the processor 201 and the memory 202 communicate through the bus 203. When the machine-readable instructions are executed by the processor 201, the steps of the power consumption simulation method for a system-on-a-chip as described in any of the above embodiments are executed.

[0062] Specifically, when the machine-readable instructions are executed by the processor 201, the following processing can be performed: obtaining a preset case for the system-on-a-chip (SoC), the operating status of each intellectual property core (IP core) of the SoC when running the preset case, and the operating parameters of the SoC, wherein the operating status is used to indicate whether the IP core participates in running the preset case; simulating a periodic waveform file of the SoC running the preset case based on the preset case, the operating status of each IP core, and the operating parameters; and performing power consumption simulation on the periodic waveform file according to the operating status and operating parameters of each IP core using a power consumption simulation tool to obtain a periodic simulated power consumption waveform.

[0063] Based on the same concept, this application also provides a computer-readable storage medium storing a computer program, which, when run by a processor, executes the steps of the power consumption simulation method for a system-on-a-chip provided in the above embodiments.

[0064] Specifically, the storage medium can be a general-purpose storage medium, such as a portable disk or hard disk. When the computer program on the storage medium is run, it can execute the aforementioned system-on-a-chip power consumption simulation method. By setting a preset case and determining the working state of each intellectual property core and the operating parameters of the system-on-a-chip when running the preset case, a periodic waveform file is simulated according to the preset case, the working state of each intellectual property core, and the operating parameters of the system-on-a-chip. Then, power consumption simulation is performed on the periodic waveform file according to the working state and operating parameters of each intellectual property core using a power consumption simulation tool to obtain a periodic simulated power consumption waveform. This solves the technical problem in the prior art where power consumption simulation is performed on all units involved in each power domain, resulting in inaccurate results, and achieves the technical effect of improving the accuracy of power consumption simulation.

[0065] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and devices described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division; in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0066] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0067] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0068] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0069] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for simulating the power consumption of a system-on-a-chip, characterized in that, The method includes: The system acquires a preset case for a system-on-a-chip (SoC), the working status of each intellectual property core of the SoC when running the preset case, and the operating parameters of the SoC. The working status is used to indicate whether the intellectual property core participates in running the preset case. Based on the preset case, the working state of each intellectual property core, and the operating parameters, the periodic waveform file of the system-on-a-chip when running the preset case is simulated. The periodic waveform file is simulated using a power consumption simulation tool according to the operating state and operating parameters of each intellectual property core to obtain the periodic simulated power consumption waveform.

2. The method according to claim 1, characterized in that, The method further includes: Determine the actual periodic power consumption waveform of the system-on-a-chip when running the preset case; Error analysis is performed on the actual power consumption waveform and the simulated power consumption waveform of the cycle. If the error analysis results do not meet the preset error conditions, the periodic waveform file is redefined, or the working state of each intellectual property core is redefined, or the power consumption simulation tool is calibrated.

3. The method according to claim 2, characterized in that, The operating parameters include chip voltage, and the actual power consumption waveform of the system-on-a-chip during the operation of the preset case is determined by the following method: The measured voltage and current values ​​of the chip within the time window corresponding to the periodic waveform file are obtained using a post-silicon test board. The target chip voltage is calculated using a preset voltage correction factor and the measured voltage value. The preset voltage correction factor is used to reduce the difference between the measured voltage value and the chip voltage. The actual power consumption waveform of the cycle is determined based on the target chip voltage and the measured current value.

4. The method according to claim 1, characterized in that, The operating states include the participating operation state, the cut-off state, and the reset state. The "participation in operation" state indicates that the intellectual property core participates in the operation of the preset case; the "disconnection" state indicates that the intellectual property core does not participate in the operation of the preset case and sets a power gating; and the "reset" state indicates that the intellectual property core does not participate in the operation of the preset case and does not set a power gating, thus pulling up a reset signal.

5. The method according to claim 4, characterized in that, The operating parameters include chip voltage and chip temperature, and the periodic simulation power consumption waveform is obtained through the following method: The periodic waveform file is converted into the target format corresponding to the simulation accelerator. The periodic waveform file in the target format, the chip voltage, and the chip temperature are input into a power consumption simulation tool to perform power consumption simulation, so as to obtain the periodic simulated power consumption waveform of the system-on-a-chip.

6. The method according to claim 1, characterized in that, The operating parameters include the chip frequency, and the periodic waveform file of the system-on-a-chip when running the preset case is obtained through simulation in the following manner: The preset case, the working state of each intellectual property core, and the chip frequency are input to the simulation accelerator to simulate the preset waveform file generated when the system-on-a-chip cycles through the preset case; Extract the periodic waveform file located in one running cycle from the preset waveform file.

7. The method according to claim 6, characterized in that, An operating cycle is determined in the following way: When the system-on-a-chip is simulating the preset case in a loop, the bandwidth utilization on the advanced scalable interface bus is read. The operating cycle of the preset waveform file is determined based on the changes in bandwidth utilization over the entire time period.

8. The method according to claim 7, characterized in that, The method further includes: The actual power consumption waveform of the system-on-a-chip when running the preset case is obtained, and the running cycle is calibrated by the actual power consumption waveform.

9. An electronic device, characterized in that, include: The system includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. The machine-readable instructions are executed by the processor to perform the steps of the power consumption simulation method for a system-on-a-chip as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the power consumption simulation method for a system-on-a-chip as described in any one of claims 1 to 8.

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