A chip leakage power consumption optimization method and device based on graph partitioning

Abstract

The present specification relates to the field of chip design and manufacturing, and particularly to a chip leakage power consumption optimization method and device based on graph partitioning. The method comprises: judging whether there is timing path margin in a chip, wherein the chip has physical perception capability; if yes, identifying low threshold voltage devices in the chip according to a plurality of preset constraint conditions, and performing graph partitioning on the device layout of the chip; based on the processing result of the graph partitioning, determining target optimization devices from the low threshold voltage devices that meet the preset constraint conditions; replacing the target optimization devices with high threshold voltage devices to optimize the chip leakage power consumption containing the target optimization devices. The present application constructs an optimized leakage power consumption operation space based on a physically perceived engineering environment. Through graph partitioning and replacement constraints, the combined logic devices are analyzed, replaced and optimized in a limited range, the data scale is controllable, the chip layout is optimized in the chip design and implementation process, and the optimization efficiency is improved.

Description

Technical Field

[0001] This specification relates to the field of chip design and manufacturing, and in particular to a method and apparatus for optimizing chip leakage power consumption based on graph segmentation. Background Technology

[0002] With advancements in chip manufacturing processes, leakage current accounts for an increasingly larger proportion of total power consumption in chip products. The impact of leakage current on chip applications is now significant and has become a key focus in chip design and implementation.

[0003] Standard cells in chip manufacturing exhibit different leakage power consumption values ​​at different threshold voltages, with cells having lower threshold voltages tending to have higher leakage power consumption. Replacing cells with lower threshold voltages (ULVT) is a major engineering solution for optimizing leakage power consumption, while meeting performance and area requirements.

[0004] However, the industry currently faces three main problems with this method: (1) The replacement process lacks classification analysis of circuit timing and combinational logic devices. The industry's main replacement solutions either analyze and replace all logic units in the circuit or primarily target sequential logic units. In timing diagrams, combinational logic units involve more start and end points of timing paths, and their leakage current consumption issues differ from sequential logic, requiring categorized analysis and handling. The biggest difference between sequential and combinational logic lies in their scale; combinational logic devices are often far more numerous in chip implementations than sequential logic. Replacing multi-pin combinational logic elements will affect the timing path of their load. These paths have numerous branches; if the scope of combinational logic units to be replaced cannot be accurately determined, timing deterioration will occur, triggering negative feedback in optimization. Some techniques for optimizing leakage current consumption simply exhaust replacement based on the timing margin on the path, indiscriminately replacing sequential and combinational devices without considering the constraints on the replacement of combinational logic devices.

[0005] (2) The process of optimizing leakage power consumption lacks physical perception considerations and does not take into account the physical limitations in actual production. It is basically based on pure logic analysis and replacement.

[0006] With the rapid development of advanced processes, physical factors have become extremely important in optimizing leakage current and power consumption. Engineering data based on physical layout is more accurate and reliable. For combinational logic devices, there is a positive linear relationship between the number of cells and the number of pins. In physical implementation, the number of pins represents the amount of layout and routing resources occupied. In some areas with special requirements, there is also the issue of long routing resources. That is, the replacement range of combinational logic devices must ensure the rationality of layout and routing resources. Replacing pure logic is not a true way to optimize leakage current and power consumption in physical implementation.

[0007] (3) The replacement process lacks consideration or optimization of engineering practice efficiency.

[0008] The efficiency of chip design and implementation has a significant impact on product release and application. Optimizing leakage current power consumption is an engineering problem that has already reached the gate-level stage of the circuit. With large circuit scales and numerous instance units, the implementation process inherently requires more runtime. Therefore, optimization solutions, i.e., replacing ULVT technology, must consider the efficiency of engineering implementation. The engineering practice process is highly dependent on the final result of physical implementation. Optimizing leakage current power consumption is in the final stage of implementation; if unconverged power consumption problems are encountered later, even more time will be consumed.

[0009] In addition, the target units selected in the existing technology lack specificity, resulting in excessively large target sizes and low triggering efficiency. Summary of the Invention

[0010] To address the problems in the prior art, this specification provides a method and apparatus for optimizing chip leakage power consumption based on graph segmentation. The method includes: determining whether the chip has timing path margin, wherein the chip has physical sensing capability; if so, identifying low-threshold voltage devices in the chip according to multiple preset constraints, and performing graph segmentation on the device layout of the chip; based on the graph segmentation processing result, determining a target optimized device that satisfies the preset constraints from the low-threshold voltage devices; and replacing the target optimized device with a high-threshold voltage device to optimize the leakage power consumption of the chip containing the target optimized device.

[0011] According to one aspect of an embodiment of this specification, the preset constraint condition is determined by the following formula: ; ；Where x represents the preset number of rectangular segments, y represents the preset threshold for the number of cells within a rectangle, z represents the preset threshold for cell density within a rectangle, b represents the replacement efficiency, a represents the number of cells that can be replaced with high threshold voltage cells, m represents the preset timing margin threshold for passing through timing path j, and n represents the preset bus delay threshold for passing through timing path j. Let k represent the set of first target rectangles, and k represent the k-th rectangle element in the set of first target rectangles. Let j represent the target optimization device set, and j represent the index of the j-th combined device element in the target optimization device set.

[0012] According to one aspect of the embodiments of this specification, identifying low-threshold voltage devices in the chip based on a variety of preset constraints and performing graph segmentation on the device layout of the chip includes: segmenting the physical layout of the chip according to a preset number of rectangle segments to generate a first candidate rectangle.

[0013] According to one aspect of the embodiments of this specification, determining the target optimized device that satisfies the preset constraints from the low threshold voltage devices based on the graph segmentation processing result includes: selecting a first target rectangle from the first candidate rectangles according to a preset rectangle number threshold and a preset rectangle density threshold; and selecting the target optimized device from the first target rectangle according to a preset timing margin threshold and a preset bus delay threshold.

[0014] According to one aspect of the embodiments of this specification, selecting target optimized devices from a first candidate rectangle based on a preset timing margin threshold and a preset bus delay threshold includes: determining whether a combinational logic device in each candidate rectangle is a violation based on the preset timing margin threshold; if so, excluding the first combinational logic device on the timing path of the violation combinational logic device; determining whether the ratio of line delay to bus delay of the violation combinational logic device and the remaining second combinational logic devices other than the first combinational logic device meets the preset bus delay threshold; if so, determining the second combinational logic device as the target optimized device.

[0015] According to one aspect of the embodiments of this specification, dividing the physical layout of a chip according to the number of rectangle divisions further includes: determining the number of rectangle divisions based on the maximum number of task submission threads of the machine; and dividing the physical layout into multiple first candidate rectangles of equal area according to the number of rectangle divisions.

[0016] According to one aspect of the embodiments of this specification, replacing the target optimized device with a high threshold voltage device and optimizing the leakage power consumption of the target optimized device includes: selecting a target library cell with a subthreshold voltage of the same type as the target optimized device from the library cells for replacing the target optimized device.

[0017] This specification provides a chip leakage power optimization device based on graph segmentation. The device includes: a judgment unit for judging whether the chip has timing path margin, wherein the chip has physical sensing capability; a graph segmentation unit for identifying low-threshold voltage devices in the chip and performing graph segmentation on the device layout of the chip according to multiple preset constraints if the chip has timing path margin; a determination unit for determining a target optimization device that meets the preset constraints from the low-threshold voltage devices based on the graph segmentation processing result; and an optimization unit for replacing the target optimization device with a high-threshold voltage device to optimize the leakage power of the chip containing the target optimization device.

[0018] This specification also provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the graph segmentation-based chip leakage power optimization method.

[0019] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the graph segmentation-based chip leakage power optimization method.

[0020] This solution constructs an optimized leakage current and power consumption operating space based on a physically aware engineering environment. Through graph partitioning and replacement constraints, combinational logic devices are analyzed, replaced, and optimized within a limited scope, with controllable data scale. This optimizes chip layout and improves optimization efficiency during chip design and implementation. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 The figure shown is a schematic diagram of an implementation system for a chip leakage power consumption optimization method based on graph segmentation according to an embodiment of this specification. Figure 2 The diagram shown is a flowchart of a chip leakage power optimization method based on graph segmentation according to an embodiment of this specification. Figure 3 The diagram shown is a flowchart of another method for determining the design parameter extraction results after cross-validation, according to an embodiment of this specification. Figure 4The diagram shown is a flowchart of a method for selecting target optimized devices from a first candidate rectangle according to an embodiment of this specification. Figure 5 The diagram shown is a flowchart of a method for graph segmentation of a chip according to an embodiment of this specification. Figure 6 The diagram shown is a schematic diagram of a segmented chip according to an embodiment of this specification; Figure 7 The diagram shown is a flowchart illustrating the physical implementation of one embodiment and the control group in this specification. Figure 8 The diagram shown is a schematic representation of a chip leakage power optimization device based on graph segmentation according to an embodiment of this specification. Figure 9 The diagram shown is a structural schematic of a computer device according to an embodiment of this specification.

[0023] Explanation of symbols in the attached drawings: 101. Terminal; 102. Server; 601. First candidate rectangle; 602, Second candidate rectangle; 603, Third candidate rectangle; 604, the fourth candidate rectangle; 605. The fifth candidate rectangle; 606, the sixth candidate rectangle; 801. Judgment Unit; 802. Graph segmentation unit; 803. Determine the unit; 804, Optimization Unit; 902. Computer equipment; 904, Processor; 906. Memory; 908. Drive mechanism; 910. Input / Output Module; 912. Input devices; 914. Output devices; 916. Presentation equipment; 918. Graphical User Interface; 920. Network interface; 922. Communication link; 924. Communication bus. Detailed Implementation

[0024] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0026] This specification provides the operational steps of the methods described in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operational steps may be included. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only possible execution order. In actual system or device products, the methods shown in the embodiments or drawings can be executed sequentially or in parallel.

[0027] It should be noted that the chip leakage power optimization method and apparatus based on graph segmentation described in this specification can be used in the fields of chip design and manufacturing, as well as in the field of electronic circuit technology. This specification does not limit the application fields of the chip leakage power optimization method and apparatus based on graph segmentation.

[0028] like Figure 1 The figure shown is a schematic diagram of an implementation system for a chip leakage power consumption optimization method based on graph segmentation according to an embodiment of the present invention.

[0029] The implementation system may include a terminal 101 and a server 102. The terminal 101 and the server 102 communicate via a network, which may include a local area network (LAN), a wide area network (WAN), the Internet, or a combination thereof, and is connected to a website, user equipment (e.g., computing devices), and a backend system. Operators can send chip data and preset constraints to the server 102 through the terminal 101. After receiving the preset constraints, the server 102 identifies low-threshold voltage devices in the chip and performs graph segmentation on the chip's device layout. Based on the graph segmentation results, it determines target optimized devices that meet the preset constraints from the low-threshold voltage devices. It then replaces the target optimized devices with high-threshold voltage devices to optimize the chip's leakage power consumption, and sends the optimized analysis results back to the terminal 101.

[0030] In the embodiments of this specification, the server 102 may be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms.

[0031] In an optional embodiment, terminal 101 may be an electronic device, including but not limited to self-service terminal equipment, desktop computers, tablet computers, laptops, smart wearable devices, etc. Optionally, the operating system running on the electronic device may include, but is not limited to, Android, iOS, Linux, Windows, etc. Of course, terminal 101 is not limited to the aforementioned physical electronic devices; it may also be software running on the aforementioned electronic devices.

[0032] In addition, it should be noted that, Figure 1 The example shown is merely one application environment provided by this disclosure. In practical applications, it may include multiple terminals 101, and this specification does not impose any restrictions.

[0033] Figure 2 The diagram shown is a flowchart of a chip leakage power optimization method based on graph segmentation according to an embodiment of this specification, which specifically includes the following steps: Step 201: Determine whether the chip with physical sensing capability has timing path margin.

[0034] This specification describes how to determine whether a chip has timing path margins in an engineering environment. The engineering environment specifically refers to the industrial scenario, electronic device integration scenario, or testing and verification scenario where the chip is actually deployed and running. The engineering environment accurately reflects the chip's actual operating state, such as workload, voltage fluctuations, and temperature changes. The chip studied in this application possesses timing margin awareness and physical attribute awareness capabilities.

[0035] Timing margin awareness refers to the chip's ability to acquire real-time transmission delay data, clock cycle data, and setup / hold time parameters for each timing path through its built-in timing monitoring module, thereby obtaining its own timing performance status. Physical attribute awareness refers to the chip's ability to perceive key physical information such as its device layout, interconnect length, device threshold voltage type, and chip operating temperature, providing data support for subsequent optimization decisions.

[0036] In this step, the first step is to determine whether the chip has available timing path margin, specifically including: (1) Extract the actual transmission delay time of each timing path of each combinational logic device in the chip; (2) Determine the clock cycle corresponding to the path; (3) Calculate the timing path margin for each timing path based on the clock cycle and the actual transmission delay time. If at least one timing path has a timing path margin greater than zero, and this margin value will not cause a timing violation due to device replacement, then it is determined that the chip has available timing path margin. If the timing path margin of all timing paths is less than or equal to zero, then it is determined that the chip has no available timing path margin, and such a chip will not be used as the target for subsequent optimization of leakage power consumption.

[0037] By determining whether there is any timing path margin, chips with potential for leakage current and power consumption optimization can be accurately selected, avoiding the possibility of chip malfunction due to optimization operations performed on chips with tight timing constraints. This provides a prerequisite for subsequent leakage current and power consumption optimization based on device replacement.

[0038] Step 202: If yes, identify low-threshold voltage devices in the chip according to various preset constraints, and perform graph segmentation on the device layout of the chip.

[0039] In the embodiments of this specification, the library units classify and label devices with different threshold voltages. For low threshold voltage devices, the library unit names stored in the library units typically contain "LVT", "LV", or "L", such as ULVT, LVT, etc. Therefore, this step identifies low threshold voltage devices in the chip by querying the names belonging to the library unit type.

[0040] In some embodiments of this specification, the preset constraints can be represented by the following formula: ; ； Where x represents the preset number of rectangular segments, y represents the preset threshold for the number of cells within a rectangle, z represents the preset threshold for cell density within a rectangle, b represents the replacement efficiency, a represents the number of cells that can be replaced with high threshold voltage cells, m represents the preset timing margin threshold for passing through timing path j, and n represents the preset bus delay threshold for passing through timing path j. Let k represent the set of first target rectangles, and k represent the k-th rectangle element in the set of first target rectangles. Let j represent the target optimization device set, and j represent the index of the j-th combined device element in the target optimization device set.

[0041] In this step, a graph segmentation method is used to segment the chip's device layout and optimize the leakage power consumption of the combined devices within the chip. Specifically, based on the polygonal data of the chip's physical layout, a predetermined number of quadrilateral rectangles are segmented, and each rectangle is treated as a candidate object. All combinational logic device objects on the physical layout are then converted into combinational logic devices within multiple rectangles, and leakage power consumption of the combinational devices is optimized. In other words, by rapidly segmenting the geometric shape to obtain subsets, the scope of analysis and processing is narrowed.

[0042] Step 203: Based on the graph segmentation processing results, determine the target optimized device that satisfies the constraint conditions from the low threshold voltage devices.

[0043] In this step, from the low threshold voltage devices contained in each candidate matrix obtained by graph segmentation, the target optimized devices that meet the requirements are selected according to the preset constraints (y, z, m and n) in step 202.

[0044] Step 204: Replace the target optimized device with a high threshold voltage device to optimize the leakage power consumption of the chip containing the target optimized device.

[0045] This step can replace the target optimized device with a device having a higher threshold voltage than the low threshold voltage device. For example, at least one of the high threshold voltage devices (LVT / RVT) in the library unit can replace the low threshold voltage target optimized device. Specifically, a target library unit with a secondary voltage of the same type as the target optimized device is selected from the library unit to replace the target optimized device. In some embodiments of this application, an LVT can be used to replace the ULVT. In this application, the combinational logic devices in the low threshold voltage state are screened and analyzed, the data scale is controllable, and the efficiency can be improved; in the optimization of combinational devices, multi-threaded parallel constraint design is used to improve the efficiency of replacing and optimizing chip leakage power consumption; the relevant attributes of the unit are maintained at the corresponding stage after the low threshold voltage unit replacement is completed, and the physical layout optimization is performed incrementally without the need to introduce third-party tools, which can further improve process efficiency and data consistency.

[0046] Figure 3 The diagram shown is a flowchart of a method for screening target optimization devices according to an embodiment of this specification, which specifically includes the following steps: Step 301: Divide the physical layout of the chip according to the preset number of rectangles to generate the first candidate rectangle.

[0047] In this step, the preset rectangle segmentation number represents the maximum number of rectangles pre-set for graph segmentation, also known as Box Count, denoted as x. A larger target rectangle count indicates a greater number of rectangles to be analyzed after graph segmentation, resulting in lower efficiency in replacing combinational logic devices.

[0048] After determining the number of target rectangles, the physical layout of the chip is divided into equal-area sections, resulting in multiple rectangles of equal area. These rectangles are the first candidate rectangles. Figure 6 The diagram shown is a schematic of a segmented chip according to an embodiment of this specification. The chip M is divided into six first candidate rectangles of equal area: first candidate rectangle 601, second candidate rectangle 602, third candidate rectangle 603, fourth candidate rectangle 604, fifth candidate rectangle 605, and sixth candidate rectangle 606.

[0049] In some embodiments of this specification, the chip may be initially divided into two or more regions according to its shape and size, and then each region may be divided into equal-area sections according to the number of target rectangles. This step does not limit the method for generating the first candidate rectangle.

[0050] Step 302: Select the first target rectangle from the first candidate rectangles based on the preset threshold for the number of units within the rectangle and the preset threshold for the density of units within the rectangle.

[0051] After determining the first candidate rectangle in step 301, not all first candidate rectangles are objects to replace the target device. It is also necessary to select the first target rectangle from the first candidate rectangles based on the threshold of the number of units in the rectangle and the threshold of the unit density in the rectangle.

[0052] In this step, the cell count threshold within a rectangle represents the pre-set upper limit of the total number of components allowed in a single rectangle (also known as the maximum number of components allowed in a single rectangle), also called Cell Count, denoted as y. It represents the maximum number of components a candidate rectangle can contain. Here, "cell" represents various types of electronic components, not just combinational logic devices. The cell count threshold y within a rectangle is negatively correlated with efficiency b. The higher the total number of components allowed in a single rectangle, the more components are in the box, the larger the set of objects to be analyzed, and the lower the engineering efficiency.

[0053] In this step, the cell density threshold within a rectangle represents the maximum area ratio of combinational logic devices within a pre-defined single rectangle, also known as the maximum layout density or Density, denoted as z. The cell density threshold z is negatively correlated with efficiency b. A larger maximum layout density constraint results in less space for replacing combinational logic devices. Because combinational logic devices typically have multiple pins connected to other peripheral combinational logic devices via wires, when replacing combinational logic devices within the first candidate rectangle with higher density, the higher the density, the more peripheral combinational logic devices and connections are involved. This affects the peripheral combinational logic devices connected to the current combinational logic device, thus reducing the efficiency of replacement. Therefore, the cell density threshold within a rectangle cannot be set too high.

[0054] In some embodiments of this specification, z can be set to 0.5 to filter rectangles with an in-rectangle cell density less than or equal to 0.5 from two or more first candidate rectangles, and these rectangles are then selected as candidate processing objects. Candidate rectangles with an in-rectangle cell density greater than 0.5 are excluded and not further processed. This application does not limit the specific values ​​of the in-rectangle cell number threshold and the in-rectangle cell density threshold.

[0055] In this step, after determining the threshold for the number of cells within a rectangle and the threshold for the density of cells within a rectangle, all first candidate rectangles are traversed. Candidate rectangles whose number of cells within a rectangle does not exceed the threshold for the number of cells within a rectangle, and whose density of cells within a rectangle is less than or equal to the threshold for the density of cells within a rectangle, are selected. Candidate rectangles that meet these conditions are then identified as the first target rectangles. This completes the selection of the first target rectangles.

[0056] Step 303: Select target optimized devices from the first target rectangle based on the preset timing margin threshold and the preset bus delay threshold.

[0057] Based on the screening of the first target rectangle completed in step 302, this step screens the target combinational logic units (i.e., the target optimized devices in this step) in the first target rectangle.

[0058] In this step, the preset timing margin threshold is the minimum available timing path margin among all timing paths corresponding to the first target rectangle (i.e., the critical margin value that will not cause a timing violation after replacing the combinational logic devices within the rectangle). It can also be understood as the minimum constraint value (slack) of the margin through timing path j, denoted as m. Here, m is negatively correlated with the number of replacements a. The larger the preset timing margin threshold is set, the more timing paths are excluded, and the smaller the number of replaceable combinational logic devices in the first target rectangle.

[0059] For example, in the current study of combinational logic unit p in the first target rectangle B, specifically, we study whether there is a timing margin for the j-th timing path corresponding to each pin p on combinational logic unit p. If there is no timing margin, then the j-th timing path is in violation, and other combinational devices on the violation path will also be excluded at the same time.

[0060] In this step, the preset bus delay threshold, denoted as n, represents the upper limit of the ratio of the net delay of the combinational logic devices within the first target rectangle to the bus transmission delay. n is positively correlated with the number of replacements, a. The smaller the preset bus delay threshold is set, the more j are excluded from the target set, and the smaller a is.

[0061] In this application, the timing path margins corresponding to all low-threshold voltage combinational logic devices within each first target rectangle are extracted, along with the bus transmission delays between the low-threshold voltage combinational devices and the core functional modules and clock modules in the chip. Combinational logic devices with timing path margins greater than or equal to a preset timing margin threshold and bus transmission delays less than or equal to a preset bus delay threshold are selected from the first target rectangles. These selected combinational logic devices are the target optimized devices.

[0062] For a detailed explanation of the preset constraints in this application, please refer to Table 1: Table 1 Summary of preset constraints for optimizing leakage current and power consumption of combined components in the circuit

[0063] This application constructs an optimized leakage power consumption space based on a physically aware engineering environment; it judges and screens combinational logic devices to determine the target range; within the limited target range, it uses graph partitioning to optimize the combinational logic ULVT devices. Multi-threaded constraint design is implemented during the engineering optimization process to improve the efficiency of replacing and optimizing chip leakage power consumption. At the corresponding stage after replacement, physical layout optimization is incrementally performed by constraining the state attributes of the cells, maintaining the QoR of chip design and implementation, and optimizing chip leakage power consumption.

[0064] Figure 4 The diagram shown is a flowchart of a method for selecting target optimized devices from a first candidate rectangle according to an embodiment of this specification.

[0065] In this specification, each pin of the combinational logic device in the chip has a corresponding timing path. The timing path represents the complete delay link from the input pin into the combinational logic of the combinational logic device, through the internal logic gates, and finally out from the output pin.

[0066] Step 401: Determine whether the combinational logic devices in each candidate rectangle are in violation based on the timing margin threshold.

[0067] This step determines whether a combinational logic device is a case study based on timing margins. Timing margin represents the difference between the available time and the actual time consumed by the timing path. When the timing margin is positive (Slack > 0), the actual path delay is less than the available path delay, indicating timing convergence and stable operation. When the timing margin is 0 (Slack = 0), the actual path delay equals the available path time, indicating that the timing requirements are met without redundancy. When the timing margin is negative (Slack < 0), the actual path delay is less than the available path time, indicating timing failure and potential functional errors in the chip.

[0068] Step 402: If yes, then exclude the first combinational logic device on the timing path of the combinational logic device that violated the rule.

[0069] Once the combinational logic device that violated the rules in the first candidate rectangle is identified, the other combinational logic devices connected to the timing path of that violating combinational logic device are referred to as the first combinational logic device. The first combinational logic device is also unusable and may have a functional error; therefore, it is excluded.

[0070] Step 403: Determine whether the ratio of line delay to bus delay for the faulty combinational logic device and the remaining second combinational logic devices other than the first combinational logic device meets the preset bus delay threshold.

[0071] After excluding the non-compliant combinational devices and the first combinational logic devices from the study object in step 402, the remaining second combinational logic devices in each first candidate rectangle are studied. Specifically, it is determined whether the second combinational logic device meets the preset bus delay threshold.

[0072] In this specification, bus delay refers to the total time it takes for a signal to be stably sampled at the receiving end from its output at the transmitting end on the bus inside the chip or between chips. This avoids excessive use of high-level routing resources by the implementation tools. This step determines whether the ratio of the line delay on the j-th timing path of the combinational logic device to the bus delay of the combinational logic device is less than or equal to a preset bus delay threshold.

[0073] Step 404: If yes, determine the second combinational logic device as the target optimized device.

[0074] In this step, if the ratio of line delay to bus delay is less than a preset threshold, the second combinational logic device is determined to be the target optimized device, that is, a replaceable low threshold voltage combinational logic device.

[0075] Figure 5 The diagram shown is a flowchart of a method for graph segmentation of a chip according to an embodiment of this specification, which specifically includes the following steps: Step 501: Determine the preset number of rectangle segments based on the maximum number of task submission threads on the machine.

[0076] In engineering practice, the number of combinational logic devices in chip circuits is enormous. In order to maximize the parallel processing efficiency of each task after physical layout partitioning, this step determines the number of rectangular partitions based on the maximum number of task submission threads on the machine running the EDA software. In some embodiments of this specification, the number of rectangular partitions can also be represented by the maximum number of power tile boxes (Box Count) of the graph partitioning.

[0077] Each Power Tile Box is an independent power supply unit within the chip. Once the size of the Box Count is determined, the number of rectangular segments can be determined by combining this with the total area of ​​the chip's physical layout. The Box Count can also be denoted as x, which is negatively correlated with the efficiency b of replacing combinational logic devices. In other words, the more rectangular segments there are, the more rectangles are analyzed, and the lower the efficiency of optimizing chip leakage power consumption.

[0078] On the one hand, the high-density distribution of combinational logic devices leads to a surge in logic computation and layout operations within a single layout area. If the number of rectangles is less than the maximum number of task submission threads, thread resources will be idle, preventing parallel processing and reducing power efficiency. On the other hand, if the number of rectangles exceeds the maximum number of task submission threads, it will cause thread contention and increased scheduling overhead, reducing the execution efficiency of layout operations related to combinational logic devices. Therefore, the number of target rectangles is determined based on the maximum number of task submission threads to ensure that the combinational logic device replacement tasks within each target rectangle can be handled in a load-balanced manner.

[0079] Step 502: Divide the physical layout into multiple first candidate rectangles of equal area according to the preset number of rectangle divisions.

[0080] In this step, the chip is segmented into graphs based on the physical coordinates of each point in the original physical layout of the chip and the number of rectangular segments for graph segmentation set in step 501.

[0081] In the embodiments of this specification, the original physical layout of the chip is typically polygonal. During the graph segmentation process, the physical layout density within a polygonal region may vary. Therefore, for a block's physical layout, different graph segmentation methods are supported for the polygonal regions. Specifically, the physical layout can be initially segmented to obtain initial segmented regions; these initial segmented regions can then be further segmented. For example, low-density regions can be graph-segmented into larger rectangles; high-density regions can be graph-segmented into smaller rectangles, thus improving engineering efficiency and extraction quality.

[0082] In this application, the main programming languages ​​used are Tcl and Python. The Tcl scripts, executed within a unified implementation tool, primarily handle the design, application, execution, and result output of custom attributes, and are tightly integrated with the implementation tool commands. The Python scripts, outside the implementation tool, are used for analyzing the results of the Tcl script execution, batch creating scripts for executing Tcl commands, and performing rectangular graph segmentation. Specifically, the steps include the following: (1) Mark all target object units.

[0083] First, the library cells implemented by the chip are labeled, and these cells are categorized according to their threshold voltages. Next, the Comb insts (hereinafter referred to as ULVT-Combs) corresponding to low threshold voltage cells are labeled. For targets that need to be labeled again during the iteration process, this is achieved by incrementing the numeric suffix of the label name. The labeling process consists of defining user attributes, setting user attributes, and obtaining insts with user attributes.

[0084] (2) Report the data of the target device with custom attributes.

[0085] The tool uses Tcl instructions to report the instance name, slack path, physical coordinates, and lib cell information for all ULVT-regs in a single file. For pre-defined constraints, the EDA tool already contains pointer information, resulting in rapid reporting, far superior to traditional echo or foreach operations. For combinational logic, only the instance name and lib cell information need to be reported.

[0086] (3) Graph segmentation and filtering.

[0087] Based on the chip's physical layout coordinates and the number of rectangular segments, a Python script is used to perform rapid chip segmentation calculations. An equal-area map segmentation logic is employed; after a certain number of segments have been created, any remaining areas smaller than a unit rectangle are directly treated as a single rectangle for further planning. This type of segmentation involves a small number of rectangles, thus not affecting analysis accuracy.

[0088] The selection of boxes involves the total number of elements and the total layout density. Based on the four-point coordinates of the box, the implementation tool is instructed to quickly report the number of elements within that area and rapidly accumulate the areas of all elements within that area to obtain the total number of elements and the layout density. This application supports traversing multiple user-specified polygonal regions. During the box selection process, a Python script records the reasons for boxes that do not meet the requirements and reports the final valid target rectangles.

[0089] (4) Replace lib cell.

[0090] The output file of step (3) above is parsed using Python, and the tcl commands for exchanging each valid target cell libcell are batch-produced into a single file. For the parallel replacement operation of combinational logic devices, the maximum number of running cores of the implementation tool needs to be set. The commands for submitting tasks in parallel are implemented by tcl instructing the relevant commands of the EDA tool. All successfully submitted parallel tasks output subtask log files.

[0091] Compared to the method of traversing all combinational logic devices in a design, this application improves the engineering efficiency of processing combinational logic devices by dividing the area into rectangular regions.

[0092] (5) Output the results.

[0093] This application designs a separate operating space during project implementation, managed by three levels of directories: Reg, Comb, and Summary, fundamentally avoiding interference with the original project data. The specific output structure is shown in the table below: Table 2-1 Engineering Practice Catalog Structure Design

[0094] One embodiment of this application is as follows: the number of Inst elements is greater than 850,000; the number of macros is 40; and the total cell area is greater than 200,000 μm. 2 The total area of ​​the map is greater than 300,000 μm. 2 The parameters of the pre-set constraints are shown in Table 3-1. The following is an example of using... Figure 7 The illustrated embodiment of this specification shows a physical implementation flowchart used in one embodiment and a control group. It includes the following processes: S1, Physical Sensing Integration; S2, Physical Layout; S3-1, Physical Layout; S3-2, Wiring. Under the same input, the situation of this embodiment and its control groups is shown in Table 3-2; the comparison results between this embodiment and the control group examples are shown in Tables 3-3, 3-4-1 to 3-4-3.

[0095] Table 3-1 Preset Constraints Table

[0096] Table 3-2 Parameter settings for embodiments using the scheme of this application

[0097] Table 3-3 Results of Example 1 using the solution of this application

[0098] Table 3-4-1 Results of Example 2 and Control Group 2 using the scheme of this application

[0099] Table 3-4-2 CtsOpt results of Example 2 and Control Group 2 using the scheme of this application.

[0100] Table 3-4-3 Results of RouteOpt for Example 2 and Control Group 2 using the scheme of this application.

[0101] Table 3-3 shows that, compared with traditional layout optimization, the proposed solution has a significant effect on optimizing chip leakage power consumption, reducing the absolute area of ​​the ULVT of combinational logic devices by 8.9%. In addition, the chip timing convergence results remain basically unchanged, the layout and routing evaluation results do not change much, and have virtually no impact on the chip area.

[0102] The data in Tables 3-4-1, 3-4-2 and 3-4-3 show that, in Place / CtsOpt / RouteOpt, the schemes in this application can effectively reduce leakage power consumption while maintaining the timing and relatively reducing the area.

[0103] Figure 8 The diagram shown is a schematic representation of a graph segmentation-based chip leakage power optimization device according to an embodiment of this specification. The basic structure of the graph segmentation-based chip leakage power optimization device is illustrated in this figure. The functional units and modules can be implemented in software, or using general-purpose chips or specific chips to implement graph segmentation-based chip leakage power optimization. The device specifically includes: The judgment unit 801 is used to determine whether the chip has timing path margin, wherein the chip has physical sensing capability; The graph segmentation unit 802 is used to identify low-threshold voltage devices in the chip and perform graph segmentation on the device layout of the chip, based on multiple preset constraints. The determining unit 803 is used to determine, based on the graph segmentation processing results, a target optimized device that meets the preset constraint conditions from the low threshold voltage devices; The optimization unit 804 is used to replace the target optimization device with a high threshold voltage device to optimize the leakage power consumption of the chip containing the target optimization device.

[0104] like Figure 9 The diagram illustrates a computer device according to an embodiment of this specification. The graph segmentation-based chip leakage power optimization method described in this application can be applied to the computer device. The computer device 902 may include one or more processors 904, such as one or more central processing units (CPUs), each of which can implement one or more hardware threads. The computer device 902 may also include any memory 906 for storing any kind of information such as code, settings, data, etc. Non-limitingly, for example, the memory 906 may include any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Further, any memory can provide volatile or non-volatile retention of information. Further, any memory can represent a fixed or removable component of the computer device 902. In one case, when the processor 904 executes associated instructions stored in any memory or combination of memories, the computer device 902 can perform any operation of the associated instructions. The computer device 902 also includes one or more drive mechanisms 908 for interacting with any memory, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.

[0105] Computer device 902 may also include an input / output module 910 (I / O) for receiving various inputs (via input device 912) and providing various outputs (via output device 914). A specific output mechanism may include a presentation device 916 and an associated graphical user interface (GUI) 918. In other embodiments, the input / output module 910 (I / O), input device 912, and output device 914 may be omitted, and the device may function solely as a computer device within a network. Computer device 902 may also include one or more network interfaces 920 for exchanging data with other devices via one or more communication links 922. One or more communication buses 924 couple the components described above together.

[0106] Communication link 922 can be implemented in any way, such as via a local area network (LAN), a wide area network (WAN) (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 922 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0107] Corresponding to Figures 2 to 5 In addition to the methods described above, embodiments of this specification also provide a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the methods described above.

[0108] This specification also provides computer-readable instructions, wherein when a processor executes the instructions, the program therein causes the processor to perform the following... Figures 2 to 5 The method shown.

[0109] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0110] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this specification generally indicates that the preceding and following related objects have an "or" relationship.

[0111] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0112] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0113] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.

[0114] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described in this specification, depending on actual needs.

[0115] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0116] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this specification, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0117] This specification uses specific embodiments to illustrate the principles and implementation methods of this specification. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this specification. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this specification. Therefore, the content of this specification should not be construed as a limitation of this specification.

Claims

1. A chip leakage power consumption optimization method based on graph segmentation, characterized in that, The method includes: Determine whether the chip has timing path margin, wherein the chip has physical sensing capability; If so, based on multiple preset constraints, identify low-threshold voltage devices in the chip and perform graph segmentation on the device layout of the chip; Based on the graph segmentation processing results, target optimized devices that meet the preset constraints are determined from the low threshold voltage devices. The target optimized device is replaced with a high threshold voltage device to optimize the leakage power consumption of the chip containing the target optimized device.

2. The method according to claim 1, characterized in that, The preset constraints are determined using the following formula: ； ； Where x represents the preset number of rectangular segments, y represents the preset threshold for the number of cells within a rectangle, z represents the preset threshold for cell density within a rectangle, b represents the replacement efficiency, a represents the number of cells that can be replaced with high threshold voltage cells, m represents the preset timing margin threshold for passing through timing path j, and n represents the preset bus delay threshold for passing through timing path j. Let k represent the set of first target rectangles, and k represent the k-th rectangle element in the set of first target rectangles. Let j represent the target optimization device set, and j represent the index of the j-th combined device element in the target optimization device set.

3. The method according to claim 1, characterized in that, Based on multiple preset constraints, low-threshold voltage devices in the chip are identified, and the chip's device layout is segmented graphically, including: The physical layout of the chip is divided according to the preset number of rectangles to generate the first candidate rectangle.

4. The method according to claim 3, characterized in that, Based on the graph segmentation processing results, the target optimized devices that satisfy the preset constraints are determined from the low threshold voltage devices, including: Based on the preset threshold for the number of units within a rectangle and the preset threshold for the density of units within a rectangle, a first target rectangle is selected from the first candidate rectangles; Based on the preset timing margin threshold and the preset bus delay threshold, target optimized devices are selected from the first target rectangle.

5. The method according to claim 4, characterized in that, Based on preset timing margin thresholds and preset bus delay thresholds, target optimized devices are selected from the first target rectangle, including: Based on the preset timing margin threshold, determine whether the combinational logic device in each candidate rectangle is in violation; If so, then exclude the first combinational logic device on the timing path of the combinational logic device that violated the rule; For combinational logic devices that have committed violations and the remaining second combinational logic devices other than the first combinational logic device, determine whether the ratio of line delay to bus delay meets a preset bus delay threshold. If so, the second combinational logic device is determined to be the target optimized device.

6. The method according to claim 3, characterized in that, The physical layout of the chip is further divided according to the preset number of rectangular divisions, including: The preset number of rectangle segments is determined based on the maximum number of task submission threads on the machine; Based on the preset number of rectangles to be divided, the physical map is divided into multiple first candidate rectangles of equal area.

7. The method according to claim 1, characterized in that, Replacing the target optimized device with a high threshold voltage device to optimize the leakage power consumption of the target optimized device includes: Select a target library cell with a subthreshold voltage of the same type as the target optimized device from the library cells, and use it to replace the target optimized device.

8. A chip leakage power consumption optimization device based on graph segmentation, characterized in that, The device includes: A judgment unit is used to determine whether the chip has timing path margin, wherein the chip has physical sensing capability; The graph segmentation unit is used to identify low-threshold voltage devices in the chip and perform graph segmentation on the device layout of the chip, based on multiple preset constraints. The determining unit is used to determine, based on the processing results of graph segmentation, a target optimized device that meets the preset constraint conditions from the low threshold voltage devices; An optimization unit is used to replace the target optimization device with a high threshold voltage device to optimize the leakage power consumption of the chip containing the target optimization device.

9. A computer device, characterized in that, The computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method according to any one of claims 1 to 7.

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