Chain-gated clock circuit and control method thereof

Abstract

The application relates to a chain type gated clock circuit and a control method thereof. The circuit comprises a plurality of cascaded gated clock units and a plurality of cascaded functional modules, each of the gated clock units is connected with the functional module of the current stage in one-to-one correspondence; wherein the gated clock unit is configured to provide a gated clock signal for the functional module of the current stage, and stop providing the gated clock signal for the functional module of the current stage after receiving a completion indication signal sent by the functional module of the current stage, and send a gated enable signal to the gated clock unit of the next stage; the functional module is configured to execute work in response to the gated clock signal, and send the completion indication signal to the gated clock unit of the current stage after the work is completed. The application significantly reduces the dynamic power consumption of the system and reduces the area of the control path itself.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a chain-gated clock circuit and its control method. Background Technology

[0002] In very large-scale digital integrated circuits, the power consumption of the clock network can account for 30% to 50% of the total dynamic power consumption, or even higher. The heavy load and frequent switching of the clock signal are major sources of power consumption. Currently, the most commonly used clock power consumption control technology is clock gating. Existing mainstream clock gating technologies are mainly divided into the following categories, but they all have shortcomings and defects in the application scenario of this invention: (1) Simple gating and integrated clock gating unit The most basic clock gating method uses an AND (or OR) gate to directly control the clock's on / off state using the enable signal. While this method is simple in structure, it is highly susceptible to glitches caused by the enable signal being out of sync with the clock, posing a serious threat to circuit reliability. To avoid glitches, the industry commonly uses integrated clock gating cells (ICGs), which typically consist of a latch and an AND gate. The latch samples the enable signal when the clock is low to ensure the stability of the gating control signal during the clock's high-level period. Although this method solves the glitch problem, its control granularity is usually limited to a single module or register group, lacking the ability to manage power consumption across multiple modules working together.

[0003] (2) Module-level gating based on independent enable signals For multiple functional modules, the traditional approach is to generate independent gating enable signals for each module. The control logic of this method is typically complex, potentially requiring intricate FSM state machine designs, counters / timers, and significant combinational logic. Independent enable generation circuits need to be designed for each module, and these circuits must meet strict timing requirements. These circuits themselves also consume additional power and area. The more complex the enable generation logic, the more substantial the dynamic power consumption. Furthermore, since the clocks of each module are independent, in scenarios with data pipeline dependencies between modules, the lack of low-overhead control schemes for hardware self-synchronization makes it difficult to achieve optimal energy efficiency control. Additionally, if the clocks of multiple modules turn on or off simultaneously, it generates huge instantaneous currents, leading to power network noise.

[0004] (3) Dynamic intelligent gating technology To further optimize power consumption, techniques such as dynamic clock gating have emerged. These techniques dynamically turn off the clock by analyzing the actual operating state of the circuit or using intelligent algorithms to predict the idle period of the module. However, these methods often introduce more complex control logic and decision circuits, increasing design complexity and the difficulty of timing convergence. The power consumption gains may be partially offset by the overhead of the control circuit itself.

[0005] In summary, existing technologies share a common dilemma: when it is necessary to coordinate clock gating of a group of time-dependent functional modules, simple decentralized control poses reliability risks or low energy efficiency; while complex centralized intelligent control incurs significant logic implementation overhead. Summary of the Invention

[0006] Therefore, it is necessary to provide a chain-gated clock circuit and its control method to address the aforementioned technical problems.

[0007] In a first aspect, embodiments of the present invention provide a chain-gated clock circuit, the circuit comprising multiple cascaded gated clock units and multiple cascaded functional modules, each gated clock unit being connected to a functional module of its own level in a one-to-one correspondence. The gated clock unit is configured to: provide a gated clock signal to the functional module at this level, and after receiving a completion indication signal sent by the functional module at this level, stop providing a gated clock signal to the functional module at this level, and send a gated enable signal to the gated clock unit at the next level. The functional module is configured to: perform work in response to the gated clock signal, and send the completion indication signal to the gated clock unit of the same level after the work is completed.

[0008] In some embodiments, the functional module is further configured to: send the completion indication signal to the gated clock unit at the next higher level after the work is completed; The gated clock unit is also configured to stop sending gated enable signals to the next level gated clock unit after receiving a completion indication signal from the next level functional module.

[0009] In some embodiments, the functional module is further configured to: In response to the gating enable signal, the local enable signal is made valid; or in response to the gating enable signal and the data ready signal, the local enable signal is made valid; when the local enable signal is valid, a gating clock signal is provided to the functional modules of this level. Upon receiving a completion indication signal from the functional module at this level, the local enable signal is invalidated.

[0010] In some embodiments, the first-level gated clock unit in the plurality of cascaded gated clock units is configured to: after the state of the top-level enable signal is set, in response to the top-level enable signal, send the gated enable signal to the next-level gated clock unit. The last-level functional module in the multiple cascaded functional modules is configured to: after completing its work, also feed back the completion indication signal to reset the state of the top-level enable signal.

[0011] In some embodiments, the first-level gated clock unit in the plurality of cascaded gated clock units is configured to: in response to the top-level enable signal, send the gate enable signal to the next-level gated clock unit, wherein the top-level enable signal is a single-clock-cycle pulse signal.

[0012] In some embodiments, the first-level gated clock unit among the plurality of cascaded gated clock units is configured to: after the state of the top-level enable signal is set, in response to the top-level enable signal, send the gated enable signal to the next-level gated clock unit; after the state of the top-level enable signal is reset, in response to the top-level enable signal, stop sending the gated enable signal to the next-level gated clock unit; the state of the top-level enable signal is reset after each of the functional modules has generated the completion indication signal.

[0013] In some embodiments, the gated clock unit is further configured to: In response to the bypass mode signal, a global clock signal is provided for the functional modules of this level.

[0014] In some embodiments, the functional module is further configured to send the completion indication signal to the next-level gated clock unit after the work is completed; The gated clock unit is further configured to: during the operation of the functional module at this level, if a new data ready signal is received, send a task suspension signal to the gated clock unit at the next higher level; after receiving a completion indication signal sent by the functional module at this level, continue to provide a gated clock signal to the functional module at this level; and after receiving a completion indication signal sent by the functional module at this level again, stop providing a gated clock signal to the functional module at this level. After receiving a completion indication signal from the next-level functional module, if the pending flag is detected to be set by the next-level gated clock unit, the gating enable signal is sent to the next-level gated clock unit. After receiving a completion indication signal from the next-level functional module again, the gating enable signal is stopped from being sent to the next-level gated clock unit.

[0015] In some embodiments, a FIFO buffer connected between two adjacent functional modules is also included; The gated clock unit is further configured to: stop sending the gate enable signal to the next level gated clock unit after receiving the completion indication signal sent by the next level functional module and the empty indication signal sent by the front-end FIFO buffer of the next level functional module. The gated clock unit is further configured to stop providing gated clock signals to the functional module at this level after receiving a completion indication signal sent by the functional module at this level and an empty indication signal sent by the front-end FIFO buffer of the functional module at this level.

[0016] Secondly, embodiments of the present invention provide a control method for a chain-gated clock circuit, applied to the circuit described in the first aspect, comprising: The control gate clock unit provides gate clock signals to the functional modules at this level, and after receiving the completion indication signal sent by the functional modules at this level, it stops providing gate clock signals to the functional modules at this level and sends a gate enable signal to the gate clock unit at the next level. The control function module performs its work in response to the gated clock signal, and sends the completion indication signal to the gated clock unit of the same level after the work is completed.

[0017] Compared with the prior art, this application has the following technical effects: (1) Significantly reduce dynamic power consumption: Through the chain structure, the gated clock signal is transmitted to the next level gated clock unit in a "wave-like" manner only when it is needed to work, which greatly reduces unnecessary clock flipping activities and thus significantly reduces the dynamic power consumption of the system.

[0018] (2) Extremely low design overhead: The gated clock unit has a simple structure. Replacing the complex central control state machine or counter with a simple distributed gated clock unit can effectively reduce the area and power consumption of the control path itself.

[0019] (3) Reduce switching noise: The gated clock signal is turned on sequentially, not simultaneously, thus smoothing the current change and effectively suppressing power network glitches and ground bounce noise caused by the simultaneous switching of a large number of clock units.

[0020] (4) Scalability: The chain-gated clock circuit is composed of a series of identical gated clock units cascaded one after another. The circuit structure is clear and can be easily expanded according to the number of functional modules. There is no need to change the logic of the gated clock units. Only the corresponding number of levels needs to be adjusted and the units can be spliced ​​together. The portability is convenient and quick. Attached Figure Description

[0021] Figure 1 This is a system block diagram of the chain-gated clock circuit in the embodiments of this application; Figure 2This is a symbol diagram of the gated clock unit in an embodiment of this application; Figure 3 This is a schematic diagram of the internal logic of the gated clock unit in an embodiment of this application; Figure 4 This is a schematic diagram of the gated clock signal control logic using the ICG unit in the embodiments of this application; Figure 5 This is a schematic diagram of the gated clock signal control logic when using DFF and AND2 gates in the embodiments of this application; Figure 6 This is a schematic diagram of the circuit module connection when the enable_out of the gated clock unit is of level type in the embodiments of this application; Figure 7 This is a timing waveform diagram in the single batch processing mode when enable_out is of level type in the embodiments of this application; Figure 8 This is a timing waveform diagram in the embodiment of this application when enable_out is in level-based streaming mode; Figure 9 This is a comparison diagram of the timing waveforms before and after the logic correction when the system_enable requirement is always 1 during the operation of the functional module cluster in this application embodiment; Figure 10 This is a schematic diagram of the circuit module connection when the enable_out of the gated clock unit is a single-cycle pulse type in the embodiment of this application; Figure 11 This is a timing waveform diagram of a single batch processing mode when enable_out is a single-cycle pulse type in the embodiments of this application; Figure 12 This is a timing waveform diagram of enable_out in the single-cycle pulse-type time-stream mode in the embodiments of this application; Figure 13 This is a schematic diagram of module connections during single-buffer processing in an embodiment of this application; Figure 14 This is a schematic diagram of the module connection with a FIFO buffer in an embodiment of this application. Detailed Implementation

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of the present invention. For those skilled in the art, the present invention can be applied to other similar scenarios based on these drawings without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0023] As indicated in this invention and the claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0024] While this invention makes various references to certain modules in an apparatus according to embodiments of the invention, any number of different modules can be used and run on a computing device and / or processor. Modules are merely illustrative, and different aspects of the apparatus and methods may use different modules.

[0025] It should be understood that when a unit or module is described as "connected" or "coupled" to other units, modules, or blocks, it may refer to a direct connection or coupling, or communication with other units, modules, or blocks, or the presence of intermediate units, modules, or blocks, unless the context explicitly indicates otherwise. The term "and / or" as used herein may include any and all combinations of one or more of the related listed items.

[0026] like Figure 1 As shown, this embodiment of the invention provides a chain-gated clock circuit, which includes multiple cascaded gated clock units (1-N) and multiple cascaded functional modules (1-N), with each gated clock unit corresponding to a functional module of its level.

[0027] The input and output signals of the chain-gated clock circuit are as follows: Global clock signal: Provides the operating clock signal for the entire chain-gated clock circuit.

[0028] Global reset signal: Provides a reset control signal for the entire chain-gated clock circuit.

[0029] Top-level enable signal: As the working enable control of the entire chain-gated clock circuit, it can be generated by an external power management unit or an external controller (such as a state machine).

[0030] Bypass mode signal: When the bypass mode signal is valid, the gated clock unit will be forced to output a global clock signal.

[0031] Working mode selection signal: Provides two working mode options: single batch processing mode and streaming mode.

[0032] Data ready signal: Indicates whether new data has arrived; it serves as a trigger signal for operation in streaming mode.

[0033] Data input signal: The data stream input terminal of the entire chain-gated clock circuit.

[0034] Work completion indication signal: Used to indicate whether the input data signal has been processed by all functional modules, indicating whether the data output signal is valid.

[0035] Data output signal: The data stream output of the entire chain-gated clock circuit.

[0036] The top-level enable signal is connected to the enable input of the first-level gated clock unit; the enable output of the first-level gated clock unit is connected to the enable input of the second-level gated clock unit; the enable output of the previous-level gated clock unit is connected to the enable input of the next-level gated clock unit, and subsequent units are cascaded step by step according to the above rules, up to the Nth level. This sequential connection of the first and last units forms a gated clock unit link.

[0037] Functional modules 1 through N are clusters of functional modules with pipelined or sequential dependencies. There are data flow, control flow, or startup order dependencies between modules. A later-level functional module must wait for the previous-level functional module to generate valid data or complete its work before it can start working.

[0038] Once the task is completed, each functional module will output a completion indication pulse signal. The completion indication signal of this functional module will then be provided to the corresponding gated clock unit.

[0039] Depending on actual needs, the completion indication signal may also be provided to the gating clock unit at the next higher level.

[0040] The gated clock unit is configured to: provide a gated clock signal to the functional module at its level; and, upon receiving a completion indication signal from the functional module at its level, stop providing the gated clock signal to the functional module at its level and send a gated enable signal to the gated clock unit at the next level. The functional module is configured to: perform work in response to the gated clock signal; and, upon completion of the work, send the completion indication signal to the gated clock unit at its level.

[0041] The functional module is further configured to send the completion indication signal to the next-level gated clock unit after the work is completed; the gated clock unit is further configured to stop sending the gated enable signal to the next-level gated clock unit after receiving the completion indication signal sent by the next-level functional module.

[0042] The functional module is further configured to: enable a local enable signal in response to the gating enable signal; or enable the local enable signal in response to both the gating enable signal and the data ready signal; provide a gating clock signal to the functional module at this level when the local enable signal is enabled; and disable the local enable signal after receiving a completion indication signal from the functional module at this level.

[0043] The first-level gated clock unit in the plurality of cascaded gated clock units is configured to: after the state of the top-level enable signal is set, in response to the top-level enable signal, send the gated enable signal to the next-level gated clock unit; the last-level functional module in the plurality of cascaded functional modules is configured to: after completing the work, also feed back the completion indication signal to reset the state of the top-level enable signal.

[0044] The first-level gated clock unit in the plurality of cascaded gated clock units is configured to: in response to the top-level enable signal, send the gate enable signal to the next-level gated clock unit, wherein the top-level enable signal is a single-clock-cycle pulse signal.

[0045] The first-level gated clock unit in the plurality of cascaded gated clock units is configured to: after the state of the top-level enable signal is set, in response to the top-level enable signal, send the gated enable signal to the next-level gated clock unit; after the state of the top-level enable signal is reset, in response to the top-level enable signal, stop sending the gated enable signal to the next-level gated clock unit; the state of the top-level enable signal is reset after each of the functional modules has generated the completion indication signal.

[0046] The gated clock unit is also configured to provide a global clock signal for the functional modules of this level in response to a bypass mode signal.

[0047] The functional module is further configured to: send the completion indication signal to the next-level gated clock unit after the work is completed; the gated clock unit is further configured to: during the operation of the functional module at this level, if a new data ready signal is received, send a task suspension signal to the previous-level gated clock unit; after receiving the completion indication signal sent by the functional module at this level, continue to provide a gated clock signal to the functional module at this level; after receiving the completion indication signal sent by the functional module at this level again, stop providing a gated clock signal to the functional module at this level; after receiving the completion indication signal sent by the functional module at the next level, if the suspension flag set by the gated clock unit at the next level is detected, continue to send a gated enable signal to the gated clock unit at the next level; after receiving the completion indication signal sent by the functional module at the next level again, stop sending a gated enable signal to the gated clock unit at the next level.

[0048] The circuit of the gated clock unit is as follows Figure 2 As shown in Table 1, the various input and output signals of the gated clock unit are described.

[0049] Table 1. Description of Input and Output Signals of the Gate Clock Unit

[0050] like Figure 3 As shown, the internal logic of the gated clock unit mainly consists of three parts.

[0051] (1) The logic for generating the local enable signal local_enable; (2) The logic for generating the enable signal enable_out of the next level functional module; (3) Control logic for generating the gated clock signal gated_clock of this functional module.

[0052] Specifically, the implementation method for generating the local enable signal local_enable is as follows: Upon reset, local_enable is forced to 0. Set action: When the operating mode is single-batch processing mode, if enable_in is sampled as high, local_enable is set to 1. When the operating mode is streaming mode, if the trigger signal external_data_ready=1 arrives while enable_in is high, local_enable is set to 1. Clear action: If the current functional module has completed its work, local_enable is cleared. Otherwise, local_enable remains unchanged.

[0053] Specifically, there are two schemes for generating the gating enable signal enable_out of the next level functional module.

[0054] The first approach: During the operation of the functional module, the corresponding gating enable signal `enable_out` remains at 1. Accordingly, the logic control method for the gating enable signal `enable_out` is as follows: Upon reset, enable_out is forced to 0; if the current functional module has completed its work, enable_out = 1; if the next functional module has completed its work, enable_out = 0 (here, the clearing of enable_out uses a handshake mechanism with a work completion flag signal); otherwise, it remains unchanged.

[0055] The working clock of the gate enable signal enable_out is preferably the falling edge of the global clock signal clk_global, because in this case, the local enable signals local_enable of the preceding and following gate clock units are seamlessly connected, and the working clock of the functional module can be provided in a timely manner without waiting period.

[0056] Optionally, the operating clock for the gate enable signal `enable_out` can also be the rising edge of the global clock signal `clk_global`. However, in this case, there is a clock cycle interval between the local enable signals `local_enable` of the preceding and following gate clock units. Consequently, the provision of the subsequent clock will also be delayed by one clock cycle.

[0057] The second approach: The gating enable signal enable_out is a single-cycle pulse signal.

[0058] Before a functional module begins operation, a gating enable signal (enable_out) pulse is provided to trigger its operation. During the operation of the functional module, the corresponding gating enable signal (enable_out) does not need to be kept at 1. The logic control method for the gating enable signal (enable_out) is as follows: the output gating enable signal (enable_out) of the gating clock unit is directly equivalent to the work completion indicator signal (work_complete) input.

[0059] The purpose of the second approach is to minimize the implementation area of ​​the gated clock unit.

[0060] Specifically, the method for generating the gated clock signal `gated_clock` for this functional module is as follows: The traditional approach may directly use an AND2 gate to generate the gated clock signal gated_clock, but this approach may result in glitches in the gated clock signal gated_clock.

[0061] As an alternative, ICG can be used to generate the gated clock signal `gated_clock`. Figure 4 As shown. In Figure 4 In the diagram: the local enable signal local_enable is connected to the enable input EN (active high) of the ICG, the global clock signal clk_global is connected to the clock input CLK of the ICG, and the output GCLK of the ICG outputs the gated clock signal gclk controlled by the local enable signal local_enable.

[0062] The gated clock signal gclk and the global clock signal clk_global are input to a 2-to-1 MUX. When the bypass mode signal bypass_mode=1, the MUX selects to output the global clock signal clk_global, the global clock is passed through, and the gated clock signal gclk is bypassed; when the bypass mode signal bypass_mode=0, the MUX selects to output the gated clock signal gclk.

[0063] If the digital standard cell library does not contain ICG, then discrete LATCH cells and AND2 gates can be used to build it, achieving the same effect as ICG.

[0064] As an alternative, a gated clock unit can be built using DFF + AND2 gates as a replacement for the ICG. For example... Figure 5 As shown, the DFF uses the falling edge of the global clock signal clk_global to sample the local enable signal local_enable, outputting the gate_en signal. The gate_en signal and the global clock signal clk_global are input into a two-input AND gate to obtain the gated clock signal gclk. The gated clock signal gclk and the global clock signal clk_global are input into a 2-to-1 MUX. When the bypass mode signal bypass_mode=1, the MUX selects to output the global clock signal clk_global; when the bypass mode signal bypass_mode=0, the MUX selects to output the gated clock signal gclk.

[0065] It should be noted that, when implementing specific embodiments, the basic implementation scheme can be adjusted in accordance with the specific actual needs, and the interface can be expanded.

[0066] Chain-gated clock circuits have single-batch processing mode and streaming mode.

[0067] The single-batch processing mode is suitable for single-batch processing tasks. After the system starts, it can automatically enter a sleep state after the task chain is completed without external intervention. This mode best reflects the advantages of "automation" and "low overhead".

[0068] The single-batch processing mode works as follows: an external controller generates a pulse signal to set the top-level enable signal `system_enable`. This enable signal propagates along the chain, and each functional module works sequentially. When the last functional module completes its work and outputs a completion indicator signal `work_complete`, this signal is fed back to automatically clear the top-level enable signal `system_enable`.

[0069] The overall workflow of single batch processing mode is as follows: When a functional module needs to be started, the top-level enable signal system_enable is set to high.

[0070] If the overall implementation scheme requires the top-level enable signal `system_enable` to remain high during the operation of the functional module cluster, then the high-level duration of the top-level enable signal `system_enable` will be greater than one system clock cycle. If the overall implementation scheme requires a single-cycle pulse signal to the top-level enable signal to trigger the operation of the functional module cluster, then the high level of the top-level enable signal `system_enable` needs to be removed promptly, ensuring that its high-level duration only lasts for one clock cycle.

[0071] The first-level gated clock unit detects that the top-level enable signal `system_enable` is high, sets the local enable signal `local_enable` to 1, and begins providing a working clock for the first-level functional module. Once the first-level functional module completes its work, it provides a completion indication signal `work_complete`. After receiving this `work_complete` indication signal, the first-level gated clock unit triggers the gated enable signal `enable_out` to 1.

[0072] The second-level gated clock unit detects that the enable signal `enable_in` is high and sets the local enable signal `local_enable` to 1, thus starting to provide gated clock signals to the second-level functional module. Once the second-level functional module completes its work, it provides a completion indication signal `work_complete`. After receiving the `work_complete` completion indication signal, the first-level gated clock unit disables the gated enable signal `enable_out`.

[0073] This process proceeds sequentially, like waves, until all functional modules are activated in turn.

[0074] Once the last functional module is completed, it provides a completion indicator signal, work_complete, which is then provided to the top level as feedback.

[0075] If the overall implementation scheme requires the top-level enable signal to remain at 1 during the operation of the functional module cluster, then the top-level enable signal system_enable should be cleared after the last-level functional module gives the completion indication signal work_complete.

[0076] If the overall implementation scheme requires a single-cycle enable pulse signal at the top level to trigger the functional module cluster to work once, then the top-level enable signal system_enable only needs to be high for one clock cycle.

[0077] Single-batch processing mode is suitable for scenarios such as image frame processing, data packet encryption / decryption, and one-time mathematical operations.

[0078] The single-batch processing mode greatly reduces the burden on the external controller. The external controller only needs to issue a "start" command and does not need to care about when the task will end.

[0079] Single-batch processing mode is suitable for scenarios such as video decoding, audio playback, and network data stream processing.

[0080] The advantage of single-batch processing mode is that the external controller has the highest privileges and can stop the entire processing chain at any time in response to high-priority events (such as user interruptions).

[0081] The streaming mode is suitable for streaming data processing. In this mode, the top-level enable signal system_enable acts as a global gate, managed by an external controller, and is suitable for continuous data streaming processing.

[0082] The streaming mode works as follows: The external controller pulls the top-level enable signal `system_enable` high when the data stream begins. As long as `system_enable` is high, the entire chain is in a "ready state" and can continuously process the input data stream. This enable chain ensures the startup order between modules. When the external controller decides to stop (e.g., when the data stream ends), it pulls the top-level enable signal `system_enable` low. After `system_enable` is pulled low, the system waits for the completion indicator signal `work_complete` from the last functional module to become valid before completely stopping, ensuring that the last frame of data is processed completely.

[0083] The overall working process of the streaming mode is as follows: When the system needs to start these functional modules, the top-level enable signal system_enable is set to high.

[0084] After the first-level gated clock unit detects that the external_data_ready indicator signal is high, it sets the local_enable signal to 1 and begins providing gated clock signals to the first-level functional modules. Once the first-level functional modules complete their work, they provide a work_complete indicator signal. Upon receiving this work_complete indicator signal, the first-level gated clock unit triggers the enable signal enable_out to be set to 1.

[0085] The second-level gated clock unit detects that the enable signal `enable_in` is high and sets the local enable signal `local_enable` to 1, thus starting to provide gated clock signals to the second-level functional module. Once the second-level functional module completes its work, it provides a completion indication signal `work_complete`. After receiving the `work_complete` completion indication signal, the first-level gated clock unit disables the gated enable signal `enable_out`.

[0086] This process proceeds sequentially, like waves, until all functional modules are activated in turn.

[0087] Before disabling the top-level enable signal system_enable, the top-level module should ensure that all functional modules have completed their operation.

[0088] In this embodiment, a chain-like transmission mechanism ensures that only the clock of the currently working functional module is active during the entire task processing process, while the clocks of all subsequent idle modules are completely turned off, thereby significantly reducing the overall flipping activity of the clock network.

[0089] A highly streamlined chain-gating structure replaces the complex central control state machine. The smaller and simpler the logic of the gating clock unit, the lower the power consumption of the control path itself. When the sum of the logic of all gating units is significantly less than that of the complex central control state machine, the functionality consumed by the gating unit itself will be far lower than that of traditional implementations.

[0090] During chip design and manufacturing, it is necessary to verify the correctness of the circuit. In normal chain-gated mode, to test the function of module 3, the top-level enable signal `system_enable` must first be enabled, and then the gating enable signal must be passed to module 3 in a wave-like manner. If module 1 or module 2 itself is defective, the enable signal may not reach module 3 at all, making it impossible to test module 3.

[0091] In this embodiment, a bypass mode signal, bypass_mode, is introduced. In test mode, bypass_mode is set to 1. At this time, the gated clock signals of all functional modules are directly connected to the global clock signal, clk_global, and are all in a normally open state. Test engineers can directly perform individual, comprehensive testing on any functional module without any limitations of the chained structure. This greatly improves test coverage and debugging efficiency.

[0092] In practical applications, for example, if the system malfunctions in normal mode (bypass_mode=0), switching to bypass_mode=1 will resolve the issue. If the system returns to normal, the problem lies in the gating clock chain logic (e.g., an enable propagation error). If the problem persists with bypass_mode=1, then the issue is definitely in the logic of each functional module itself.

[0093] Introducing the bypass mode signal bypass_mode can help quickly isolate problems, narrowing the fault location range by 50% and saving a lot of debugging time.

[0094] In scenarios where performance requirements are extremely high and power consumption is not a major concern, you can enable bypass_mode=1 to allow all functional modules to run at full speed and avoid any potential delays caused by gating.

[0095] If a timing issue is discovered in the chain gating system under certain extreme conditions in the future, it can serve as a "safe fallback" by temporarily using a bypass mode to ensure the chip's basic functions and allow time to fix the problem.

[0096] In the first example embodiment, such as Figure 6 As shown, the chain-gated clock circuit has a link depth of 4 levels. During the operation of the subsequent functional module, the gating enable signal enable_out provided by the preceding gating clock unit is continuously high. Here, the output of the gating enable signal enable_out is defined as level-type.

[0097] To facilitate the demonstration of the collaboration between the various modules of the entire circuit, functional modules 1 to 4 in the example embodiment are four instantiations of the same small design. Each module of this small design requires 10 clock cycles to operate, and a completion indicator signal (work_complete) is given at a high level on the 9th rising edge and at a low level on the 10th rising edge.

[0098] The timing waveform of the chain-gated clock circuit in single-batch processing mode is as follows: Figure 7 As shown, the timing waveform in stream processing mode is as follows: Figure 8 As shown.

[0099] Figure 7 In the chain-gated clock circuit, after the reset is completed, the global clock signal clk_global provides 44 pulses, and the gated clock signal gated_clk outputs 10 clock pulses.

[0100] Figure 8In the chain-gated clock circuit, after the reset is completed, the global clock signal clk_global provides 102 pulses, and the gated clock signal gated_clk outputs 30 clock pulses.

[0101] In this example embodiment, the total clock network flip activity is reduced by more than 70% before and after the clock is gated.

[0102] If no new data is allowed to arrive or trigger again during the operation of each functional module, then the data time interval of the top-level input must be greater than the maximum processing time of each functional module.

[0103] In single-batch processing mode, the top-level enable signal `system_enable` must be a single-cycle pulse input. If `system_enable` does not strictly adhere to this rule, and its high-level duration exceeds the processing cycle of the first gated clock unit, then the local enable signal `local_enable` will be provided again, along with the gated clock signal `gated_clk`. This level of functional module continues to work, and upon completion, a completion indicator signal `work_complete` is given. This triggers the gated enable signal `enable_out`, causing the next level of functional module to work again. As long as the top-level enable signal `system_enable` remains high, the functional module cluster will be continuously triggered to work. Furthermore, because the local enable signal `local_enable` is triggered to turn off after the completion indicator signal `work_complete` arrives, and then turns on again in the next cycle, this causes the gated clock signal `gated_clk` to pause for one clock cycle. Strictly speaking, this system response is no longer in single-batch processing mode and may not meet the requirements of actual applications. Relevant timing waveforms are as follows: Figure 9 As shown in the diagram above.

[0104] To ensure that the top-level enable signal remains continuously high throughout the entire functional module cluster operation in single-batch processing mode, the existing solution can be fine-tuned and modified to match the top-level signal, thereby enhancing fault tolerance and reliability.

[0105] The first correction method is to add a D flip-flop to the gated clock unit, use the global clock signal clk_global to clock the enable signal enable_in once, and output the signal enable_in_dly; add rising edge detection logic for the enable signal enable_in: pos_enable_in = !enable_in_dly&enable_in.

[0106] At the same time, the logic of the local enable signal local_enable needs to be adjusted as follows: In single-batch processing mode, if the current functional module provides a completion indication signal (work_complete) pulse, the local enable signal (local_enable) is cleared to zero. If pos_enable_in is detected to be 1, the local enable signal (local_enable) is set.

[0107] The second correction method is to add a work_done_flag signal to the gated clock unit.

[0108] The processing logic for the work_done_flag signal is as follows: the reset value is 0; when the current functional module provides the work_complete indicator signal pulse, the work_done_flag signal is set to 1; when the enable signal enable_in is invalid, the work_done_flag signal is cleared to zero.

[0109] The setting logic for the local enable signal local_enable needs to be adjusted as follows: In single-batch processing mode, if the local functional module provides a work_complete pulse signal, the local_enable signal is cleared to zero. The local_enable signal is only set if the work enable signal enable_in is 1 and the work_done_flag is 0.

[0110] The corrected timing waveform is as follows Figure 9 The diagram below shows the same result regardless of whether the correction method is one or two.

[0111] Figure 7 , 8 9 signals and Figure 6 The correspondence is as follows: the local_enable of gated clock units 1~4 corresponds to local_enables[0]~local_enables[3] in the waveform diagram respectively; the gated clock signal gated_clk output by gated clock units 1~4 corresponds to gated_clocks[0]~gated_clocks[3] in the waveform diagram respectively; the gated enable signal enable_out output by gated clock units 1~4 corresponds to enable_outs[0]~enable_outs[3] in the waveform diagram respectively; the completion indicator signal work_complete output by functional modules 1~4 corresponds to work_completes[0]~work_completes[3] in the waveform diagram respectively.

[0112] In the second example embodiment, a simplified scheme is provided to minimize the logic resources required for implementing the gated clock unit. In this scheme, the gate enable signal `enable_out` of the gated clock unit outputs a single-cycle pulse. The output of the gate enable signal `enable_out` is defined as pulse-type.

[0113] like Figure 10 The diagram illustrates the interconnection when the gate enable signal `enable_out` of the gated clock units are all single-cycle pulses. In this scenario, the `external_data_ready` indicator signal of all gated clock units, except for the first-level unit which is connected to the top-level input indicator signal `system_data_ready`, is fixed at 1 for all other levels. Furthermore, the `next_work_complete` indicator signal is not required for any of the gated clock units at this time. The output of the gate enable signal `enable_out` is directly equivalent to the input of the completion indicator signal `work_complete`. Based on this, some logic in the gated clock units can be trimmed and optimized, thus simplifying the interconnection between modules.

[0114] In single-batch operation mode: A single top-level enable signal, `system_enable`, is sufficient to trigger the cluster to operate once. The timing waveform is as follows: Figure 11 As shown.

[0115] In streaming mode: the top-level enable signal `system_enable` remains high, and the top-level indicator signal `system_data_ready` triggers the pipeline operation. The timing waveform is as follows: Figure 12 As shown.

[0116] In the third example embodiment, if the functional module has a single-level buffer for data input, meaning that the functional module can accept another data input during its operation (external_data_ready=1), and regardless of whether the data is new or old, the time required from the input of that data to its completion and output of the work_complete indicator signal is the same, then the corresponding gated clock unit needs to be matched to prevent it from shutting down its working clock after receiving the work_complete indicator signal from the previous data input, thus preventing the functional module from continuing to operate even if new data has not yet been processed.

[0117] In this case, it is necessary to logically extend the gated clock unit to synchronously support a single pending task.

[0118] like Figure 13As shown, the completion indicator signal `work_complete` of the Nth level functional module is input to the N-1th level gated clock unit and also to the N+1th level gated clock unit. The task pending signal output by the next level functional module is connected to the `next_pending` input port of the previous level module. The `next_pending` input port of the last level module can be processed with 0. The task pending signal `pending` of the first level module can be provided to the top level as a feedback signal. The readiness indicator signal `external_data_ready` of the first level gated clock unit is connected to the top level indicator signal `system_data_ready`. The `next_work_complete` of the last level gated clock unit is processed with 0.

[0119] The pending signal indicates that a task is pending at the current level, while next_pending indicates that a task is pending at the next level. When local_enable=1, if a new ready signal external_data_ready arrives again, the pending flag will be set to 1.

[0120] When the `work_complete` indicator arrives, if the pending flag is detected as 1, the local enable signal `local_enable` should not be disabled; it should remain high to continue providing the operating clock for this level of functional module. After the next `work_complete` indicator pulse arrives, the pending flag is cleared, the local enable signal `local_enable` is disabled, and this level of functional module stops working. When the `next_work_complete` pulse of the next level module arrives, if the `next_pending` flag of the next level is detected as 1, the `enable_out` output of the next level module should not be disabled; it should remain high. When the `next_work_complete` pulse of the next level module arrives again, the `enable_out` output of the next level module is disabled, and the next level functional module stops working.

[0121] In this example embodiment, a new readiness indicator signal external_data_ready is recorded during the operation of the functional module, and pending tasks are processed immediately after the current task is completed, thereby achieving a balance between performance and hardware overhead.

[0122] In the fourth example embodiment, a FIFO buffer is inserted between the various functional modules to maximize system throughput, allowing each module to run at a different speed, which is suitable for high data rate scenarios.

[0123] like Figure 14 As shown, the chain-gated clock circuit has a link depth of 4 levels. Assume that functional module 1 has the fastest processing speed and the shortest processing cycle, and does not require a FIFO buffer when inputting data. However, subsequent functional modules have longer processing cycles. To match the speeds of the preceding and following stages, FIFO buffers are added between each stage.

[0124] Accordingly, the gated clock unit needs to be designed with two input signals: pre_fifo_empty and post_fifo_empty. pre_fifo_empty indicates the empty flag of the FIFO connected to the front end of this functional module; a value of 1 indicates an empty FIFO. post_fifo_empty indicates the empty flag of the FIFO connected to the back end of this functional module; a value of 1 also indicates an empty FIFO.

[0125] The empty flag of the Nth level FIFO (FIFO N) is input to the post_fifo_empty terminal of the Nth level gated clock unit and the pre_fifo_empty terminal of the N+1th level gated clock unit.

[0126] exist Figure 14 In this process, because the front end of functional module 1 does not perform FIFO processing on the input data stream, `pre_fifo_empty` is processed by line 1. The back end of the last-level functional module does not have a FIFO connection, so `post_fifo_empty` is processed by line 1. The completion indicator signal `work_complete` of the Nth-level functional module is input to the `work_complete` terminal of the Nth-level gated clock unit and the `next_work_complete` terminal of the (N-1)th-level gated clock unit.

[0127] In this example embodiment, the gated clock unit is further configured to: stop sending a gated enable signal to the next-level gated clock unit after receiving a completion indication signal sent by the next-level functional module and an empty indication signal sent by the front-end FIFO buffer of the next-level functional module; the gated clock unit is further configured to: stop providing a gated clock signal to the current-level functional module after receiving a completion indication signal sent by the current-level functional module and an empty indication signal sent by the front-end FIFO buffer of the current-level functional module.

[0128] Once the current functional module completes (work_complete=1), the next functional module is immediately enabled (enable_out=1). The next functional module is disabled when it completes its work (next_work_complete=1) and the FIFO buffer connected to the back end of the current functional module (i.e., the FIFO connected to the front end of the next functional module) is empty (post_fifo_empty=1). This indicates that the data flow processing required by the next functional module has been completed.

[0129] It should be noted that the back-end FIFO buffer of the current functional module is actually the front-end FIFO buffer of the next functional module; they physically refer to the same thing.

[0130] When the enable signal enable_in of the current level is detected to be valid, the local enable signal local_enable is immediately set to 1; once the current functional module completes its work, work_complete=1 and its front-end FIFO flag is empty, indicating that the data flow work required by the current functional module has been completed, then local_enable is cleared.

[0131] In a preferred embodiment, all read and write operations of the FIFO buffers use the global clock signal clk_global.

[0132] Since the gated clock signals of each module in this application all originate from the same global clock signal clk_global, and the start and stop of the gated clock signal will not change the clock phase, there is no real asynchronous clock domain problem. Therefore, synchronous FIFO is a completely applicable and optimal technical choice.

[0133] The synchronous FIFO buffer design used in this example avoids the complexity of cross-clock domain synchronization, ensures reliable data caching during the period when the gated clock signal is off, guarantees data integrity, and has lower design overhead compared to the asynchronous FIFO buffer design.

[0134] In an alternative approach, an asynchronous FIFO buffer can be used for data buffering, where the write clock is connected to the gate clock signal of the preceding functional module, and the read clock is connected to the gate clock signal of the following functional module. However, due to the start-stop characteristics of the gate clock signal, the pointer synchronization mechanism and empty / full judgment of the asynchronous FIFO may face challenges. Therefore, a synchronous FIFO buffer is the preferred solution of this invention.

[0135] In order to minimize the dynamic power consumption of the overall system, the operating clock of the FIFO buffer is not connected to the global clock signal, but is also subject to clock gating control.

[0136] Specifically, each intelligent gating unit adds an output port and directs its internal local enable signal local_enable to this output port for use by peripheral circuits.

[0137] The local enable signal `local_enable` of the previous stage and the local enable signal `local_enable` of the next stage are ORed to obtain the enable signal `fifo_clk_en`, which is used as the clock gating enable for the FIFO buffer. When the enable signal `fifo_clk_en` is valid, a working clock signal is provided to the FIFO buffer; otherwise, the FIFO has no working clock signal.

[0138] When the local enable signal local_enable of the current level is valid, a working clock signal is provided for the FIFO buffer, which is for the purpose of completing the FIFO buffer write operation; when the local enable signal local_enable of the next level is valid, a working clock signal is provided for the FIFO buffer, which is for the purpose of completing the FIFO buffer read operation.

[0139] To prevent FIFO buffer overflow, this embodiment can also introduce a backpressure mechanism: when the FIFO buffer is full, a full flag signal "full" is sent to the current-level functional module. Upon receiving the full flag signal "full", the current-level functional module suspends operation until the FIFO buffer is no longer full. For the top-level control system, when the full flag signal "full" of FIFO1 is valid, the input data stream should be paused.

[0140] When the current functional module completes its work (work_complete=1), it writes the output data to the FIFO buffer. If the backpressure mechanism is enabled, the write enable of the FIFO buffer is jointly controlled by the completion indicator signal work_complete of the preceding module and the non-full condition of the FIFO buffer.

[0141] The read enable of the FIFO buffer is jointly controlled by the local enable signal `local_enable` of the subsequent module and the non-empty condition of the FIFO buffer. When the subsequent functional module is ready to work, it can read data from the FIFO buffer and start working when its gated clock is on and the FIFO buffer is not empty.

[0142] The write operation occurs when the current module finishes its work. At this time, the local enable signal local_enable of the current module is 1, so the write clock signal is valid (because the write clock is a global clock signal and the write enable signal is valid).

[0143] Read operations occur when the local enable signal `local_enable` of the next-level module is 1 and the FIFO buffer is not empty. The read clock signal is a global clock signal, but the read enable signal is controlled by the local enable signal `local_enable` of the next-level module.

[0144] This embodiment achieves a unified approach to data flow control and power management by deeply coordinating the status flags of the FIFO buffer with the gated clock signal, ensuring data integrity while further optimizing system power consumption.

[0145] In the fifth example embodiment, when the top-level enable signal is invalid, all functional modules will also stop working. Simultaneously, all gating clock units at each level will no longer output gating clock signals, and their internal register outputs will not toggle, significantly reducing the dynamic power consumption of the entire system. However, if a global clock is still provided, the entire system will still experience dynamic power consumption loss, which occurs in each gating clock unit. After all, the clock input of the register also has an input capacitor, and if the clock keeps toggling, dynamic power consumption loss is inevitable.

[0146] To completely eliminate the dynamic power consumption of the chain-gated clock circuit system, a logic can be added at the top level: when the top-level enable is invalid, the input to the global clock is turned off. Thus, when the top-level enable signal is invalid, the dynamic power consumption of the gated clock circuit system can be reduced to zero. Of course, this logic can also be implemented within the gated clock circuit system itself.

[0147] This example embodiment is applicable to scenarios where the corresponding top-level enable signal is always at a valid high level during the operation of the functional module cluster.

[0148] This application's chain-gated clock circuit is suitable for integrated circuits where there are dependencies in data flow, control flow, or startup sequence between modules. It is primarily applicable to the following core scenarios: (1) Pipeline data processing system Typical examples: Image signal processors (ISPs), audio codecs, cryptographic pipelines, and specific layers of neural network accelerators.

[0149] Working mode: Data sequentially goes through multiple stages such as "sampling -> preprocessing -> core processing -> postprocessing". Each subsequent stage (B) must wait for valid data to be produced by the preceding stage (A) before it can begin processing.

[0150] (2) System startup / shutdown in an orderly manner Typical examples: power management of complex SoCs, core wake-up sequences in multi-core systems, and processing units of communication protocol stacks.

[0151] Operating mode: The system has strict power-on / power-off sequence requirements. For example, the I / O power domain must be powered on before the core power domain, and the cache controller must be initialized before the CPU core.

[0152] (3) Other similar module clusters with producer-consumer relationships Operating mode characteristics: The clock activity of the consumer module is completely wasted until the producer module provides valid data.

[0153] Secondly, embodiments of the present invention provide a control method for a chain-gated clock circuit, applied to the circuit described in the first aspect, comprising: The control gate clock unit provides gate clock signals to the functional modules at this level, and after receiving the completion indication signal sent by the functional modules at this level, it stops providing gate clock signals to the functional modules at this level and sends a gate enable signal to the gate clock unit at the next level. The control function module performs its work in response to the gated clock signal, and sends the completion indication signal to the gated clock unit of the same level after the work is completed.

[0154] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0155] The chain-gated clock circuit and its control method of this invention are primarily aimed at IC integrated circuit design. Those skilled in the art should understand that when the target platform is an FPGA, this can be achieved by transforming its core control concept (i.e., the chain-gated enable propagation mechanism) into control of the register clock enable terminal, which also falls within the protection spirit of this invention.

[0156] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A chain-gated clock circuit, characterized in that, The circuit includes multiple cascaded gated clock units and multiple cascaded functional modules, with each gated clock unit corresponding to a functional module of its level. The gated clock unit is configured to: provide a gated clock signal to the functional module at this level, and after receiving a completion indication signal sent by the functional module at this level, stop providing a gated clock signal to the functional module at this level, and send a gated enable signal to the gated clock unit at the next level. The functional module is configured to: perform work in response to the gated clock signal, and send the completion indication signal to the gated clock unit of the same level after the work is completed.

2. The circuit according to claim 1, characterized in that, The functional module is also configured to send the completion indication signal to the next higher level gated clock unit after the work is completed; The gated clock unit is also configured to stop sending gated enable signals to the next level gated clock unit after receiving a completion indication signal from the next level functional module.

3. The circuit according to claim 1, characterized in that, The functional module is also configured as follows: In response to the gating enable signal, the local enable signal is made valid; or in response to the gating enable signal and the data ready signal, the local enable signal is made valid; when the local enable signal is valid, a gating clock signal is provided to the functional modules of this level. Upon receiving a completion indication signal from the functional module at this level, the local enable signal is invalidated.

4. The circuit according to claim 1, characterized in that, The first-level gated clock unit in the plurality of cascaded gated clock units is configured to: after the state of the top-level enable signal is set, in response to the top-level enable signal, send the gate enable signal to the next-level gated clock unit. The last-level functional module in the multiple cascaded functional modules is configured to: after completing its work, also feed back the completion indication signal to reset the state of the top-level enable signal.

5. The circuit according to claim 1, characterized in that, The first-level gated clock unit in the plurality of cascaded gated clock units is configured to: in response to the top-level enable signal, send the gate enable signal to the next-level gated clock unit, wherein the top-level enable signal is a single-clock-cycle pulse signal.

6. The circuit according to claim 1, characterized in that, The first-level gated clock unit in the plurality of cascaded gated clock units is configured to: after the state of the top-level enable signal is set, in response to the top-level enable signal, send the gate enable signal to the next-level gated clock unit. After the state of the top-level enable signal is reset, in response to the top-level enable signal, the sending of the gating enable signal to the next level gating clock unit is stopped; the state of the top-level enable signal is reset after the completion indication signal is generated in each of the functional modules.

7. The circuit according to claim 1, characterized in that, The gated clock unit is also configured to: In response to the bypass mode signal, a global clock signal is provided for the functional modules of this level.

8. The circuit according to claim 1, characterized in that, The functional module is also configured to send the completion indication signal to the next level gated clock unit after the work is completed; The gated clock unit is further configured to: during the operation of the functional module at this level, if a new data ready signal is received, send a task suspension signal to the gated clock unit at the next higher level; after receiving a completion indication signal sent by the functional module at this level, continue to provide a gated clock signal to the functional module at this level; and after receiving a completion indication signal sent by the functional module at this level again, stop providing a gated clock signal to the functional module at this level. After receiving a completion indication signal from the next-level functional module, if the pending flag is detected to be set by the next-level gated clock unit, the gating enable signal is sent to the next-level gated clock unit. After receiving a completion indication signal from the next-level functional module again, the gating enable signal is stopped from being sent to the next-level gated clock unit.

9. The circuit according to claim 1, characterized in that, It also includes a FIFO buffer connected between two adjacent functional modules; The gated clock unit is further configured to: stop sending the gate enable signal to the next level gated clock unit after receiving the completion indication signal sent by the next level functional module and the empty indication signal sent by the front-end FIFO buffer of the next level functional module. The gated clock unit is further configured to stop providing gated clock signals to the functional module at this level after receiving a completion indication signal sent by the functional module at this level and an empty indication signal sent by the front-end FIFO buffer of the functional module at this level.

10. A control method for a chain-gated clock circuit, applied to the circuit as described in any one of claims 1-9, characterized in that, include The control gate clock unit provides gate clock signals to the functional modules at this level, and after receiving the completion indication signal sent by the functional modules at this level, it stops providing gate clock signals to the functional modules at this level and sends a gate enable signal to the gate clock unit at the next level. The control function module performs its work in response to the gated clock signal, and sends the completion indication signal to the gated clock unit of the same level after the work is completed.

Images