A method, system for multi-level branch prediction hardware power optimization in an integrated circuit
By dynamically disabling the read enable signal of redundant branch target memory in the integrated circuit, combined with a hardware data comparator and a prediction level mask register array, the problem of invalid power consumption and heat generation caused by redundant reading of multi-level branch target memory is solved, achieving low power consumption management and improved stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG UNIV
- Filing Date
- 2026-05-12
- Publication Date
- 2026-07-07
AI Technical Summary
Redundant reads of multi-level branch target memory in existing integrated circuits lead to ineffective power consumption and chip overheating. Existing technologies reduce chip throughput by inserting hardware wait cycles or truncating the physical pipeline.
The hardware control logic queries the prediction level mask register array when a branch instruction is entered, dynamically disables the redundant branch target memory read enable signal, and combines the hardware data comparator to latch data level by level and generate physical entries of the prediction level mask register array, and updates the redundancy mask configuration in real time.
It significantly reduces chip dynamic power consumption, improves the heat generation problem caused by frequent cache access, and achieves fine-grained low-power management of multi-level cache without sacrificing instruction fetch performance, thereby improving the stability of the architecture.
Smart Images
Figure CN122174788B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit chip design, specifically relating to a method and system for optimizing hardware power consumption through multi-level branch prediction in integrated circuits. Background Technology
[0002] With the continuous evolution of integrated circuit manufacturing processes, the "power wall" problem of microprocessor chips is becoming increasingly severe. In the front-end design of modern high-performance superscalar processors, to balance extremely low branch prediction latency and extremely high prediction accuracy, a deeply pipelined (e.g., P0 to P4 clock cycle stages) multi-level branch target memory architecture built by physical hardware is widely adopted. The multi-level branch target memory hardware typically includes a high-speed first-level static random access memory, a medium-capacity second-level static random access memory, and a third-level static random access memory that occupies a large amount of chip area.
[0003] In existing chip hardware architectures, to maximize timing performance, processors typically use hardware control logic to raise the "read enable" pins of the static random access memory (SRAM) for all branches in parallel during the instruction fetch phase. However, the actual instruction flow characteristics of chips show that the physical data residing in the lower-level caches (such as L1 and L2) of SRAM for a large number of regular branches is completely redundant with the data in the higher-level caches (such as L3). If the extremely power-intensive L3 SRAM is forcibly woken up in parallel every clock cycle, it will cause a massive amount of ineffective capacitance switching in the internal transistors, leading to severe dynamic power consumption and heat generation problems in the chip.
[0004] Existing technologies for reducing chip power consumption often achieve this by inserting hardware wait cycles or interrupting the physical pipeline. This inevitably leads to "fetch bubbles" at the chip front end, severely reducing chip throughput. The key technological barrier in high-end integrated circuit chip design is how to precisely shield redundant static random access memory reads using pure hardware logic circuits without introducing additional fetch bubbles. Summary of the Invention
[0005] The purpose of this invention is to provide a method and system for optimizing hardware power consumption for multi-level branch prediction in integrated circuits, so as to solve the problems of invalid power consumption and chip overheating caused by redundant reading of multi-level branch target memory in existing integrated circuits.
[0006] To achieve the above objectives, the technical solution of the present invention is as follows:
[0007] When a branch instruction enters the chip's P0 clock cycle, the hardware extracts the current instruction address and uses it to query the prediction level mask register array. If the query is successful, the written physical table entry is read, and the hardware control logic sets the redundant branch target memory read enable signal low based on the level mask bit in the physical table entry, thus entering the instruction execution stage. If the query fails, the hardware control logic sets the read enable signals of the first, second, and third level branch target memories high and performs the following hardware data comparison.
[0008] During clock cycle P1, the data output from the first-level branch target memory is latched; during clock cycle P2, the data output from the second-level branch target memory is latched; during clock cycle P3, the data output from the third-level branch target memory is latched. Data alignment is performed using D flip-flops, and the data latched in the memory is processed by a hardware data comparator configured inside the chip. This process identifies redundant branch target memories, generates physical entries for the prediction level mask register array, and writes them to the prediction level mask register array in real time, thus entering the instruction execution stage.
[0009] When an instruction address write or jump error occurs, a physical synchronization rollback is performed, and the hardware control logic immediately and asynchronously clears the physical table entry cached at that address.
[0010] Preferably, the hardware data comparator includes the following operations:
[0011] Based on the data latched during clock cycles P1-P3, logical operations are performed on the output results of the three-level branch target memory during clock cycle P3: if the data in the first-level branch target memory is redundant with the data in the third-level branch target memory, then only the read enable signal of the first-level branch target memory is set to high level and always kept on; if the data in the second-level branch target memory is redundant with the data in the third-level branch target memory, and there is no cache hit in the first-level branch target memory, then the read enable signal of the second-level branch target memory is set to high level.
[0012] Preferably, the P3 clock cycle is:
[0013] During the P3 clock cycle, D flip-flops are used to perform time-lapse alignment of target memory for different branches, thereby aggregating the data latch results of different branches.
[0014] Preferably, the prediction level mask register array lookup table is used:
[0015] During the P0 clock cycle, the hardware sends the instruction address to the prediction hierarchy mask register array, queries the tag bit of the address in the hierarchy mask register array, and if the query is successful, it uses the logic control circuit to force the read enable pin of the corresponding register to go low according to the tag bit.
[0016] Preferred, physical entries:
[0017] This includes valid bits, tag bits, and hierarchical masking flag bits. When a reset occurs, the hardware logic sends a batch clear signal to this bit, and at the same time, the hierarchical masking flag is physically disabled. The hierarchical masking flag is connected to the branch target memory at different levels through mutually exclusive control line level signals.
[0018] Preferably, physical synchronization rollback includes:
[0019] When an instruction address is abnormal, the hardware logic circuit directly connects the write enable signal line of the target memory of the corresponding branch to the asynchronous clear pin of the prediction level mask register array.
[0020] Preferably, instruction address write or jump exceptions include:
[0021] During the fetch phase, writing to the same address in the first and second level branch target memory triggers an instruction address exception; during the instruction execution phase, an instruction address exception is triggered when a jump exception occurs due to an incorrect instruction address fetch.
[0022] Preferably, writing to the prediction level mask register array includes:
[0023] The mutual exclusion level signal generated by the hardware data comparator and combinational logic gates within the P3 clock cycle is used to generate the read enable signal of the corresponding branch target memory through logic gate operations, and is immediately written into the prediction level mask register array for data latching.
[0024] Preferred prediction level mask register array:
[0025] Predictive hierarchy mask register arrays are extremely low-latency register files or very small-capacity memory located at the front end of the chip.
[0026] A multi-level branch prediction hardware power optimization system in an integrated circuit includes:
[0027] In the instruction fetch module, when a branch instruction enters the chip's P0 clock cycle, the hardware fetches the current instruction address and uses this address to query the prediction level mask register array. If the query is successful, the written physical table entry is read, and the hardware control logic sets the redundant branch target memory read enable signal to low level according to the level mask bit in the physical table entry, thus entering the instruction execution stage. If the query fails, the hardware control logic sets the read enable signals of the first, second, and third level branch target memories to high level, thus entering the logic gate operation module.
[0028] The logic gate operation module latches the data output from the first-level branch target memory in clock cycle P1; latches the data output from the second-level branch target memory in clock cycle P2; and latches the data output from the third-level branch target memory in clock cycle P3. Data alignment is performed through D flip-flops. At the same time, the hardware data comparator configured inside the chip performs logic gate operations on the data latched in the memory, determines redundant branch target memories, generates physical entries for the prediction level mask register array, and writes them into the prediction level mask register array in real time, thus entering the instruction execution stage.
[0029] The reset module performs a physical synchronous rollback when an instruction address write or jump error occurs. The hardware control logic immediately clears the physical table entry cached at that address asynchronously.
[0030] Compared with the prior art, the technical solution provided by this invention has the following advantages:
[0031] This invention designs a low-latency predictive level mask register array that quickly completes address lookup in the P0 cycle and dynamically disables the read enable pin of the redundant branch target cache according to hardware logic, thereby reducing invalid read operations, significantly reducing chip dynamic power consumption, and improving the heat generation problem caused by frequent cache access.
[0032] Based on the P1-P3 clock cycles, the cache data at each level is latched sequentially. Combined with the hardware comparator, cache redundancy is automatically determined, mutual exclusion level masking flags are generated and latched and updated in real time. The entire process is a pure hardware closed-loop control without the need for software intervention. It achieves fine-grained low-power management of multi-level caches without sacrificing instruction fetch performance.
[0033] By using a hard-wired design between the branch target cache write enable signal and the asynchronous clear pin of the PLMA array, the shielding configuration is instantly reset when the cache entry is overwritten or when an error correction occurs during jump, allowing the hardware to quickly return to the full parallel working mode, avoiding control logic errors caused by data updates, and improving the stability of the architecture. Attached Figure Description
[0034] Figure 1 This refers to the physical entries of the on-chip PLMA register array involved in this invention. Detailed Implementation
[0035] This invention is applied to microprocessor chips containing multi-level on-chip cache units. The chip includes a multi-cycle (e.g., P0-P4 clock cycles) hardware pipeline and first-level, second-level, and third-level branch target caches composed of physical memory macros. To further understand the invention, a detailed description is provided in conjunction with embodiments.
[0036] A method for optimizing hardware power consumption in integrated circuits by predicting multi-level branches includes:
[0037] S1. When a branch instruction enters the chip's P0 clock cycle, the hardware extracts the current instruction address and uses this address to query the prediction level mask register array. If the query is successful, the written physical table entry is read, and the hardware control logic sets the redundant branch target memory read enable signal to low level according to the physical table entry, entering the instruction execution stage. If the query fails, the hardware control logic sets the read enable signals of the first, second, and third level branch target memories to high level, entering S2.
[0038] When a branch instruction enters the processor's branch prediction pipeline for the first time (or re-enters after a cache miss), the prediction level mask array (PLMA) has not yet recorded the instruction's level mask information.
[0039] During the P0 clock cycle, the instruction address of the instruction enters the PLMA and reads the physical table entry. If a miss occurs, the chip hardware control logic sets the read enable signals of the first, second, and third level branch target memories to a high level, and all levels of memory arrays are activated in parallel.
[0040] Preferred prediction level mask register array:
[0041] Predictive hierarchy mask register arrays are extremely low-latency register files or very small-capacity memory located at the front end of the chip.
[0042] PLMA is an extremely low-latency register file or a very small-capacity static random access memory built on the front end of the chip.
[0043] Preferred, physical entries:
[0044] This includes valid bit bits, tag bit bits, and hierarchy mask flag bits. Upon reset, the hardware logic sends a bulk clear signal to these bits, and simultaneously, the hierarchy mask flag bits are physically disabled. The hierarchy mask flag bits are connected to different levels of branch target memory via mutually exclusive control line level signals.
[0045] like Figure 1 As shown, the physical entries in PLMA include:
[0046] Valid bit (1-bit flip-flop): When a physical write replacement or chip global reset occurs, the hardware logic sends a batch clear signal to this bit, causing the hierarchical masking flag bit to fail instantly and completing the synchronous reset of the cache management state.
[0047] Tag bit (multi-bit register): Records the high-order bits of the physical address of the instruction. Address tag comparison is completed through a pure hardware digital comparator to suppress hash address collisions and avoid the generation and output of error masking control signals.
[0048] Level masking flags (mask flag 1 and mask flag 2): These use mutually exclusive control line level signals coupled to the read enable logic units of each level of branch target memory via on-chip physical hardwires to achieve dynamic hardware shutdown control of redundant caches. If mask flag 1 is set to 1, it indicates that the first-level branch target cache has a cache hit and is redundant with other branch target caches, and the read enable pins of the second and third-level branch target caches can be masked. If mask flag 2 is set to 1, it indicates that the second-level branch target cache has a cache hit and is redundant with other branch target caches, and the read enable pin of the third-level branch target cache can be masked.
[0049] Preferably, the prediction level mask register array lookup table is used:
[0050] During the P0 clock cycle, the hardware sends the instruction address to the prediction hierarchy mask register array, queries the tag bit of the address in the hierarchy mask register array, and if the query is successful, it uses the logic control circuit to force the read enable pin of the corresponding register to go low according to the tag bit.
[0051] Specifically, there are three scenarios. Scenario 1: If only the first-level branch target memory is high (valid) when the PLMA physical port outputs, the combinational logic gates in the control circuit will force the read enable physical pins of the second and third-level branch target memories to go low, keeping these large memory arrays in sleep mode, eliminating power consumption from dynamic transistor switching, and thus reducing chip heat generation.
[0052] In the second scenario, if the PLMA physical port outputs a high level for the second-level branch target memory, the combinational logic gate in the control circuit will only pull down the read enable physical pin of the third-level branch target memory, putting it into a sleep state.
[0053] In scenario three, if PLMA is not hit, the chip enters the baseline state, where the read enable pins of all level branch target memories are pulled high in parallel.
[0054] S2. During clock cycle P1, latch the data output from the first-level branch target memory; during clock cycle P2, latch the data output from the second-level branch target memory; during clock cycle P3, latch the data output from the third-level branch target memory. At the same time, the hardware data comparator configured inside the chip performs logic gate operations on the data latched in the memory, determines redundant branch target caches, generates physical entries for the prediction level mask register array, and writes them into the prediction level mask register array in real time, thus entering the instruction execution stage.
[0055] Preferably, the P3 clock cycle is:
[0056] During the P3 clock cycle, D flip-flops are used to perform latching alignment of target caches for different branches, thereby aggregating the data latching results of different branches.
[0057] As the pipeline advances, different physical access delays in the branch target memories at each level create misaligned data streams on the bus. Specifically: in clock cycle P1, the first-level branch target memory data L0_D is latched using a D flip-flop; in clock cycle P2, the second-level branch target memory data L1_D is latched using a D flip-flop; and in clock cycle P3, the third-level branch target memory data L2_D is latched using a D flip-flop. Within the current clock cycle P3, the D flip-flops aggregate the first-level branch target memory signal lines with a two-step delay, the second-level branch target memory signal lines with a one-step delay, and the current third-level branch target memory signal lines.
[0058] Data comparison is performed using a hardware data comparator configured inside the chip.
[0059] Preferably, the hardware data comparator includes the following operations:
[0060] Based on the data latched during clock cycles P1-P3, logical operations are performed on the output results of the three-level branch target cache during clock cycle P3: if the data in the first-level branch target memory is redundant with the data in the third-level branch target memory, then only the read enable signal of the first-level branch target memory is set to high level and always kept on; if the data in the second-level branch target memory is redundant with the data in the third-level branch target memory, and there is no cache hit in the first-level branch target memory, then the read enable signal of the second-level branch target memory is set to high level.
[0061] If L0_D == L2_D, it indicates a cache hit in the first-level branch target memory and redundancy with the third-level branch target memory cache. The logic gate sets the read enable pin of the first-level branch target memory to high, and simultaneously drives the logic gate to set the read enable pins of both the first and second-level branch target memories to low. If the first-level branch target memory cache misses, but L1_Data == L2_Data, it indicates a cache hit in the second-level branch target memory and redundancy with the third-level branch target memory cache. The logic gate sets the read enable pin of the second-level branch target memory to high, and simultaneously drives the logic gate to set the read enable pin of the second-level branch target memory to low.
[0062] Store the high-order bits of the instruction address into the tag bit of the physical table entry.
[0063] When the hardware comparator confirms data bus consistency and a valid bit is high, it sets the read enable pin of the first-level branch target memory high via an AND gate. By introducing an inverted signal from a NOT gate as a mutual exclusion barrier, the read enable pin of the second-level branch target memory is set high only when the first-level branch target memory hit fails and the second-level branch target memory hit succeeds. The generated pin level signals are then written to the corresponding level mask flag bits.
[0064] The pin level signals of the first and second level branch target memory are used to generate write enable signals through logic NOT gates and stored in the valid bits of the physical table entries to complete the PLMA write operation of the on-chip front end.
[0065] In particular, to reduce instruction fetch bubbling, this invention adheres to the principle that the first-level branch target memory must never be masked. Regardless of how the chip's hardware state machine transitions, the read enable pin of the first-level branch target memory, being normally open (or unmasked) on the physical connection, must never be disconnected by the aforementioned hardware logic. This ensures that the chip can output the target address bus signal to the front end in the shortest possible clock cycle, eliminating instruction fetch bubbling at its hardware root.
[0066] S3. When the instruction address is abnormal, a physical synchronization rollback is performed, and the hardware control logic immediately clears the physical table entry of the address cache asynchronously.
[0067] To prevent the failure to detect abnormal instruction address status when the read pin is blocked, this invention employs strong synchronization logic for physical connections triggered by write operations.
[0068] Preferably, instruction address anomalies include:
[0069] During the fetch phase, writing to the same address in the first and second level branch target memory triggers an instruction address exception; during the instruction execution phase, an instruction address exception is triggered when a jump exception occurs due to an incorrect instruction address fetch.
[0070] When the chip writes new data to the first and second level branch target memory, causing the old entries to be physically overwritten, or when a jump error occurs due to an instruction address abnormality during the execution phase, the hardware unit in the execution phase writes a new predicted instruction address to the second level branch target memory, triggering an instruction address abnormality and causing a physical synchronization rollback mechanism.
[0071] Preferably, physical synchronization rollback includes:
[0072] When an instruction address is abnormal, the hardware logic circuit directly connects the write enable signal line of the corresponding branch target register to the asynchronous clear pin of the prediction level mask register array.
[0073] The hardware directly connects the write enable signal line of the corresponding branch target memory to the asynchronous clear pin of the PLMA array. Once a write occurs, the corresponding level mask flag in the PLMA physical table entry is instantly reset, forcing the chip to fall back to the full parallel access mode of the multi-level branch target cache in the next clock cycle.
[0074] This solution will be described in detail through examples:
[0075] When a branch instruction enters the chip's P0 clock cycle, the hardware circuit extracts the program counter (get instruction address) bus signal and inputs it to the on-chip PLMA at the pipeline front end for high-speed hardware table lookup.
[0076] If the PLMA physical port output mask flag 1 is 1 (valid), the combinational logic gates in the control circuit will force the read enable physical pins of the second and third level branch target caches to go low, keeping these large memory arrays in sleep mode and eliminating power consumption from dynamic transistor switching.
[0077] If the PLMA physical port output mask identifier 2 is 1 (valid), the combinational logic gate in the control circuit will force the read enable physical pin of the third-level branch target buffer to go low.
[0078] If PLMA is not hit, the chip enters the baseline state, and the read enable pins of all level branch target caches are pulled high in parallel.
[0079] During the P1 clock cycle, the output data L0_D of the first-level branch target buffer is latched.
[0080] During the P2 clock cycle, the output data L1_D of the second-level branch target buffer is latched.
[0081] During the P3 clock cycle, the output data L2_D of the third-level branch target cache is latched and compared. If L0_D == L2_D, then mask flag 1 is set to 1; if L0_D is invalid (cache miss) and L1_D == L2_D, then mask flag 2 is set to 1. Specifically, regardless of the chip's hardware state machine transitions, the read enable pin of the first-level branch target cache, being normally open (or unmasked) on the physical connection, must never be interrupted by the aforementioned mask logic. This ensures that the chip can output the target address bus signal to the front end in the shortest possible clock cycle, eliminating instruction fetch bubbles at the hardware level.
[0082] Physical entries such as Mask Identifier 1 and Mask Identifier 2 are written to the PLMA hardware array on the on-chip front end in real time.
[0083] To prevent the failure to detect abnormal states when read pins are shielded, this invention employs strong synchronization logic for physical connections triggered by write operations. When the chip writes new data to the first-level or second-level branch target buffer, causing old entries to be physically overwritten, or when the execution end writes new predicted data to the second-level branch target buffer due to an abnormality, the hardware directly connects the write enable signal line of the corresponding branch target buffer to the asynchronous clear pin of the PLMA array. Furthermore, once a write operation occurs, the corresponding PLMA mask is instantly reset, forcing the chip to fall back to the multi-level branch target buffer parallel mode in the next clock cycle.
[0084] A multi-level branch prediction hardware power optimization system in an integrated circuit includes:
[0085] In the instruction fetch module, when an instruction enters the chip's P0 clock cycle, the hardware fetches the current instruction address and uses that address to query the prediction level mask register array. If the query is successful, the written physical table entry is read, and the hardware control logic sets the redundant branch target memory read enable signal to low level according to the physical table entry, thus entering the instruction execution stage. If the query fails, the hardware control logic sets the read enable signals of the first, second, and third level branch target memories to high level, thus entering the logic gate operation module.
[0086] The logic gate operation module latches the data output from the first-level branch target memory during clock cycle P1; latches the data output from the second-level branch target memory during clock cycle P2; and latches the data output from the third-level branch target memory during clock cycle P3. At the same time, the hardware data comparator configured inside the chip performs logic gate operations on the data latched in the memory, determines redundant branch target memories, generates physical entries for the prediction level mask register array, and writes them into the prediction level mask register array in real time, thus entering the instruction execution stage.
[0087] The reset module performs a physical synchronization rollback when the instruction address is abnormal, and the hardware control logic immediately clears the physical table entry cached at that address asynchronously.
Claims
1. A method of multi-level branch prediction hardware power optimization in an integrated circuit, comprising: It includes the following steps: S1. When a branch instruction enters the chip's P0 clock cycle, the hardware extracts the current instruction address and uses this address to query the prediction level mask register array. If the query is successful, the written physical table entry is read, and the hardware control logic sets the redundant branch target memory read enable signal to low level according to the level mask bit in the physical table entry, thus entering the instruction execution stage. If the query fails, the hardware control logic sets the read enable signals of the first, second, and third level branch target memories to high level, thus entering S2. S2. During the P1 clock cycle, latch the data output from the first-level branch target memory; during the P2 clock cycle, latch the data output from the second-level branch target memory; during the P3 clock cycle, latch the data output from the third-level branch target memory. Data alignment is performed using D flip-flops. Simultaneously, the hardware data comparator configured inside the chip performs logic gate operations on the latched data to determine redundant branch target memories and generate physical entries for the prediction level mask register array. These entries are then written to the prediction level mask register array in real time, and the instruction execution phase begins. S3. When an instruction address write or jump error occurs, a physical synchronization rollback is performed, and the hardware control logic immediately clears the physical table entry cached at that address asynchronously.
2. The method for optimizing hardware power consumption in a multi-level branch prediction integrated circuit according to claim 1, characterized in that, The hardware data comparator in S2 includes the following operations: Based on the data latched in clock cycles P1-P3, logical operations are performed on the output results of the three-level branch target memory in clock cycle P3: if the data of the first-level branch target memory is redundant with the data of the third-level branch target memory, then only the read enable signal of the first-level branch target memory is set to high level and always kept on. If the data in the second-level branch target memory is redundant with the data in the third-level branch target memory, and there is no cache hit in the first-level branch target memory, then the read enable signal of the second-level branch target memory is set to high level.
3. The method for optimizing hardware power consumption in a multi-level branch prediction system for integrated circuits according to claim 1, characterized in that, S2 P3 clock cycle: During the P3 clock cycle, D flip-flops are used to perform time-lapse alignment of target memory for different branches, thereby aggregating the data latch results of different branches.
4. The method for hardware power consumption optimization of multi-level branch prediction in integrated circuits according to claim 1, characterized in that, S1 prediction hierarchy mask register array lookup table: During the P0 clock cycle, the hardware sends the instruction address to the prediction hierarchy mask register array, queries the tag bit of the address in the hierarchy mask register array, and if the query is successful, it uses the logic control circuit to force the read enable pin of the corresponding register to go low according to the tag bit.
5. The hardware power consumption optimization method for multi-level branch prediction in integrated circuits according to claim 1, characterized in that, Physical entries in S1: This includes valid bits, tag bits, and hierarchical masking flag bits. When a reset occurs, the hardware logic sends a batch clear signal to this bit, and at the same time, the hierarchical masking flag is physically disabled. The hierarchical masking flag is connected to the branch target memory at different levels through mutually exclusive control line level signals.
6. The method for hardware power consumption optimization of multi-level branch prediction in integrated circuits according to claim 1, characterized in that, Physical synchronization rollback in S3 includes: When an instruction address is abnormal, the hardware logic circuit directly connects the write enable signal line of the target memory of the corresponding branch to the asynchronous clear pin of the prediction level mask register array.
7. The method for hardware power consumption optimization of multi-level branch prediction in integrated circuits according to claim 1, characterized in that, S3 instruction address write or jump exceptions include: During the fetch phase, writing to the same address in the first and second level branch target memory triggers an instruction address exception; during the instruction execution phase, an instruction address exception is triggered when a jump exception occurs due to an incorrect instruction address fetch.
8. The method for hardware power consumption optimization of multi-level branch prediction in integrated circuits according to claim 1, characterized in that, The write-to-prediction-level mask register array in S2 includes: The mutual exclusion level signal generated by the hardware data comparator and combinational logic gates within the P3 clock cycle is used to generate the read enable signal of the corresponding branch target memory through logic gate operations, and is immediately written into the prediction level mask register array for data latching.
9. The method for optimizing hardware power consumption in multi-level branch prediction in integrated circuits according to claim 1, characterized in that, S1 Prediction-level mask register array: Predictive hierarchy mask register arrays are extremely low-latency register files or very small-capacity memory located at the front end of the chip.
10. A hardware power consumption optimization system for multi-level branch prediction in integrated circuits, characterized in that, include: In the instruction fetch module, when a branch instruction enters the chip's P0 clock cycle, the hardware fetches the current instruction address and uses this address to query the prediction level mask register array. If the query is successful, the written physical table entry is read, and the hardware control logic sets the redundant branch target memory read enable signal to low level according to the level mask bit in the physical table entry, thus entering the instruction execution stage. If the query fails, the hardware control logic sets the read enable signals of the first, second, and third level branch target memories to high level, thus entering the logic gate operation module. The logic gate operation module latches the data output from the first-level branch target memory in clock cycle P1; latches the data output from the second-level branch target memory in clock cycle P2; and latches the data output from the third-level branch target memory in clock cycle P3. Data alignment is performed through D flip-flops. At the same time, the hardware data comparator configured inside the chip performs logic gate operations on the data latched in the memory, determines redundant branch target memories, generates physical entries for the prediction level mask register array, and writes them into the prediction level mask register array in real time, thus entering the instruction execution stage. The reset module performs a physical synchronous rollback when an instruction address write or jump error occurs. The hardware control logic immediately clears the physical table entry cached at that address asynchronously.