A printed circuit board surface defect detection method based on a TIDE-Net network

Abstract

This invention discloses a method for detecting surface defects on printed circuit boards (PCBs) based on the TIDE-Net network, belonging to the field of PCB surface defect detection technology. Based on the YOLO11 target detection framework, this invention designs an RGFE module to replace the shallow structure in the backbone network, replacing the original C3k2 module, thereby enhancing the shallow feature extraction capability of the backbone network. Furthermore, an SDPPN neck network is designed as the basic neck network, and then an ELA mechanism is introduced to improve it, resulting in an improved neck network TDSFPN. This achieves efficient interaction of multi-scale features and dynamic enhancement of salient regions, significantly improving the model's detection performance for small target defects on PCBs. Finally, an ECSC detection head is constructed, which establishes consistent feature representations between classification and regression branches through cross-scale shared convolution and adaptive scale calibration mechanisms, making predictions more stable and reliable. Simultaneously, a joint spatial and channel recalibration strategy is combined to effectively enhance the response to key defect regions, thereby further improving the overall detection performance.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board (PCB) surface defect detection technology, and specifically to a PCB surface defect detection method based on TIDE-Net network. Background Technology

[0002] Printed Circuit Boards (PCBs), as fundamental hardware in the electronics and information industry, provide the necessary assembly platform for various electronic components. However, various types of damage are inevitable during PCB manufacturing, such as vias, rodent bites, open circuits, and short circuits. These defects can lead to electrical system malfunctions and even safety accidents like fires. Therefore, how to efficiently and accurately identify various PCB defects has become a critical research topic that urgently needs to be addressed.

[0003] Traditional PCB defect detection methods, such as manual visual inspection, while simple to operate, are easily affected by human factors, such as fatigue and visual errors. This not only increases production costs but also reduces inspection efficiency. Electrical testing methods test the impedance characteristics of key points on the PCB circuit design one by one. While flexible and intuitive, this method requires probe contact with the circuitry, making it a destructive contact testing method. With the continuous expansion of production scale, the limitations of traditional inspection methods have become increasingly apparent. Subsequently, with the rapid development of artificial intelligence, industry and academia have made significant progress in PCB inspection through machine learning technology, achieving automatic identification of PCB defects. However, machine learning methods still require manual intervention and parameter adjustment to handle some defect problems.

[0004] In recent years, with the widespread application of deep learning technologies such as convolutional neural networks in the field of PCB defect detection, detection technologies have continuously broken through the technical bottlenecks of traditional methods, rapidly developing towards lightweight, real-time, and high robustness. Among these, two-stage detection algorithms exhibit excellent defect identification accuracy, but due to the need to generate a large number of candidate regions during the inference process, the computational burden and time complexity increase significantly, resulting in slower detection speeds and difficulty in meeting the real-time detection requirements of PCB production lines. In contrast, single-stage detection algorithms have a speed advantage and can perform efficient inference, but they are somewhat lacking in detection accuracy.

[0005] The above problems urgently need to be solved. To address this, a method for detecting surface defects on printed circuit boards based on the TIDE-Net network is proposed. Summary of the Invention

[0006] The technical problem to be solved by this invention is: how to detect PCB surface defects with high accuracy and meet the speed requirements of real-time production lines. It provides a printed circuit board surface defect detection method based on TIDE-Net network, which further improves the detection accuracy of PCB defects while ensuring a certain detection speed.

[0007] The present invention solves the above-mentioned technical problems through the following technical solution, and the present invention includes the following steps:

[0008] S1: Dataset Preprocessing

[0009] Obtain a public dataset of PCB surface defects and preprocess the images in the dataset;

[0010] S2: Network Improvement

[0011] Based on the YOLO11 target detection network, an RGFE module, an improved neck network TDSFPN, and an ECSC detection head were designed to obtain the TIDE-Net network.

[0012] S3: Model Training

[0013] The TIDE-Net network was trained using the training set to obtain a PCB surface defect detection model;

[0014] S4: Defect Detection

[0015] Input the test set into the PCB surface defect detection model, and output the defect detection results and detection speed.

[0016] Furthermore, in step S1, the specific processing procedure is as follows:

[0017] S11: Divide the images into training and testing sets according to a set ratio;

[0018] S12: Perform brightness adjustment, cutout, random rotation, cropping, mirroring, and noise addition operations on the images to expand the images in the training set;

[0019] S13: Perform mosaic data augmentation on the images in the training set and resize the images.

[0020] Furthermore, in step S2, the specific processing procedure is as follows:

[0021] S21: The shallow structure in the backbone network of the YOLO11 target detection network is replaced by the C3k2 module by using the RGFE module based on the reparameterization and multi-scale feature fusion mechanism.

[0022] S22: Design the SDFPN neck network as the basic neck network, and then introduce the ELA mechanism to improve it, resulting in the improved neck network TDSFPN, which replaces the neck network of the YOLO11 object detection network.

[0023] S23: Construct an ECSC detection head to replace the original detection head of the YOLO11 object detection network.

[0024] Furthermore, in step S21, the specific process of the RGFE module is as follows:

[0025] S211: Input image First, a 1×1 convolutional layer is used to expand the number of feature channels, resulting in a tensor. The processing formula is as follows:

[0026] ;

[0027] in, Indicates the number of hidden channels. For expansion coefficient, Indicates batch size. and These represent the height and width of the feature map, respectively. For the target number of channels, It is a 1×1 convolutional layer;

[0028] S212: Subsequently, the obtained tensor The material is divided uniformly along the channel dimension, and the processing formula is as follows:

[0029] ;

[0030] in, This represents the intrinsic characteristic branch, while Indicates an enhanced branch;

[0031] S213: Enhanced Branch It is fed into the RepConv layer to obtain a tensor. The processing formula is as follows:

[0032] ;

[0033] in, Indicates the number of intermediate channels. This is the channel scaling factor. It consists of 3×3 RepConv layers;

[0034] S214: Output of the RepConv layer First, a 3×3 convolutional layer is used to obtain the tensor. After passing through a 1×1 convolutional layer, a tensor is obtained. The processing formula is as follows:

[0035] ;

[0036] in, It is a 3×3 convolutional layer. It is a 1×1 convolutional layer;

[0037] S215: Characteristics of all branches , , and The layers are concatenated along the channel dimension. Finally, a 1×1 convolutional layer is used to adjust the number of channels to the required number of output channels. The processing formula is as follows:

[0038] ;

[0039] ;

[0040] in, This is the concatenated feature tensor obtained after concatenating multi-branch features. This is the final output feature tensor.

[0041] Furthermore, in step S22, the specific processing procedure for the improved neck network TDSFPN is as follows:

[0042] S221: Perform top-down cross-layer fusion of feature maps from different scales from the backbone network, first fusing high-level features... Obtained by upsampling via transposed convolution To match low-level features The spatial resolution is calculated using the following formula:

[0043] ;

[0044] in, This is a two-dimensional transpose convolution operation;

[0045] S222: High-level features after upsampling By applying the ELA direction-sensitive attention mechanism, direction-sensitive attention enhancement features are obtained. The processing formula is as follows:

[0046] ;

[0047] S223: Low-level features Local texture information is extracted using 2D convolution, and enhanced with orientation-sensitive attention features. Perform element-wise multiplication fusion to obtain the fusion feature. The processing formula is as follows:

[0048] ;

[0049] in, This represents a two-dimensional convolution operation. This represents element-wise multiplication;

[0050] S224: Merge features With upsampling features Perform element-wise additive residual fusion to obtain the final output features. The processing formula is as follows:

[0051] ;

[0052] S225: Repeat steps S221 to S224 above for different levels to enable the improved neck network TDSFPN to obtain multi-scale features that combine high-level semantics and fine-grained structural information.

[0053] Furthermore, in step S222, the ELA attention mechanism includes the following steps:

[0054] S2221: For the input feature map One-dimensional average pooling operations are performed along the horizontal and vertical directions respectively to obtain direction-specific context features. and The processing formula is as follows:

[0055] ;

[0056] in, For horizontal one-dimensional average pooling, This is a one-dimensional average pooling in the vertical direction;

[0057] S2222: Input the directional pooling results into a one-dimensional convolutional layer, a group normalization layer, and a sigmoid activation function, respectively, to obtain the horizontal and vertical attention weights. and The processing formula is as follows:

[0058] ;

[0059] in, For one-dimensional convolution, For group normalization, Use the Sigmoid activation function;

[0060] S2223: Multiply the horizontal attention weights and vertical attention weights element-wise to form a two-dimensional orientation-sensitive spatial attention map. The processing formula is as follows:

[0061] ;

[0062] in, This represents element-wise multiplication;

[0063] S2224: Apply a two-dimensional orientation-sensitive spatial attention map to the input feature map and perform element-wise multiplication to obtain enhanced features. The processing formula is as follows:

[0064] .

[0065] Furthermore, in step S23, the specific processing procedure of the ECSC detection head is as follows:

[0066] S231: Input the feature maps P3, P4, and P5 of different scales into a CGS module consisting of a 1×1 convolutional layer, a GroupNorm normalization layer, and a SiLU activation function. The 1×1 convolutional layer performs a linear channel transformation on the feature maps, the GroupNorm normalization layer normalizes the features, and the SiLU activation function enhances the feature representation ability, thereby obtaining the aligned feature maps P3, P4, and P5 respectively.

[0067] S232: The aligned feature maps P3, P4, and P5 are input into the first shared 3×3 convolutional layer, and the unified semantic modeling of features at different scales is achieved through shared parameters to obtain the first-stage shared features U3, U4, and U5.

[0068] S233: The first-stage shared features U3, U4, and U5 are input again into the second shared 3×3 convolutional layer to further enhance the cross-scale collaborative feature expression and obtain the final shared features S3, S4, and S5;

[0069] S234: Input the final shared features S3, S4, and S5 into the regression prediction branch, and output the bounding box regression coefficients or distribution regression features for each spatial location through a 1×1 convolutional layer;

[0070] S235: Input the shared features S3, S4, and S5 into the class prediction branch, and output the corresponding class probability prediction through a 1×1 convolutional layer.

[0071] Furthermore, in step S234, a scaling factor module is set in the regression prediction branch to apply a learnable scaling factor to the regression output at each scale. To achieve adaptive adjustment of regression results at different scales, the processing formula is as follows:

[0072] ;

[0073] in, This represents the original regression output at the i-th scale. This represents the regression result after adjustment by the scaling factor.

[0074] Compared with existing technologies, this invention has the following advantages: The printed circuit board surface defect detection method based on the TIDE-Net network, based on the YOLO11 target detection framework, designs an RGFE module based on reparameterization and multi-scale feature fusion mechanism to replace the shallow structure in the backbone network, thereby enhancing the shallow feature extraction capability of the backbone network. Furthermore, an SDPPN neck network is designed as the basic neck network, and then an ELA mechanism is introduced to improve it, resulting in an improved neck network TDSFPN. This achieves efficient interaction of multi-scale features and dynamic enhancement of salient regions, significantly improving the model's detection performance for small target defects on PCBs. Finally, an ECSC is constructed. The detection head establishes consistent feature representations between classification and regression branches through cross-scale shared convolution and adaptive scale calibration mechanisms, making predictions more stable and reliable. Simultaneously, the combined spatial and channel recalibration strategy effectively enhances the response to key defect regions, further improving overall detection performance. The designed PCB surface defect detection model achieves 98.24% mAP on the PKU-Market-PCB public dataset from the Peking University Human-Computer Interaction Laboratory, and reaches a detection speed of 106.5c-FPS on an RTX3090. It demonstrates excellent balance between accuracy and real-time performance, and its overall performance ranks among the advanced levels in the current PCB defect detection field, significantly outperforming mainstream comparative models. Attached Figure Description

[0075] Figure 1 This is a flowchart of the PCB surface defect detection method based on TIDE-Net network in an embodiment of the present invention;

[0076] Figure 2 The images shown are typical defect images from the public dataset PKU-Market-PCB of the Human-Computer Interaction Laboratory of Peking University in this embodiment of the invention. Among them, (a) is a burr defect, (b) is a missing hole defect, (c) is a short circuit defect, (d) is a copper splatter defect, (e) is an open circuit defect, and (f) is a rat bite defect.

[0077] Figure 3 This is a schematic diagram of the RGFE module in an embodiment of the present invention;

[0078] Figure 4 This is a schematic diagram of the TDSFPN module in an embodiment of the present invention;

[0079] Figure 5This is a schematic diagram of the ELA attention mechanism module in an embodiment of the present invention;

[0080] Figure 6 This is a schematic diagram of the ECSC detection head structure in an embodiment of the present invention;

[0081] Figure 7 This is a diagram illustrating the PCB defect image detection effect in an embodiment of the present invention.

[0082] Figure 8 This is a schematic diagram of the architecture of the defect detection network model in an embodiment of the present invention. Detailed Implementation

[0083] The embodiments of the present invention are described in detail below. These embodiments are implemented based on the technical solution of the present invention, and provide detailed implementation methods and specific operation processes. However, the scope of protection of the present invention is not limited to the following embodiments.

[0084] like Figures 1-8 As shown, this embodiment provides a technical solution: a PCB surface defect detection method based on TIDE-Net network, including the following steps:

[0085] S1: Obtain a public dataset of PCB surface defects and preprocess the images in the dataset according to task requirements;

[0086] S2: Based on the YOLO11 target detection framework, a PCB surface defect detection network TIDE-Net was designed. This model integrates the RGFE module based on reparameterization and multi-scale feature fusion mechanism, the optimized neck network structure TDSFPN, and the constructed ECSC detection head.

[0087] S3: Train the TIDE-Net network using the training set to obtain a PCB surface defect detection model;

[0088] S4: Test the PCB surface defect detection model on the test set and output the defect detection results and detection speed.

[0089] In this embodiment, the specific processing procedure in step S1 is as follows:

[0090] S11: Divide the 693 images into a training set and a test set in an 8:2 ratio, with the training set containing 554 images and the test set containing 139 images.

[0091] S12: Due to the small number of samples, the training set was expanded by adjusting brightness, cutout, random rotation, cropping, mirroring, and adding noise. After expansion, the training set has 10,554 images and the test set has 139 images.

[0092] S13: Perform mosaic data augmentation on the images in the training set, and adjust the size of the processed images to 640×640 as the image input size for the model.

[0093] In this embodiment, the specific processing procedure of step S2 is as follows:

[0094] S21: Design an RGFE module based on reparameterization and multi-scale feature fusion mechanism to replace the shallow structure in the backbone network and replace the original C3k2 module.

[0095] S22: Design the SDFPN neck network as the basic neck network, and then introduce the ELA mechanism to improve it, resulting in the improved neck network TDSFPN;

[0096] S23: An ECSC detection head was constructed to replace the original detection head of the YOLO11 object detection framework.

[0097] More specifically, in step S21, the C3k2 module is replaced with the RGFE module, and the specific processing procedure for the RGFE module is as follows:

[0098] S211: Input image First, a 1×1 convolutional layer is used to expand the number of feature channels, resulting in a tensor. This facilitates feature separation, and the processing formula is as follows:

[0099]

[0100] in, Indicates the number of hidden channels. For expansion coefficient, Indicates batch size. and These represent the height and width of the feature map, respectively. For the target number of channels, It is a 1×1 convolutional layer;

[0101] S212: Subsequently, the obtained tensor The material is divided uniformly along the channel dimension, and the processing formula is as follows:

[0102]

[0103] in, This represents the intrinsic characteristic branch, while Indicates an enhanced branch;

[0104] S213: Enhanced Branch It is fed into the RepConv layer to obtain a tensor. The processing formula is as follows:

[0105]

[0106] in, Indicates the number of intermediate channels. This is the channel scaling factor. It is a 3×3 parameterized convolutional layer;

[0107] S214: Output of the RepConv layer First, a 3×3 convolutional layer is used to obtain the tensor. After passing through a 1×1 convolutional layer, a tensor is obtained. The processing formula is as follows:

[0108]

[0109] in, It is a 3×3 convolutional layer. It is a 1×1 convolutional layer;

[0110] S215: Characteristics of all branches , , and The layers are concatenated along the channel dimension. Finally, a 1×1 convolutional layer is used to adjust the number of channels to the required number of output channels. The processing formula is as follows:

[0111]

[0112]

[0113] in, This is the concatenated feature tensor obtained after concatenating multi-branch features. This is the final output feature tensor.

[0114] More specifically, in step S22, the specific processing procedure for the TDSFPN neck network includes the following steps:

[0115] S221: Perform top-down cross-layer fusion of feature maps from different scales from the backbone network, first fusing high-level features... (For example, features from layer P5) are obtained through upsampling via transposed convolution. To match low-level features The spatial resolution of features (e.g., features in layer P4) is processed using the following formula:

[0116] ;

[0117] in, This is a two-dimensional transpose convolution operation;

[0118] S222: High-level features after upsampling By applying the ELA direction-sensitive attention mechanism, direction-sensitive attention enhancement features are obtained. The processing formula is as follows:

[0119]

[0120] in, This indicates direction-sensitive attentional operation;

[0121] S223: Low-level features Local texture information is extracted using 2D convolution, and enhanced with orientation-sensitive attention features. Perform element-wise multiplication fusion to obtain the fusion feature. The processing formula is as follows:

[0122]

[0123] in, This represents a two-dimensional convolution operation. This represents element-wise multiplication;

[0124] S224: Merge features With upsampling features Perform element-wise additive residual fusion to obtain the final output features. The processing formula is as follows:

[0125]

[0126] The Add operation is used to supplement high-level semantic information and maintain gradient flow stability.

[0127] S225: Repeat the above steps for different levels to enable TDSFPN to obtain multi-scale features that combine high-level semantics and fine-grained structural information, thereby achieving enhanced representation of minute defects and irregular defects.

[0128] More specifically, the TDSFPN neck network includes an ELA orientation-sensitive attention mechanism module, enabling the network to selectively enhance the recognition of strip-shaped irregular defects while suppressing activation of irrelevant backgrounds. The ELA attention mechanism includes the following steps:

[0129] For the input feature map One-dimensional average pooling operations are performed along the horizontal and vertical directions respectively to obtain direction-specific context features. and The processing formula is as follows:

[0130]

[0131] The directional pooling results are then fed into a one-dimensional convolution, group normalization, and a sigmoid activation function, respectively, to obtain the horizontal and vertical attention weights. and The processing formula is as follows:

[0132]

[0133] Multiply the horizontal attention weights and vertical attention weights element-wise to form a two-dimensional orientation-sensitive spatial attention map. The processing formula is as follows:

[0134]

[0135] The directional attention map is applied to the input feature map and element-wise multiplication is performed to obtain the enhanced features. The processing formula is as follows:

[0136]

[0137] More specifically, in step S23, the specific processing procedure of the ECSC detection head includes the following steps:

[0138] S231: The feature maps P3, P4, and P5 from different scales in the feature pyramid are input into a CGS module consisting of a 1×1 convolutional layer, a GroupNorm normalization layer, and a SiLU activation function. The 1×1 convolution performs a linear channel transformation on the feature maps, the GroupNorm normalization layer normalizes the features, and the SiLU activation function enhances the feature representation ability, thereby obtaining the aligned feature maps P3, P4, and P5 respectively.

[0139] S232: The aligned feature maps P3, P4, and P5 are input into the first shared 3×3 convolutional layer, and the unified semantic modeling of features at different scales is achieved through shared parameters to obtain the first-stage shared features U3, U4, and U5.

[0140] S233: The first-stage shared features U3, U4, and U5 are input again into the second shared 3×3 convolutional layer to further enhance the cross-scale collaborative feature expression, resulting in the final shared features S3, S4, and S5;

[0141] S234: The final shared features S3, S4, and S5 are input into the regression prediction branch, and the bounding box regression coefficients or distribution regression features for each spatial location are output through a 1×1 convolutional layer. A scale module is set in the regression prediction branch to apply a learnable scale factor to the regression output at each scale. To achieve adaptive adjustment of regression results at different scales, the processing formula is as follows:

[0142]

[0143] in, This represents the original regression output at the i-th scale. This represents the regression result after adjustment by the scaling factor;

[0144] S235: Input the shared features S3, S4, and S5 into the class prediction branch, and output the corresponding class probability prediction through a 1×1 convolutional layer.

[0145] In this embodiment, the specific processing procedure of step S3 is as follows:

[0146] S31: Experimental Environment Configuration. Model training was conducted in a high-performance computing environment with the following operating conditions: an Intel(R) Xeon(R) Silver 4214 processor with a clock speed of 2.20 GHz; an NVIDIA GeForce RTX3090 graphics processor; 128GB of system memory; and Linux operating system to ensure stability during large-scale training and parallel computing. The model was built and trained using the PyTorch 2.7.1 deep learning framework with CUDA version 12.2 for GPU acceleration. Python 3.9.23 was used as the primary programming language. All training hyperparameters were kept consistent to ensure comparability of the experiments. Specific training parameters included an image size of 640×640, 300 training epochs, a batch size of 32, SGD optimizer, an initial learning rate of 0.01, momentum of 0.937, and weight decay of 0.0005.

[0147] S32: Model evaluation metrics. During training, multiple evaluation metrics are used to comprehensively evaluate the model performance. Evaluation metrics include: mAP@0.5 (average accuracy when IoU=0.5), mAP@0.5:0.95 (average accuracy from IoU 0.5 to 0.95), FPS (used to evaluate the model's inference speed), Params (used to measure the model's parameter size), and GFLOPs (used to measure the model's computational complexity).

[0148] S33: During the training process, in order to comprehensively evaluate the performance of each module in the TIDE-Net framework, a series of ablation experiments were carried out based on the YOLO11s baseline model. Table 1 shows the results of the ablation experiments.

[0149] Table 1 Comparison of ablation experiments

[0150]

[0151] S34: After training, save the weights of the final TIDE-Net model (PCB surface defect detection model).

[0152] In this embodiment, the specific processing procedure of step S4 is as follows:

[0153] S41: Input the test set into the TIDE-Net model (PCB surface defect detection model).

[0154] S42: Outputs the network's detection results and detection speed.

[0155] The improvements of the TIDE-Net model compared to the baseline model are as follows:

[0156] The C3k2 modules in layers P2 and P3 of the backbone network are replaced with RGFE modules, and the C3k2 module in layer P3 of the neck network is also replaced with an RGFE module. The detection head is replaced with an ECSC detection head. The backbone network includes a first RGFE module, a second RGFE module, a first 3×3 convolutional layer, a second 3×3 convolutional layer, and a first C3k2 module. The first RGFE module sequentially passes through the first 3×3 convolutional layer, the second RGFE module, the second 3×3 convolutional layer, and the first C3k2 module. The neck network includes a first ELA module, a first 1×1 convolutional layer, a first downsampling module, a second ELA module, a second 1×1 convolutional layer, a third ELA module, a first Multiply operation unit, a first Add operation unit, a second C3k2 module, a second downsampling module, a fourth ELA module, a third 1×1 convolutional layer, a fifth ELA module, a second Multiply operation unit, a second Add operation unit, and a third RGFE module. The C2PSA module is connected to the first ELA module and then outputs features through the first 1×1 convolutional layer.

[0157] The first downsampling module is connected to the first 1×1 convolutional layer, and the second ELA module is connected to the first C3k2 module. The output features of the second ELA module after passing through the second 1×1 convolutional layer and the output features of the first downsampling module after passing through the third ELA module are processed by the first Multiply operation unit. The output features of the first Multiply operation and the output features of the first downsampling module are processed by the first Add operation unit and sent to the second C3k2 module.

[0158] The second downsampling module is connected to the first downsampling module, and the fourth ELA module is connected to the second RGFE module. The output features of the fourth ELA module after passing through the third 1×1 convolutional layer and the output features of the second downsampling module after passing through the fifth ELA module are processed by the second Multiply operation unit. The output features of the second Multiply operation unit and the output features of the second downsampling module are processed by the second Add operation unit and sent to the third RGFE module. The features output by the third RGFE module, the second C3k2 module and the first 1×1 convolutional layer are input into the ECSC detection head network.

[0159] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for detecting surface defects on printed circuit boards based on TIDE-Net networks, characterized in that, Includes the following steps: S1: Dataset Preprocessing Obtain a public dataset of PCB surface defects and preprocess the images in the dataset; S2: Network Improvement Based on the YOLO11 target detection network, an RGFE module, an improved neck network TDSFPN, and an ECSC detection head were designed to obtain the TIDE-Net network. S3: Model Training The TIDE-Net network was trained using the training set to obtain a PCB surface defect detection model; S4: Defect Detection Input the test set into the PCB surface defect detection model, and output the defect detection results and detection speed.

2. The method for detecting surface defects on printed circuit boards based on TIDE-Net network according to claim 1, characterized in that, In step S1, the specific processing procedure is as follows: S11: Divide the images into training and testing sets according to a set ratio; S12: Perform brightness adjustment, cutout, random rotation, cropping, mirroring, and noise addition operations on the images to expand the images in the training set; S13: Perform mosaic data augmentation on the images in the training set and resize the images.

3. The method for detecting surface defects on printed circuit boards based on TIDE-Net network according to claim 1, characterized in that, In step S2, the specific processing procedure is as follows: S21: The shallow structure in the backbone network of the YOLO11 target detection network is replaced by the C3k2 module by using the RGFE module based on the reparameterization and multi-scale feature fusion mechanism. S22: Design the SDFPN neck network as the basic neck network, and then introduce the ELA mechanism to improve it, resulting in the improved neck network TDSFPN, which replaces the neck network of the YOLO11 object detection network. S23: Construct an ECSC detection head to replace the original detection head of the YOLO11 object detection network.

4. The method for detecting surface defects on printed circuit boards based on TIDE-Net network according to claim 3, characterized in that, In step S21, the specific process of the RGFE module is as follows: S211: Input image First, a 1×1 convolutional layer is used to expand the number of feature channels, resulting in a tensor. The processing formula is as follows: ； in, Indicates the number of hidden channels. For expansion coefficient, Indicates batch size. and These represent the height and width of the feature map, respectively. For the target number of channels, It is a 1×1 convolutional layer; S212: Subsequently, the obtained tensor The material is divided uniformly along the channel dimension, and the processing formula is as follows: ； in, This represents the intrinsic characteristic branch, while Indicates an enhanced branch; S213: Enhanced Branch It is fed into the RepConv layer to obtain a tensor. The processing formula is as follows: ； in, Indicates the number of intermediate channels. This is the channel scaling factor. It consists of 3×3 RepConv layers; S214: Output of the RepConv layer First, a 3×3 convolutional layer is used to obtain the tensor. After passing through a 1×1 convolutional layer, a tensor is obtained. The processing formula is as follows: ； in, It is a 3×3 convolutional layer. It is a 1×1 convolutional layer; S215: Characteristics of all branches , , and The layers are concatenated along the channel dimension. Finally, a 1×1 convolutional layer is used to adjust the number of channels to the required number of output channels. The processing formula is as follows: ； ； in, This is the concatenated feature tensor obtained after concatenating multi-branch features. This is the final output feature tensor.

5. The method for detecting surface defects on printed circuit boards based on TIDE-Net network according to claim 4, characterized in that, In step S22, the specific processing procedure for the improved neck network TDSFPN is as follows: S221: Perform top-down cross-layer fusion of feature maps from different scales from the backbone network, first fusing high-level features... Obtained by upsampling via transposed convolution To match low-level features The spatial resolution is calculated using the following formula: ； in, This is a two-dimensional transpose convolution operation; S222: High-level features after upsampling By applying the ELA direction-sensitive attention mechanism, direction-sensitive attention enhancement features are obtained. The processing formula is as follows: ； S223: Low-level features Local texture information is extracted using 2D convolution, and enhanced with orientation-sensitive attention features. Perform element-wise multiplication fusion to obtain the fusion feature. The processing formula is as follows: ； in, This represents a two-dimensional convolution operation. This represents element-wise multiplication; S224: Merge features With upsampling features Perform element-wise additive residual fusion to obtain the final output features. The processing formula is as follows: ； S225: Repeat steps S221 to S224 above for different levels to enable the improved neck network TDSFPN to obtain multi-scale features that combine high-level semantics and fine-grained structural information.

6. The method for detecting surface defects on printed circuit boards based on TIDE-Net network according to claim 5, characterized in that, In step S222, the ELA attention mechanism includes the following steps: S2221: For the input feature map One-dimensional average pooling operations are performed along the horizontal and vertical directions respectively to obtain direction-specific context features. and The processing formula is as follows: ； in, For horizontal one-dimensional average pooling, This is a one-dimensional average pooling in the vertical direction; S2222: Input the directional pooling results into a one-dimensional convolutional layer, a group normalization layer, and a sigmoid activation function, respectively, to obtain the horizontal and vertical attention weights. and The processing formula is as follows: ； in, For one-dimensional convolution, For group normalization, Use the Sigmoid activation function; S2223: Multiply the horizontal attention weights and vertical attention weights element-wise to form a two-dimensional orientation-sensitive spatial attention map. The processing formula is as follows: ； in, This represents element-wise multiplication; S2224: Apply a two-dimensional orientation-sensitive spatial attention map to the input feature map and perform element-wise multiplication to obtain enhanced features. The processing formula is as follows: 。 7. The method for detecting surface defects on printed circuit boards based on TIDE-Net network according to claim 6, characterized in that, In step S23, the specific processing procedure of the ECSC detection head is as follows: S231: Input the feature maps P3, P4, and P5 of different scales into a CGS module consisting of a 1×1 convolutional layer, a GroupNorm normalization layer, and a SiLU activation function. The 1×1 convolutional layer performs a linear channel transformation on the feature maps, the GroupNorm normalization layer normalizes the features, and the SiLU activation function enhances the feature representation ability, thereby obtaining the aligned feature maps P3, P4, and P5 respectively. S232: The aligned feature maps P3, P4, and P5 are input into the first shared 3×3 convolutional layer, and the unified semantic modeling of features at different scales is achieved through shared parameters to obtain the first-stage shared features U3, U4, and U5. S233: The first-stage shared features U3, U4, and U5 are input again into the second shared 3×3 convolutional layer to further enhance the cross-scale collaborative feature expression and obtain the final shared features S3, S4, and S5; S234: Input the final shared features S3, S4, and S5 into the regression prediction branch, and output the bounding box regression coefficients or distribution regression features for each spatial location through a 1×1 convolutional layer; S235: Input the shared features S3, S4, and S5 into the class prediction branch, and output the corresponding class probability prediction through a 1×1 convolutional layer.

8. The method for detecting surface defects on printed circuit boards based on TIDE-Net network according to claim 7, characterized in that, In step S234, a scaling factor module is set in the regression prediction branch to apply a learnable scaling factor to the regression output at each scale. To achieve adaptive adjustment of regression results at different scales, the processing formula is as follows: ； in, This represents the original regression output at the i-th scale. This represents the regression result after adjustment by the scaling factor.

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