Semiconductor system for input and output data

Abstract

A semiconductor system includes a control device including a first region and a second region, the control device generating commands and data in the first region in response to external commands and external data, and outputting the commands and data to the second region. The semiconductor system includes a memory device vertically stacked on the second region, the memory device receiving the commands and data from the second region, and performing internal operations. The control device is longer than the memory device by the first region.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. Provisional Application No. 63 / 728,952, filed December 6, 2024; U.S. Provisional Application No. 63 / 826,717, filed June 19, 2025; and U.S. Patent Application No. 19 / 382,036, filed November 6, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure generally relates to a semiconductor system, and more specifically, to a semiconductor system for inputting and outputting data. Background Technology

[0003] Recently, cascaded memory systems, such as high-bandwidth memory (HBM) devices, have been widely used in various applications due to their high bandwidth and energy efficiency. Unlike traditional memory systems that use parallel data buses, cascaded memory systems consist of stacked memory devices, which include a base chip and multiple memory chips interconnected via through-silicon vias (TSVs). Cascaded memory devices include physical interfaces, such as a physical layer for communicating with a processor. This physical layer is designed for high-speed data transfer and efficient communication. Summary of the Invention

[0004] In one embodiment, a semiconductor system includes: a control device comprising a first region and a second region, which generates commands and data in the first region in response to external commands and external data, and outputs the commands and data to the second region; and a memory device vertically stacked on the second region, which receives the commands and data from the second region and performs internal operations. The length of the control device may be longer than the length of the first region than the length of the memory device.

[0005] In one embodiment, a semiconductor system includes: a control device comprising a first region and a second region, which generates commands and data in the first region in response to external commands and external data, and outputs the commands and data to the second region; a first memory device vertically stacked on the second region, which performs internal operations by receiving the commands and data from the second region; and a second memory device vertically stacked on the second region, which also performs internal operations by receiving the commands and data from the second region. The first memory device and the second memory device may be horizontally disposed on the second region.

[0006] In one embodiment, a semiconductor system includes: a control device including a first region and a second region different from the first region, generating commands and data in the first region in response to external commands and external data, and outputting the commands and data to the second region; and a memory device including a first set of channels and a second set of channels vertically stacked on the second region, wherein the memory device performs internal operations through the first set of channels and the second set of channels by receiving the commands and data from the second region. The length of the control device may be longer than the first region than the memory device.

[0007] In one embodiment, a semiconductor system includes: a control device including a first basic through-silicon via (TSV) region and a second basic TSV region disposed horizontally, outputting commands and data through the first basic TSV region and outputting the commands and data through the second basic TSV region; a first memory device including a first core TSV region disposed horizontally, wherein the first core TSV region receives the commands and data from the first basic TSV region and outputs the data; and a second memory device including a second core TSV region disposed horizontally, wherein the second core TSV region receives the commands and data from the second basic TSV region and outputs the data.

[0008] In one embodiment, a semiconductor system includes an HBM device, a first processing circuit, and a second processing circuit. The HBM device includes a first physical region and a second physical region. First data is input and output through the first physical region, and second data is input and output through the second physical region. The first processing circuit is connected to the first physical region and performs arithmetic operations by receiving the first data. The second processing circuit is connected to the second physical region and performs arithmetic operations by receiving the second data. The first physical region and the second physical region are located at the boundary of the HBM device.

[0009] In one embodiment, a semiconductor system includes: a first HBM device including a first physical region and inputting and outputting first data through the first physical region; a first processing circuit that performs an arithmetic operation by receiving the first data through the first physical region and performing the arithmetic operation by receiving second data through a second physical region; a second HBM device including the second physical region and a third physical region, inputting and outputting the second data through the second physical region and inputting and outputting third data through the third physical region; a second processing circuit that performs an arithmetic operation by receiving the third data through the third physical region and performing an arithmetic operation by receiving fourth data through a fourth physical region; and a third HBM device including a fourth physical region and inputting and outputting fourth data through the fourth physical region, wherein the first physical region is disposed at a boundary of the first HBM device, the second physical region and the third physical region are disposed at a boundary of the second HBM device, and the fourth physical region is disposed at a boundary of the third HBM device.

[0010] In one embodiment, a semiconductor system includes: an internal interface disposed along a first direction (vertical direction) for receiving commands and data and outputting the commands and data; and internal input and output lines disposed along a second direction (horizontal direction) for electrically connecting to the internal interface, receiving the commands and data from the internal interface, and outputting the commands and data, wherein the first direction and the second direction are configured as orthogonal directions.

[0011] In one embodiment, a semiconductor system includes: an internal interface disposed along a first direction (vertical direction) for receiving and outputting a first command and a second command, as well as first data and second data; a first internal input and output line disposed along a second direction (horizontal direction) electrically connected to the internal interface for receiving the first command and the first data from the internal interface and outputting the first command and the first data; and a second internal input and output line disposed along the second direction, electrically connected to the internal interface for receiving the second command and the second data from the internal interface and outputting the second command and the second data, wherein the first direction and the second direction are configured as orthogonal directions.

[0012] In one embodiment, a semiconductor system includes: a first internal interface disposed along a first direction (vertical direction) and receiving and outputting a first command and a second command, as well as first data and second data; a first internal input and output line disposed along a second direction (horizontal direction), electrically connected to the first internal interface, receiving the first command and the first data from the first internal interface, and outputting the first command and the first data; a second internal input and output line disposed along the second direction, electrically connected to the internal interface, receiving the second command and the second data from the internal interface, and outputting the second command and the second data; and a second internal interface disposed along the first direction, generating a transmission command by receiving the second command, generating transmission data by receiving the second data, and outputting the transmission command and the transmission data to the outside of the semiconductor system. Attached Figure Description

[0013] Figure 1 This is a block diagram illustrating the construction of a semiconductor system according to an embodiment of the present disclosure.

[0014] Figure 2 This is a block diagram illustrating the construction of a control device according to an embodiment of the present disclosure.

[0015] Figure 3 This is a block diagram illustrating the construction of a first memory device and a second memory device according to embodiments of the present disclosure.

[0016] Figure 4 This is a block diagram illustrating the construction of a control device according to an embodiment of the present disclosure.

[0017] Figure 5 This is a block diagram illustrating the construction of a first memory device and a second memory device according to embodiments of the present disclosure.

[0018] Figure 6 This is a block diagram illustrating the construction of a control device according to an embodiment of the present disclosure.

[0019] Figure 7 This is a block diagram illustrating the construction of a first memory device and a second memory device according to embodiments of the present disclosure.

[0020] Figure 8 This is a block diagram illustrating the construction of a semiconductor system according to an embodiment of the present disclosure.

[0021] Figure 9 and Figure 10 This is a block diagram illustrating the construction of a semiconductor system according to an embodiment of the present disclosure.

[0022] Figure 11 This is a block diagram illustrating the construction of an HMB device according to an embodiment of the present disclosure.

[0023] Figure 12 This is a block diagram illustrating the construction of a control device according to an embodiment of the present disclosure.

[0024] Figure 13 This is a block diagram illustrating the construction of a control device according to an embodiment of the present disclosure.

[0025] Figure 14 This is a block diagram illustrating the construction of a memory device according to an embodiment of the present disclosure.

[0026] Figure 15 This is a block diagram illustrating the construction of a control device according to an embodiment of the present disclosure.

[0027] Figure 16 This is a block diagram illustrating the construction of a control device according to an embodiment of the present disclosure.

[0028] Figure 17 This is a block diagram illustrating the construction of a memory device according to an embodiment of the present disclosure.

[0029] Figure 18 This is a block diagram illustrating the construction of a control device according to an embodiment of the present disclosure.

[0030] Figure 19 This is a block diagram illustrating the construction of a control device according to an embodiment of the present disclosure.

[0031] Figure 20 This is a block diagram illustrating the construction of a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0032] In the following description of embodiments, the term "preset" indicates that the value of a parameter is predetermined when it is used in a process or algorithm. According to embodiments, the value of a parameter may be set at the start of a process or algorithm or during the execution of a process or algorithm.

[0033] Terms such as "first" and "second" used to distinguish various components are not limited to any particular component. For example, a first component can be called a second component, and vice versa.

[0034] When a component is described as "coupled" or "connected" to another component, it should be understood that these components can be directly coupled or interconnected, or they can be coupled or connected to each other through another component inserted between them. In contrast, when a component is described as "directly coupled" or "directly connected" to another component, it should be understood that these components are directly coupled or interconnected without any other components in between. Similarly, when a component is described as being situated on another component, it should be understood that these components can be directly interconnected, or they can be interconnected through another component inserted between them. In contrast, when a component is described as being directly situated on another component, it should be understood that these components are directly situated on each other without any other components inserted between them.

[0035] The present disclosure will be described below by way of examples. The examples are for illustrative purposes only, and the scope of the present disclosure is not limited to the examples.

[0036] Figure 1 This is a block diagram illustrating the construction of a semiconductor system 1B according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor system 1B may include a control device 100B and a first memory device (1... st MEM) 200B and second memory device (2 nd MEM) 300B.

[0037] Control device 100B can generate commands (CMD) and data (DATA). Control device 100B can output commands (CMD) and data (DATA) to a first memory device 200B and a second memory device 300B. Control device 100B can receive data (DATA) from the first memory device 200B and the second memory device 300B. Control device 100B can be a basic chip or controller for controlling the operation of the first memory device 200B and the second memory device 300B.

[0038] The control device 100B may include a first region 110B and a second region 120B. The first region 110B may be configured to generate commands (CMD) and data (DATA). The first region 110B may be configured such that heat is generated when commands (CMD) and data (DATA) are generated. The second region 120B is the region that receives commands (CMD) and data (DATA) from the first region 110B. The second region 120B is the region where commands (CMD) and data (DATA) are output and subsequently sent to the first memory device 200B and the second memory device 300B. The upper portion of the first region 110B may be configured as a first setting space.

[0039] The first region 110B may include a physical region (D2D PHY) 111B and an internal interface region (INT IF) 112B.

[0040] Physical area 111B can generate commands (CMD) and data (DATA) based on signals received from external devices (e.g., various devices such as a host, processor, and test equipment). Physical area 111B can output commands (CMD) and data (DATA) to internal interface area 112B. Physical area 111B can be the physical layer (PHY) responsible for the generation, transmission, reception, and physical connection of signals and data between external devices and control device 100B.

[0041] Internal interface area 112B can receive commands CMD and data DATA from physical area 111B. Internal interface area 112B can output commands CMD and data DATA to internal input and output lines by adjusting the input and output order of commands CMD and data DATA. Figure 2 MIO1 and MIO2 in the PHY). Internal interface area 112B can be an interface—the interface defines the timing and sequence of signals transmitted between the physical layer (PHY) and internal circuitry, as well as input and output signals. Internal interface area 112B, internal input and output lines ( Figure 2 MIO1 and MIO2 in the chip can be implemented as a network-on-chip (NoC). The NoC can be set up as a transmission path to connect various internal circuits in the chip.

[0042] The second region 120B may include a first memory controller (1 st MC)121B, First Basic Interface Area (1 st DFI) 122B, First Basic TSV Area (1 st TSV PHY) 123B, Second Memory Controller (2 nd MC)125B, Second Basic Interface Area (2 nd DFI) 126B and the second basic TSV area (2 nd DFI) 127B.

[0043] The first memory controller 121B can be connected via internal input and output lines ( Figure 2 The first memory controller 121B (MIO1 and MIO2) receives commands CMD and data DATA. The first memory controller 121B can output commands CMD and data DATA to control the operation of the first memory device 200B.

[0044] The first basic interface area 122B can receive commands CMD and data DATA from the first memory controller 121B. The first basic interface area 122B can output commands CMD and data DATA to the first basic TSV area 123B by adjusting the input and output order of commands CMD and data DATA.

[0045] The first basic TSV area 123B can receive commands (CMD) and data (DATA) from the first basic interface area 122B. The first basic TSV area 123B can output commands (CMD) and data (DATA) to the first memory device 200B through multiple TSVs.

[0046] The second memory controller 125B can be connected via internal input and output lines ( Figure 2 The second memory controller 125B (MIO1 and MIO2) receives commands CMD and data DATA. The second memory controller 125B can output commands CMD and data DATA to control the operation of the second memory device 300B.

[0047] The second basic interface area 126B can receive commands CMD and data DATA from the second memory controller 125B. The second basic interface area 126B can output commands CMD and data DATA to the second basic TSV area 127B by adjusting the input and output order of commands CMD and data DATA.

[0048] The second basic TSV area 127B can receive commands (CMD) and data (DATA) from the second basic interface area 126B. The second basic TSV area 127B can output commands (CMD) and data (DATA) to the second memory device 300B through multiple TSVs.

[0049] The first memory device 200B can receive commands CMD and data DATA from the first basic TSV region 123B. The first memory device 200B can perform internal operations based on the commands CMD and data DATA. After a write operation begins, the first memory device 200B can store data DATA based on the commands CMD. After a read operation begins, the first memory device 200B can output the stored data DATA based on the commands CMD. The first memory device 200B can be a memory device comprising multiple stacked core chips.

[0050] The second memory device 300B can receive commands CMD and data DATA from the second basic TSV region 127B. The second memory device 300B can perform internal operations based on the commands CMD and data DATA. After a write operation begins, the second memory device 300B can store data DATA based on the commands CMD. After a read operation begins, the second memory device 300B can output the stored data DATA based on the commands CMD. The second memory device 300B can be a memory device comprising multiple stacked core chips.

[0051] The first memory device 200B and the second memory device 300B can be disposed on the second region 120B of the control device 100B. The first memory device 200B and the second memory device 300B can be vertically stacked on the second region 120B of the control device 100B. For example, the first memory device 200B and the second memory device 300B can be located on the control device 100B by means of another component inserted therebetween. For example, the first memory device 200B and the second memory device 300B can be at least partially vertically located on the control device 100B and connected to the control device 100B by means of another component inserted therebetween. For example, the first memory device 200B and the second memory device 300B can be directly located on the control device 100B without the need for another component inserted therebetween. For example, the first memory device 200B and the second memory device 300B can be at least partially vertically located on the control device 100B without the need for another component inserted therebetween. The first memory device 200B and the second memory device 300B can be horizontally disposed on the second region 120B of the control device 100B. The first memory device 200B and the second memory device 300B are both connected to the control device 100B and can input and output data DATA with the same bandwidth. The bandwidth can be set to the amount of data input and output within a preset time.

[0052] The combined length of the first memory device 200B and the second memory device 300B may be shorter than the length of the second region 120B of the control device 100B. The length of the control device 100B may be longer than the combined length of the first memory device 200B and the second memory device 300B, which is the length of the first region 110B.

[0053] As described above, the semiconductor system 1B according to embodiments of this disclosure can increase bandwidth because the first memory device 200B and the second memory device 300B are jointly connected to the control device 100B and input and output data DATA. The semiconductor system 1B can prevent or mitigate heat dissipation from the areas where the command CMD and data DATA are generated to the memory devices (e.g., 200B, 300B) because the memory devices are not stacked above the locations where the command CMD and data DATA are generated.

[0054] Figure 2 This is a block diagram illustrating the construction of a control device 100B according to an embodiment of the present disclosure. Figure 2 As shown, the control device 100B may include a first region 110B and a second region 120B.

[0055] The first region 110B may include the physical region 111B and the internal interface region 112B.

[0056] Physical area 111B can be accessed from external devices (e.g., Figure 8 The physical region 111B receives external commands EC from an external device (e.g., a processor in the processor) to generate command CMD. The physical region 111B can generate command CMD by buffering or decoding external commands EC. Both the external command EC and command CMD are represented as a signal, but may each include multiple bits. The physical region 111B can generate command CMD from external devices (e.g., a processor in the processor). Figure 8 The processor in the internal interface area 111B receives external data ED to generate data DATA. Physical area 111B can also generate external data ED by receiving data DATA from internal interface area 112B. Physical area 111B can output external data ED to external devices (e.g., ...). Figure 8 (The processor in the process). External data ED and data DATA are both represented as a single signal, but may include multiple bits. In one embodiment, external command EC and external data ED are received from outside the first and second regions.

[0057] Internal interface region 112B can receive commands (CMD) and data (DATA) from physical region 111B. Internal interface region 112B can output commands (CMD) and data (DATA) to the first internal input / output line MIO1 by adjusting the input and output order of commands (CMD) and data (DATA) controlling the operation of the first memory device 200B and the second memory device 300B. Internal interface region 112B can also output commands (CMD) and data (DATA) to the second internal input / output line MIO2 by adjusting the input and output order of commands (CMD) and data (DATA) controlling the operation of the first memory device 200B and the second memory device 300B. The first internal input / output line MIO1 and the second internal input / output line MIO2 can be located in the central region (CENTER) of control device 100B.

[0058] The first region 110B can be set as the region for generating commands (CMD) and data (DATA). The first region 110B can also be set as the region where heat is generated when commands (CMD) and data (DATA) are generated. The first region 110B can be located in the left-hand region (LEFT) of the control device 100B on the X-axis.

[0059] The second region 120B may include a first memory controller (1) for controlling the operation of the first memory device 200B. st MC) 121B-1, First Basic Interface Area (1 st DFI) 121B-2, First Basic TSV Area (1 st TSV PHY) 121B-3, Second Memory Controller (2 nd MC)122B-1, Second Basic Interface Area (2 nd DFI) 122B-2 and the second basic TSV area (2 nd TSV PHY) 122B-3. The first memory controller 121B-1, the first basic interface region 121B-2, and the first basic TSV region 121B-3 can control the first set of channels included in the first memory device 200B ( Figure 3 The components that control the operation of CH1 to CH4 in the first memory device 200B. The second memory controller 122B-1, the second basic interface region 122B-2, and the second basic TSV region 122B-3 can be components that control the operation of the second set of channels (CH1 to CH4) included in the first memory device 200B. Figure 3 The components for the operation of CH5 to CH8 in the memory controller. Each of the first memory controller 121B-1, the first basic interface region 121B-2 and the first basic TSV region 121B-3, and the second memory controller 122B-1, the second basic interface region 122B-2 and the second basic TSV region 122B-3 can be a component for the operation of CH5 to CH8 in the memory controller. Figure 1 The first memory controller 121B, the first basic interface region 122B, and the first basic TSV region 123B are shown.

[0060] The first memory controller 121B-1, the first basic interface area 121B-2, and the first basic TSV area 121B-3 can be arranged along the horizontal direction (i.e., the X direction) of the control device 100B. The second memory controller 122B-1, the second basic interface area 122B-2, and the second basic TSV area 122B-3 can be arranged along the horizontal direction (i.e., the X direction) of the control device 100B.

[0061] The first memory controller 121B-1 can be electrically connected to the first internal input and output line MIO1. The first memory controller 121B-1 can receive control signals via the first internal input and output line MIO1 to the first set of channels included in the first memory device 200B. Figure 3 The first memory controller 121B-1 can output commands CMD and data DATA for the operation of CH1 to CH4 in the first memory device 200B. Figure 3 The commands CMD and data DATA for operations (CH1 to CH4 in the table).

[0062] The first basic interface area 121B-2 can be electrically connected to the first memory controller 121B-1. The first basic interface area 121B-2 can receive commands CMD and data DATA from the first memory controller 121B-1. The first basic interface area 121B-2 can output commands CMD and data DATA to the first basic TSV area 121B-3 by adjusting the input and output order of commands CMD and data DATA.

[0063] The first basic TSV area 121B-3 can be electrically connected to the first basic interface area 121B-2. The first basic TSV area 121B-3 can receive commands (CMD) and data (DATA) from the first basic interface area 121B-2. The first basic TSV area 121B-3 can output commands (CMD) and data (DATA) to the first core TSV area (1) included in the first memory device 200B via multiple TSVs. st CORE TSV PHY) Figure 3 (210B in the middle).

[0064] The first memory controller 121B-1, the first basic interface region 121B-2, and the first basic TSV region 121B-3 can be sequentially arranged from the center region CENTER of the control device 100B along the first direction D1. The first direction D1 can be set from the center region CENTER to the first edge region TOP. The first edge region TOP can be set as the upper region of the control device 100B on the Y-axis. The first edge region TOP can be arranged in a direction outward from the center region CENTER.

[0065] The second memory controller 122B-1 can be electrically connected to the second internal input and output line MIO2. The second memory controller 122B-1 can receive control signals from the second set of channels included in the first memory device 200B via the second internal input and output line MIO2. Figure 3 The second memory controller 122B-1 can output commands CMD and data DATA for the operation of the second set of channels (CH5 to CH8) included in the first memory device 200B. Figure 3 The commands CMD and data DATA for operations (CH5 to CH8) in the table.

[0066] The second basic interface area 122B-2 can be electrically connected to the second memory controller 122B-1. The second basic interface area 122B-2 can receive commands CMD and data DATA from the second memory controller 122B-1. The second basic interface area 122B-2 can output commands CMD and data DATA to the second basic TSV area 122B-3 by adjusting the input and output order of commands CMD and data DATA.

[0067] The second basic TSV area 122B-3 can be electrically connected to the second basic interface area 122B-2. The second basic TSV area 122B-3 can receive commands (CMD) and data (DATA) from the second basic interface area 122B-2. The second basic TSV area 122B-3 can output commands (CMD) and data (DATA) to the second core TSV area (2) included in the first memory device 200B via multiple TSVs. nd CORE TSV PHY) Figure 3 (220B in the middle).

[0068] The second memory controller 122B-1, the second basic interface region 122B-2, and the second basic TSV region 122B-3 can be sequentially arranged from the center region (CENTER) of the control device 100B along the second direction (D2). The second direction (D2) can be set from the center region (CENTER) to the second edge region (BOTTOM). The second edge region (BOTTOM) can be set as the lower region of the control device 100B on the Y-axis. The second edge region (BOTTOM) can be arranged in a direction outward from the center region (CENTER). The first edge region (TOP) and the second edge region (BOTTOM) can be arranged from the center region (CENTER) in opposite directions.

[0069] The second region 120B may include a third memory controller (3) for controlling the operation of the second memory device 300B. rd MC)123B-1, Third Basic Interface Area (3 rd DFI) 123B-2, Third Basic TSV Area (3 rd TSV PHY) 123B-3, Fourth Memory Controller (3 rd MC)124B-1, Fourth Basic Interface Area (4 th DFI) 124B-2 and the fourth basic TSV area (4 th TSV PHY) 124B-3. The third memory controller 123B-1, the third basic interface area 123B-2, and the third basic TSV area 123B-3 can control the first set of channels included in the second memory device 300B ( Figure 3 The components that control the operation of CH1 to CH4 in the second memory device 300B. The fourth memory controller 124B-1, the fourth basic interface region 124B-2, and the fourth basic TSV region 124B-3 can be components that control the operation of the second set of channels (CH1 to CH4) included in the second memory device 300B. Figure 3 The components for the operation of CH5 to CH8 in the memory controller. Each of the third memory controller 123B-1, the third basic interface region 123B-2 and the third basic TSV region 123B-3, and the fourth memory controller 124B-1, the fourth basic interface region 124B-2 and the fourth basic TSV region 124B-3 can be Figure 1 The second memory controller 125B, the second basic interface region 126B, and the second basic TSV region 127B are shown in the figure.

[0070] The third memory controller 123B-1, the third basic interface area 123B-2, and the third basic TSV area 123B-3 can be arranged along the horizontal direction (i.e., the X direction) of the control device 100B. The fourth memory controller 124B-1, the fourth basic interface area 124B-2, and the fourth basic TSV area 124B-3 can be arranged along the horizontal direction (i.e., the X direction) of the control device 100B.

[0071] The third memory controller 123B-1 can be electrically connected to the first internal input and output line MIO1. The third memory controller 123B-1 can receive control signals from the first set of channels included in the second memory device 300B via the first internal input and output line MIO1. Figure 3 The third memory controller 123B-1 can output commands CMD and data DATA for the operation of the first group of channels (CH1 to CH4) included in the second memory device 300B. Figure 3 The commands CMD and data DATA for operations (CH1 to CH4 in the table).

[0072] The third basic interface area 123B-2 can be electrically connected to the third memory controller 123B-1. The third basic interface area 123B-2 can receive commands CMD and data DATA from the third memory controller 123B-1. The third basic interface area 123B-2 can output commands CMD and data DATA to the third basic TSV area 123B-3 by adjusting the input and output order of commands CMD and data DATA.

[0073] The third basic TSV area 123B-3 can be electrically connected to the third basic interface area 123B-2. The third basic TSV area 123B-3 can receive commands (CMD) and data (DATA) from the third basic interface area 123B-2. The third basic TSV area 123B-3 can output commands (CMD) and data (DATA) to the third core TSV area (3) included in the second memory device 300B via multiple TSVs. rd CORE TSV PHY) Figure 3 (310B in the middle).

[0074] The third memory controller 123B-1, the third basic interface area 123B-2, and the third basic TSV area 123B-3 can be sequentially arranged from the central area CENTER of the control device 100B along the first direction D1.

[0075] The fourth memory controller 124B-1 can be electrically connected to the second internal input and output line MIO2. The fourth memory controller 124B-1 can receive control signals from the second set of channels included in the second memory device 300B via the second internal input and output line MIO2. Figure 3 The fourth memory controller 124B-1 can output commands CMD and data DATA for the operation of the second set of channels (CH5 to CH8) included in the second memory device 300B. Figure 3 The commands CMD and data DATA for operations (CH5 to CH8) in the table.

[0076] The fourth basic interface area 124B-2 can be electrically connected to the fourth memory controller 124B-1. The fourth basic interface area 124B-2 can receive commands CMD and data DATA from the fourth memory controller 124B-1. The fourth basic interface area 124B-2 can output commands CMD and data DATA to the fourth basic TSV area 124B-3 by adjusting the input and output order of commands CMD and data DATA.

[0077] The fourth basic TSV region 124B-3 can be electrically connected to the fourth basic interface region 124B-2. The fourth basic TSV region 124B-3 can receive commands (CMD) and data (DATA) from the fourth basic interface region 124B-2. The fourth basic TSV region 124B-3 can output commands (CMD) and data (DATA) to the fourth core TSV region (4) included in the second memory device 300 via multiple TSVs. th CORE TSV PHY) Figure 3 (320B ​​in the middle).

[0078] The fourth memory controller 124B-1, the fourth basic interface area 124B-2, and the fourth basic TSV area 124B-3 can be sequentially arranged from the central area CENTER of the control device 100B along the second direction D2.

[0079] The second region 120B can be configured to receive commands (CMD) and data (DATA) from the first region 110B and output them to the first memory device 200B and the second memory device 300B. The second region 120B can be located in the right-hand region (RIGHT) of the control device 100B along the X-axis.

[0080] Figure 3 This is a block diagram illustrating the construction of a first memory device 200B and a second memory device 300B according to embodiments of the present disclosure.

[0081] The first memory device 200B may include a first channel CH1 to an eighth channel CH8, a first core TSV region 210B, and a second core TSV region 220B.

[0082] The first core TSV region 210B and the second core TSV region 220B can be arranged along the horizontal direction (i.e., the X direction) of the first memory device 200B.

[0083] Channels CH1 through CH8 can independently receive commands (CMD) and data (DATA) through internal operations. After a write operation begins, channels CH1 through CH8 can store data (DATA) based on the command (CMD). After a read operation begins, channels CH1 through CH8 can output data (DATA) based on the command (CMD).

[0084] Channels CH1 through CH4 can be electrically connected to the first core TSV region 210B. Channels CH1 through CH4 can receive commands (CMD) and data (DATA) from the first core TSV region 210B. Channels CH1 through CH4 can also output data (DATA) to the first core TSV region 210B. After an internal write operation begins, channels CH1 through CH4 can store data (DATA) based on commands (CMD). After a internal read operation begins, channels CH1 through CH4 can output data (DATA) based on commands (CMD). Channels CH1 through CH4 can be configured as the first group of channels.

[0085] Channels 5 through 8 can be electrically connected to the second core TSV region 220B. Channels 5 through 8 can receive commands (CMD) and data (DATA) from the second core TSV region 220B. Channels 5 through 8 can also output data (DATA) to the second core TSV region 220B. After an internal write operation begins, channels 5 through 8 can store data (DATA) based on commands (CMD). After a internal read operation begins, channels 5 through 8 can output data (DATA) based on commands (CMD). Channels 1 through 4 can be configured as the first group of channels. Channels 5 through 8 can be configured as the second group of channels.

[0086] The first channel CH1 to the fourth channel CH4 can be located in the central region CENTER of the first memory device 200B. The fifth channel CH5 to the eighth channel CH8 can be located in the central region CENTER of the first memory device 200B.

[0087] The first core TSV region 210B can be electrically connected to the first basic TSV region 121B-3 of the control device 100B. The first core TSV region 210B can receive commands (CMD) and data (DATA) from the first basic TSV region 121B-3. The first core TSV region 210B can receive commands (CMD) and data (DATA) through multiple TSVs. The first core TSV region 210B can output commands (CMD) and data (DATA) to the first channel CH1 to the fourth channel CH4. The first core TSV region 210B can receive data (DATA) from the first channel CH1 to the fourth channel CH4 and output data (DATA) to the first basic TSV region 121B-3. The first core TSV region 210B can be positioned from the center region (CENTER) along a first direction D1. The first direction D1 can be set from the center region (CENTER) to the first edge region (TOP). The first edge region (TOP) can be set as the upper region of the first memory device 200B on the Y-axis. The first edge region (TOP) can be arranged from the center region (CENTER) in an outward direction.

[0088] The second core TSV region 220B can be electrically connected to the second basic TSV region 122B-3 of the control device 100B. The second core TSV region 220B can receive commands (CMD) and data (DATA) from the second basic TSV region 122B-3. The second core TSV region 220B can receive commands (CMD) and data (DATA) through multiple TSVs. The second core TSV region 220B can output commands (CMD) and data (DATA) to channels 5 (CH5) to 8 (CH8). The second core TSV region 220B can receive data (DATA) from channels 5 (CH5) to 8 (CH8) and output data (DATA) to the second basic TSV region 122B-3. The second core TSV region 220B can be positioned from the center region (CENTER) along a second direction (D2). The second direction (D2) can be set from the center region (CENTER) to the second edge region (BOTTOM). The second edge region (BOTTOM) can be set as the lower region of the first memory device 200B on the Y-axis. The second edge region (BOTTOM) can be arranged from the center region (CENTER) in an outward direction. The first edge region TOP and the second edge region BOTTOM can be arranged from the center region CENTER in opposite directions.

[0089] The first memory device 200B can be arranged in the left region LEFT of the X-axis.

[0090] The second memory device 300B may include a first channel CH1 to an eighth channel CH8, a third core TSV region 310B, and a fourth core TSV region 320B.

[0091] The third core TSV region 310B and the fourth core TSV region 320B can be arranged along the horizontal direction (i.e., the X direction) of the second memory device 300B.

[0092] Channels CH1 through CH8 can independently receive commands (CMD) and data (DATA) through internal operations. After a write operation begins, channels CH1 through CH8 can store data (DATA) based on the command (CMD). After a read operation begins, channels CH1 through CH8 can output data (DATA) based on the command (CMD).

[0093] Channels CH1 through CH4 can be electrically connected to the third core TSV region 310B. Channels CH1 through CH4 can receive commands (CMD) and data (DATA) from the third core TSV region 310B. Channels CH1 through CH4 can also output data (DATA) to the third core TSV region 310B. After an internal write operation begins, channels CH1 through CH4 can store data (DATA) based on commands (CMD). After a internal read operation begins, channels CH1 through CH4 can output data (DATA) based on commands (CMD). Channels CH1 through CH4 can be configured as the first group of channels.

[0094] Channels 5 through 8 (CH8) can be electrically connected to the fourth core TSV region 320B. Channels 5 through 8 (CH8) can receive commands (CMD) and data (DATA) from the fourth core TSV region 320B. Channels 5 through 8 (CH8) can also output data (DATA) to the fourth core TSV region 320B. After an internal write operation begins, channels 5 through 8 (CH8) can store data (DATA) based on commands (CMD). After a internal read operation begins, channels 5 through 8 (CH8) can output data (DATA) based on commands (CMD). Channels 5 through 8 (CH8) can be configured as a second group of channels.

[0095] The first channel CH1 to the eighth channel CH8 can be located in the central area CENTER of the second memory device 300B.

[0096] The third core TSV region 310B can be electrically connected to the third basic TSV region 123B-3 of the control device 100B. The third core TSV region 310B can receive commands (CMD) and data (DATA) from the third basic TSV region 123B-3. The third core TSV region 310B can receive commands (CMD) and data (DATA) through multiple TSVs. The third core TSV region 310B can output commands (CMD) and data (DATA) to the first channel CH1 to the fourth channel CH4. The third core TSV region 310B can receive data (DATA) from the first channel CH1 to the fourth channel CH4 and output data (DATA) to the third basic TSV region 123B-3. The third core TSV region 310B can be set from the center region CENTER along the first direction D1.

[0097] The fourth core TSV area 320B can be electrically connected to the fourth basic TSV area 124B-3 of the control device 100B. The fourth core TSV area 320B can receive commands (CMD) and data (DATA) from the fourth basic TSV area 124B-3. The fourth core TSV area 320B can receive commands (CMD) and data (DATA) through multiple TSVs. The fourth core TSV area 320B can output commands (CMD) and data (DATA) to channels 5 (CH5) to 8 (CH8). The fourth core TSV area 320B can receive data (DATA) from channels 5 (CH5) to 8 (CH8) and output data (DATA) to the fourth basic TSV area 124B-3. The fourth core TSV area 320B can be set from the center area (CENTER) along the second direction (D2).

[0098] The second memory device 300B can be located in the right region of the X-axis.

[0099] As described above, the semiconductor system 1B according to embodiments of this disclosure can increase bandwidth because the first memory device 200B and the second memory device 300B are jointly connected to the control device 100B and input and output data DATA. The semiconductor system 1B can prevent or reduce heat dissipation from the areas where commands CMD and data DATA are generated to the memory devices because the memory devices (e.g., 200B, 300B) are not stacked on top of the areas where commands CMD and data DATA are generated.

[0100] Figure 4 This is a block diagram illustrating the construction of a control device according to an embodiment of the present disclosure. In one embodiment, the control device 100B-1 represents... Figure 1 The control device 100B shown is as follows. Figure 4As shown, the control device 100B-1 may include a first region 110B-1 and a second region 120B-1.

[0101] The first region 110B-1 may include a physical region (D2D PHY) 111B-1 and an internal interface region (INT IF) 112B-1.

[0102] Physical region 111B-1 can be based on external devices (e.g., Figure 8 The physical region 111B-1 can generate the command CMD from the external command EC (external command EC) of the processor in the system. The physical region 111B-1 can generate the command CMD by buffering or decoding the external command EC. Both the external command EC and the command CMD are represented as a signal, but may each include multiple bits. The physical region 111B-1 can generate the command CMD from an external device (e.g., a processor in the system). Figure 8 The processor in the internal interface area 111B-1 receives external data ED to generate data DATA. Physical area 111B-1 can generate external data ED by receiving data DATA from internal interface area 112B-1. Both external data ED and data DATA are represented as a single signal, but may each include multiple bits.

[0103] Internal interface region 112B-1 can receive commands (CMD) and data (DATA) from physical region 111B-1. Internal interface region 112B-1 can output commands (CMD) and data (DATA) to the first internal input / output line MIO1 by adjusting the input and output order of commands (CMD) and data (DATA) controlling the operation of the first memory device 200B-1 and the second memory device 300B-1. Internal interface region 112B-1 can also output commands (CMD) and data (DATA) to the second internal input / output line MIO2 by adjusting the input and output order of commands (CMD) and data (DATA) controlling the operation of the first memory device 200B-1 and the second memory device 300B-1. The first internal input / output line MIO1 can be located in the first edge region TOP of control device 100B-1. The second internal input / output line MIO2 can be located in the second edge region BOTTOM of control device 100B-1.

[0104] The first region 110B-1 can be configured as the region for generating commands (CMD) and data (DATA). The first region 110B-1 can be configured such that heat is generated during the generation of commands (CMD) and data (DATA). The first region 110B-1 can be located in the left-hand region (LEFT) of the control device 100B-1 along the X-axis.

[0105] The second region 120B-1 may include a first memory controller (1) for controlling the operation of the first memory device 200B-1.st MC) 121B-11, First Basic Interface Area (1 st DFI) 121B-21, First Basic TSV Area (1 st TSV PHY) 121B-31, Second Memory Controller (2 nd MC) 122B-11, Second Basic Interface Area (2 nd DFI) 122B-21 and the second basic TSV area (2 nd TSV PHY) 122B-31. The first memory controller 121B-11, the first basic interface region 121B-21, and the first basic TSV region 121B-31 can be used to control the first set of channels included in the first memory device 200B-1 ( Figure 5 The components that control the operation of CH1 to CH4 in the first memory device 200B-1. The second memory controller 122B-11, the second basic interface region 122B-21, and the second basic TSV region 122B-31 can be components that control the operation of the second set of channels (CH1 to CH4) included in the first memory device 200B-1. Figure 5 The components of the operation of CH5 to CH8 in the middle.

[0106] The first memory controller 121B-11, the first basic interface region 121B-21, and the first basic TSV region 121B-31 can be arranged along the horizontal direction (i.e., the X direction) of the control device 100B-1. The second memory controller 122B-11, the second basic interface region 122B-21, and the second basic TSV region 122B-31 can be arranged along the horizontal direction (i.e., the X direction) of the control device 100B-1.

[0107] The first memory controller 121B-11 can be electrically connected to the first internal input and output line MIO1. The first memory controller 121B-11 can receive control signals via the first internal input and output line MIO1 to the first set of channels included in the first memory device 200B-1. Figure 5 The first memory controller 121B-11 can output commands CMD and data DATA for the operation of CH1 to CH4 in the first memory device 200B-1. Figure 5 The commands CMD and data DATA for operations (CH1 to CH4 in the table).

[0108] The first basic interface area 121B-21 can be electrically connected to the first memory controller 121B-11. The first basic interface area 121B-21 can receive commands CMD and data DATA from the first memory controller 121B-11. The first basic interface area 121B-21 can output commands CMD and data DATA to the first basic TSV area 121B-31 by adjusting the input and output order of commands CMD and data DATA.

[0109] The first basic TSV region 121B-31 can be electrically connected to the first basic interface region 121B-21. The first basic TSV region 121B-31 can receive commands (CMD) and data (DATA) from the first basic interface region 121B-21. The first basic TSV region 121B-31 can output commands (CMD) and data (DATA) to the first core TSV region (1) included in the first memory device 200B-1 via multiple TSVs. st CORE TSV PHY) Figure 5 (210B-1 in the middle).

[0110] The first memory controller 121B-11, the first basic interface region 121B-21, and the first basic TSV region 121B-31 can be sequentially arranged from the first edge region TOP of the control device 100B-1 along the second direction D2. The second direction D2 can be set from the first edge region TOP to the center region CENTER. The first edge region TOP can be set as the upper region of the control device 100B-1 on the Y-axis. The first edge region TOP can be arranged from the center region CENTER in an outward direction.

[0111] The second memory controller 122B-11 can be electrically connected to the second internal input and output line MIO2. The second memory controller 122B-11 can receive control signals via the second internal input and output line MIO2 to the second set of channels included in the first memory device 200B-1. Figure 5 The second memory controller 122B-11 can output commands CMD and data DATA for the operation of the second set of channels (CH5 to CH8) included in the first memory device 200B-1. Figure 5 The commands CMD and data DATA for operations (CH5 to CH8) in the table.

[0112] The second basic interface area 122B-21 can be electrically connected to the second memory controller 122B-11. The second basic interface area 122B-21 can receive commands CMD and data DATA from the second memory controller 122B-11. The second basic interface area 122B-21 can output commands CMD and data DATA to the second basic TSV area 122B-31 by adjusting the input and output order of commands CMD and data DATA.

[0113] The second basic TSV region 122B-31 can be electrically connected to the second basic interface region 122B-21. The second basic TSV region 122B-31 can receive commands (CMD) and data (DATA) from the second basic interface region 122B-21. The second basic TSV region 122B-31 can output commands (CMD) and data (DATA) through multiple TSVs to the second core TSV region (2) included in the first memory device 200B-1. nd CORE TSV PHY) Figure 5 (220B-1 in the middle).

[0114] The second memory controller 122B-11, the second basic interface region 122B-21, and the second basic TSV region 122B-31 can be sequentially arranged from the second edge region BOTTOM of the control device 100B-1 along the first direction D1. The first direction D1 can be set to the direction from the second edge region BOTTOM to the center region CENTER. The second edge region BOTTOM can be set to the lower region of the control device 100B-1 on the Y-axis. The second edge region BOTTOM can be arranged from the center region CENTER in an outward direction. The first edge region BOTTOM and the second edge region BOTTOM can be arranged from the center region CENTER in opposite directions.

[0115] The second region 120B-1 may include a third memory controller (3) for controlling the operation of the second memory device 300B-1. rd MC) 123B-11, Third Basic Interface Area (3 rd DFI) 123B-21, Third Basic TSV Area (3 rd TSV PHY) 123B-31, Fourth Memory Controller (4 th MC) 124B-11, Fourth Basic Interface Area (4 th DFI) 124B-21 and the fourth basic TSV area (4 thh TSV PHY) 124B-31. The third memory controller 123B-11, the third basic interface area 123B-21, and the third basic TSV area 123B-31 can be used to control the first set of channels included in the second memory device 300B-1 (h ... Figure 5 The components that control the operation of CH1 to CH4 in the second memory device 300B-1. The fourth memory controller 124B-11, the fourth basic interface region 124B-21, and the fourth basic TSV region 124B-31 can be components that control the operation of the second set of channels (CH1 to CH4) included in the second memory device 300B-1. Figure 5 The components of the operation of CH5 to CH8 in the middle.

[0116] The third memory controller 123B-11, the third basic interface area 123B-21, and the third basic TSV area 123B-31 can be arranged along the horizontal direction (i.e., the X direction) of the control device 100B-1. The fourth memory controller 124B-11, the fourth basic interface area 124B-21, and the fourth basic TSV area 124B-31 can be arranged along the horizontal direction (i.e., the X direction) of the control device 100B-1.

[0117] The third memory controller 123B-11 can be electrically connected to the first internal input and output line MIO1. The third memory controller 123B-11 can receive control signals from the first set of channels included in the second memory device 300B-1 via the first internal input and output line MIO1. Figure 5 The third memory controller 123B-11 can output commands CMD and data DATA for the operation of the first group of channels (CH1 to CH4) included in the second memory device 300B-1. Figure 5 The commands CMD and data DATA for operations (CH1 to CH4 in the table).

[0118] The third basic interface area 123B-21 can be electrically connected to the third memory controller 123B-11. The third basic interface area 123B-21 can receive commands CMD and data DATA from the third memory controller 123B-11. The third basic interface area 123B-21 can output commands CMD and data DATA to the third basic TSV area 123B-31 by adjusting the input and output order of commands CMD and data DATA.

[0119] The third basic TSV area 123B-31 can be electrically connected to the third basic interface area 123B-21. The third basic TSV area 123B-31 can receive commands (CMD) and data (DATA) from the third basic interface area 123B-21. The third basic TSV area 123B-31 can output commands (CMD) and data (DATA) to the third core TSV area (3) included in the second memory device 300B-1 via multiple TSVs. rd CORE TSV PHY) Figure 5 (310B-1 in the middle).

[0120] The third memory controller 123B-11, the third basic interface area 123B-21, and the third basic TSV area 123B-31 can be sequentially arranged from the first edge area TOP of the control device 100A along the second direction D2.

[0121] The fourth memory controller 124B-11 can be electrically connected to the second internal input and output line MIO2. The fourth memory controller 124B-11 can receive control signals from the second set of channels included in the second memory device 300B-1 via the second internal input and output line MIO2. Figure 5 The fourth memory controller 124B-11 can output commands CMD and data DATA for the operation of CH5 to CH8 in the second memory device 300B-1. Figure 5 The commands CMD and data DATA for operations (CH5 to CH8) in the table.

[0122] The fourth basic interface area 124B-21 can be electrically connected to the fourth memory controller 124B-11. The fourth basic interface area 124B-21 can receive commands (CMD) and data (DATA) from the fourth memory controller 124B-11. The fourth basic interface area 124B-21 can output commands (CMD) and data (DATA) to the fourth basic TSV area 124B-31 by adjusting the input and output order of these commands.

[0123] The fourth basic TSV area 124B-31 can be electrically connected to the fourth basic interface area 124B-21. The fourth basic TSV area 124B-31 can receive commands (CMD) and data (DATA) from the fourth basic interface area 124B-21. The fourth basic TSV area 124B-31 can output commands (CMD) and data (DATA) to the fourth core TSV area (4) included in the second memory device 300B-1 via multiple TSVs. th CORE TSV PHY) Figure 5 (320B-1 in the middle).

[0124] The fourth memory controller 124B-11, the fourth basic interface region 124B-21, and the fourth basic TSV region 124B-31 can be sequentially set from the second edge region BOTTOM of the control device 100B-1 along the first direction D1.

[0125] The second region 120B-1 can be configured to receive commands CMD and data DATA from the first region 110B-1 and output them to the first memory device 200B-1 and the second memory device 300B-1. The second region 120B-1 can be located in the right region RIGHT on the X-axis of the control device 100B-1.

[0126] Figure 5 This is a block diagram illustrating the construction of a first memory device 200B-1 and a second memory device 300B-1 according to embodiments of the present disclosure.

[0127] The first memory device 200B-1 may include a first channel CH1 to an eighth channel CH8, a first core TSV region 210B-1, and a second core TSV region 220B-1.

[0128] The first core TSV region 210B-1 and the second core TSV region 220B-1 can be arranged along the horizontal direction (i.e., the X direction) of the first memory device 200B-1.

[0129] Channels CH1 through CH8 can independently receive commands (CMD) and data (DATA) through internal operations. After a write operation begins, channels CH1 through CH8 can store data (DATA) based on the command (CMD). After a read operation begins, channels CH1 through CH8 can output data (DATA) based on the command (CMD).

[0130] Channels CH1 through CH4 can be electrically connected to the first core TSV region 210B-1. Channels CH1 through CH4 can receive commands (CMD) and data (DATA) from the first core TSV region 210B-1. Channels CH1 through CH4 can also output data (DATA) to the first core TSV region 210B-1. After an internal write operation begins, channels CH1 through CH4 can store data (DATA) based on commands (CMD). After a internal read operation begins, channels CH1 through CH4 can output data (DATA) based on commands (CMD). Channels CH1 through CH4 can be designated as the first group of channels.

[0131] Channels 5 through 8 (CH8) can be electrically connected to the second core TSV area 220B-1. Channels 5 through 8 (CH8) can receive commands (CMD) and data (DATA) from the second core TSV area 220B-1. Channels 5 through 8 (CH8) can also output data (DATA) to the second core TSV area 220B-1. After an internal write operation begins, channels 5 through 8 (CH8) can store data (DATA) based on commands (CMD). After a internal read operation begins, channels 5 through 8 (CH8) can output data (DATA) based on commands (CMD). Channels 5 through 8 (CH8) can be configured as a second group of channels.

[0132] The first channel CH1 to the fourth channel CH4 can be located in the first edge region TOP of the first memory device 200B-1. The fifth channel CH5 to the eighth channel CH8 can be located in the second edge region BOTTOM of the first memory device 200B-1.

[0133] The first core TSV region 210B-1 can be electrically connected to the first base TSV region 121B-31 of the control device 100B-1. The first core TSV region 210B-1 can receive commands (CMD) and data (DATA) from the first base TSV region 121B-31. The first core TSV region 210B-1 can receive commands (CMD) and data (DATA) through multiple TSVs. The first core TSV region 210B-1 can output commands (CMD) and data (DATA) to first channels CH1 to fourth channels CH4. The first core TSV region 210B-1 can receive data (DATA) from first channels CH1 to fourth channels CH4 and output data (DATA) to the first base TSV region 121B-31. The first core TSV region 210B-1 can be located in the center region (CENTER). The first core TSV region 210B-1 can be located from the first edge region (TOP) along a second direction D2. The second direction D2 can be set from the first edge region (TOP) to the center region (CENTER). The first edge region TOP can be set as the upper region of the first memory device 200B-1 on the Y-axis. The first edge region TOP can be arranged from the center region CENTER in an outward direction.

[0134] The second core TSV region 220B-1 can be electrically connected to the second base TSV region 122B-31 of the control device 100B-1. The second core TSV region 220B-1 can receive commands (CMD) and data (DATA) from the second base TSV region 122B-31. The second core TSV region 220B-1 can receive commands (CMD) and data (DATA) through multiple TSVs. The second core TSV region 220B-1 can output commands (CMD) and data (DATA) to channels 5 (CH5) to 8 (CH8). The second core TSV region 220B-1 can receive data (DATA) from channels 5 (CH5) to 8 (CH8) and output data (DATA) to the second base TSV region 122B-31. The second core TSV region 220B-1 can be located in the center region (CENTER). The second core TSV region 220B-1 can be located from the second edge region (BOTTOM) along a first direction (D1). The first direction (D1) can be set from the second edge region (BOTTOM) to the center region (CENTER). The second edge region BOTTOM can be set as the lower region of the first memory device 200B-1 on the Y-axis. The second edge region BOTTOM can be arranged from the center region CENTER in an outward direction. The first edge region TOP and the second edge region BOTTOM can be arranged from the center region CENTER in opposite directions.

[0135] The first memory device 200B-1 can be located in the left region LEFT of the X-axis.

[0136] The second memory device 300B-1 may include a first channel CH1 to an eighth channel CH8, a third core TSV region 310B-1, and a fourth core TSV region 320B-1.

[0137] The third core TSV region 310B-1 and the fourth core TSV region 320B-1 can be arranged along the horizontal direction (i.e., the X direction) of the second memory device 300B-1.

[0138] Channels CH1 through CH8 can independently receive commands (CMD) and data (DATA) through internal operations. After a write operation begins, channels CH1 through CH8 can store data (DATA) based on the command (CMD). After a read operation begins, channels CH1 through CH8 can output data (DATA) based on the command (CMD).

[0139] Channels CH1 through CH4 can be electrically connected to the third core TSV region 310B-1. Channels CH1 through CH4 can receive commands (CMD) and data (DATA) from the third core TSV region 310B-1. Channels CH1 through CH4 can also output data (DATA) to the third core TSV region 310B-1. After an internal write operation begins, channels CH1 through CH4 can store data (DATA) based on commands (CMD). After a internal read operation begins, channels CH1 through CH4 can output data (DATA) based on commands (CMD). Channels CH1 through CH4 can be designated as the first group of channels.

[0140] Channels 5 through 8 (CH8) can be electrically connected to the fourth core TSV region 320B-1. Channels 5 through 8 (CH8) can receive commands (CMD) and data (DATA) from the fourth core TSV region 320B-1. Channels 5 through 8 (CH8) can also output data (DATA) to the fourth core TSV region 320B-1. After an internal write operation begins, channels 5 through 8 (CH8) can store data (DATA) based on commands (CMD). After a internal read operation begins, channels 5 through 8 (CH8) can output data (DATA) based on commands (CMD). Channels 5 through 8 (CH8) can be configured as a second group of channels.

[0141] The first channel CH1 to the fourth channel CH4 can be located in the first edge region TOP of the second memory device 300B-1. The fifth channel CH5 to the eighth channel CH8 can be located in the second edge region BOTTOM of the second memory device 300B-1.

[0142] The third core TSV region 310B-1 can be electrically connected to the third base TSV region 123B-31 of the control device 100B-1. The third core TSV region 310B-1 can receive commands (CMD) and data (DATA) from the third base TSV region 123B-31. The third core TSV region 310B-1 can receive commands (CMD) and data (DATA) through multiple TSVs. The third core TSV region 310B-1 can output commands (CMD) and data (DATA) to the first channel CH1 to the fourth channel CH4. The third core TSV region 310B-1 can receive data (DATA) from the first channel CH1 to the fourth channel CH4 and output data (DATA) to the third base TSV region 123B-31. The third core TSV region 310B-1 can be set in the center region (CENTER). The third core TSV region 310B-1 can be set from the first edge region (TOP) along the second direction D2.

[0143] The fourth core TSV region 320B-1 can be electrically connected to the fourth base TSV region 124B-31 of the control device 100B-1. The fourth core TSV region 320B-1 can receive commands (CMD) and data (DATA) from the fourth base TSV region 124B-31. The fourth core TSV region 320B-1 can receive commands (CMD) and data (DATA) through multiple TSVs. The fourth core TSV region 320B-1 can output commands (CMD) and data (DATA) to channels CH5 through CH8. The fourth core TSV region 320B-1 can receive data (DATA) from channels CH5 through CH8 and output data (DATA) to the fourth base TSV region 124B-31. The fourth core TSV region 320B-1 can be set in the center region (CENTER). The fourth core TSV region 320B-1 can be set from the second edge region (BOTTOM) along the first direction D1.

[0144] The second memory device 300B-1 can be set in the right region of the X-axis.

[0145] As described above, the semiconductor system 1B according to embodiments of this disclosure can increase bandwidth because the first memory device 200B-1 and the second memory device 300B-1 are jointly connected to the control device 100B-1 and input and output data DATA. The semiconductor system 1B can prevent or reduce heat dissipation from the areas generating commands CMD and data DATA to the memory devices because the memory devices (e.g., 200B-1 and 300B-1) are not stacked on top of the areas generating commands CMD and data DATA.

[0146] Figure 6This is a block diagram illustrating the construction of a control device 100 according to an embodiment of the present disclosure. Figure 6 As shown, the control device 100B-2 may include a first region 110B-2 and a second region 120B-2.

[0147] The first region 110B-2 may include a physical region (D2D PHY) 111B-2 and an internal interface region (INT IF) 112B-2.

[0148] Physical region 111B-2 can be based on external devices (e.g., Figure 8 The physical region 111B-2 can generate the command CMD by buffering or decoding the external command EC (external command EC). Both the external command EC and the command CMD are represented as a signal, but may each include multiple bits. The physical region 111B-2 can generate the command CMD from an external device (e.g., a processor in the system). Figure 8 The processor in the internal interface area 111B-2 receives external data ED to generate data DATA. Physical area 111B-2 can generate external data ED by receiving data DATA from internal interface area 112B-2. Physical area 111B-2 can output external data ED to external devices (e.g., ...). Figure 8 (The processor in the middle). External data ED and data DATA are each represented as a signal, but may each include multiple bits.

[0149] Internal interface region 112B-2 can receive commands (CMD) and data (DATA) from physical region 111B-2. Internal interface region 112B-2 can output commands (CMD) and data (DATA) to the first internal input / output line MIO1 by adjusting the input and output order of commands (CMD) and data (DATA) controlling the operation of the first memory device 200B-2 and the second memory device 300B-2. Internal interface region 112B-2 can also output commands (CMD) and data (DATA) to the second internal input / output line MIO2 by adjusting the input and output order of commands (CMD) and data (DATA) controlling the operation of the first memory device 200B-2 and the second memory device 300B-2. The first internal input / output line MIO1 can be located in the central region (CENTER) of control device 100B-2. The second internal input / output line MIO2 can be located in the second peripheral region (BOTTOM) of control device 100B-2.

[0150] The first region 110B-2 can be set as the region for generating commands (CMD) and data (DATA). The first region 110B-2 can be set as the region that generates heat during the generation of commands (CMD) and data (DATA). The first region 110B-2 can be located in the left-hand region (LEFT) of the control device 100B-2 on the X-axis.

[0151] The second region 120B-2 may include a first memory controller (1) for controlling the operation of the first memory device 200B-2. st MC) 121B-12, First Basic Interface Area (1 st DFI) 121B-22, First Basic TSV Area (1 st TSV PHY) 121B-32, Second Memory Controller (2 nd MC) 122B-12, Second Basic Interface Area (2 nd DFI) 122B-22, Second TSV Area (2 nd TSV PHY) 122B-32. The first memory controller 121B-12, the first basic interface region 121B-22, and the first basic TSV region 121B-32 can be used to control the first set of channels included in the first memory device 200B-2 ( Figure 7 The components that control the operation of CH1 to CH4 in the first memory device 200B-2. The second memory controller 122B-12, the second basic interface region 122B-22, and the second basic TSV region 122B-32 can be components that control the operation of the second set of channels (CH1 to CH4) included in the first memory device 200B-2. Figure 7 The components of the operation of CH5 to CH8 in the middle.

[0152] The first memory controller 121B-12, the first basic interface region 121B-22, and the first basic TSV region 121B-32 can be arranged along the horizontal direction (i.e., the X direction) of the control device 100B-2. The second memory controller 122B-12, the second basic interface region 122B-22, and the second basic TSV region 122B-32 can be arranged along the horizontal direction (i.e., the X direction) of the control device 100B-2.

[0153] The first memory controller 121B-12 can be electrically connected to the first internal input and output line MIO1. The first memory controller 121B-12 can receive control signals via the first internal input and output line MIO1 to the first set of channels included in the first memory device 200B-2. Figure 7 The first memory controller 121B-12 can output commands CMD and data DATA for the operation of CH1 to CH4 in the first memory device 200B-2. Figure 7The commands CMD and data DATA for operations (CH1 to CH4 in the table).

[0154] The first basic interface area 121B-22 can be electrically connected to the first memory controller 121B-12. The first basic interface area 121B-22 can receive commands CMD and data DATA from the first memory controller 121B-12. The first basic interface area 121B-22 can output commands CMD and data DATA to the first basic TSV area 121B-32 by adjusting the input and output order of commands CMD and data DATA.

[0155] The first basic TSV region 121B-32 can be electrically connected to the first basic interface region 121B-22. The first basic TSV region 121B-32 can receive commands (CMD) and data (DATA) from the first basic interface region 121B-22. The first basic TSV region 121B-32 can output commands (CMD) and data (DATA) to the first core TSV region (1) included in the first memory device 200B-2 via multiple TSVs. st CORE TSV PHY) Figure 7 (210B-2 in the middle).

[0156] The first memory controller 121B-12, the first basic interface region 121B-22, and the first basic TSV region 121B-32 can be sequentially arranged from the center region CENTER of the control device 100B-2 along the first direction D1. The first direction D1 can be set from the center region CENTER to the first edge region TOP. The first edge region TOP can be set as the upper region of the control device 100B-2 on the Y-axis. The first edge region TOP can be arranged from the center region CENTER in an outward direction.

[0157] The second memory controller 122B-12 can be electrically connected to the second internal input and output line MIO2. The second memory controller 122B-12 can receive control signals via the second internal input and output line MIO2 to the second set of channels included in the first memory device 200B-2. Figure 7 The second memory controller 122B-12 can output commands CMD and data DATA for the operation of the second set of channels (CH5 to CH8) included in the first memory device 200B-2. Figure 7 The commands CMD and data DATA for operations (CH5 to CH8) in the table.

[0158] The second basic interface area 122B-22 can be electrically connected to the second memory controller 122B-12. The second basic interface area 122B-22 can receive commands (CMD) and data (DATA) from the second memory controller 122B-12. The second basic interface area 122B-22 can output commands (CMD) and data (DATA) to the second basic TSV area 122B-32 by adjusting the input and output order of these commands.

[0159] The second basic TSV region 122B-32 can be electrically connected to the second basic interface region 122B-22. The second basic TSV region 122B-32 can receive commands (CMD) and data (DATA) from the second basic interface region 122B-22. The second basic TSV region 122B-32 can output commands (CMD) and data (DATA) to the second core TSV region (2) included in the first memory device 200B-2 via multiple TSVs. nd CORE TSV PHY) Figure 7 (220B-2 in the middle).

[0160] The second memory controller 122B-12, the second basic interface region 122B-22, and the second basic TSV region 122B-32 can be sequentially arranged from the second edge region BOTTOM of the control device 100B-2 along the first direction D1. The first direction D1 can be set to the direction from the second edge region BOTTOM to the center region CENTER. The second edge region BOTTOM can be set to the lower region of the control device 100B-2 on the Y-axis. The second edge region BOTTOM can be arranged from the center region CENTER in an outward direction. The first edge region BOTTOM and the second edge region BOTTOM can be arranged from the center region CENTER in opposite directions.

[0161] The second region 120B-2 may include a third memory controller (3) for controlling the operation of the second memory device 300B-2. rd MC)123B-12, Third Basic Interface Area (3 rd DFI I) 123B-22, Third Basic TSV Area (3 rd TSVPHY) 123B-32, Fourth Memory Controller (4 th MC) 124B-12, Fourth Basic Interface Area (4 th DFI) 124B-22 and the fourth basic TSV area (4 thTSV PHY) 124B-32. The third memory controller 123B-12, the third basic interface area 123B-22, and the third basic TSV area 123B-32 can be used to control the first set of channels included in the second memory device 300B-2 ( Figure 7 The components that control the operation of CH1 to CH4 in the second memory device 300B-2. The fourth memory controller 124B-12, the fourth basic interface region 124B-22, and the fourth basic TSV region 124B-32 can be components that control the operation of the second set of channels (CH1 to CH4) included in the second memory device 300B-2. Figure 7 The components of the operation of CH5 to CH8 in the middle.

[0162] The third memory controller 123B-12, the third basic interface area 123B-22, and the third basic TSV area 123B-32 can be arranged along the horizontal direction (i.e., the X direction) of the control device 100B-2. The fourth memory controller 124B-12, the fourth basic interface area 124B-22, and the fourth basic TSV area 124B-32 can also be arranged along the horizontal direction (i.e., the X direction) of the control device 100B-2.

[0163] The third memory controller 123B-12 can be electrically connected to the first internal input and output line MIO1. The third memory controller 123B-12 can receive commands CMD and data DATA through the first internal input and output line MIO1. These commands CMD and data DATA control the first set of channels included in the second memory device 300B-2. Figure 7 The operation of CH1 to CH4 in the second memory device 300B-2. The third memory controller 123B-12 can output control of the first group of channels (CH1 to CH4) included in the second memory device 300B-2. Figure 7 The commands CMD and data DATA for operations (CH1 to CH4 in the table).

[0164] The third basic interface area 123B-22 can be electrically connected to the third memory controller 123B-12. The third basic interface area 123B-22 can receive commands (CMD) and data (DATA) from the third memory controller 123B-12. The third basic interface area 123B-22 can output commands (CMD) and data (DATA) to the third basic TSV area 123B-32 by adjusting the input and output order of commands (CMD) and data (DATA).

[0165] The third basic TSV area 123B-32 can be electrically connected to the third basic interface area 123B-22. The third basic TSV area 123B-32 can receive commands (CMD) and data (DATA) from the third basic interface area 123B-22. The third basic TSV area 123B-32 can output commands (CMD) and data (DATA) to the third core TSV area (3) included in the second memory device 300B-2 via multiple TSVs. rd CORE TSV PHY) Figure 7 (310B-2 in the middle).

[0166] The third memory controller 123B-12, the third basic interface area 123B-22, and the third basic TSV area 123B-32 can be sequentially arranged from the central area CENTER of the control device 100B-2 along the first direction D1.

[0167] The fourth memory controller 124B-12 can be electrically connected to the second internal input and output line MIO2. The fourth memory controller 124B-12 can receive control signals from the second set of channels included in the second memory device 300B-2 via the second internal input and output line MIO2. Figure 7 The fourth memory controller 124B-12 can output commands CMD and data DATA for the operation of CH5 to CH8 in the second memory device 300B-2. Figure 7 The commands CMD and data DATA for operations (CH5 to CH8) in the table.

[0168] The fourth basic interface area 124B-22 can be electrically connected to the fourth memory controller 124B-12. The fourth basic interface area 124B-22 can receive commands (CMD) and data (DATA) from the fourth memory controller 124B-12. The fourth basic interface area 124B-22 can output commands (CMD) and data (DATA) to the fourth basic TSV area 124B-32 by adjusting the input and output order of these commands.

[0169] The fourth basic TSV area 124B-32 can be electrically connected to the fourth basic interface area 124B-22. The fourth basic TSV area 124B-32 can receive commands (CMD) and data (DATA) from the fourth basic interface area 124B-22. The fourth basic TSV area 124B-32 can output commands (CMD) and data (DATA) to the fourth core TSV area (4) included in the second memory device 300B-2 via multiple TSVs. th CORE TSV PHY) Figure 7 (320B-2 in the middle).

[0170] The fourth memory controller 124B-12, the fourth basic interface region 124B-22, and the fourth basic TSV region 124B-32 can be sequentially set from the second edge region BOTTOM of the control device 100B-2 along the first direction D1.

[0171] The second region 120B-2 can be configured to receive commands CMD and data DATA from the first region 110B-2 and output them to the first memory device 200B-2 and the second memory device 300B-2. The second region 120B-2 can be located in the right region (RIGHT) of the control device 100B-2 on the X-axis.

[0172] Figure 7 This is a block diagram illustrating the construction of a first memory device 200B-2 and a second memory device 300B-2 according to embodiments of the present disclosure.

[0173] The first memory device 200B-2 may include a first channel CH1 to an eighth channel CH8, a first core TSV region 210B-2, and a second core TSV region 220B-2.

[0174] The first core TSV region 210B-2 and the second core TSV region 220B-2 can be arranged along the horizontal direction (i.e., the X direction) of the first memory device 200B-2.

[0175] Channels CH1 through CH8 can independently receive commands (CMD) and data (DATA) through internal operations. After a write operation begins, channels CH1 through CH8 can store data (DATA) based on the command (CMD). After a read operation begins, channels CH1 through CH8 can output data (DATA) based on the command (CMD).

[0176] Channels CH1 through CH4 can be electrically connected to the first core TSV region 210B-2. Channels CH1 through CH4 can receive commands (CMD) and data (DATA) from the first core TSV region 210B-2. Channels CH1 through CH4 can also output data (DATA) to the first core TSV region 210B-2. After an internal write operation begins, channels CH1 through CH4 can store data (DATA) based on commands (CMD). After a internal read operation begins, channels CH1 through CH4 can output data (DATA) based on commands (CMD). Channels CH1 through CH4 can be designated as the first group of channels.

[0177] Channels 5 through 8 (CH8) can be electrically connected to the second core TSV area 220B-2. Channels 5 through 8 (CH8) can receive commands (CMD) and data (DATA) from the second core TSV area 220B-2. Channels 5 through 8 (CH8) can also output data (DATA) to the second core TSV area 220B-2. After an internal write operation begins, channels 5 through 8 (CH8) can store data (DATA) based on commands (CMD). After a internal read operation begins, channels 5 through 8 (CH8) can output data (DATA) based on commands (CMD). Channels 5 through 8 (CH8) can be configured as a second group of channels.

[0178] The first channel CH1 to the fourth channel CH4 can be located in the central region CENTER of the first memory device 200B-2. The fifth channel CH5 to the eighth channel CH8 can be located in the second edge region BOTTOM of the first memory device 200B-2.

[0179] The first core TSV region 210B-2 can be electrically connected to the first base TSV region 121B-32 of the control device 100B-2. The first core TSV region 210B-2 can receive commands (CMD) and data (DATA) from the first base TSV region 121B-32. The first core TSV region 210B-2 can receive commands (CMD) and data (DATA) through multiple TSVs. The first core TSV region 210B-2 can output commands (CMD) and data (DATA) to the first channel CH1 to the fourth channel CH4. The first core TSV region 210B-2 can receive data (DATA) from the first channel CH1 to the fourth channel CH4 and output data (DATA) to the first base TSV region 121B-32. The first core TSV region 210B-2 can be positioned from the center region (CENTER) along a first direction D1. The first direction D1 can be set from the center region (CENTER) to the first edge region (TOP). The first edge region (TOP) can be set as the upper region of the first memory device 200B-2 on the Y-axis. The first edge region (TOP) can be arranged from the center region (CENTER) in an outward direction.

[0180] The second core TSV region 220B-2 can be electrically connected to the second base TSV region 122B-32 of the control device 100B-2. The second core TSV region 220B-2 can receive commands (CMD) and data (DATA) from the second base TSV region 122B-32. The second core TSV region 220B-2 can receive commands (CMD) and data (DATA) through multiple TSVs. The second core TSV region 220B-2 can output commands (CMD) and data (DATA) to channels 5 (CH5) to 8 (CH8). The second core TSV region 220B-2 can receive data (DATA) from channels 5 (CH5) to 8 (CH8) and output data (DATA) to the second base TSV region 122B-32. The second core TSV region 220B-2 can be located in the center region (CENTER). The second core TSV region 220B-2 can be located from the second edge region (BOTTOM) along a first direction (D1). The first direction (D1) can be set from the second edge region (BOTTOM) to the center region (CENTER). The second edge region BOTTOM can be set as the lower region of the first memory device 200B-2 on the Y-axis. The second edge region BOTTOM can be arranged from the center region CENTER in an outward direction. The first edge region TOP and the second edge region BOTTOM can be arranged from the center region CENTER in opposite directions.

[0181] The first memory device 200B-2 can be located in the left region LEFT on the X-axis of the first memory device 200B-2.

[0182] The second memory device 300B-2 may include a first channel CH1 to an eighth channel CH8, a third core TSV region 310B-2, and a fourth core TSV region 320B-2.

[0183] The third core TSV region 310B-2 and the fourth core TSV region 320B-2 can be arranged along the horizontal direction (i.e., the X direction) of the second memory device 300B-2.

[0184] Channels CH1 through CH8 can independently receive commands (CMD) and data (DATA) through internal operations. After a write operation begins, channels CH1 through CH8 can store data (DATA) based on the command (CMD). After a read operation begins, channels CH1 through CH8 can output data (DATA) based on the command (CMD).

[0185] Channels CH1 through CH4 can be electrically connected to the third core TSV region 310B-2. Channels CH1 through CH4 can receive commands (CMD) and data (DATA) from the third core TSV region 310B-2. Channels CH1 through CH4 can also output data (DATA) to the third core TSV region 310B-2. After an internal write operation begins, channels CH1 through CH4 can store data (DATA) based on commands (CMD). After a internal read operation begins, channels CH1 through CH4 can output data (DATA) based on commands (CMD). Channels CH1 through CH4 can be designated as the first group of channels.

[0186] Channels 5 through 8 (CH8) can be electrically connected to the fourth core TSV region 320B-2. Channels 5 through 8 (CH8) can receive commands (CMD) and data (DATA) from the fourth core TSV region 320B-2. Channels 5 through 8 (CH8) can also output data (DATA) to the fourth core TSV region 320B-2. After an internal write operation begins, channels 5 through 8 (CH8) can store data (DATA) based on commands (CMD). After a internal read operation begins, channels 5 through 8 (CH8) can output data (DATA) based on commands (CMD). Channels 5 through 8 (CH8) can be configured as a second group of channels.

[0187] The first channel CH1 to the fourth channel CH4 can be located in the central region CENTER of the second memory device 300B-2. The fifth channel CH5 to the eighth channel CH8 can be located in the second peripheral region BOTTOM of the second memory device 300B-2.

[0188] The third core TSV region 310B-2 can be electrically connected to the third base TSV region 123B-32 of the control device 100B-2. The third core TSV region 310B-2 can receive commands (CMD) and data (DATA) from the third base TSV region 123B-32. The third core TSV region 310B-2 can receive commands (CMD) and data (DATA) through multiple TSVs. The third core TSV region 310B-2 can output commands (CMD) and data (DATA) to the first channel CH1 to the fourth channel CH4. The third core TSV region 310B-2 can receive data (DATA) from the first channel CH1 to the fourth channel CH4 and output data (DATA) to the third base TSV region 123B-32. The third core TSV region 310B-2 can be set in the first edge region TOP. The third core TSV region 310B-2 can be arranged from the center region CENTER along the first direction D1.

[0189] The fourth core TSV region 320B-2 can be electrically connected to the fourth base TSV region 124B-32 of the control device 100B-2. The fourth core TSV region 320B-2 can receive commands (CMD) and data (DATA) from the fourth base TSV region 124B-32. The fourth core TSV region 320B-2 can receive commands (CMD) and data (DATA) through multiple TSVs. The fourth core TSV region 320B-2 can output commands (CMD) and data (DATA) to channels 5 (CH5) to 8 (CH8). The fourth core TSV region 320B-2 can receive data (DATA) from channels 5 (CH5) to 8 (CH8) and output data (DATA) to the fourth base TSV region 124B-32. The fourth core TSV region 320B-2 can be set in the center region (CENTER). The fourth core TSV region 320B-2 can be set from the second edge region (BOTTOM) along the first direction (D1).

[0190] The second memory device 300B-2 can be set in the right region (RIGHT) on the X-axis.

[0191] As described above, the semiconductor system 1B according to embodiments of this disclosure can increase bandwidth because the first memory device 200B-2 and the second memory device 300B-2 are jointly connected to the control device 100B-2 and input and output data DATA. The semiconductor system 1B can prevent or reduce heat dissipation from the areas generating commands (CMD) and data DATA to the memory devices because the memory devices (i.e., 200B-2 and 300B-2) are not stacked above the areas generating commands (CMD) and data DATA. The interfaces of the TSVs connected to the control devices 100B, 100B-1, 100B-2 and the memory devices 200B, 200B-1, 200B-2, 300B, 300B-1, 300B-2 can be arranged differently / in different ways in the semiconductor system 1B.

[0192] Figure 8 This is a block diagram illustrating the construction of a semiconductor device 3B according to an embodiment of the present disclosure. Figure 8 As shown, the semiconductor device 3B may include a PCB 11, a substrate 13, an interposer 15, an HBM device 17, and a processor 19.

[0193] PCB 11 connects multiple electronic components to form an electronic circuit (not shown). Copper layers, solder masks, and silkscreen layers can be formed on PCB 11. Circuit paths for transmitting signals or electricity can be formed in the copper layers. Solder masks prevent or mitigate damage to the circuit and protect specific areas where components may be soldered. Furthermore, silkscreen layers indicate the location or information of electronic components in the form of characters or symbols printed on the surface of PCB 11.

[0194] The substrate 13 is formed on the PCB 11 via bump pads (e.g., 115) and can mechanically support the interposer 15, HBM device 17, and processor 19. The substrate 13 can typically be made of an insulator, i.e., the physical substrate of the PCB 11. Materials for the substrate 13 include FR4, an insulator made of glass fiber and epoxy resin; ceramics capable of withstanding high temperatures and suitable for use in high-frequency circuits or high-temperature environments due to their thermal conductivity; and polyimide, used as a flexible PCB substrate due to its flexibility.

[0195] Intermediate layer 15 is formed on substrate 13 via bump pads and may include wires connecting electronic components (e.g., HBM device 17 and processor 19) with mismatched bubble factors or pin arrangements. Intermediate layer 15 can convert signals in different interfaces.

[0196] HBM device 17 can be formed on interposer layer 15 via microbump pads (e.g., 117). HBM device 17 can store data applied by processor 19 or output data stored in HBM device 17 to processor 19 under the control of processor 19. HBM device 17 may include control device 150, first memory device 160, and second memory device 170. First memory device 160 and second memory device 170 can be stacked on control device 150 via microbump pads. Each of first memory device 160 and second memory device 170 can be implemented using multiple core chips vertically stacked via microbump pads. Control device 150, first memory device 160, and second memory device 170 can be vertically stacked via TSVs.

[0197] The control device 150 can generate a command CMD by receiving an external command EC from the processor 19, and can generate data DATA by receiving external data ED from the processing device 19. The control device 150 may include a first area in which the command CMD and data DATA are generated. Figure 1 , 2 (as shown in Figures 4 and 6, 110B, 110B-1, and 110B-2). The first region can be configured to generate heat when generating command CMD and data DATA. Control device 150 can output command CMD and data DATA to a first memory device 160 and a second memory device 170. Control device 150 may include a second region ( Figure 1 , 2 (As shown in Figures 4 and 6, 120B, 120B-1, and 120B-2), commands CMD and data DATA are received from the first region and output to the first memory device 160 and the second memory device 170. The memory devices are not stacked on the first region. The first memory device 160 and the second memory device 170 may be disposed on the second region of the control device 150.

[0198] The first memory device 160 and the second memory device 170 can each store data DATA by performing internal operations based on command CMD, and output the data DATA in each memory device. The first memory device 160 and the second memory device 170 can each include multiple independently operating channels. Figure 3 , Figure 5 and Figure 7 CH1 to CH8 in the middle). Multiple channels ( Figure 3 , Figure 5 and Figure 7 CH1 to CH8 in the table can each store or output data DATA through independent operations.

[0199] HBM device 17 can increase bandwidth because the first memory device 160 and the second memory device 170 are jointly connected to the control device 150 and input and output data DATA. HBM device 17 can prevent or reduce heat dissipation from the areas of generating command CMD and data DATA to the memory devices because the memory devices are not stacked on top of the areas of generating command CMD and data DATA. The interfaces of TSVs connected to the control device 150, the first memory device 160 and the second memory device 170 can be arranged differently in HBM device 17.

[0200] Processor 19 can send commands (CMD) and data (DATA) to control device 150 via wires formed within interposer layer 15, and can receive data (DATA) from control device 150. Processor 19 can send various commands and signals to control the internal operations of control device 150, first memory device 160, and second memory device 170, and can receive the results of internal operations.

[0201] Figure 9 This is a block diagram illustrating the construction of a semiconductor system 5C according to an embodiment of the present disclosure. Figure 9 As shown, the semiconductor system 5C may include a first processing circuit (1) st PRC CT) 100C, Second Processing Circuit (2 nd PRC CT) 200C, Third Processing Circuit (3 rd PRC CT) 300C, First HBM Device (1 st HMB) 410C, Second HMB Device (2 nd HMB) 420C, Third HMB Device (3 rd HMB) 430C and the fourth HMB device (4 th HMB) 440C.

[0202] The first processing circuit 100C can be electrically connected to the first HBM device 410C and the second HBM device 420C. The first processing circuit 100C can be... Figure 8 The intermediate layer 15 shown is electrically connected to the first HBM device 410C and the second HBM device 420C. The first processing circuit 100C can control the operation of the first HBM device 410C and the second HBM device 420C. The first processing circuit 100C can perform arithmetic operations by receiving data DATA from the first HBM device 410C and the second HBM device 420C.

[0203] The second processing circuit 200C can be electrically connected to the first HBM device 410C and the second HBM device 420C. The second processing circuit 200C can... Figure 8The intermediate layer 15 shown is electrically connected to the first HBM device 410C and the second HBM device 420C. The second processing circuit 200C can control the operation of the first HBM device 410C and the second HBM device 420C. The second processing circuit 200C can perform arithmetic operations by receiving data DATA from the first HBM device 410C and the second HBM device 420C. The second processing circuit 200C can be electrically connected to the third HBM device 430C and the fourth HBM device 440C. The second processing circuit 200C can... Figure 8 The intermediate layer 15 shown is electrically connected to the third HBM device 430C and the fourth HBM device 440C. The second processing circuit 200C can control the operation of the third HBM device 430C and the fourth HBM device 440C. The second processing circuit 200C can perform arithmetic operations by receiving data DATA from the third HBM device 430C and the fourth HBM device 440C. The second processing circuit 200C can perform arithmetic operations by receiving data DATA from at least one of the first HBM device 410C, the second HBM device 420C, the third HBM device 430C, and the fourth HBM device 440C.

[0204] The third processing circuit 300C can be electrically connected to the third HBM device 430C and the fourth HBM device 440C. The third processing circuit 300C can... Figure 8 The intermediate layer 15 shown is electrically connected to the third HBM device 430C and the fourth HBM device 440C. The third processing circuit 300C can control the operation of the third HBM device 430C and the fourth HBM device 440C. The third processing circuit 300C can perform arithmetic operations by receiving data DATA from the third HBM device 430C and the fourth HBM device 440C.

[0205] The first processing circuit 100C, the second processing circuit 200C, and the third processing circuit 300C can each be implemented using a graphics processing unit (GPU) device and a neural processing unit (NPU) device.

[0206] Arithmetic operations can include training and inference operations. A training operation can be defined as an operation in which an artificial intelligence (AI) model learns rules, patterns, or relationships by optimizing weights and parameters from given data. An inference operation can be defined as an operation in which an AI model quickly derives results from new data using the weights learned in the training operation.

[0207] The first HBM device 410C, the second HBM device 420C, the third HBM device 430C, and the fourth HBM device 440C may each include: Figures 1 to 8The control device 100B, the first memory device 200B, and the second memory device 300B are shown. The first HBM device 410C, the second HBM device 420C, the third HBM device 430C, and the fourth HBM device 440C can each store data DATA and output the data DATA stored in each HBM device.

[0208] The first HBM device 410C, the second HBM device 420C, the third HBM device 430C, and the fourth HBM device 440C can each be set in a specific configuration. Figure 1 , Figure 2 , Figure 4 and Figure 6 The physical regions (D2D PHY) 111B, 111B-1, and 111B-2 shown are located at their boundaries. The first HBM device 410C, the second HBM device 420C, the third HBM device 430C, and the fourth HBM device 440C can each be electrically connected to the first processing circuit 100C, the second processing circuit 200C, and the third processing circuit 300C via the physical regions D2D PHY. The first HBM device 410C, the second HBM device 420C, the third HBM device 430C, and the fourth HBM device 440C can be shared by the first processing circuit 100C, the second processing circuit 200C, and the third processing circuit 300C via the physical regions D2D PHY.

[0209] The semiconductor system 5C according to an embodiment of this disclosure has multiple HBM devices electrically connected to multiple processing circuits, thus expanding the data capacity used in arithmetic operations of the processing circuits. The semiconductor system 5C has multiple HBM devices shared by multiple processing circuits, thus expanding the number of processing circuits used in arithmetic operations. The semiconductor system 5C can perform arithmetic operations quickly because the multiple HBM devices are electrically connected to multiple processing circuits to perform arithmetic operations.

[0210] Figure 10 This is a block diagram illustrating the construction of a semiconductor system 5C-1 according to an embodiment of the present disclosure. Figure 10 As shown, the semiconductor system 5C-1 may include a first processing circuit (1 st PRC CT) 500C, Second Processing Circuit (2 nd PRC CT) 600C, Third Processing Circuit (3 rd PRC CT) 700C, First HBM Device (1 st HMB) 810C, Second HMB Device (2 nd HMB) 820C, Third HMB Device (3 rd HMB) 830C, Fourth HMB Device (4 thHMB) 840C, Fifth HMB Device (5 th HMB) 850C, Sixth HMB Device (6 th HMB) 860C, Seventh HMB Device (7 th HMB) 870C and the eighth HMB device (8 th HMB) 880C.

[0211] The first processing circuit 500C can be electrically connected to the first HBM device 810C and the second HBM device 820C. The first processing circuit 500C can... Figure 8 The intermediate layer 15 shown is electrically connected to the first HBM device 810C and the second HBM device 820C. The first processing circuit 500C can control the operation of the first HBM device 810C and the second HBM device 820C. The first processing circuit 500C can perform arithmetic operations by receiving data DATA from the first HBM device 810C and the second HBM device 820C. The first processing circuit 500C can be electrically connected to the third HBM device 830C and the fourth HBM device 840C. The first processing circuit 500C can... Figure 8 The intermediate layer 15 shown is electrically connected to the third HBM device 830C and the fourth HBM device 840C. The first processing circuit 500C can control the operation of the third HBM device 830C and the fourth HBM device 840C. The first processing circuit 500C can perform arithmetic operations by receiving data DATA from the third HBM device 830C and the fourth HBM device 840C. The first processing circuit 500C can perform arithmetic operations by receiving data DATA from at least any one of the first HBM device 810C, the second HBM device 820C, the third HBM device 830C, and the fourth HBM device 840C.

[0212] The second processing circuit 600C can be electrically connected to the third HBM device 830C and the fourth HBM device 840C. The second processing circuit 600C can... Figure 8 The intermediate layer 15 shown is electrically connected to the third HBM device 830C and the fourth HBM device 840C. The second processing circuit 600C can control the operation of the third HBM device 830C and the fourth HBM device 840C. The second processing circuit 600C can perform arithmetic operations by receiving data DATA from the third HBM device 830C and the fourth HBM device 840C. The second processing circuit 600C can be electrically connected to the fifth HBM device 850C and the sixth HBM device 860C. The second processing circuit 600C can... Figure 8The intermediate layer 15 shown is electrically connected to the fifth HBM device 850C and the sixth HBM device 860C. The second processing circuit 600C can control the operation of the fifth HBM device 850C and the sixth HBM device 860C. The second processing circuit 600C can perform arithmetic operations by receiving data DATA from the fifth HBM device 850C and the sixth HBM device 860C. The second processing circuit 600C can also perform arithmetic operations by receiving data DATA from at least any one of the third HBM device 830C, the fourth HBM device 840C, the fifth HBM device 850C, and the sixth HBM device 860C.

[0213] The third processing circuit 700C can be electrically connected to the fifth HBM device 850C and the sixth HBM device 860C. The third processing circuit 700C can... Figure 8 The intermediate layer 15 shown is electrically connected to the fifth HBM device 850C and the sixth HBM device 860C. The third processing circuit 700C can control the operation of the fifth HBM device 850C and the sixth HBM device 860C. The third processing circuit 700C can perform arithmetic operations by receiving data DATA from the fifth HBM device 850C and the sixth HBM device 860C. The third processing circuit 700C can be electrically connected to the seventh HBM device 870C and the eighth HBM device 880C. The third processing circuit 700C can... Figure 8 The intermediate layer 15 shown is electrically connected to the seventh HBM device 870C and the eighth HBM device 880C. The third processing circuit 700C can control the operation of the seventh HBM device 870C and the eighth HBM device 880C. The third processing circuit 700C can perform arithmetic operations by receiving data DATA from the seventh HBM device 870C and the eighth HBM device 880C. The third processing circuit 700C can perform arithmetic operations by receiving data DATA from at least any one of the fifth HBM device 850C, the sixth HBM device 860C, the seventh HBM device 870C, and the eighth HBM device 880C.

[0214] The first processing circuit 500C, the second processing circuit 600C, and the third processing circuit 700C can each be implemented using a graphics processing unit (GPU) device and a neural processing unit (NPU) device.

[0215] The first HBM device 810C, the second HBM device 820C, the third HBM device 830C, the fourth HBM device 840C, the fifth HBM device 850C, the sixth HBM device 860C, the seventh HBM device 870C, and the eighth HBM device 880C may each include Figures 1 to 8The control device 100B, first memory device 200B, and second memory device 300B are shown. The first HBM device 810C, second HBM device 820C, third HBM device 830C, fourth HBM device 840C, fifth HBM device 850C, sixth HBM device 860C, seventh HBM device 870C, and eighth HBM device 880C can each store data DATA and output the data DATA stored in their respective HBM devices.

[0216] The first HBM device 810C, the second HBM device 820C, the third HBM device 830C, the fourth HBM device 840C, the fifth HBM device 850C, the sixth HBM device 860C, the seventh HBM device 870C, and the eighth HBM device 880C can each be set in a specific configuration. Figure 1 , Figure 2 , Figure 4 and Figure 6 The boundaries of the physical regions (D2D PHY) 111B, 111B-1, and 111B-2 shown are shown. The first HBM device 810C, the second HBM device 820C, the third HBM device 830C, the fourth HBM device 840C, the fifth HBM device 850C, the sixth HBM device 860C, the seventh HBM device 870C, and the eighth HBM device 880C can each be electrically connected to the first processing circuit 500C, the second processing circuit 600C, and the third processing circuit 700C through the physical region D2D PHY. The first HBM device 810C, the second HBM device 820C, the third HBM device 830C, the fourth HBM device 840C, the fifth HBM device 850C, the sixth HBM device 860C, the seventh HBM device 870C, and the eighth HBM device 880C can be shared by the first processing circuit 500C, the second processing circuit 600C, and the third processing circuit 700C through the physical area D2D PHY.

[0217] The semiconductor system 5C-1 according to an embodiment of this disclosure has multiple HBM devices electrically connected to multiple processing circuits, thus expanding the data capacity used in arithmetic operations of the processing circuits. The semiconductor system 5C-1 has multiple HBM devices shared by multiple processing circuits, thus expanding the number of processing circuits used in arithmetic operations. The semiconductor system 5C-1 can perform arithmetic operations quickly because the multiple HBM devices are electrically connected to multiple processing circuits to perform arithmetic operations.

[0218] Figure 11 This is a block diagram illustrating the construction of an HBM device 7C according to an embodiment of the present disclosure. Figure 11 As shown, the HBM device 7C may include a control device 11C, a memory device 12C, and a first virtual die set (1st DUMMY) 13C and the second virtual nude set (2 nd DUMMY) 14C.

[0219] Control device 11C can generate commands (CMD) and data (DATA). Control device 11C can output commands (CMD) and data (DATA) to memory device 12C. Control device 11C can receive data (DATA) from memory device 12C. Control device 11C can be a controller or a base chip that controls the operation of memory device 12C.

[0220] The control device 11C may include a first region 110C, a second region 120C, and a third region 130C. The upper portion of the first region 110C may be designated as a first setting space. The upper portion of the second region 120C may be designated as a second setting space. The upper portion of the third region 130C may be designated as a third setting space. The first region 110C may be designated as a region for generating commands (CMD) and data (DATA), and for inputting and outputting commands (CMD) and data (DATA). Heat may be generated when the first region 110C inputs and outputs commands (CMD) and data (DATA). The second region 120C may be designated as a region for receiving commands (CMD) and data (DATA) from the first region 110C and outputting commands (CMD) and data (DATA) to the memory device 12C, and for receiving data (DATA) from the memory device 12C and outputting data (DATA) to both the first region 110C and the third region 130C. The third region 130C may be designated as a region for receiving commands (CMD) and data (DATA) and inputting and outputting commands (CMD) and data (DATA). The third zone 130C can be configured to output command CMD and data DATA to another HBM device, processing circuitry, or external device, and to input command CMD and data DATA from another HBM device, processing circuitry, or external device. Heat may be generated when the third zone 130C inputs and outputs command CMD and data DATA.

[0221] The first region 110C may include the first physical region (1 st D2D PHY) 111C and the first internal interface area (1 st INT IF) 112C.

[0222] The first physical region 111C can be based on the processing circuit ( Figure 9 and Figure 10The first physical area 111C can output the command CMD and data DATA to the first internal interface area 112C. The first physical area 111C can receive data DATA from the first internal interface area 112C and output the data DATA to the processing circuit. Figure 9 and Figure 10 (PRC CT in the text). The first physical region 111C can be the physical layer PHY responsible for the generation, transmission, reception and physical connection of signals and data between external devices and control devices 11C.

[0223] The first internal interface area 112C can receive commands CMD and data DATA from the first physical area 111C. The first internal interface area 112C can output commands CMD and data DATA to internal input and output lines by adjusting the input and output order of the commands CMD and data DATA. Figure 12 MIO1 and MIO2 in the middle). The first internal interface area 112C can be connected to internal input and output lines ( Figure 12 The MIO1 and MIO2 in the PHY layer receive data DATA and output data DATA to the first physical area 111C. The first internal interface area 112C can output command CMD and data DATA to the second area 120C and the third area 130C by adjusting the input and output order of command CMD and data DATA. The first internal interface area 112C can be an interface for the timing and sequence of signals transmitted between the physical layer PHY and internal circuitry, as well as input and output signals. The first internal interface area 112C and the internal input and output lines ( Figure 12 MIO1 and MIO2 in the chip can be implemented in a network on-chip (NoC). A network on-chip (NoC) can be configured as a transmission path connecting several types of internal circuits within the chip.

[0224] The second region 120C may include a memory controller (MC) 121C, a basic interface region (DFI) 122C, and a basic TSV region (TSV PHY) 123C.

[0225] The memory controller 121C can be connected via internal input and output lines ( Figure 12 The memory controller 121C receives commands CMD and data DATA from MIO1 and MIO2. The memory controller 121C can output commands CMD and data DATA to the base interface area 122C to control the operation of the memory device 12C. The memory controller 121C can receive data DATA from the base interface area 122C and output data DATA to the internal input and output lines (MIO1 and MIO2). Figure 12 (MIO1 and MIO2 in the text).

[0226] The basic interface area 122C can receive commands CMD and data DATA from the memory controller 121C. The basic interface area 122C can output commands CMD and data DATA to the basic TSV area 123C by adjusting the input and output order of commands CMD and data DATA. The basic interface area 122C can receive data DATA from the basic TSV area 123C and output data DATA to the memory controller 121C.

[0227] The basic TSV area 123C can receive commands (CMD) and data (DATA) from the basic interface area 122C. The basic TSV area 123C can output commands (CMD) and data (DATA) to the memory device 12C through multiple TSVs. The basic TSV area 123C can receive data (DATA) from the memory device 12C and output data (DATA) to the basic interface area 122C.

[0228] The memory controller 121C, the basic interface area 122C, and the basic TSV area 123C can be positioned in the horizontal direction (i.e., the X direction) of the control device 11C.

[0229] The third region 130C may include a second internal interface region (2 nd INT IF) 131C and the second physical region (2ntD2D PHY) 132C.

[0230] The second internal interface area 131C can access internal input and output lines ( Figure 12 The second internal interface region 131C receives commands (CMD) and data (DATA) from MIO1 and MIO2. The second internal interface region 131C can output commands (CMD) and data (DATA) to the second physical region 132C by adjusting the input and output order of these commands. The second internal interface region 131C can define the timing and sequence of signals transmitted between the physical layer PHY and internal circuitry, as well as the interface for input and output signals. The second internal interface region 131C can be implemented in a network-on-chip (NoC).

[0231] The second physical area 132C can receive commands (CMD) and data (DATA) from the second internal interface area 131C. The second physical area 132C can output commands (CMD) and data (DATA) to another HBM device and processing circuit. Figure 9 and Figure 10 (PRC CT in the text). The second physical region 132C can be the physical layer PHY responsible for the generation, transmission, reception, and physical connection of signals and data between external devices and control devices 11C.

[0232] The memory device 12C may include multiple vertically stacked core dies. The memory device 12C may be located in a second setup space. The memory device 12C may receive commands CMD and data DATA from the underlying TSV region 123C. The memory device 12C may perform internal operations based on the commands CMD and data DATA. After a write operation begins, the memory device 12C may store data DATA in the multiple core dies based on the commands CMD. After a read operation begins, the memory device 12C may output the data DATA stored in the multiple core dies to the underlying TSV region 123C based on the commands CMD.

[0233] The first virtual die group 13C can be vertically stacked on the first region 110C of the control device 11C. The first virtual die group 13C can be disposed in a first mounting space. The first virtual die group 13C can have multiple virtual dies (not shown) stacked thereon. The first virtual die group 13C can have the same height as the memory device 12C. According to one embodiment, the first virtual die group 13C can be a single virtual die. According to one embodiment, the first mounting space in which the first virtual die group 13C is formed can be an empty space. The first virtual die group 13C can dissipate heat generated from the first region 110C of the control device 11C. The multiple virtual dies (not shown) included in the first virtual die group 13C can facilitate heat dissipation because the multiple virtual dies are connected via multiple TSVs through multiple microbump pads.

[0234] The second virtual die group 14C can be vertically stacked on the third region 130C of the control device 11C. The second virtual die group 14C can be disposed in a third mounting space. The second virtual die group 14C can have multiple virtual dies (not shown) stacked thereon. According to one embodiment, the second virtual die group 14C can be a single virtual die. According to one embodiment, the third mounting space forming the second virtual die group 14C can be an empty space. The second virtual die group 14C can dissipate heat generated from the third region 130C of the control device 11C. The multiple virtual dies (not shown) included in the second virtual die group 14C facilitate heat dissipation because the multiple virtual dies are connected via multiple TSVs through multiple microbump pads.

[0235] The HBM device 7C according to an embodiment of the present disclosure can prevent the generated heat from spreading to the memory device because the memory device is not stacked on the area where heat is generated due to the input and output of commands (CMD) and data (DATA). The HBM device 7C according to an embodiment of the present disclosure can facilitate heat dissipation because the virtual die set is stacked on the area where heat is generated due to the input and output of commands (CMD) and data (DATA).

[0236] Figure 12 This is a block diagram illustrating the construction of a control device 11C according to an embodiment of the present disclosure. Figure 12 As shown, the control device 11C may include a first region 110C, a second region 120C, and a third region 130C.

[0237] The first region 110C may include the first physical region (1 st D2D PHY) 111C and the first internal interface area (1 st INT IF) 112C.

[0238] The first physical region 111C can be accessed from the processing circuit ( Figure 9 and Figure 10 The first physical region 111C can generate a command CMD by receiving an external command EC from the PRC CT. The external command EC and command CMD are each shown as a single signal, but may each include multiple bits. The first physical region 111C can generate a command CMD by receiving an external command EC from the processing circuit (…). Figure 9 and Figure 10 The PRC CT in the first physical region 111C receives external data ED to generate data DATA. The first physical region 111C can also generate external data ED by receiving data DATA from the first internal interface region 112C. The first physical region 111C can output the external data ED to the processing circuitry. Figure 9 and Figure 10 (PRC CT in the text). External data ED and data DATA are each represented as a single signal, but may each include multiple bits.

[0239] The first internal interface region 112C can receive commands CMD and data DATA from the first physical region 111C. The first internal interface region 112C can output commands CMD and data DATA controlling the operation of the memory device 12C to the first internal input / output line MIO1 by adjusting the input and output order of commands CMD and data DATA. The first internal interface region 112C can also output commands CMD and data DATA controlling the operation of the memory device 12C to the second internal input / output line MIO2 by adjusting the input and output order of commands CMD and data DATA. The first internal input / output line MIO1 and the second internal input / output line MIO2 can be located in the central region CENTER of the control device 11C. The first internal interface region 112C, the first internal input / output line MIO1, and the second internal input / output line MIO2 can be implemented in a network on-chip (NoC).

[0240] The first region 110C can be configured to generate commands (CMD) and data (DATA), and to input and output commands (CMD) and data (DATA). Heat may be generated when the first region 110C inputs and outputs commands (CMD) and data (DATA). The first region 110C can be located in the left-hand region (LEFT) of the control device 11C on the X-axis.

[0241] The second region 120C may include a first memory controller (1) for controlling the operation of the memory device 12C. st MC) 121C-1, First Basic Interface Area (1 st DFI) 121C-2, First Basic TSV Area (1 st TSV PHY) 121C-3, Second Memory Controller (2 nd MC)122C-1, Second Basic Interface Area (2 nd DFI) 122C-2 and the second basic TSV area (2 nd TSV PHY) 122C-3. The first memory controller 121C-1, the first basic interface region 121C-2, and the first basic TSV region 121C-3 can be used to control the first set of channels included in the memory device 12C ( Figure 14 The components for operating CH1 to CH4 in the memory device 12C. The second memory controller 122C-1, the second basic interface region 122C-2, and the second basic TSV region 122C-3 can be components for controlling the operation of the second set of channels (CH1 to CH4) included in the memory device 12C. Figure 14 The components for the operation of CH5 to CH8 in the memory controller. Each of the first memory controller 121C-1, the first basic interface region 121C-2 and the first basic TSV region 121C-3, and the second memory controller 122C-1, the second basic interface region 122C-2 and the second basic TSV region 122C-3 can be used Figure 11 The memory controller 121C, the basic interface region 122C, and the basic TSV region 123C shown are used to implement this.

[0242] The first memory controller 121C-1, the first basic interface area 121C-2, the first basic TSV area 121C-3, the second memory controller 122C-1, the second basic interface area 122C-2, and the second basic TSV area 122C-3 can be arranged in the horizontal direction (i.e., the X direction) of the control device 11C.

[0243] The first memory controller 121C-1 can be electrically connected to the first internal input and output line MIO1. The first memory controller 121C-1 can receive control signals from the first set of channels included in the memory device 12C via the first internal input and output line MIO1. Figure 14 The first memory controller 121C-1 can output commands CMD and data DATA for the operation of CH1 to CH4 in the memory device 12C. Figure 14 The first memory controller 121C-1 can receive data DATA from the first basic interface area 121C-2 and output data DATA to the first internal input and output line MIO1.

[0244] The first basic interface area 121C-2 can be electrically connected to the first memory controller 121C-1. The first basic interface area 121C-2 can receive commands (CMD) and data (DATA) from the first memory controller 121C-1. The first basic interface area 121C-2 can output commands (CMD) and data (DATA) to the first basic TSV area 121C-3 by adjusting the input and output order of the commands (CMD) and data (DATA). The first basic interface area 121C-2 can receive data (DATA) from the first basic TSV area 121C-3 and output data (DATA) to the first memory controller 121C-1.

[0245] The first basic TSV region 121C-3 can be electrically connected to the first basic interface region 121C-2. The first basic TSV region 121C-3 can receive commands (CMD) and data (DATA) from the first basic interface region 121C-2. The first basic TSV region 121C-3 can output commands (CMD) and data (DATA) to the first core TSV region (1) included in the memory device 12C via multiple TSVs. st CORE TSV PHY) Figure 14 (210C in the middle). The first basic TSV area 121C-3 can receive data DATA from the memory device 12C and output data DATA to the first basic interface area 121C-2.

[0246] The first memory controller 121C-1, the first basic interface region 121C-2, and the first basic TSV region 121C-3 can be sequentially arranged from the center region CENTER of the control device 11C along the first direction D1. The first direction D1 can be set from the center region CENTER to the first edge region TOP. The first edge region TOP can be set as the upper region of the control device 11C on the Y-axis.

[0247] The second memory controller 122C-1 can be electrically connected to the second internal input and output line MIO2. The second memory controller 122C-1 can receive control signals from the second set of channels included in the memory device 12C via the second internal input and output line MIO2. Figure 14 The second memory controller 122C-1 can output commands CMD and data DATA for the operation of the second set of channels (CH5 to CH8) included in the memory device 12C. Figure 14 The second memory controller 122C-1 can receive data DATA from the second basic interface area 122C-2 and output data DATA to the second internal input and output line MIO2.

[0248] The second basic interface area 122C-2 can be electrically connected to the second memory controller 122C-1. The second basic interface area 122C-2 can receive commands (CMD) and data (DATA) from the second memory controller 122C-1. The second basic interface area 122C-2 can output commands (CMD) and data (DATA) to the second basic TSV area 122C-3 by adjusting the input and output order of the commands (CMD) and data (DATA). The second basic interface area 122C-2 can receive data (DATA) from the second basic TSV area 122C-3 and output data (DATA) to the second memory controller 121C-2.

[0249] The second basic TSV region 122C-3 can be electrically connected to the second basic interface region 122C-2. The second basic TSV region 122C-3 can receive commands (CMD) and data (DATA) from the second basic interface region 122C-2. The second basic TSV region 122C-3 can output commands (CMD) and data (DATA) to the second core TSV region (2) included in the memory device 12C via multiple TSVs. nd CORE TSV PHY) Figure 14 (220C in the middle). The second basic TSV area 122C-3 can receive data DATA from the memory device 12C and output data DATA to the second basic interface area 122C-2.

[0250] The second memory controller 122C-1, the second basic interface region 122C-2, and the second basic TSV region 122C-3 can be sequentially arranged from the center region CENTER of the control device 11C along the second direction D2. The second direction D2 can be set to the direction from the center region CENTER to the second edge region BOTTOM. The second edge region BOTTOM can be set to the lower region of the control device 11C on the Y-axis.

[0251] The second region 120C can be configured to receive commands (CMD) and data (DATA) from the first region 110C and output them to the memory device 12C. The second region 120C can be located in the central region CENTER of the control device 11C on the X-axis.

[0252] The third region 130C may include a second internal interface (2) nd INT IF) Region 131C and Second Physical Region (2 nd D2D PHY) 132C.

[0253] The second internal interface region 131C can receive commands (CMD) and data (DATA) from the first internal input and output line MIO1. The second internal interface region 131C can adjust the input and output order of commands (CMD) and data (DATA) to output the received commands (CMD) and data (DATA) to the second physical region 132C. The second internal interface region 131C can also receive commands (CMD) and data (DATA) from the second internal input and output line MIO2. The second internal interface region 131C can adjust the input and output order of commands (CMD) and data (DATA) to output the received commands (CMD) and data (DATA) to the second physical region 132C. The second internal interface region 131C can be implemented in a network-on-chip (NoC).

[0254] The second physical area 132C can receive commands CMD and data DATA from the second internal interface area 131C. The second physical area 132C can output commands CMD, which are received as transmission commands TC. The second physical area 132C can output data DATA, which is received as transmission data TD. The second physical area 132C can output transmission commands TC and transmission data TD to another HBM device and processing circuit. Figure 9 and Figure 10 PRC CT in (the context of the PRC CT).

[0255] The third area 130C can be configured to receive commands (CMD) and data (DATA) from the second area 120C. The third area 130C can also be configured to input and output commands (TC) and data (TD) generated from the received commands (CMD) and data (DATA). The third area 130C can be configured to input commands (CMD) and data (DATA) to another HBM device, processing circuit, or external device, and to output commands (CMD) and data (DATA) from another HBM device, processing circuit, or external device. The third area 130C can be located in the right-hand area (RIGHT) of the control device 11C on the X-axis.

[0256] exist Figure 12 In the Network-on-Chip (NoC), the first internal interface region 112C, the second internal interface region 131C, the first internal input / output line MIO1, and the second internal input / output circuit MIO2 implemented in the network-on-chip (NoC) can be implemented in a first form. The first form refers to the form in which the first internal input and output line MIO1 and the second internal input and output line MIO2, implemented along the X-axis in the horizontal direction of the control device 11C, are arranged between the first internal interface region 112C and the second internal interface region 131C, wherein the first internal interface region 112C and the second internal interface region 131C are implemented along the Y-axis in the vertical direction of the control device 11C.

[0257] In the first configuration, the first memory controller 121C-1, the first basic interface region 121C-2, and the first basic TSV region 121C-3 can be sequentially arranged from the central region CENTER, which is provided with the first internal input and output lines MIO1, along the first direction D1. In the first configuration, the second memory controller 122C-1, the second basic interface region 122C-2, and the second basic TSV region 122C-3 can be sequentially arranged from the central region CENTER, which is provided with the second internal input and output lines MIO2, along the second direction D2.

[0258] Figure 13 This is a block diagram illustrating the construction of a control device 11C according to an embodiment of the present disclosure. Figure 13 As shown, the control device 11C may include a first region 110C and a second region 120C.

[0259] The first region 110C may include the first physical region (1 st D2D PHY) 111C and the first internal interface area (1 st INT IF) 112C.

[0260] The first physical region 111C and the first internal interface region 112C have the same Figure 12 The first physical region 111 and the first internal interface region 112C shown have the same structure, so their detailed description is omitted.

[0261] and Figure 12 The first internal input / output line MIO1 shown is different. Figure 13 The first internal input / output line MIO1 shown is connected to the first internal interface area 112C and the first memory controller (1). st Between MC) 121C-4, and it can input and output commands CMD and data DATA. (and) Figure 12 The second internal input and output lines MIO2 shown are different. Figure 13The second internal input and output line MIO2 shown is connected to the first internal interface area 112C and the second memory controller (2). nd It is located between MC122C-4 and can input and output commands CMD and data DATA. The first internal input and output line MIO1 and the second internal input and output line MIO2 can be implemented in the on-chip network (NoC).

[0262] The first region 110C can be configured as an area for generating commands (CMD) and data (DATA), as well as for inputting and outputting commands (CMD) and data (DATA). Heat may be generated when commands (CMD) and data (DATA) are input or output in the first region 110C. The first region 110C can be located in the left-hand region (LEFT) of the control device 11C on the X-axis.

[0263] The second region 120C may include a first memory controller 121C-4 that controls the operation of the memory device 12C, and a first basic interface region (1 st DFI) 121C-5, First Basic TSV Area (1 st TSV PHY) 121C-6, Second Memory Controller 122C-4, Second Basic Interface Area (2 nd DFI) 122C-5 and the second basic TSV area (2 nd TSV PHY) 122C-6.

[0264] The first memory controller 121C-4, the first basic interface region 121C-5, the first basic TSV region 121C-6, the second memory controller 122C-4, the second basic interface region 122C-5, and the second basic TSV region 122C-6 have the same characteristics as... Figure 12 The first memory controller 121C-1, the first basic interface region 121C-2, the first basic TSV region 121C-3, the second memory controller 122C-1, the second basic interface region 122C-2, and the second basic TSV region 122C-3 shown have the same structure, therefore their detailed description is omitted.

[0265] The second region 120C can be configured to receive commands (CMD) and data (DATA) from the first region 110C and output them to the memory device 12C. The second region 120C can be located in the right-hand region (RIGHT) of the control device 11C on the X-axis.

[0266] exist Figure 13In this implementation, the first internal interface region 112C, the first internal input / output line MIO1, and the second internal input / output circuit MIO2, implemented in the network-on-chip (NoC), can be implemented in a second form. The second form refers to a configuration where the first internal interface region 112C is implemented vertically along the Y-axis direction of the control device 11C, and the first internal input / output line MIO1 and the second internal input / output line MIO2 are implemented horizontally along the X-axis direction of the control device 11C.

[0267] In the second configuration, the first memory controller 121C-4, the first basic interface region 121C-5, and the first basic TSV region 121C-6 can be sequentially arranged from the central region CENTER, which is provided with the first internal input and output lines MIO1, along the first direction D1. In the second configuration, the second memory controller 122C-4, the second basic interface region 122C-5, and the second basic TSV region 122C-6 can be sequentially arranged from the central region CENTER, which is provided with the second internal input and output lines MIO2, along the second direction D2.

[0268] Although not shown, in one embodiment, the first region 110C may be located in the right region (RIGHT) of the control device 11C on the X-axis. Therefore, the second region 120C, which controls the operation of the memory device 12C, is located in the left region (LEFT) of the control device on the X-axis, and the internal interface region 112C, the first internal input and output line MIO1, and the second internal input and output line MIO2 may be connected thereto, thereby implementing a network-on-chip (NoC).

[0269] Figure 14 This is a block diagram illustrating the construction of a memory device 12C according to an embodiment of the present disclosure.

[0270] The memory device 12C may include a first channel CH1 to an eighth channel CH8, a first core TSV region 210C, and a second core TSV region 220C.

[0271] Channels CH1 through CH8 can independently receive commands (CMD) and data (DATA) by executing internal operations. After a write operation begins, channels CH1 through CH8 can store data (DATA) based on commands (CMD). After a read operation begins, channels CH1 through CH8 can output data (DATA) based on commands (CMD).

[0272] Channels CH1 through CH4 can be electrically connected to the first core TSV region 210C. Channels CH1 through CH4 can receive commands (CMD) and data (DATA) from the first core TSV region 210C. Channels CH1 through CH4 can also output data (DATA) to the first core TSV region 210C. After an internal write operation begins, channels CH1 through CH4 can store data (DATA) based on commands (CMD). After a internal read operation begins, channels CH1 through CH4 can output data (DATA) based on commands (CMD). Channels CH1 through CH4 can be designated as the first group of channels.

[0273] Channels 5 through 8 (CH8) can be electrically connected to the second core TSV region 220C. Channels 5 through 8 (CH8) can receive commands (CMD) and data (DATA) from the second core TSV region 220C. Channels 5 through 8 (CH8) can output data (DATA) to the second core TSV region 220C. After an internal write operation begins, channels 5 through 8 (CH8) can store data (DATA) based on commands (CMD). After an internal read operation begins, channels 5 through 8 (CH8) can output data (DATA) based on commands (CMD). Channels 5 through 8 (CH8) can be configured as a second group of channels.

[0274] The first channel CH1 to the fourth channel CH4 can be located in the central region CENTER of the memory device 12C. The fifth channel CH5 to the eighth channel CH8 can be located in the central region CENTER of the memory device 12C.

[0275] The first core TSV region 210C can be electrically connected to the first basic TSV regions 121C-3 and 121C-6 of the control device 11C. The first core TSV region 210C can receive commands (CMD) and data (DATA) from the first basic TSV regions 121C-3 and 121C-6. The first core TSV region 210C can receive commands (CMD) and data (DATA) through multiple TSVs. The first core TSV region 210C can output commands (CMD) and data (DATA) to the first channel CH1 to the fourth channel CH4. The first core TSV region 210C can receive data (DATA) from the first channel CH1 to the fourth channel CH4 and output data (DATA) to the first basic TSV regions 121C-3 and 121C-6. The first core TSV region 210C can be set from the center region CENTER along a first direction D1. The first direction D1 can be set from the center region CENTER to the first edge region TOP. The first edge region TOP can be set as the upper region of the memory device 12C on the Y-axis.

[0276] The second core TSV region 220C can be electrically connected to the second basic TSV regions 122C-3 and 122C-6 of the control device 11C. The second core TSV region 220C can receive commands (CMD) and data (DATA) from the second basic TSV regions 122C-3 and 122C-6. The second core TSV region 220C can receive commands (CMD) and data (DATA) through multiple TSVs. The second core TSV region 220C can output commands (CMD) and data (DATA) to channels CH5 to CH8. The second core TSV region 220C can receive data (DATA) from channels CH5 to CH8 and output data (DATA) to the second basic TSV regions 122C-3 and 122C-6. The second core TSV region 220C can be set from the center region (CENTER) along the second direction D2. The second direction D2 can be set from the center region (CENTER) to the second edge region (BOTTOM). The second edge region (BOTTOM) can be set as the lower region of the memory device 12C on the Y-axis.

[0277] The HBM device 7C according to an embodiment of the present disclosure can prevent the generated heat from spreading to the memory device because the memory device is not stacked on the area where heat is generated due to the input and output of commands (CMD) and data (DATA). The HBM device 7C according to an embodiment of the present disclosure can facilitate heat dissipation because the virtual die set is stacked on the area where heat is generated due to the input and output of commands (CMD) and data (DATA).

[0278] Figure 15 This is a block diagram illustrating the construction of the control device 11C-1 according to an embodiment of the present disclosure. Figure 15 As shown, the control device 11C-1 may include a first region 110C-1, a second region 120C-1, and a third region 130C-1.

[0279] The first region 110C-1 may include the first physical region (1 st D2D PHY) 111C-1 and the first internal interface area (1 st INT IF) 112C-1.

[0280] The first physical region 111C-1 can be processed by the processing circuit ( Figure 9 and Figure 10 The first physical region 111C-1 can generate a command CMD by receiving an external command EC from the PRC CT. The external command EC and command CMD are each shown as a single signal, but may each include multiple bits. The first physical region 111C-1 can generate a command CMD by receiving an external command EC from the processing circuit (…). Figure 9 and Figure 10 The PRC CT in the first physical area 111C-1 receives external data ED to generate data DATA. The first physical area 111C-1 can also receive data DATA from the first internal interface area 112C-1 to generate external data ED. The first physical area 111C-1 can output the external data ED to the processing circuit. Figure 9 and Figure 10 (PRC CT in the text). External data ED and data DATA are each represented as a single signal, but may each include multiple bits.

[0281] The first internal interface area 112C-1 can receive commands CMD and data DATA from the first physical area 111C-1. The first internal interface area 112C-1 can control the memory device (…) by adjusting the input and output order of commands CMD and data DATA. Figure 17 The command CMD and data DATA of the operation of the 12C-1 in the first internal interface area 112C-1 are output to the first internal input and output line MIO1. The first internal interface area 112C-1 can control the memory device ( ) by adjusting the input and output order of the command CMD and data DATA. Figure 17The commands CMD and data DATA of the operation of the control device 11C-1 (12C-1) are output to the second internal input and output line MIO2. The first internal input and output line MIO1 can be set in the first edge region TOP of the control device 11C-1. The second internal input and output line MIO2 can be set in the second edge region BOTTOM of the control device 11C-1. The first internal interface region 112C-1, the first internal input and output line MIO1, and the second internal input and output line MIO2 can be implemented in a network on-chip (NoC).

[0282] The first region 110C-1 can be configured to generate commands (CMD) and data (DATA) and to input and output commands (CMD) and data (DATA). Heat may be generated when the first region 110C-1 inputs and outputs commands (CMD) and data (DATA). The first region 110C-1 can be located in the left-hand region (LEFT) of the control device 11C-1 on the X-axis.

[0283] The second region 120C-1 may include a first memory controller (1) for controlling the operation of the memory device 12C-1. st MC) 121C-11, First Basic Interface Area (1 st DFI) 121C-21, First Basic TSV Area (1 st TSV PHY) 121C-31, Second Memory Controller (2 nd MC) 122C-11, Second Basic Interface Area (2 nd DFI) 122C-21 and the second basic TSV area (2 nd TSV PHY) 122C-31. The first memory controller 121C-11, the first basic interface region 121C-21, and the first basic TSV region 121C-31 can be used to control the memory device ( Figure 17 The first group of channels included in 12C-1) Figure 17 The components for the operation of CH1 to CH4). The second memory controller 122C-11, the second basic interface region 122C-21, and the second basic TSV region 122C-31 can be components for controlling the memory device (CH1 to CH4). Figure 17 The second group of channels included in 12C-1) Figure 17 The components for the operation of CH5 to CH8). Each of the first memory controller 121C-11, the first basic interface region 121C-21 and the first basic TSV region 121C-31, and the second memory controller 122C-11, the second basic interface region 122C-21 and the second basic TSV region 122C-31 can be used with Figure 11The memory controller 121C, the basic interface region 122C, and the basic TSV region 123C shown are used to implement this.

[0284] The first memory controller 121C-11, the first basic interface area 121C-21, the first basic TSV area 121C-31, the second memory controller 122C-11, the second basic interface area 122C-21, and the second basic TSV area 122C-31 can be arranged in the horizontal direction (i.e., the X direction) of the control device 11C-1.

[0285] The first memory controller 121C-11 can be electrically connected to the first internal input and output line MIO1. The first memory controller 121C-11 can receive control signals for the memory device via the first internal input and output line MIO1. Figure 17 The first group of channels included in 12C-1) Figure 17 The first memory controller 121C-11 can output control commands (CMD) and data (DATA) for the operation of memory devices (CH1 to CH4). Figure 17 The first group of channels included in 12C-1) Figure 17 The first memory controller 121C-11 can receive data DATA from the first basic interface area 121C-21 and output data DATA to the first internal input and output line MIO1.

[0286] The first basic interface area 121C-21 can be electrically connected to the first memory controller 121C-11. The first basic interface area 121C-21 can receive commands (CMD) and data (DATA) from the first memory controller 121C-11. The first basic interface area 121C-21 can output commands (CMD) and data (DATA) to the first basic TSV area 121C-31 by adjusting the input and output order of the commands (CMD) and data (DATA). The first basic interface area 121C-21 can receive data (DATA) from the first basic TSV area 121C-31 and output data (DATA) to the first memory controller 121C-11.

[0287] The first basic TSV area 121C-31 can be electrically connected to the first basic interface area 121C-21. The first basic TSV area 121C-31 can receive commands (CMD) and data (DATA) from the first basic interface area 121C-21. The first basic TSV area 121C-31 can output commands (CMD) and data (DATA) to a memory device via multiple TSVs. Figure 17 The first core TSV region (1 in 12C-1) includes stCORE TSV PHY) Figure 17 210C-1). The first basic TSV region 121C-31 can be obtained from the memory device ( Figure 17 The 12C-1 section receives data DATA and outputs data DATA to the first basic interface area 121C-21.

[0288] The first memory controller 121C-11, the first basic interface region 121C-21, and the first basic TSV region 121C-31 can be sequentially arranged from the first edge region TOP of the control device 11C-1 along the second direction D2. The second direction D2 can be set to the direction from the first edge region TOP to the center region CENTER. The first edge region TOP can be set to the upper region of the control device 11C-1 on the Y-axis.

[0289] The second memory controller 122C-11 can be electrically connected to the second internal input and output line MIO2. The second memory controller 122C-11 can receive control signals for the memory device via the second internal input and output line MIO2. Figure 17 The second group of channels included in 12C-1) Figure 17 The second memory controller 122C-11 can output control commands (CMD and DATA) for the operation of memory devices (CH5 to CH8). Figure 17 The second group of channels included in 12C-1) Figure 17 The second memory controller 122C-11 can receive data DATA from the second basic interface area 122C-21 and output data DATA to the second internal input and output line MIO2.

[0290] The second basic interface area 122C-21 can be electrically connected to the second memory controller 122C-11. The second basic interface area 122C-21 can receive commands (CMD) and data (DATA) from the second memory controller 122C-11. The second basic interface area 122C-21 can output commands (CMD) and data (DATA) to the second basic TSV area 122C-31 by adjusting the input and output order of the commands (CMD) and data (DATA). The second basic interface area 122C-21 can receive data (DATA) from the second basic TSV area 122C-31 and output data (DATA) to the second memory controller 121C-21.

[0291] The second basic TSV area 122C-31 can be electrically connected to the second basic interface area 122C-21. The second basic TSV area 122C-31 can receive commands (CMD) and data (DATA) from the second basic interface area 122C-21. The second basic TSV area 122C-31 can output commands (CMD) and data (DATA) to a memory device via multiple TSVs. Figure 17 The second core TSV region (2) included in 12C-1) nd CORE TSV-PHY) Figure 17 220C-1). The second basic TSV region 122C-31 can be obtained from the memory device ( Figure 17 The 12C-1 section receives data DATA and outputs data DATA to the second basic interface area 122C-21.

[0292] The second memory controller 122C-11, the second basic interface region 122C-21, and the second basic TSV region 122C-31 can be sequentially arranged from the second edge region BOTTOM of the control device 11C-1 along the first direction D1. The first direction D1 can be set to the direction from the second edge region BOTTOM to the center region CENTER. The second edge region BOTTOM can be set to the lower region of the control device 11C-1 on the Y-axis.

[0293] The second region 120C-1 can be configured to receive commands CMD and data DATA from the first region 110C-1 and output commands CMD and data DATA to a memory device. Figure 17 The second region 120C-1 can be set in the central region CENTER of the control device 11C-1 on the X-axis.

[0294] The third region 130C-1 may include a second internal interface region (2) nd INT IF) 131C-1 and the second physical region (2 nd D2D PHY) 132C-1.

[0295] The second internal interface region 131C-1 can receive commands (CMD) and data (DATA) from the first internal input and output line MIO1. The second internal interface region 131C-1 can adjust the input and output order of commands (CMD) and data (DATA) to output the received commands (CMD) and data (DATA) to the second physical region 132C-1. The second internal interface region 131C-1 can also receive commands (CMD) and data (DATA) from the second internal input and output line MIO2. The second internal interface region 131C-1 can adjust the input and output order of commands (CMD) and data (DATA) to output the received commands (CMD) and data (DATA) to the second physical region 132C-1. The second internal interface region 131C-1 can be implemented in a network-on-chip (NoC).

[0296] The second physical area 132C-1 can receive commands CMD and data DATA from the second internal interface area 131C-1. The second physical area 132C-1 can output commands CMD, which are received as transmission commands TC. The second physical area 132C-1 can output data DATA, which is received as transmission data TD. The second physical area 132C-1 can output transmission commands TC and transmission data TD to another HBM device and processing circuit. Figure 9 and Figure 10 PRC CT in (the context of the PRC CT).

[0297] The third area 130C-1 can be configured to receive commands (CMD) and data (DATA) from the second area 120C-1. The third area 130C-1 can also be configured to input and output transmission commands (TC) and transmission data (TD) from the received commands (CMD) and data (DATA). The third area 130C-1 can be configured to input commands (CMD) and data (DATA) to another HBM device, processing circuit, or external device, and to output commands (CMD) and data (DATA) from another HBM device, processing circuit, or external device. The third area 130C-1 can be located in the right-hand area (RIGHT) of the control device 11C-1 on the X-axis.

[0298] exist Figure 15In the Network on-Chip (NoC), the first internal interface region 112C-1, the second internal interface region 131C-1, the first internal input / output line MIO1, and the second internal input / output circuit MIO2 implemented in the network on-chip (NoC) can be implemented in a first form. The first form refers to the form in which the first internal input and output line MIO1 and the second internal input and output line MIO2, implemented in the horizontal direction of the control device 11C-1 along the X-axis, are arranged between the first internal interface region 112C-1 and the second internal interface region 131C-1, wherein the first internal interface region 112C-1 and the second internal interface region 131C-1 are implemented in the vertical direction of the control device 11C-1 along the Y-axis.

[0299] In the first configuration, the first memory controller 121C-11, the first basic interface region 121C-21, and the first basic TSV region 121C-31 can be sequentially arranged from the first edge region TOP, where the first internal input and output lines MIO1 are arranged, along the second direction D2. In the first configuration, the second memory controller 122C-11, the second basic interface region 122C-21, and the second basic TSV region 122C-31 can be sequentially arranged from the second edge region BOTTOM, where the second internal input and output lines MIO2 are arranged, along the first direction D1.

[0300] Figure 16 This is a block diagram illustrating the construction of the control device 11C-1 according to an embodiment of the present disclosure. Figure 16 As shown, the control device 11C-1 may include a first region 110C-1 and a second region 120C-1.

[0301] The first region 110C-1 may include the first physical region (1 st D2D PHY) 111C-1 and the first internal interface area (1 st INT IF) 112C-1.

[0302] The first physical region 111C-1 and the first internal interface region 112C-1 have the same Figure 15 The first physical region 1118-1 and the first internal interface region 112C-1 shown have the same structure, so their detailed description is omitted.

[0303] and Figure 15 The first internal input and output lines MIO1 shown are different. Figure 16 The first internal input and output line MIO1 shown is connected to the first internal interface area 112C-1 and the first memory controller (1). st Between MC) 121C-41, and it can input and output commands CMD and data DATA. (and...) Figure 15The second internal input and output lines MIO2 shown are different. Figure 16 The second internal input and output line MIO2 shown is connected to the first internal interface area 112C-1 and the second memory controller (2). nd The MC) 122C-41 can input and output commands CMD and data DATA. The first internal interface area 112C-1, the first internal input and output line MIO1, and the second internal input and output line MIO2 can be implemented in the on-chip network (NoC).

[0304] The first region 110C-1 can be configured to generate commands (CMD) and data (DATA) and to input and output commands (CMD) and data (DATA). Heat may be generated when the first region 110C-1 inputs and outputs commands (CMD) and data (DATA). The first region 110C-1 can be located in the left-hand region (LEFT) of the control device 11C-1 on the X-axis.

[0305] The second region 120C-1 may include a first memory controller 121C-41 that controls the operation of the memory device 12C-1, and a first basic interface region (1 st DFI) 121C-51, First Basic TSV Area (1 st TSV PHY) 121C-61, Second Memory Controller 122C-41, Second Basic Interface Area (2 nd DFI) 122C-51 and the second basic TSV area (2 nd TSV PHY) 122C-61.

[0306] The first memory controller 121C-41, the first basic interface region 121C-51, the first basic TSV region 121C-61, the second memory controller 122C-41, the second basic interface region 122C-51, and the second basic TSV region 122C-61 have the same characteristics as... Figure 15 The first memory controller 121C-11, the first basic interface region 121C-21, the first basic TSV region 121C-31, the second memory controller 122C-11, the second basic interface region 122C-21, and the second basic TSV region 122C-31 shown have the same structure, therefore their detailed description is omitted.

[0307] The second region 120C-1 can be configured to receive commands (CMD) and data (DATA) from the first region 110C-1 and output them to the memory device 12C-1. The second region 120C-1 can be located in the right-hand region (RIGHT) of the control device 11C-1 on the X-axis.

[0308] Implemented in a network-on-a-chip (NoC) and Figure 16 The first internal interface region 112C-1, the first internal input and output line MIO1, and the second internal input and output line MIO2 shown can be implemented in a second form. The second form refers to a form in which the first internal interface region 112C-1 is provided in the vertical direction of the control device 11C-1 along the Y-axis, and the first internal input and output line MIO1 and the second internal input and output line MIO2 are provided in the horizontal direction of the control device 11C-1 along the X-axis.

[0309] In the second configuration, the first memory controller 121C-41, the first basic interface region 121C-51, and the first basic TSV region 121C-61 can be sequentially arranged from the first edge region TOP, which is provided with the first internal input and output lines MIO1, along the second direction D2. In the second configuration, the second memory controller 122C-41, the second basic interface region 122C-51, and the second basic TSV region 122C-61 can be sequentially arranged from the second edge region BOTTOM, which is provided with the second internal input and output lines MIO2, along the first direction D1.

[0310] Although not shown, in one embodiment, the first region 110C-1 may be located in the right region (RIGHT) of the control device 11C-1 on the X-axis. Therefore, the second region 120C-1, which controls the operation of the memory device 12C-1, is arranged in the left region (LEFT) of the control device on the X-axis. The internal interface region 112C-1, the first internal input and output line MIO1, and the second internal input and output line MIO2 may be connected to implement a network on-chip (NoC).

[0311] Figure 17 This is a block diagram illustrating the construction of a memory device 12C-1 according to an embodiment of the present disclosure.

[0312] The memory device 12C-1 may include a first channel CH1 to an eighth channel CH8, a first core TSV region 210C-1, and a second core TSV region 220C-1.

[0313] Channels CH1 through CH8 can independently receive commands (CMD) and data (DATA) by executing internal operations. After a write operation begins, channels CH1 through CH8 can store data (DATA) based on commands (CMD). After a read operation begins, channels CH1 through CH8 can output data (DATA) based on commands (CMD).

[0314] Channels CH1 through CH4 can be electrically connected to the first core TSV region 210C-1. Channels CH1 through CH4 can receive commands (CMD) and data (DATA) from the first core TSV region 210C-1. Channels CH1 through CH4 can also output data (DATA) to the first core TSV region 210C-1. After an internal write operation begins, channels CH1 through CH4 can store data (DATA) based on commands (CMD). After a internal read operation begins, channels CH1 through CH4 can output data (DATA) based on commands (CMD). Channels CH1 through CH4 can be designated as the first group of channels.

[0315] Channels 5 through 8 (CH8) can be electrically connected to the second core TSV area 220C-1. Channels 5 through 8 (CH8) can receive commands (CMD) and data (DATA) from the second core TSV area 220C-1. Channels 5 through 8 (CH8) can also output data (DATA) to the second core TSV area 220C-1. After an internal write operation begins, channels 5 through 8 (CH8) can store data (DATA) based on commands (CMD). After a internal read operation begins, channels 5 through 8 (CH8) can output data (DATA) based on commands (CMD). Channels 5 through 8 (CH8) can be configured as a second group of channels.

[0316] The first channel CH1 to the fourth channel CH4 can be located in the first edge region TOP of the memory device 12C-1. The fifth channel CH5 to the eighth channel CH8 can be located in the second edge region BOTTOM of the memory device 12C-1.

[0317] The first core TSV region 210C-1 can be electrically connected to the first basic TSV regions 121C-31 and 121C-61 of the control device 11C-1. The first core TSV region 210C-1 can receive commands (CMD) and data (DATA) from the first basic TSV regions 121C-31 and 121C-61. The first core TSV region 210C-1 can receive commands (CMD) and data (DATA) through multiple TSVs. The first core TSV region 210C-1 can output commands (CMD) and data (DATA) to the first channel CH1 to the fourth channel CH4. The first core TSV region 210C-1 can receive data (DATA) from the first channel CH1 to the fourth channel CH4 and output data (DATA) to the first basic TSV regions 121C-31 and 121C-61. The first core TSV region 210C-1 can be located in the center region (CENTER). The first core TSV region 210C-1 can be located from the first edge region (TOP) along the second direction D2. The second direction D2 can be set to the direction from the first edge region TOP to the center region CENTER. The first edge region TOP can be set to the upper region of the memory device 12C-1 on the Y-axis.

[0318] The second core TSV region 220C-1 can be electrically connected to the second basic TSV regions 122C-31 and 122C-61 of the control device 11C-1. The second core TSV region 220C-1 can receive commands (CMD) and data (DATA) from the second basic TSV regions 122C-31 and 122C-61. The second core TSV region 220C-1 can receive commands (CMD) and data (DATA) through multiple TSVs. The second core TSV region 220C-1 can output commands (CMD) and data (DATA) to channels CH5 to CH8. The second core TSV region 220C-1 can receive data (DATA) from channels CH5 to CH8 and output data (DATA) to the second basic TSV regions 122C-31 and 122C-61. The second core TSV region 220C-1 can be located in the center region (CENTER). The second core TSV region 220C-1 can be located from the second edge region (BOTTOM) along the first direction D1. The first direction D1 can be set to the direction from the second edge region BOTTOM to the center region CENTER. The second edge region BOTTOM can be set to the lower region of the memory device 12C-1 on the Y-axis.

[0319] The HBM device 7C according to an embodiment of the present disclosure can prevent the generated heat from spreading to the memory device because the memory device is not stacked on the area where heat is generated due to the input and output of commands (CMD) and data (DATA). The HBM device 7C according to an embodiment of the present disclosure can facilitate heat dissipation because the virtual die set is stacked on the area where heat is generated due to the input and output of commands (CMD) and data (DATA).

[0320] Figure 18 This is a block diagram illustrating the construction of the control device 11C-2 according to an embodiment of the present disclosure. Figure 18 As shown, the control device 11C-2 may include a first region 110C-2, a second region 120C-2, and a third region 130C-2.

[0321] The first region 110C-2 may include the first physical region (1 st D2D PHY) 111C-2 and the first internal interface area (1 st INT IF) 112C-2.

[0322] The first physical region 111C-2 can be processed by the processing circuit ( Figure 9 and Figure 10 The first physical region 111C-2 can generate a command CMD by receiving an external command EC from the PRC CT. The external command EC and command CMD are each shown as a single signal, but may each include multiple bits. The first physical region 111C-2 can generate a command CMD by receiving an external command EC from the processing circuit (…). Figure 9 and Figure 10 The PRC CT in the first physical area 111C-2 receives external data ED to generate data DATA. The first physical area 111C-2 can also receive data DATA from the first internal interface area 112C-2 to generate external data ED. The first physical area 111C-2 can output the external data ED to the processing circuit. Figure 9 and Figure 10 (PRC CT in the text). External data ED and data DATA are each represented as a single signal, but may each include multiple bits.

[0323] The first internal interface area 112C-2 can receive commands CMD and data DATA from the first physical area 111C-2. The first internal interface area 112C-2 can control the memory device (…) by adjusting the input and output order of commands CMD and data DATA. Figure 20The command CMD and data DATA of the operation of the first internal interface area 112C-2 are output to the first internal input and output line MIO1. The first internal interface area 112C-2 can control the memory device ( ) by adjusting the input and output order of the command CMD and data DATA. Figure 20 The commands CMD and data DATA of the operation (112C-2) are output to the second internal input and output line MIO2. The first internal input and output line MIO1 can be located in the central region CENTER of the control device 111C-2. The second internal input and output line MIO2 can be located in the second edge region BOTTOM of the control device 11C-2. The first internal interface region 112C-2, the first internal input and output line MIO1, and the second internal input and output line MIO2 can be implemented in a network-on-chip (NoC).

[0324] The first region 110C-2 can be configured to generate commands (CMD) and data (DATA) and to input and output commands (CMD) and data (DATA). Heat may be generated when the first region 110C-2 inputs and outputs commands (CMD) and data (DATA). The first region 110C-12 can be configured in the left-hand region (LEFT) of the control device 11C-2 on the X-axis.

[0325] The second region 120C-2 may include a control memory device ( Figure 20 The first memory controller (1) operates in 12C-2) st MC) 121C-12, First Basic Interface Area (1 st DFI) 121C-22, First Basic TSV Area (1 st TSVPHY)121C-32, Second Memory Controller (2 nd MC)122C-12, Second Basic Interface Area (2 nd DFI) 122C-22 and the second basic TSV area (2 nd TSV PHY) 122C-32. The first memory controller 121C-12, the first basic interface region 121C-22, and the first basic TSV region 121C-32 can be used to control the memory device ( Figure 20 The first group of channels included in 12C-2) Figure 20 The components for the operation of CH1 to CH4). The second memory controller 122C-12, the second basic interface region 122C-22, and the second basic TSV region 122C-32 can be components for controlling the memory device (CH1 to CH4). Figure 20 The second set of channels included in 12C-2) Figure 20The components for the operation of CH5 to CH8). Each of the first memory controller 121C-12, the first basic interface region 121C-22 and the first basic TSV region 121C-32, and the second memory controller 122C-12, the second basic interface region 122C-22 and the second basic TSV region 122C-32 can be used with Figure 11 The memory controller 121C, the basic interface region 122C, and the basic TSV region 123C shown are used to implement this.

[0326] The first memory controller 121C-12, the first basic interface area 121C-22, the first basic TSV area 121C-32, the second memory controller 122C-12, the second basic interface area 122C-22, and the second basic TSV area 122C-32 can be arranged in the horizontal direction (i.e., the X direction) of the control device 11C-2.

[0327] The first memory controller 121C-12 can be electrically connected to the first internal input and output line MIO1. The first memory controller 121C-12 can receive control signals for the memory device via the first internal input and output line MIO1. Figure 20 The first group of channels included in 12C-2) Figure 20 The first memory controller 121C-12 can output control commands (CMD) and data (DATA) for the operation of memory devices (CH1 to CH4). Figure 20 The first group of channels included in 12C-2) Figure 20 The first memory controller 121C-12 can receive data DATA from the first basic interface area 121C-22 and output data DATA to the first internal input and output line MIO1.

[0328] The first basic interface area 121C-22 can be electrically connected to the first memory controller 121C-12. The first basic interface area 121C-22 can receive commands (CMD) and data (DATA) from the first memory controller 121C-12. The first basic interface area 121C-22 can output commands (CMD) and data (DATA) to the first basic TSV area 121C-32 by adjusting the input and output order of the commands (CMD) and data (DATA). The first basic interface area 121C-22 can receive data (DATA) from the first basic TSV area 121C-32 and output data (DATA) to the first memory controller 121C-12.

[0329] The first basic TSV area 121C-32 can be electrically connected to the first basic interface area 121C-22. The first basic TSV area 121C-32 can receive commands (CMD) and data (DATA) from the first basic interface area 121C-22. The first basic TSV area 121C-32 can output commands (CMD) and data (DATA) to a memory device via multiple TSVs. Figure 20 The first core TSV region (1 in 12C-2) includes st CORE TSV PHY) Figure 20 210C-2). The first basic TSV region 121C-32 can be obtained from the memory device ( Figure 20 The 12C-2 section receives data DATA and outputs data DATA to the first basic interface area 121C-22.

[0330] The first memory controller 121C-12, the first basic interface region 121C-22, and the first basic TSV region 121C-32 can be sequentially arranged from the center region CENTER of the control device 11C-2 along the first direction D1. The first direction D1 can be set from the center region CENTER to the first edge region TOP. The first edge region TOP can be set as the upper region of the control device 11C-2 on the Y-axis.

[0331] The second memory controller 122C-12 can be electrically connected to the second internal input and output line MIO2. The second memory controller 122C-12 can receive control signals for the memory device via the second internal input and output line MIO2. Figure 20 The second set of channels included in 12C-2) Figure 20 The second memory controller 122C-12 can output control commands (CMD and DATA) for the memory device (CH5 to CH8). Figure 20 The second set of channels included in 12C-2) Figure 20 The second memory controller 122C-12 can receive data DATA from the second basic interface area 122C-22 and output data DATA to the second internal input and output line MIO2.

[0332] The second basic interface area 122C-22 can be electrically connected to the second memory controller 122C-12. The second basic interface area 122C-22 can receive commands (CMD) and data (DATA) from the second memory controller 122C-12. The second basic interface area 122C-22 can output commands (CMD) and data (DATA) to the second basic TSV area 122C-32 by adjusting the input and output order of the commands (CMD) and data (DATA). The second basic interface area 122C-22 can receive data (DATA) from the second basic TSV area 122C-32 and output data (DATA) to the second memory controller 121C-22.

[0333] The second basic TSV area 122C-32 can be electrically connected to the second basic interface area 122C-22. The second basic TSV area 122C-32 can receive commands (CMD) and data (DATA) from the second basic interface area 122C-22. The second basic TSV area 122C-32 can output commands (CMD) and data (DATA) to a memory device via multiple TSVs. Figure 20 The second core TSV region (2) included in 12C-2) nd CORE TSV-PHY) Figure 20 220C-2). The second basic TSV region 122C-32 can be obtained from the memory device ( Figure 20 The 12C-2 section receives data DATA and outputs data DATA to the second basic interface area 122C-22.

[0334] The second memory controller 122C-12, the second basic interface region 122C-22, and the second basic TSV region 122C-32 can be sequentially arranged from the second edge region BOTTOM of the control device 11C-2 along the first direction D1. The first direction D1 can be set to the direction from the second edge region BOTTOM to the center region CENTER. The second edge region BOTTOM can be set to the lower region of the control device 11C-2 on the Y-axis.

[0335] The second region 120C-2 can be configured to receive commands CMD and data DATA from the first region 110C-2 and output commands CMD and data DATA to a memory device. Figure 20 (12C-2 in the middle). The second region 120C-2 can be set in the center region CENTER of the control device 11C-2 on the X-axis.

[0336] The third region 130C-2 may include a second internal interface region (2 nd INT IF) 131C-2 and the second physical region (2nd D2D PHY) 132C-2.

[0337] The second internal interface region 131C-2 can receive commands (CMD) and data (DATA) from the first internal input and output line MIO1. The second internal interface region 131C-2 can adjust the input and output order of commands (CMD) and data (DATA) to output the received commands (CMD) and data (DATA) to the second physical region 132C-2. The second internal interface region 131C-2 can also receive commands (CMD) and data (DATA) from the second internal input and output line MIO2. The second internal interface region 131C-2 can adjust the input and output order of commands (CMD) and data (DATA) to output the received commands (CMD) and data (DATA) to the second physical region 132C-2. The second internal interface region 131C-2 can be implemented in a network-on-chip (NoC).

[0338] The second physical area 132C-2 can receive commands CMD and data DATA from the second internal interface area 131C-2. The second physical area 132C-2 can output commands CMD, which are received as transmission commands TC. The second physical area 132C-2 can output data DATA, which is received as transmission data TD. The second physical area 132C-2 can output transmission commands TC and transmission data TD to another HBM device and processing circuit. Figure 9 and Figure 10 PRC CT in (the context of the PRC CT).

[0339] The third area 130C-2 can be configured to receive commands (CMD) and data (DATA) from the second area 120C-2. The third area 130C-2 can be configured to input and output transmission commands (TC) and transmission data (TD) generated from the received commands (CMD) and data (DATA). The third area 130C-2 can be configured to input commands (CMD) and data (DATA) to another HBM device, processing circuit, or external device, and to output commands (CMD) and data (DATA) from another HBM device, processing circuit, or external device. The third area 130C-2 can be located in the right-hand area (RIGHT) of the control device 11C-2 on the X-axis.

[0340] exist Figure 18In the Network-on-Chip (NoC), the first internal interface region 112C-2, the second internal interface region 131C-2, the first internal input / output line MIO1, and the second internal input / output circuit MIO2 implemented in the network-on-chip (NoC) can be implemented in a first form. The first form refers to the form in which the first internal input and output line MIO1 and the second internal input and output line MIO2, implemented along the X-axis in the horizontal direction of the control device 11C-2, are arranged between the first internal interface region 112C-2 and the second internal interface region 131C-2, wherein the first internal interface region 112C-2 and the second internal interface region 131C-2 are implemented along the Y-axis in the vertical direction of the control device 11C-2.

[0341] In the first configuration, the first memory controller 121C-12, the first basic interface region 121C-22, and the first basic TSV region 121C-32 can be sequentially arranged from the central region CENTER, which is provided with the first internal input and output lines MIO1, along the first direction D1. In the first configuration, the second memory controller 122C-12, the second basic interface region 122C-22, and the second basic TSV region 122C-32 can be sequentially arranged from the second edge region BOTTOM, which is provided with the second internal input and output lines MIO2, along the first direction D1.

[0342] Figure 19 This is a block diagram illustrating the construction of the control device 11C-2 according to an embodiment of the present disclosure. Figure 19 As shown, the control device 11C-2 may include a first region 110C-2 and a second region 120C-2.

[0343] The first region 110C-2 may include the first physical region (1 st D2D PHY) 111C-2 and the first internal interface area (1 st INT IF) 112C-2.

[0344] The first physical region 111C-2 and the first internal interface region 112C-2 have the same Figure 18 The first physical region 111C-2 and the second internal interface region 112C-2 shown have the same structure, so their detailed description is omitted.

[0345] and Figure 18 The first internal input and output lines MIO1 shown are different. Figure 19 The first internal input and output line MIO1 shown is connected to the first internal interface area 112C-2 and the first memory controller (1). st Between MC) 121C-42, and it can input and output commands CMD and data DATA. (and) Figure 18The second internal input and output lines MIO2 shown are different. Figure 19 The second internal input and output line MIO2 shown is connected to the first internal interface area 112C-2 and the second memory controller (2). nd The MC) 122C-42 can input and output commands CMD and data DATA. The first internal interface area 112C-2, the first internal input and output line MIO1 and the second internal input and output line MIO2 can be implemented in the on-chip network (NoC).

[0346] The first region 110C-2 can be configured to generate commands (CMD) and data (DATA) and to input and output commands (CMD) and data (DATA). Heat may be generated when the first region 110C-2 inputs and outputs commands (CMD) and data (DATA). The first region 110C-2 can be located in the left-hand region (LEFT) of the control device 11C-2 on the X-axis.

[0347] The second region 120C-2 may include a first memory controller 121C-42 for controlling the operation of the memory device 12C-2, and a first basic interface region (1 st DFI) 121C-52, First Basic TSV Area (1 st TSV PHY) 121C-62, Second Memory Controller 122C-42, Second Basic Interface Area (2 nd DFI) 122C-52 and the second basic TSV area (2 nd TSV PHY) 122C-62.

[0348] The first memory controller 121C-42, the first basic interface region 121C-52, the first basic TSV region 121C-62, the second memory controller 122C-42, the second basic interface region 122C-52, and the second basic TSV region 122C-62 have the same characteristics as... Figure 18 The first memory controller 121C-12, the first basic interface region 121C-22, the first basic TSV region 121C-32, the second memory controller 122C-12, the second basic interface region 122C-22, and the second basic TSV region 122C-32 shown have the same structure, therefore their detailed description is omitted.

[0349] The second region 120C-2 can be configured to receive commands (CMD) and data (DATA) from the first region 110C-2 and output them to the memory device 12C-2. The second region 120C-2 can be located within the right-hand region (RIGHT) of the control device 11C-2 on the X-axis.

[0350] Figure 19 The first internal interface region 112C-2, the first internal input and output line MIO1, and the second internal input and output line MIO2 implemented in the Network on-Chip (NoC) shown can be implemented in a second form. The second form refers to a form in which the first internal interface region 112C-2 is provided in the vertical direction of the control device 11C-2 along the Y-axis, and the first internal input and output line MIO1 and the second internal input and output line MIO2 are provided in the horizontal direction of the control device 11C-2 along the X-axis.

[0351] In the second configuration, the first memory controller 121C-42, the first basic interface region 121C-52, and the first basic TSV region 121C-62 can be sequentially arranged from the central region CENTER, where the first internal input and output lines MIO1 are arranged, along the first direction D1. In the second configuration, the second memory controller 122C-42, the second basic interface region 122C-52, and the second basic TSV region 122C-62 can be sequentially arranged from the second edge region BOTTOM, where the second internal input and output lines MIO2 are arranged, along the first direction D1.

[0352] Although not shown, in one embodiment, the first region 110C-2 may be located in the right region (RIGHT) of the control device 11C-2 along the X-axis. Therefore, the second region 120C-2, which controls the operation of the memory device 12C-2, is located in the left region (LEFT) of the control device along the X-axis. The internal interface region 112C-2, the first internal input and output line MIO1, and the second internal input and output line MIO2 may be connected to implement a network-on-chip (NoC).

[0353] Figure 20 This is a block diagram illustrating the construction of a memory device 12C-2 according to an embodiment of the present disclosure.

[0354] The memory device 12C-2 may include a first channel CH1 to an eighth channel CH8, a first core TSV region 210C-2, and a second core TSV region 220C-2.

[0355] Channels CH1 through CH8 can independently receive commands (CMD) and data (DATA) through internal operations. After a write operation begins, channels CH1 through CH8 can store data (DATA) based on the command (CMD). After a read operation begins, channels CH1 through CH8 can output data (DATA) based on the command (CMD).

[0356] Channels CH1 through CH4 can be electrically connected to the first core TSV region 210C-2. Channels CH1 through CH4 can receive commands (CMD) and data (DATA) from the first core TSV region 210C-2. Channels CH1 through CH4 can also output data (DATA) to the first core TSV region 210C-2. After an internal write operation begins, channels CH1 through CH4 can store data (DATA) based on commands (CMD). After a internal read operation begins, channels CH1 through CH4 can output data (DATA) based on commands (CMD). Channels CH1 through CH4 can be designated as the first group of channels.

[0357] Channels 5 through 8 (CH8) can be electrically connected to the second core TSV area 220C-2. Channels 5 through 8 (CH8) can receive commands (CMD) and data (DATA) from the second core TSV area 220C-2. Channels 5 through 8 (CH8) can also output data (DATA) to the second core TSV area 220C-2. After an internal write operation begins, channels 5 through 8 (CH8) can store data (DATA) based on commands (CMD). After a internal read operation begins, channels 5 through 8 (CH8) can output data (DATA) based on commands (CMD). Channels 5 through 8 (CH8) can be configured as a second group of channels.

[0358] The first channel CH1 to the fourth channel CH4 can be located in the central region CENTER of the memory device 12C-2. The fifth channel CH5 to the eighth channel CH8 can be located in the second edge region BOTTOM of the memory device 12C-2.

[0359] The first core TSV region 210C-2 can be electrically connected to the first basic TSV regions 121C-32 and 121C-62 of the control device 11C-2. The first core TSV region 210C-2 can receive commands (CMD) and data (DATA) from the first basic TSV regions 121C-32 and 121C-62. The first core TSV region 210C-2 can receive commands (CMD) and data (DATA) through multiple TSVs. The first core TSV region 210C-2 can output commands (CMD) and data (DATA) to the first channel CH1 to the fourth channel CH4. The first core TSV region 210C-2 can receive data (DATA) from the first channel CH1 to the fourth channel CH4 and output data (DATA) to the first basic TSV regions 121C-32 and 121C-62. The first core TSV region 210C-2 can be set from the center region (CENTER) along a first direction D1. The first direction D1 can be set from the center region (CENTER) to the first edge region (TOP). The first edge region TOP can be set as the upper region of the memory device 12C-2 on the Y-axis.

[0360] The second core TSV region 220C-2 can be electrically connected to the second basic TSV regions 122C-32 and 122C-62 of the control device 11C-2. The second core TSV region 220C-2 can receive commands (CMD) and data (DATA) from the second basic TSV regions 122C-32 and 122C-62. The second core TSV region 220C-2 can receive commands (CMD) and data (DATA) through multiple TSVs. The second core TSV region 220C-2 can output commands (CMD) and data (DATA) to channels CH5 to CH8. The second core TSV region 220C-2 can receive data (DATA) from channels CH5 to CH8 and output data (DATA) to the second basic TSV regions 122C-32 and 122C-62. The second core TSV region 220C-2 can be located in the center region (CENTER). The second core TSV region 220C-2 can be located from the second edge region (BOTTOM) along the first direction D1. The first direction D1 can be set to the direction from the second edge region BOTTOM to the center region CENTER. The second edge region BOTTOM can be set to the lower region of the memory device 12C-2 on the Y-axis.

[0361] The HBM device 7C according to an embodiment of the present disclosure can prevent the generated heat from spreading to the memory device because the memory device is not stacked on the area where heat is generated due to the input and output of command CMD and data DATA. The HBM device 7C according to an embodiment of the present disclosure can promote heat dissipation because the virtual die set is stacked on the area where heat is generated due to the input and output of command CMD and data DATA.

Claims

1. A semiconductor system, comprising: A control device includes a first region and a second region different from the first region, the control device generating commands and data in the first region in response to external commands and external data, and outputting the commands and data to the second region; and A memory device, vertically stacked on the second region, receives the commands and data from the second region and performs internal operations. The length of the control device is longer than that of the memory device in the first region.

2. The semiconductor system according to claim 1, wherein, The first region is the region where heat is generated when the command and the data are generated.

3. The semiconductor system according to claim 1, wherein the control device comprises: A physical area that generates the commands and data by receiving external commands and external data from an external device located outside the control device; An internal interface area receives the commands and the data, and outputs the commands and the data to internal input and output lines by adjusting the input and output order of the commands and the data; A memory controller that receives the commands and the data via the internal input and output lines, and outputs the commands and the data to control the operation of the memory device; The basic interface area receives the commands and data from the memory controller and outputs the commands and data by adjusting the input and output order of the commands and data; as well as A basic TSV region that receives the commands and data from the basic interface region and outputs the commands and data to the memory device, wherein TSV refers to a through-silicon via.

4. The semiconductor system according to claim 3, wherein: The physical area and the internal interface area are located in the first area, and The internal input and output lines, the memory controller, the basic interface area, and the basic TSV area are located in the second area.

5. The semiconductor system according to claim 4, wherein: The internal input and output lines are located in the central area of ​​the second region of the control device. The memory controller, the basic interface region, and the basic TSV region are arranged sequentially from the central region along a first direction. The first direction is defined as the direction from the center region of the control device to the edge region, and The edge region is located in the direction outward from the center region of the control device.

6. The semiconductor system according to claim 4, wherein: The internal input and output lines are arranged in the edge region of the second area of ​​the control device. The memory controller, the basic interface region, and the basic TSV region are arranged sequentially from the edge region along the second direction. The second direction is defined as the direction from the edge region to the center region of the control device, and The edge region is located in the direction outward from the center region of the control device.

7. The semiconductor system according to claim 1, wherein: The memory device includes multiple channels and a core TSV region, and The core TSV region receives the commands and data from the control device and outputs the commands and data to the multiple channels.

8. The semiconductor system according to claim 7, wherein: The plurality of channels are located in the central region of the memory device. The core TSV region is located from the central region along a first direction. The first direction is defined as the direction from the center region of the memory device to the edge region, and The edge region is located in the direction outward from the center region of the memory device.

9. The semiconductor system according to claim 7, wherein: The plurality of channels are disposed in the edge region of the memory device. The core TSV region is positioned from the edge region along a second direction. The second direction is defined as the direction from the edge region to the center region of the memory device, and The edge region is located in the direction outward from the center region of the memory device.

10. A semiconductor system, comprising: A control device includes a first region and a second region different from the first region, the control device generating commands and data in the first region in response to external commands and external data, and outputting the commands and data to the second region; A first memory device is vertically stacked on the second region and performs internal operations by receiving the commands and data from the second region; as well as A second memory device, vertically stacked on the second region, performs the internal operations by receiving the commands and data from the second region. The first memory device and the second memory device are horizontally disposed on the second region.

11. The semiconductor system of claim 10, wherein, The first memory device and the second memory device are both connected to the control device.

12. The semiconductor system of claim 10, wherein, The first memory device and the second memory device are both connected to the control device, and each inputs and outputs data with substantially the same bandwidth.

13. The semiconductor system of claim 10, wherein: The sum of the lengths of the first memory device and the second memory device is shorter than the length of the second region. The length of the control device is longer than the sum of the lengths of the first memory device and the second memory device by a first region.

14. The semiconductor system of claim 10, wherein, The control device includes: A physical region that generates the commands and data by receiving external commands and external data from an external device located outside the physical region; An internal interface area receives the commands and the data, and outputs the commands and the data to internal input and output lines by adjusting the input and output order of the commands and the data; A first memory controller receives the commands and the data via the internal input and output lines, and outputs the commands and the data to control the operation of the first memory device; The second memory controller receives the commands and the data through the internal input and output lines, and outputs the commands and the data to control the operation of the second memory device; A first basic interface area receives the command and the data from the first memory controller and outputs the command and the data by adjusting the input and output order of the command and the data; The second basic interface area receives the commands and the data from the second memory controller and outputs the commands and the data by adjusting the input and output order of the commands and the data; A first basic TSV region receives the command and the data from the first basic interface region and outputs the command and the data to a first memory device, wherein TSV refers to a through-silicon via; and The second basic TSV region receives the commands and data from the second basic interface region and outputs the commands and data to the second memory device.

15. The semiconductor system of claim 14, wherein: The physical region and the internal interface region are located in the first region. The internal input and output lines, the first memory controller, the second memory controller, the first basic interface area, the second basic interface area, the first basic TSV area, and the second basic TSV area are located in the second area.

16. The semiconductor system of claim 15, wherein: The internal input and output lines are located in the central area of ​​the second region of the control device. The first memory controller, the first basic interface region, and the first basic TSV region are arranged sequentially from the central region along a first direction. The second memory controller, the second basic interface region, and the second basic TSV region are arranged sequentially from the central region along the first direction. The first direction is set as the direction from the center region of the control device to the edge region, and The edge region is located in the direction outward from the center region of the control device.

17. The semiconductor system of claim 15, wherein: The internal input and output lines are located in the edge region of the second area of ​​the control device. The first memory controller, the first basic interface region, and the first basic TSV region are arranged sequentially from the edge region along the second direction. The second memory controller, the second basic interface region, and the second basic TSV region are sequentially arranged from the edge region along the second direction. The second direction is set as the direction from the edge region to the center region of the control device, and The edge region is located in the direction outward from the center region of the control device.

18. The semiconductor system of claim 10, wherein: The first memory device includes multiple channels and a first core TSV region, and The first core TSV region receives the commands and data from the control device and outputs the commands and data to the plurality of channels.

19. The semiconductor system of claim 18, wherein: The plurality of channels are located in the central region of the first memory device. The first core TSV region is positioned from the central region along a first direction. The first direction is set from the center region of the first memory device to the edge region, and The edge region is located in the direction outward from the center region of the first memory device.

20. The semiconductor system of claim 18, wherein: The multiple channels are located in the edge region of the first memory device. The first core TSV region is set from the edge region along the second direction. The second direction is defined as the direction from the edge region to the center region of the first memory device, and The edge region is located in the direction outward from the center region of the first memory device.

21. The semiconductor system of claim 10, wherein: The second memory device includes multiple channels and a second core TSV region, and The second core TSV region receives the commands and data from the control device and outputs the commands and data to the plurality of channels.

22. The semiconductor system of claim 21, wherein: The plurality of channels are disposed in the central region of the second memory device. The second core TSV region is positioned from the central region along the first direction. The first direction is set as a direction from the center region to the edge region of the second memory device, and The edge region is located in the direction outward from the center region of the second memory device.

23. The semiconductor system of claim 11, wherein: The multiple channels are located in the edge region of the second memory device. The second core TSV region is located from the edge region along the second direction. The second direction is configured as a direction from the edge region to the center region of the second memory device, and The edge region is located in the direction outward from the center region of the second memory device.

24. A semiconductor system, comprising: A control device includes a first region and a second region different from the first region, the control device generating commands and data in the first region in response to external commands and external data, and outputting the commands and data to the second region; and A memory device includes a first set of channels and a second set of channels vertically stacked on a second region, and the memory device performs internal operations via the first set of channels and the second set of channels by receiving commands and data from the second region. The length of the control device is longer than that of the memory device by a first region.

25. The semiconductor system of claim 24, wherein, In response to the generation of the command and the data, heat is generated in the first region.

26. The semiconductor system of claim 24, wherein, The control device includes: A physical region that generates the commands and data by receiving external commands and data from an external device located outside the physical region; An internal interface area receives the command and the data, and outputs the command and the data to a first internal input and output line and a second internal input and output line by adjusting the input and output order of the command and the data. A first memory controller receives the commands and the data via the first internal input and output lines, and outputs the commands and the data to control the operation of the memory device; The second memory controller receives the commands and the data via the second internal input and output lines, and outputs the commands and the data to control the operation of the memory device; A first basic interface area receives the command and the data from the first memory controller and outputs the command and the data by adjusting the input and output order of the command and the data; The second basic interface area receives the commands and the data from the second memory controller and outputs the commands and the data by adjusting the input and output order of the commands and the data; A first basic TSV region receives the command and the data from the first basic interface region and outputs the command and data to a first set of channels of the memory device, where TSV refers to a through-silicon via; and The second basic TSV region receives the commands and data from the second basic interface region and outputs the commands and data to the second set of channels of the memory device.

27. The semiconductor system of claim 26, wherein: The physical region and the internal interface region are located in the first region. The first internal input and output line, the second internal input and output line, the first memory controller, the second memory controller, the first basic interface area, the second basic interface area, the first basic TSV area, and the second basic TSV area are disposed in the second area.

28. The semiconductor system of claim 27, wherein: The first internal input / output line and the second internal input / output line are located in the central region of the second area of ​​the control device. The first memory controller, the first basic interface region, and the first basic TSV region are arranged sequentially from the central region along a first direction. The second memory controller, the second basic interface region, and the second basic TSV region are arranged sequentially from the central region along a second direction. Both the first direction and the second direction are set to be from the center region of the control device to the edge region. The edge region is located in the direction outward from the center region of the control device, and The first direction and the second direction are opposite directions.

29. The semiconductor system of claim 27, wherein: The first internal input and output lines are located in the first edge region of the second region of the control device. The second internal input and output lines are located in the second edge region of the second area of ​​the control device. The first memory controller, the first basic interface region, and the first basic TSV region are arranged sequentially from the first edge region along a first direction. The second memory controller, the second basic interface region, and the second basic TSV region are sequentially arranged from the second edge region along the second direction. Both the first edge region and the second edge region are located in the direction outward from the center region of the control device, and The first direction and the second direction are opposite directions.

30. The semiconductor system of claim 27, wherein: The first internal input and output lines are located in the central region of the second area of ​​the control device. The second internal input and output lines are located in the edge region of the second area of ​​the control device. The first memory controller, the first basic interface region, and the first basic TSV region are arranged sequentially from the central region along a first direction. The second memory controller, the second basic interface region, and the second basic TSV region are sequentially arranged from the edge region along the first direction, and The edge region is located in the direction outward from the center region of the control device.

31. The semiconductor system of claim 24, wherein: The memory device includes the first group of channels, the second group of channels, a first core TSV region, and a second core TSV region. The first core TSV region receives the command and the data from the control device, and outputs the command and the data to the first set of channels. The second core TSV region receives the commands and data from the control device and outputs the commands and data to the second set of channels.

32. The semiconductor system according to claim 31, wherein: The first group of channels and the second group of channels are located in the central region of the memory device. The first core TSV region is positioned from the central region along a first direction. The second core TSV region is positioned from the central region along a second direction. Both the first direction and the second direction are set to be from the center region of the memory device to the edge region. The edge region is located in the direction outward from the center region of the memory device, and The first direction and the second direction are opposite directions.

33. The semiconductor system according to claim 31, wherein: The first set of channels is located in the first edge region of the memory device. The second set of channels is disposed in the second edge region of the memory device. The first core TSV region is set from the first edge region along a first direction. The second core TSV region is positioned from the second edge region along the second direction. Both the first direction and the second direction are configured to run from the center region of the memory device to the edge region. Both the first edge region and the second edge region are located in the direction outward from the center region of the memory device, and The first direction and the second direction are opposite directions.

34. The semiconductor system of claim 31, wherein: The first set of channels is located in the central region of the memory device. The second set of channels is located in the edge region of the memory device. The first core TSV region is positioned from the central region along a first direction. The second core TSV region is disposed from the edge region along the first direction, and The edge region is located in the direction outward from the center region of the memory device.

35. A semiconductor system, comprising: A control device includes a first basic TSV region and a second basic TSV region arranged in a horizontal direction. The control device outputs commands and data through the first basic TSV region and outputs the commands and data through the second basic TSV region, wherein TSV refers to through silicon via. A first memory device includes a first core TSV region disposed in a horizontal direction, wherein the first core TSV region receives the command and the data from a first base TSV region, and the first core TSV region outputs the data. as well as A second memory device includes a second core TSV region disposed in a horizontal direction, wherein the second core TSV region receives the command and the data from the second base TSV region, and the second core TSV region outputs the data.

36. The semiconductor system of claim 35, wherein, The first memory device and the second memory device are both connected to the control device to input and output the data.

37. The semiconductor system of claim 35, wherein, The control device includes: A physical region that generates the commands and data by receiving external commands and data from an external device located outside the physical region; An internal interface area receives the commands and the data, and outputs the commands and the data to internal input and output lines by adjusting the input and output order of the commands and the data; A first memory controller receives the commands and the data via the internal input and output lines, and outputs the commands and the data to control the operation of the first memory device; The second memory controller receives the commands and the data through the internal input and output lines, and outputs the commands and the data to control the operation of the second memory device; A first basic interface area receives the command and the data from the first memory controller and outputs the command and the data by adjusting the input and output order of the command and the data; The second basic interface area receives the commands and the data from the second memory controller and outputs the commands and the data by adjusting the input and output order of the commands and the data; The first basic TSV region receives the command and the data from the first basic interface region and outputs the command and the data to the first memory device; and The second basic TSV region receives the command and the data from the second basic interface region and outputs the command and the data to the second memory device.

38. The semiconductor system of claim 35, wherein: The first memory device further includes a first set of channels arranged horizontally, and The first core TSV region receives the command and the data from the control device and outputs the command and the data to the first set of channels.

39. The semiconductor system according to claim 35, wherein: The second memory device further includes a second set of channels arranged horizontally, and The second core TSV region receives the commands and data from the control device and outputs the commands and data to the second set of channels.

40. A semiconductor system, comprising: An HBM device includes a first physical region and a second physical region. The HBM device inputs and outputs first data through the first physical region and inputs and outputs second data through the second physical region. HBM stands for High Bandwidth Memory. A first processing circuit is connected to the first physical region and performs arithmetic operations by receiving the first data; as well as A second processing circuit, connected to the second physical region, performs arithmetic operations by receiving the second data. The first physical region and the second physical region are located at the boundary of the HBM device.

41. The semiconductor system of claim 40, wherein, The HBM device is connected to both the first processing circuit and the second processing circuit.

42. The semiconductor system according to claim 41, wherein, The HBM device includes: A control device comprising a first region to a third region, wherein the first region inputs and outputs the first data, a second region generates the first data and the second data, and the third region inputs and outputs the second data; and A memory device, vertically stacked on the second region, receives commands from the second region and inputs and outputs the first data and the second data.

43. The semiconductor system according to claim 42, wherein, The control device includes: The first physical region generates the command and inputs and outputs the first data; A first internal interface area, which is electrically connected to the first physical area and internal input and output lines, and adjusts the input and output order of the command and the first data; A second internal interface area, electrically connected to the second physical area and the internal input and output lines, and adjusting the input and output order of the second data; and The second physical region is used for inputting and outputting the second data.

44. The semiconductor system of claim 43, wherein: The control device also includes a memory controller, a basic interface region, and a basic TSV region. The first physical region and the first internal interface region are located in the first region. The internal input and output lines, the memory controller, the basic interface area, and the basic TSV area are located in the second area, and The second internal interface area and the second physical area are located in the third area.

45. The semiconductor system of claim 44, wherein: The internal input and output lines are located in the central region of the second area of ​​the control device. The memory controller, the basic interface region, and the basic TSV region are arranged sequentially from the central region along a first direction, and The first direction is set from the central region of the control device to the edge region.

46. ​​The semiconductor system of claim 44, wherein: The internal input and output lines are located in the edge region of the second area of ​​the control device. The memory controller, the basic interface region, and the basic TSV region are arranged sequentially from the edge region along the second direction, and The second direction is set from the edge region of the control device to the center region.

47. The semiconductor system of claim 42, wherein: The memory device includes multiple channels and a core TSV region, and The core TSV region receives the command, the first data, and the second data from the control device, and outputs the command, the first data, and the second data to the plurality of channels, and receives the first data and the second data from the plurality of channels and outputs the first data and the second data to the control device.

48. The semiconductor system of claim 47, wherein: The plurality of channels are located in the central region of the memory device. The core TSV region is positioned from the central region along a first direction, and The first direction is set from the central region of the memory device to the edge region.

49. The semiconductor system of claim 47, wherein: The plurality of channels are disposed in the edge region of the memory device. The core TSV region is positioned from the edge region along a second direction, and The second direction is set from the edge region of the memory device to the center region.

50. A semiconductor system, comprising: A first HBM device includes a first physical region and inputs and outputs first data through the first physical region, wherein HBM refers to high bandwidth memory. A first processing circuit performs arithmetic operations by receiving the first data via the first physical region and by receiving the second data via the second physical region. The second HBM device includes a second physical region and a third physical region, inputs and outputs the second data through the second physical region, and inputs and outputs the third data through the third physical region; The second processing circuit performs arithmetic operations by receiving the third data via the third physical region, and performs the arithmetic operations by receiving the fourth data via the fourth physical region; and The third HBM device includes the fourth physical region and inputs and outputs the fourth data through the fourth physical region. The first physical region is located at the boundary of the first HBM device, the second physical region and the third physical region are located at the boundary of the second HBM device, and the fourth physical region is located at the boundary of the third HBM device.

51. A semiconductor system, comprising: An internal interface, disposed along a first direction, wherein the internal interface receives commands and data, and outputs the commands and data; and Internal input and output lines, arranged along a second direction, are electrically connected to the internal interface. These internal input and output lines receive commands and data from the internal interface and output the commands and data. The first direction is approximately orthogonal to the second direction.

52. The semiconductor system of claim 51, wherein the first direction is a vertical direction and the second direction is a horizontal direction.

53. The semiconductor system of claim 51, further comprising a memory controller disposed along the second direction, electrically connected to the internal input and output lines, and controlling the memory device by receiving the commands and the data from the internal output and input lines.

54. The semiconductor system according to claim 53, wherein, The memory controller is arranged along the first direction from the internal input and output lines that are arranged along the second direction.

55. The semiconductor system of claim 53, further comprising: A basic interface area, which is arranged along the second direction, is electrically connected to the memory controller and receives and outputs the commands and the data; and A basic TSV region, disposed along the second direction, is electrically connected to the basic interface region, the basic TSV region receiving the command and the data, and outputting the command and the data to the memory device.

56. The semiconductor system of claim 55, wherein, The memory controller, the basic interface region, and the basic TSV region are arranged sequentially from the internal input and output lines along the first direction.

57. The semiconductor system of claim 55, wherein, The memory device includes a core TSV region disposed along the second direction, electrically connected to the base TSV region, receiving the commands and the data, and outputting the commands and the data to multiple channels.

58. A semiconductor system, comprising: An internal interface, which is set along a first direction, receives and outputs a first command and a second command, as well as first data and second data; A first internal input and output line, which is arranged along a second direction, is electrically connected to the internal interface, receives the first command and the first data from the internal interface, and outputs the first command and the first data; as well as A second internal input and output line, arranged along the second direction, is electrically connected to the internal interface, receives the second command and the second data from the internal interface, and outputs the second command and the second data. The first direction is approximately orthogonal to the second direction.

59. The semiconductor system of claim 58, wherein the first direction is a vertical direction and the second direction is a horizontal direction.

60. The semiconductor system of claim 58, further comprising: A first memory controller is disposed along the second direction, electrically connected to the first internal input and output lines, receives the first command and the first data from the first internal input and output lines, and outputs the first command and the first data. A first basic interface area is disposed along the second direction, electrically connected to the first memory controller, and receives and outputs the first command and the first data; as well as A first basic TSV region is disposed along the second direction, electrically connected to the first basic interface region, receiving the first command and the first data, and outputting the first command and the first data to the first memory device.

61. The semiconductor system of claim 60, wherein, The first memory controller, the first basic interface region, and the first basic TSV region are arranged sequentially from the first internal input and output lines along the first direction.

62. The semiconductor system of claim 60, wherein, The first memory device includes: A first core TSV region, disposed along the second direction, is electrically connected to the first base TSV region, receives the first command and the first data from the first base TSV region, and outputs the first command and the first data; and The first set of channels is electrically connected to the first core TSV region and operates by receiving the first command and the first data from the first core TSV region.

63. The semiconductor system of claim 58, further comprising: A second memory controller is disposed along the second direction, electrically connected to the second internal input and output lines, receives the second command and the second data from the second internal output and input lines, and outputs the second command and the second data. The second basic interface area is disposed along the second direction, electrically connected to the second memory controller, and receives and outputs the second command and the second data; as well as The second basic TSV region is disposed along the second direction, electrically connected to the second basic interface region, receives the second command and the second data, and outputs the second command and the second data to the second memory device.

64. The semiconductor system of claim 63, wherein, The second memory controller, the second basic interface area, and the second basic TSV area are arranged sequentially from the second internal input and output lines along the first direction.

65. The semiconductor system of claim 63, wherein, The second memory device includes: A second core TSV region, disposed along the second direction, is electrically connected to the second base TSV region, receives the second command and the second data from the second base TSV region, and outputs the second command and the second data; and The second set of channels is electrically connected to the second core TSV area and operates by receiving the second command and the second data from the second core TSV area.

66. A semiconductor system, comprising: A first internal interface is provided along a first direction and receives and outputs a first command and a second command, as well as first data and second data. A first internal input and output line is arranged along a second direction and electrically connected to the first internal interface to receive the first command and the first data from the first internal interface and to output the first command and the first data. The second internal input and output line is arranged along the second direction and electrically connected to the first internal interface. It receives the second command and the second data from the first internal interface and outputs the second command and the second data. as well as The second internal interface, which is arranged along the first direction, generates a transmission command by receiving the second command, generates transmission data by receiving the second data, and outputs the transmission command and the transmission data to the outside of the semiconductor system.

67. The semiconductor system of claim 66, wherein the first direction is a vertical direction and the second direction is a horizontal direction.

68. The semiconductor system of claim 66, further comprising: A memory controller, disposed along the second direction, is electrically connected to the first internal input and output lines, receives the first command and the first data from the first internal input and output lines, and outputs the first command and the first data; A basic interface area, which is disposed along the second direction, is electrically connected to the memory controller and receives and outputs the first command and the first data; as well as A basic TSV region, which is disposed along the second direction, is electrically connected to the basic interface region, receives the first command and the first data, and outputs the first command and the first data to a memory device.

69. The semiconductor system of claim 68, wherein, The memory controller, the basic interface region, and the basic TSV region are arranged sequentially from the first internal input and output lines along the first direction.

70. The semiconductor system of claim 68, wherein, The memory device includes: A core TSV region, disposed along the second direction, is electrically connected to the base TSV region, receives the first command and the first data from the base TSV region, and outputs the first command and the first data; and Multiple channels are electrically connected to the core TSV region and operate by receiving the first command and the first data from the core TSV region.

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