Non-volatile memory, storage device including the same, and method thereof

Abstract

Non-volatile memories, storage devices including the same, and methods thereof are provided. The storage device includes a plurality of non-volatile memories and a storage controller connected to the plurality of non-volatile memories through a data line. The plurality of non-volatile memories are connected to each other through an internal clock line separate from the data line and an internal data line synchronized with the internal clock line. Each of the plurality of non-volatile memories transmits an internal data signal including peak current prediction time information through the internal data line.

Description

Technical Field

[0001] The embodiments of this disclosure described herein relate to non-volatile memories capable of performing inter-memory communication, storage devices including such memories, and methods thereof. Background Technology

[0002] Semiconductor memory devices can be broadly categorized into volatile memory and non-volatile memory. Volatile memory (e.g., DRAM or SRAM) offers fast read and write speeds, but the data stored in it is lost when the power is turned off. Conversely, non-volatile memory retains its data even when the power is off. A representative example of non-volatile memory is flash memory.

[0003] Non-volatile memory can perform various memory access operations (e.g., programming, reading, and erasing). The power required for each memory access operation may differ. For example, memory access operations require more power than sequential programming operations, thus generating peak current. Because events that simultaneously generate peak current can be fatal to the operation of memory devices, it may be necessary to predict and manage peak current. Summary of the Invention

[0004] Embodiments of this disclosure provide a nonvolatile memory capable of performing inter-memory communication to share prediction timing information of peak current, a storage device including the same, and a method thereof.

[0005] According to an embodiment, a storage device includes: a plurality of non-volatile memories and a storage controller, the storage controller being connected to the plurality of non-volatile memories via data lines. The plurality of non-volatile memories are interconnected via an internal clock line separate from the data lines and an internal data line synchronized with the internal clock lines, and each of the plurality of non-volatile memories transmits an internal data signal including prediction timing information of peak current via the internal data lines.

[0006] According to an embodiment, a method for using a non-volatile memory includes: obtaining an internal data signal that includes prediction timing information of the peak current of the non-volatile memory; and transmitting the internal data signal via an internal data line synchronized with an internal clock line.

[0007] According to an embodiment, a non-volatile memory includes: a memory cell array; an input / output circuit connected to a data line for transmitting write or read data associated with the memory cell array, an internal clock line separate from the data line, and an internal data line synchronized with the internal clock line; and a control logic circuit that, based on control of the input / output circuit, transmits an internal data signal including prediction timing information of peak current through the internal data line. Attached Figure Description

[0008] The above and other objects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0009] Figure 1 This is a block diagram of a storage device according to some example embodiments.

[0010] Figure 2 Based on some example embodiments Figure 1 Block diagram of the storage controller.

[0011] Figure 3 Based on some example embodiments Figure 1 Example block diagram of non-volatile memory.

[0012] Figure 4 This illustrates some example embodiments. Figure 3 A circuit diagram of an example of a memory block in a memory cell array.

[0013] Figure 5 Several non-volatile memories according to some example embodiments are shown.

[0014] Figure 6 and Figure 7 Internal data signals are shown according to some example embodiments.

[0015] Figure 8 This is a timing diagram of inter-memory communication based on some example embodiments.

[0016] Figure 9 It is a timing diagram of inter-memory communication and buffered data when the predicted timing information of different non-volatile memories overlaps with each other, according to some example embodiments.

[0017] Figure 10 This is a timing diagram of inter-memory communication and buffered data when the header changes, based on some example embodiments.

[0018] Figure 11 It is a timing diagram of inter-memory communication and buffered data when a predicted time change occurs, based on some example embodiments.

[0019] Figure 12 This is a timing diagram of peak current information sharing operations and programming operations of a storage device according to some example embodiments.

[0020] Figure 13 It is a timing diagram of the internal clock signal and internal data signal according to some example embodiments.

[0021] Figure 14 This is a flowchart of an operation method for a non-volatile memory according to some example embodiments.

[0022] Figure 15 This is a flowchart of an operational method based on predicted time information, according to some example embodiments.

[0023] Figure 16 This is a flowchart of an internal data signal transmission method according to some example embodiments.

[0024] Figure 17 This is a flowchart of an internal data signal transmission method according to some example embodiments. Detailed Implementation

[0025] The embodiments of this disclosure will now be described in detail and clearly to enable those skilled in the art to readily implement this disclosure.

[0026] Figure 1 This is a block diagram of a storage device according to some example embodiments.

[0027] refer to Figure 1 According to some example embodiments, the storage device 1000 may include a storage controller 1100 and a plurality of non-volatile memories 1200a to 1200k.

[0028] The storage controller 1100 can be configured to control multiple non-volatile memories 1200a to 1200k under the control of a host or according to commands from the host. For example, upon request from the host, the storage controller 1100 can write data to or read data stored in the multiple non-volatile memories 1200a to 1200k. The storage controller 1100 can be connected to the multiple non-volatile memories 1200a to 1200k via a data line DQ. Through the data line DQ, the storage controller 1100 can transmit commands CMD and addresses ADDR to the multiple non-volatile memories 1200a to 1200k, or exchange data DAT (e.g., program data or read data) with the multiple non-volatile memories 1200a to 1200k.

[0029] Multiple non-volatile memories 1200a to 1200k can be connected to the memory controller 1100 via data line DQ. Under the control of the memory controller 1100, the multiple non-volatile memories 1200a to 1200k can store data or transfer stored data to the memory controller 1100. For example, the multiple non-volatile memories 1200a to 1200k can be implemented using NAND flash memory devices, but the embodiments of this disclosure are not limited thereto. The multiple non-volatile memories 1200a to 1200k may include k non-volatile memories (k is a natural number), and each non-volatile memory 1200a to 1200k can be implemented using a chip or a die.

[0030] In some example embodiments, multiple non-volatile memories 1200a to 1200k can be interconnected via an internal clock line ICLKL separate from the data line DQ and an internal data line IDATL synchronized with the internal clock line ICLKL. In this disclosure, the operation of multiple non-volatile memories 1200a to 1200k exchanging or sharing signals, information, and data via the internal data line IDATL can be referred to as "inter-memory communication." Inter-memory communication can be performed independently of the memory controller 1100. According to some example embodiments, the memory controller 1100 can manage policies, requirements, settings, etc., associated with inter-memory communication.

[0031] An internal clock line ICLKL can be configured to provide an internal clock signal ICLK for synchronizing the internal data line IDATL during inter-memory communication. According to some example embodiments, one of a plurality of non-volatile memories 1200a to 1200k can be configured to generate the internal clock signal ICLK. According to some example embodiments, one of the plurality of non-volatile memories 1200a to 1200k, defined or set as the primary non-volatile memory, can be configured to generate the internal clock signal ICLK. In this disclosure, the primary non-volatile memory can be defined as a non-volatile memory that manages policies, requirements, settings, etc., associated with inter-memory communication. The non-volatile memory that generates the internal clock signal ICLK can transmit the internal clock signal ICLK via the internal clock line ICLKL.

[0032] The internal data signal IDATS, transmitted / received via the internal data line IDATL, can include information generated or processed from each non-volatile memory. The internal data line IDATL can be implemented independently of the data line DQ connected to the aforementioned memory controller 1100 for inter-memory communication. The internal data signal IDATS is synchronized with the internal clock signal ICLK.

[0033] In some example embodiments, each of the plurality of non-volatile memories 1200a to 1200k may include a peak current manager. That is, the plurality of non-volatile memories 1200a to 1200k may include a plurality of peak current managers PCM1 to PCMk.

[0034] Multiple peak current managers PCM1 to PCMk can be configured to calculate (or predict) peak current quantities by considering one or more of the following: 1) independent processing tasks (or threads) for performing various memory access operations (e.g., read operations, programming operations, and erase operations) required by the memory controller 1100, and 2) the current quantities used by multiple non-volatile memories 1200a to 1200k, etc. In some example embodiments, the multiple peak current managers PCM1 to PCMk can be configured to calculate (or predict) the occurrence prediction time of the peak current by considering the processing tasks, current quantities, etc., as described above. Hereinafter, for ease of description, information about the peak current, including the peak current quantity and the occurrence prediction time, may be referred to as "peak current information".

[0035] Multiple peak current managers PCM1 to PCMk can generate an internal data signal IDATS (or internal data packet) that includes prediction timing information of the peak current or information about the peak current quantity obtained through calculation (or prediction). In this document, the prediction timing information can indicate the predicted time of the peak current occurrence, or it can indicate the number of remaining cycles from the transmission time of the internal data signal IDATS to the internal clock ICLK of the predicted occurrence time, i.e., the number of remaining cycles or the remaining time.

[0036] The internal data signal IDATS can be a digital signal obtained by encoding prediction time information or current quantity information.

[0037] In some example embodiments, the internal data signal IDATS may include a header and a body following the header. The header may indicate whether the body includes any information. For example, when the header indicates a first logic level (e.g., logic high or logic low), the body may include prediction timing information. For example, when the header indicates a second logic level (e.g., logic low or logic high), the body may include current quantity information. Therefore, multiple peak current managers PCM1 to PCMk may include peak current-related information in the internal data signal IDATS, the type of which varies depending on the logic level setting of the header.

[0038] Alternatively, in some example embodiments, the internal data signal IDATS may consist only of the body excluding the header.

[0039] Multiple non-volatile memories 1200a to 1200k can transmit internal data signals IDATS generated by multiple peak current managers PCM1 to PCMk via the internal data line IDATL.

[0040] Multiple peak current managers PCM1 to PCMk can be controlled based on the internal data signal IDATS to schedule operations for multiple non-volatile memories 1200a to 1200k. Specifically, each peak current manager can receive peak current information from the other non-volatile memories via the internal data line IDATL. In addition to the peak current information obtained from the respective non-volatile memories, each peak current manager can collectively manage the peak current information included in the internal data signal IDATS received from the other non-volatile memories.

[0041] In some example embodiments, each peak current manager may stop operations scheduled for each non-volatile memory when the peak current indicated by the current quantity information is greater than or equal to a threshold.

[0042] In some example embodiments, each peak current manager can sum the peak current amount indicated by the peak current information it manages. When the summation value is greater than or equal to a threshold, each peak current manager can stop operations scheduled for each non-volatile memory.

[0043] In some example embodiments, at the predicted occurrence time of the peak current, indicated by the prediction time information, each peak current manager can stop operations scheduled for each non-volatile memory. That is, when the occurrence of a peak current is predicted from the remaining non-volatile memories, each peak current manager can pre-check the predicted occurrence time of the peak current for the remaining non-volatile memories via the received internal data signal IDATS. At the checked predicted occurrence time (or before the predicted occurrence time), each peak current manager can stop operations already scheduled for the non-volatile memories, thereby preventing excessive power consumption.

[0044] By using an internal data line IDATL for non-volatile memory, implemented independently of the data line DQ connected to the memory controller 1100, the memory device 1000 according to the above embodiment is able to share the peak current occurrence prediction time without being limited by the memory device 1000 protocol. Furthermore, each non-volatile memory is able to anticipate the peak current before it occurs.

[0045] Figure 2 Based on some example embodiments Figure 1 Block diagram of the storage controller.

[0046] refer to Figure 2According to some example embodiments, the storage controller 1100 may include a central processing unit (CPU) 1110, an internal communication manager 1120, a working memory 1130, a host interface 1140, and a memory interface 1150.

[0047] CPU 1110 can drive firmware executable in storage controller 1100. For example, CPU 1110 can drive various firmware or software loaded into working memory 1130. Alternatively, CPU 1110 can execute firmware or software responsible for the functions of the storage device, such as host interface layer (HIL) or flash interface layer (FIL).

[0048] In some example embodiments, when the internal communication manager 1120 is provided as a software module, the CPU 1110 can execute the software module corresponding to the internal communication manager 1120, and in addition to executing operations related to management policies, requirements, settings, etc. associated with inter-memory communication, it can also execute operations of the memory controller 1100 of this disclosure.

[0049] In some example embodiments, CPU 1110 may include multiple cores. Each of the multiple cores may be implemented using a separate processor core. The multiple cores may include host cores, flash translation layer (FTL) cores, and NAND cores.

[0050] The host core can be defined as a storage device (e.g., Figure 1 The host core (1000) is an internal core that performs HIL-related operations. For example, the host core can handle requests received from the host through the host interface 1140.

[0051] An FTL core can be defined as an internal core of a storage device that performs operations related to the FTL. For example, an FTL core can control a NAND core based on requests received from the host core, enabling operations in non-volatile memory (e.g., ...). Figure 1 Read, write, or erase operations are performed in (1200a to 1200k). Alternatively, by using FTL, the FTL core can perform address mapping operations, such that the logical block address (LBA) transferred from the host is mapped to the physical block address (PBA) corresponding to the physical location in the non-volatile memory.

[0052] A NAND core can be defined as the internal core of a storage device that performs operations related to the FTL (Fulfilled Memory Layer). For example, under the control of the FTL core, the NAND core can control the memory interface 1150 to perform non-volatile memory operations.

[0053] The internal communication manager 1120 can be configured to manage policies, requirements, settings, etc., associated with inter-memory communication. In some example embodiments, the internal communication manager 1120 can configure the primary non-volatile memory for inter-memory communication. Instead of the memory controller 1100, the primary non-volatile memory configured through the internal communication manager 1120 can manage policies, requirements, settings, etc., associated with inter-memory communication, or can generate and transmit internal clock signals.

[0054] In some example embodiments, the internal communication manager 1120 can manage the allocated time intervals for transmitting internal data signals separately for each non-volatile memory. For example, the internal communication manager 1120 can set the size (or length) of the time interval (e.g., the number of cycles of the internal clock signal allocated to each non-volatile memory), can allocate specific non-volatile memories for each time interval, or can set the order in which the time intervals will be allocated to the non-volatile memories.

[0055] According to some example embodiments, the internal communication manager 1120 may be omitted. In this case, the storage controller 1100 may not participate in inter-memory communication, and the operation of the internal communication manager 1120 according to the above embodiments may be performed solely through the main non-volatile memory or through multiple non-volatile memories.

[0056] Data or software (or firmware) used to control the storage controller 1100 is loaded into the working memory 1130. The software or data loaded into the working memory 1130 is driven or processed by the CPU 1110. The flash translation layer driven by the CPU 1110 performs functions such as address management, garbage collection, and wear leveling.

[0057] Host interface 1140 provides an interface between the host and storage controller 1100. The host and storage controller 1100 can be connected via one of a variety of standardized interfaces. In this document, standardized interfaces include various interfaces such as Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, External SATA (e-SATA) interface, Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI) interface, PCI Express (PCI-E) interface, Universal Serial Bus (USB) interface, IEEE 1394 interface, Universal Flash Memory (UFS) interface, and card interface.

[0058] The memory interface 1150 provides an interface between the memory controller 1100 and the non-volatile memory. For example, data processed by the CPU 1110 can be stored in the non-volatile memory through the memory interface 1150, or data read from the non-volatile memory can be transferred to the memory controller 1100 through the memory interface 1150.

[0059] In some example embodiments, in addition to the components described above, the storage controller 1100 may also include a read-only memory (ROM) or error-correcting code (ECC) block for storing code data required for boot operations.

[0060] Figure 3 Based on some example embodiments Figure 1 Example block diagram of non-volatile memory.

[0061] refer to Figure 3 According to some example embodiments, the non-volatile memory 1200 may include a memory cell array 1210, a row decoder 1220, a page buffer circuit 1230, a control logic circuit 1240, a voltage generation circuit 1250, a register 1260, and an input / output circuit 1270. Furthermore, although... Figure 3 As not shown, the non-volatile memory 1200 may further include components such as column logic, a pre-decoder, a temperature sensor, a command decoder, and an address decoder. Furthermore, the non-volatile memory 1200 may be... Figure 1 One of the multiple non-volatile memories 1200a to 1200k shown.

[0062] The storage cell array 1210 may include multiple storage blocks BLK0 to BLKm-1 (where m is a positive integer). Each storage block BLK0 to BLKm-1 may include multiple storage cells. Each storage block BLK0 to BLKm-1 may consist of multiple pages. Each page may consist of multiple storage cells. Each storage block may correspond to an erase unit, and each page may correspond to a read or program unit. The multiple storage blocks BLK0 to BLKm-1 may be included in a single storage plane, but embodiments of this disclosure are not limited thereto. The storage cell array 1210 may be connected to the page buffer circuit 1230 via bit lines BL and to the line decoder 1220 via word lines WL, serial select lines SSL, and ground select lines GSL.

[0063] In some example embodiments, the memory cell array 1210 may include a 3D memory cell array. The 3D memory cell array may be implemented using multiple levels and may include word lines or bit lines shared between levels.

[0064] The row decoder 1220 can select one of the memory blocks BLK0 to BLKm-1 of the memory cell array 1210 in response to the row address RADDR. The row decoder 1220 can also select a word line of the selected memory block in response to the row address RADDR. The row decoder 1220 transmits a voltage VWL corresponding to the operating mode to the selected word line of the selected memory block. In programming operations, the row decoder 1220 transmits a programming voltage and a verification voltage to the selected word line, and a pass voltage to the unselected word line. In reading operations, the row decoder 1220 transmits a read voltage to the selected word line, and a read pass voltage to the unselected word line.

[0065] Page buffer circuit 1230 may include multiple page buffers. The multiple page buffers can be connected to memory cells via bit lines BL. Page buffer circuit 1230 can select at least one bit line BL in response to a column address CADDR provided from control logic circuit 1240. Page buffer circuit 1230 can operate as a write driver or a sense amplifier depending on the operating mode. For example, in a programming operation, page buffer circuit 1230 can apply a bit line voltage corresponding to the data to be programmed to the selected bit line. In a read operation, page buffer circuit 1230 can read data stored in the memory cell by sensing the current or voltage of the selected bit line.

[0066] The control logic circuit 1240 can control various operations of the non-volatile memory 1200. In response to the command CMD and / or address ADDR, the control logic circuit 1240 can output various control signals for programming data in the memory cell array 1210, reading data from the memory cell array 1210, or erasing data stored in the memory cell array 1210. For example, the control logic circuit 1240 can output voltage control signal VTG_C, row address RADDR, column address CADDR, etc.

[0067] The control logic circuit 1240 may include independent processing tasks (or threads) for performing various memory access operations (e.g., read operations, program operations, and erase operations). Processing tasks may be defined based on various memory cells (e.g., die, block, plane, and page). Because the power consumption of processing tasks may be the same or different, it may be necessary to manage the power of multiple non-volatile memories 1200 in individual or multiple ways. For example, in the case of sequential programming operations, the probability of generating large peak currents is higher due to the frequent use of multiple memory cells by the task.

[0068] In some example embodiments, the control logic circuitry 1240 may include a peak current manager (PCM). The peak current manager (PCM) may perform reference... Figure 1The operations described above. In some example embodiments, the peak current manager (PCM) can obtain prediction timing information and / or current quantity information of the peak current, and can generate an internal data signal IDATS including the prediction timing information or current quantity information. The peak current manager (PCM) can generate peak current information (PCI) including prediction timing information and / or current quantity information, and can buffer or store the generated peak current information (PCI) in register 1260. Alternatively, the peak current manager (PCM) can program the peak current information (PCI) into the memory cell array 1210.

[0069] In some example embodiments, the peak current manager (PCM) may include a prediction time counter configured to calculate the prediction time indicated by the prediction time information of the peak current.

[0070] In some example embodiments, the control logic circuit 1240 may buffer the peak current information PCI in register 1260 at least one cycle before the time interval allocated for transmitting the peak current information PCI.

[0071] In some example embodiments, when the buffered prediction timing information changes, the peak current manager PCM can buffer the changed prediction timing information in register 1260.

[0072] Alternatively, the peak current manager (PCM) can generate an internal data signal (IDATS) that includes peak current information (PCI), and can provide the generated internal data signal (IDATS) to the input / output circuitry 1270. In some example embodiments, the peak current manager (PCM) can provide the internal data signal (IDATS) to the input / output circuitry 1270 in each time interval allocated to the non-volatile memory 1200. Therefore, the input / output circuitry 1270 can send the internal data signal (IDATS) to the remaining non-volatile memory in each allocated time interval.

[0073] In some example embodiments, the peak current manager (PCM) can control the operations scheduled for the non-volatile memory 1200 based on the internal data signal IDATS received from the remaining non-volatile memory. For example, when the scheduled operation is a programming operation and the current quantity information indicated by the internal data signal IDATS is greater than or equal to a threshold, the peak current manager (PCM) can stop generating or providing the voltage control signal VTG_C corresponding to the programming voltage, or it can stop generating or providing the row address RADDR and / or column address CADDR.

[0074] Alternatively, when the scheduled operation is a programmed operation and the prediction time information indicated by the internal data signal IDATS indicates that the prediction time has arrived or is about to arrive, the peak current manager PCM may stop generating or providing the voltage control signal VTG_C corresponding to the programmed voltage, or may stop generating or providing the row address RADDR and / or column address CADDR.

[0075] In some example embodiments, based on the control of the input / output circuit 1270, the control logic circuit 1240 can receive the internal data signal IDATS from the remaining non-volatile memory via the internal data line IDATL, or can send the generated internal data signal IDATS to the remaining non-volatile memory via the internal data line IDATL.

[0076] The voltage generation circuit 1250 can generate various voltages for performing programming, reading, and erasing operations based on the voltage control signal VTG_C. For example, the voltage generation circuit 1250 can generate programming voltage, reading voltage, and programming verification voltage as word line voltages VWL. For example, the programming voltage can be generated using incremental step pulse programming (ISPP).

[0077] Register 1260 may store peak current information PCI generated or obtained according to the above embodiments. In this case, the peak current information PCI may be associated with non-volatile memory 1200, or with other non-volatile memory. Alternatively, when encoding prediction timing information, register 1260 may store the occurrence prediction time or remaining cycle number mapped to the encoded bit. Alternatively, when encoding current quantity information, register 1260 may store the current quantity mapped to the encoded bit. For example, register 1260 may store a mapping table that defines the mapping relationship between encoded bits and occurrence prediction time, remaining cycle number, or current quantity.

[0078] The input / output circuit 1270 can be configured to receive commands (CMD), addresses (ADDR), data, etc., from the memory controller. The commands (CMD) and addresses (ADDR) received through the input / output circuit 1270 can be provided to the control logic circuit 1240.

[0079] In some example embodiments, the input / output circuit 1270 may be connected to an internal data line IDATL and an internal clock line ICLKL, which are separate from the data line DQ. The input / output circuit 1270 can receive an internal clock signal via the internal clock line ICLKL and can transmit or receive an internal data signal IDATS synchronously with the internal clock signal via the internal data line IDATL. The input / output circuit 1270 may receive the internal data signal IDATS from the control logic circuit 1240, or it may transmit the internal data signal IDATS received from the remaining non-volatile memory to the control logic circuit 1240.

[0080] Furthermore, the input / output circuit 1270 can be connected to the data line DQ, and the input / output circuit 1270 can receive write data to be written to the memory cell array 1210 via the data line DQ, or can transmit read data read from the memory cell array 1210 via the data line DQ. For example, the input / output circuit 1270 can transmit program data received via the data line DQ to the page buffer circuit 1230, or can send data read via the page buffer circuit 1230 to an external source (e.g., a memory controller).

[0081] According to the above embodiment, the non-volatile memory 1200 can share prediction timing information with the remaining non-volatile memory through the internal data line IDATL.

[0082] Figure 4 This illustrates some example embodiments. Figure 3 The circuit diagram shows an example of a memory block in a memory cell array. For ease of description, it is assumed that a memory block contains four strings STR1 to STR4.

[0083] refer to Figure 4 The storage block BLKa may include multiple strings STR1 to STR4 vertically stacked on a substrate. The multiple strings STR1 to STR4 may be arranged in a first direction (i.e., the X-axis direction) and a second direction (i.e., the Y-axis direction).

[0084] Strings in the same column from STR1 to STR4 can be connected to the same bit line. For example, the first string STR1 and the second string STR2 can be connected to the first bit line BL1, and the third string STR3 and the fourth string STR4 can be connected to the second bit line BL2.

[0085] Each of the multiple strings STR1 to STR4 may include multiple unit transistors. Each unit transistor may include a charge-trap flash memory (CTF) storage cell, but embodiments of this disclosure are not limited thereto. The multiple unit transistors may be stacked in a third-party upward (i.e., Z-axis direction).

[0086] Multiple strings STR1 through STR4 can be connected together to a common source line CSL. For example, as shown below. Figure 4 As shown, the common source line CSL can be connected to the lower ends of multiple strings STR1 to STR4. However, this is provided only as an example. It is sufficient that the common source line CSL is electrically connected to the lower ends of strings STR1 to STR4, and this disclosure is not limited to the case where the common source line CSL is physically located at the lower ends of strings STR1 to STR4. For ease of description, the structure and configuration of the strings will be described below based on the first string STR1. The remaining strings STR2, STR3, and STR4 can be structurally similar to the first string STR1, and therefore, additional descriptions will be omitted to avoid redundancy.

[0087] Multiple unit transistors can be connected in series between the first bit line BL1 and the common source line CSL. For example, multiple unit transistors may include GIDL transistors GDT1 and GDT2, a string select transistor SST, memory cells MC1 to MC5, a pseudo memory cell DMC, and a ground select transistor GST.

[0088] The first GIDL transistor GDT1 can be located at the bottom end of the string STR1. For example, the first GIDL transistor GDT1 can be connected to the common source line CSL at the bottom end of the string STR1. However, this is provided as an example, and embodiments of this disclosure are not limited thereto. The gate of the first GIDL transistor GDT1 can be connected to the first GIDL line GIDL1a.

[0089] The second GIDL transistor GDT2 can be positioned at the upper end of the string STR1, specifically between the string select transistor SST and the memory cell MC5. That is, the second GIDL transistor GDT2 can be connected to the first bit line BL1 via the string select transistor SST. The gate of the first GIDL transistor GDT1 can be connected to the first GIDL line GIDL1a.

[0090] GIDL transistors GDT1 and GDT2 in Figure 4 The GIDL transistor is shown to be located at both the lower and upper ends of string STR1. However, this is provided only as an example. According to embodiments, the GIDL transistor may be located only at the upper end of string STR1, or the GIDL transistor may be located only at the lower end of string STR1.

[0091] The string select transistor SST can be positioned at the top of the string STR. The string select transistor SST can be connected to the first line BL1 at the top of the string STR1. The gate of the string select transistor SST can be connected to the string select line SSLa. However, this is provided only as an example. According to an embodiment, a plurality of string select transistors connected in series can be positioned between the first line BL1 and the second GIDL transistor GDT2.

[0092] A ground select transistor GST can be disposed between the dummy memory cell DMC and the first GIDL transistor GDT1. The gate of the ground select transistor GST can be connected to the ground select line GSLa. However, this is provided only as an example. According to an embodiment, a plurality of ground select transistors connected in series can be disposed between the dummy memory cell DMC and the first GIDL transistor GDT1.

[0093] The first memory cell MC1 to the fifth memory cell MC5 can be connected in series between the string select transistor SST and the pseudo memory cell DMC. The gates of the first memory cell MC1 to the fifth memory cell MC5 can be connected to the first word line WL1 to the fifth word line WL5, respectively.

[0094] A pseudo memory cell (DMC) can be disposed between the first memory cell (MC1) and the ground select transistor (GST). The gate of the pseudo memory cell (DMC) can be connected to the pseudo word line (DWL). However, this is provided only as an example. According to an embodiment, a plurality of pseudo memory cells connected in series can be disposed between the first memory cell (MC1) and the ground select transistor (GST). Alternatively, an additional pseudo memory cell can be disposed between the series select transistor (SST) and the fifth memory cell (MC5). Alternatively, an additional pseudo memory cell can be disposed between memory cells (MC1 to MC5). Alternatively, a pseudo memory cell (DMC) may not be disposed.

[0095] Figure 5 Several non-volatile memories according to some example embodiments are shown.

[0096] refer to Figure 5 The multiple non-volatile memories 1200a to 1200k include multiple peak current managers PCM1 to PCMk. The multiple non-volatile memories 1200a to 1200k can perform the following operations through the multiple peak current managers PCM1 to PCMk: generating and sharing internal data signals IDATS according to the above embodiments, and stopping operations based on peak current information. Specifically, the internal data signals IDATS may include prediction timing information, and the non-volatile memories receiving the corresponding internal data signals IDATS can pre-check the predicted timing of peak current occurrence through the internal data signals IDATS and can respond to the occurrence of peak current.

[0097] Multiple non-volatile memories 1200a to 1200k can be connected via the internal data line IDATL and the internal clock line ICLKL, and can share the internal data signal IDATS with each other via the internal data line IDATL.

[0098] In some example embodiments, one (or one or more) of the plurality of non-volatile memories 1200a to 1200k may further include a clock generator 1280 configured to generate an internal clock signal ICLK for the plurality of non-volatile memories 1200a to 1200k. According to the above embodiments, the clock generator 1280 can generate the internal clock signal ICLK for inter-memory communication. That is, the internal clock ICLK generated from the clock generator 1280 is used only for inter-memory communication and is separate from the clock signal that can be provided from the memory controller. The generated internal clock signal ICLK can be transmitted by one (or one or more) of the non-volatile memories via an internal clock line ICLKL.

[0099] In some example embodiments, when no peak current is predicted within a preset or predefined prediction window, multiple peak current managers PCM1 to PCMk included in multiple non-volatile memories 1200a to 1200k can be disabled. Alternatively, when no peak current is predicted within a preset or predefined prediction window after one or more non-volatile memories have shared the internal data signal IDATS, multiple peak current managers PCM1 to PCMk can be disabled (or can enter a sleep (or idle) mode). After the prediction window has passed, the multiple peak current managers PCM1 to PCMk can be re-enabled.

[0100] In some example embodiments, based on the peak current manager being disabled and / or the peak current not being predicted within a preset or predefined prediction window, the clock generator 1280 may stop generating the internal clock signal ICLK, or may output the internal clock signal ICLK indicating a specific logic level (e.g., logic low) or high impedance (Hi-Z) state. For example, this may be based on control logic circuitry (e.g., reference...). Figure 3 The control logic circuit can control the clock generator 1280 to generate or stop generating the internal clock signal ICLK. The control logic circuit can also control the clock generator 1280 not to generate the internal clock signal ICLK if the peak current is not predicted within a preset or predefined prediction window.

[0101] In some example embodiments, multiple peak current managers PCM1 to PCMk can be enabled or disabled based on a ready / busy signal (not shown) indicating the operating state of the non-volatile memory. That is, the multiple peak current managers PCM1 to PCMk can be enabled only during memory access operations and disabled in other states.

[0102] According to the above embodiments, when multiple peak current managers PCM1 to PCMk are disabled, the internal clock signal ICLK can indicate a specific logic level (e.g., logic low) or high impedance (Hi-Z) state without switching.

[0103] According to the above embodiments, multiple non-volatile memories 1200a to 1200k can internally generate an internal clock signal ICLK for inter-memory communication, and multiple peak current managers PCM1 to PCMk can be disabled when there is no need to predict peak current, thereby reducing power consumption.

[0104] Figure 6 and Figure 7 Internal data signals are shown according to some example embodiments.

[0105] First, refer to Figure 6 According to some example embodiments, the internal data signal IDATS may include a header and a body. The header may indicate the information contained in the body following the header. For example, the header may be one bit in size and may correspond to one cycle of the internal clock signal ICLK. Alternatively, unlike the example shown, the header may be two bits or more in size.

[0106] The body can be multi-bit and can be configured differently depending on the amount of information shared through it. Similar to the header, one bit of the body can correspond to one clock cycle of the internal clock signal ICLK. Depending on the logic level of the header, the body can include prediction timing information, predefined specific time intervals, or current quantity information. The prediction timing information, specific time intervals, or current quantity information indicated by the multi-bit pointers included in the body can be stored in a mapping table. Non-volatile memory can obtain the information indicated by the body based on the mapping table.

[0107] Next, refer to Figure 7 According to some example embodiments, the internal data signal IDATS may consist only of a body. The body may include prediction timing information or current quantity information. According to various embodiments, the information included in the body may be indicated. For example, when the body includes a first number of bits, the body may include prediction timing information. Alternatively, when the body includes a second number of bits, the body may include current quantity information. For example, non-volatile memory may pre-transmit separate signals (or data packets) via internal data lines to indicate the type of information to be shared.

[0108] Figure 8 These are timing diagrams of inter-memory communication based on some example embodiments. Hereinafter, a time point “tx” (where x is a natural number) is defined to indicate any arbitrary time point in each figure, and it is reasonable for any time point to be the same as or different from one another.

[0109] refer to Figure 8 The internal clock signal ICLK is used for inter-memory communication, while the internal data signal IDATS is synchronized with the internal clock signal ICLK. Multiple non-volatile memories can share the internal data signal IDATS, which includes prediction timing information or current quantity information of peak current, through inter-memory communication. The internal data signal IDATS can be implemented according to the above embodiments (e.g., refer to...). Figure 6 and Figure 7 ).

[0110] One of a plurality of non-volatile memories sends an internal data signal IDATS to the remaining non-volatile memories within a time interval allocated specifically to that non-volatile memory. Depending on the size of the internal data signal IDATS, each time interval may have multiple clock cycles of the internal clock signal ICLK. A clock cycle of the internal clock signal ICLK belonging to a time interval may correspond to one period. Figure 8 In some cases, a cycle has four clocks, but the embodiments of this disclosure are not limited thereto. In some example embodiments, the time interval allocated to each non-volatile memory can be repeated every given number of cycles, denoted as "x" (where x is a natural number of 2 or greater). For example, when inter-memory communication is performed between the first non-volatile memory and the xth non-volatile memory, the first non-volatile memory can transmit the first internal data signal IDATS1 in a first time interval INT1 defined as the time interval from t1 to t2, and can transmit the (x+1)th internal data signal IDATSx+1 in the (x+1)th time interval INTx+1 defined as the time interval from tx+1 to tx+2. The xth non-volatile memory can transmit the xth internal data signal IDATSx in the xth time interval INTx defined as the time interval from tx to tx+1. Furthermore, the first non-volatile memory to the xth non-volatile memory can sequentially transmit the internal data signal IDATS during the first time interval INT1 to the xth time interval INTx.

[0111] In some example embodiments, each internal data signal IDATS transmitted within each time interval includes predicted timing information or current quantity information of the peak current of each non-volatile memory, which is assigned a time interval respectively.

[0112] Alternatively, in some example embodiments, when the number of cycles reaches a given number "x", the non-volatile memory allocated to the time intervals can be changed.

[0113] Timing diagrams of inter-memory communication according to various embodiments of the present disclosure will now be described. As a non-limiting example, and for ease of description, the timing diagrams will be described together with the following details: Each of the first to fourth non-volatile memories transmits internal data signals within a time interval allocated to it, and this time interval repeats once every four cycles.

[0114] "BUFx" represents the peak current information buffered in each non-volatile memory (e.g., the buffer in the above-mentioned memory). Figure 3 (Peak current information in the register).

[0115] The information indicated by the internal data signals and buffered peak current includes a 1-digit header and a 3-digit body.

[0116] The logic low indicator in the header includes prediction time information, while the logic high indicator in the header includes current quantity information.

[0117] The forecast time information indicates the number of remaining periods.

[0118] The condition where the 3-digit main element is "000" indicates that the information is empty; the condition where the 3-digit main element is "001" indicates that the predicted occurrence time will arrive after one cycle; and the condition where the 3-digit main element is "111" indicates that the predicted occurrence time will arrive after seven cycles. "010" to "110" correspond to two to six cycles respectively.

[0119] However, the embodiments disclosed herein are not limited to the details described above. That is, the number of non-volatile memories, the number of cycles of internal data signal transmission repetition, the bit size of the header and / or body, the information indicated by the header logic level, the information indicated by the prediction timing information, etc., can be defined differently and are not limited to the details described above.

[0120] Figure 9 It is a timing diagram of inter-memory communication and buffered data when the predicted timing information of different non-volatile memories overlaps with each other, according to some example embodiments.

[0121] refer to Figure 9The first to fourth non-volatile memories are defined as first-buffered data to fourth-buffered data. For example, the internal data signal IDATS is a 4-bit signal, and the buffered data is 4-bit data, with the first bit corresponding to the header and the remaining bits corresponding to the body. Each internal data signal IDATS and buffered data includes predicted timing information or current information calculated (or predicted) through each non-volatile memory. When the first to fourth non-volatile memories obtain the predicted timing information or current information, they can buffer the obtained information.

[0122] The time interval from t1 to t8 can be defined as the first time interval INT1 to the seventh time interval INT7. These time intervals are allocated to non-volatile memory respectively.

[0123] In the first time interval INT1, the first buffered data BUF1, corresponding to "0100", is transmitted as the internal data signal IDATS. That is, the first non-volatile memory is shared: after four cycles from the first time interval INT1 corresponding to the transmission time point, the occurrence of a peak current is predicted in the fifth time interval INT5. The second buffered data BUF2 in the first time interval INT1, corresponding to "0011", indicates that the occurrence of a peak current is predicted in the fifth time interval INT5, three cycles from the second time interval INT2 corresponding to the transmission time point of the second non-volatile memory. That is, the prediction times of the first and second non-volatile memory events overlap.

[0124] The second non-volatile memory can receive the internal data signal IDATS from the first non-volatile memory during the first time interval INT1, and can check whether the prediction times overlap through the received internal data signal IDATS. When the prediction time information of the first non-volatile memory included in the internal data signal IDATS overlaps with the buffered prediction time information, the second non-volatile memory can change the buffered prediction time information. That is, when the prediction time information of different non-volatile memories overlaps with each other, the non-volatile memory that transmits the prediction time information later than the non-volatile memory that transmitted the prediction time information first changes and transmits the prediction time information.

[0125] exist Figure 9 In this case, the second non-volatile memory changes the buffered data from "0011" to "0101". In this paper, when the remaining number of cycles is used as the modified prediction time information for reverse calculation, the buffered data "0101" can correspond to a time interval different from the fifth time interval INT5.

[0126] Furthermore, non-volatile memory that modifies prediction timing information can delay the occurrence of peak current by stopping or postponing scheduled operations based on the modified prediction timing information.

[0127] During the period from the third time interval INT3 to the sixth time interval INT6, the internal data signal IDATS, displaying "0000", is output because the third buffer data BUF3 and the fourth buffer data BUF4 indicate that the information is empty. Specifically, the fifth time interval INT5 is the predicted occurrence time indicated by the internal data signal IDATS shared in the first time interval INT1. Therefore, during the fifth time interval INT5 or the time interval preceding it, the second to fourth non-volatile memories, excluding the first non-volatile memory, can halt scheduled operations.

[0128] In the sixth time interval INT6, the third buffer data BUF3 indicates "0100". That is, the occurrence of peak current can be predicted from the third non-volatile memory. Therefore, in the seventh time interval INT7, the third non-volatile memory can transmit the internal data signal IDATS, which includes "0100".

[0129] According to the above embodiments, when multiple prediction time information overlaps with each other, the non-volatile memory can prevent excessive peak current generation by changing the prediction time information.

[0130] Figure 10 This is a timing diagram of inter-memory communication and buffered data when the header changes, based on some example embodiments.

[0131] refer to Figure 10 According to some example embodiments, the non-volatile memory can transmit prediction timing information, and then current quantity information can be transmitted instead of prediction timing information.

[0132] For example, in the first time interval INT1, the first non-volatile memory transmits the first buffered data BUF1 corresponding to "0100" as the internal data signal IDATS without modification. That is, four cycles after the first time interval INT1, i.e. in the fifth time interval INT5, the prediction indicating that a peak current will be generated in the first non-volatile memory will be shared by the remaining non-volatile memory.

[0133] In the second time interval INT2, the second non-volatile memory transmits the second buffered data BUF2 corresponding to "0100" as the internal data signal IDATS. That is, four cycles after the second time interval INT2, which corresponds to the transmission time point of the second non-volatile memory, i.e., in the sixth time interval INT6, the prediction indicating the generation of peak current in the second non-volatile memory is shared by the remaining non-volatile memory.

[0134] During the third time interval INT3 and the fourth time interval INT4, the internal data signal IDATS, which outputs “0000”, is empty because the third buffer data BUF3 and the fourth buffer data BUF4 are empty.

[0135] The fifth time interval INT5 is the predicted time of the peak current of the first non-volatile memory shared in the first time interval INT1. In this case, it can be buffered in the fifth time interval INT5 by using the "1110" output by the internal data signal IDATS, or, unlike the example shown, it can be pre-buffered one cycle before the fifth time interval INT5.

[0136] According to some example embodiments, the non-volatile memory can transmit an internal data signal IDATS including current quantity information within any time interval following the first time interval INT1 that transmits prediction time information. According to embodiments, the arbitrary time interval can correspond to the occurrence prediction time shared within the first time interval INT1, or it can be the time interval between the first time interval INT1 and the occurrence prediction time. That is, after the non-volatile memory transmits the prediction time information, it can transmit current quantity information indicating the peak current quantity that will be generated at the occurrence prediction time.

[0137] For example, in Figure 10 In the case of the first time interval INT1, the first non-volatile memory transmits the internal data signal IDATS again in the fifth time interval INT5. In this case, the first non-volatile memory can transmit the internal data signal IDATS with a logic high header. The "110" corresponding to the body is current quantity information indicating the peak current quantity. Through the internal data signal IDATS, the remaining non-volatile memory can check what the peak current quantity is in the fifth time interval INT5.

[0138] Alternatively, unlike the example shown, when there is an additional time interval between the time interval for transmitting prediction time information and the time when the prediction occurs, the first non-volatile memory can transmit an internal data signal IDATS including current quantity information within the corresponding time interval. In this case, the remaining non-volatile memory can pre-check the peak current quantity before the prediction occurs.

[0139] The sixth time interval INT6 is the prediction time for the peak current of the shared second non-volatile memory to occur in the second time interval INT2. Similar to the first non-volatile memory, the second non-volatile memory can also transmit "1101" including current information as the internal data signal IDATS in the sixth time interval INT6.

[0140] Subsequently, in the seventh time interval INT7, since there is no prediction time, the internal data signal IDATS with “0000” can be output again.

[0141] According to the above embodiments, the non-volatile memory can additionally share the peak current to be generated at the corresponding prediction time after transmitting the prediction time information.

[0142] Figure 11 This is a timing diagram of inter-memory communication and buffered data when a predicted time change occurs, based on some example embodiments. Figure 11 In this case, the following details in the above details are changed, for example, to: Each of the first and second non-volatile memories transmits the internal data signal IDATS within a time interval allocated to it, and this time interval repeats once every two cycles.

[0143] refer to Figure 11 When the prediction time information changes after the internal data signal IDATS is transmitted in the first time interval INT1, according to some example embodiments, the non-volatile memory can transmit the internal data signal IDATS including the changed prediction time information at any time interval after the first time interval INT1. That is, the non-volatile memory can continuously share the changed prediction time information with the remaining non-volatile memory before the occurrence prediction time indicated by the prediction time information arrives.

[0144] According to an embodiment, when the prediction time of the prediction time information corresponds to the occurrence prediction time, after transmitting the internal data signal IDATS, the occurrence prediction time itself can be determined based on the aforementioned peak current manager (e.g., reference...). Figure 1 , Figure 3 and Figure 5The prediction changes based on the forecast. In this case, the non-volatile memory can again share the prediction time information indicating when the change has occurred.

[0145] According to an embodiment, when the prediction timing information is the number of remaining cycles, the prediction timing information can be changed whenever the time interval allocated to the non-volatile memory for transmitting the internal data signal IDATS arrives. In this case, the non-volatile memory can again share the prediction timing information indicating the changed number of remaining cycles.

[0146] For example, in Figure 11 In the case of the first time interval INT1, the first buffer data BUF1 corresponding to "0100" is output as the internal data signal IDATS. When the second non-volatile memory predicts the time interval five cycles after the second time interval INT2 allocated to the second non-volatile memory as the occurrence prediction time, the second buffer data BUF2 corresponds to "0101".

[0147] After the internal data signal IDATS of “0100” is transmitted in the first non-volatile memory, the first buffered data BUF1 is changed to “0010” in the second time interval INT2 (because the third time interval INT3 is the next time interval of the first non-volatile memory, and the number of remaining cycles is 2). In addition, the internal data signal IDATS of “0101” is output as the second buffered data BUF2.

[0148] In the third time interval INT3, the internal data signal IDATS of “0010” is output as the first buffered data BUF1. After the internal data signal IDATS of “0101” is transmitted in the second non-volatile memory, in the third time interval INT3, the second buffered data BUF2 is changed to “0011” (because the fourth time interval INT4 is the next time interval of the second non-volatile memory, and the number of remaining cycles is 3).

[0149] In the fourth time period INT4, the internal data signal IDATS of “0011” is output as the second buffer data BUF2.

[0150] In the fifth time interval INT5, the second buffer data BUF2 becomes "0001". Furthermore, in the fifth time interval INT5, since there is no prediction timing information to be shared, the internal data signal IDATS is output as "0000". Because the peak current of the first non-volatile memory can be generated in the fifth time interval INT5, according to the embodiment, the second non-volatile memory can stop its scheduled operations in the fifth time interval INT5.

[0151] In the sixth time interval INT6, the internal data signal IDATS of “0001” is output as the second buffered data BUF2. Because the peak current of the second non-volatile memory can be generated in the seventh time interval INT7, according to the embodiment, the first non-volatile memory can stop the scheduled operation in the seventh time interval INT7.

[0152] According to the above embodiments, non-volatile memory can allow remaining non-volatile memory to cope with the variability of prediction by sharing variable prediction time information.

[0153] Figure 12 This is a timing diagram of peak current information sharing operations and programming operations of a storage device according to some example embodiments.

[0154] refer to Figure 12 At time t1, the storage controller transmits write command 80h via data line DQ. Write command 80h instructs for data programming operations. Column and row addresses can be provided via address cycles ADDR starting from time t2.

[0155] During the time interval from t3 to t4, program data "DATA" is provided from the storage controller via data line DQ.

[0156] At time t4, the second code 10h of the write command set is provided to the non-volatile memory, and at time t5, the ready / busy signal RnB goes low. Simultaneously, inter-memory communication can begin from time t5. The non-volatile memories can share peak current information (PCI) with each other via the internal data line IDATL. Peak current information (PCI) can include prediction timing information or current quantity information.

[0157] In some example embodiments, the peak current manager according to the above embodiments (e.g., reference) Figure 1 , Figure 3 and Figure 5 The peak current manager can be enabled or disabled based on the logic level of the ready / busy signal RnB. For example, the peak current manager can be disabled when the ready / busy signal RnB transitions from logic low to logic high. Alternatively, the peak current manager can be enabled when the ready / busy signal RnB transitions from logic high to logic low.

[0158] Figure 13 It is a timing diagram of the internal clock signal and internal data signal according to some example embodiments.

[0159] refer to Figure 13The internal clock signal ICLK switches from time point t1, and the internal data signal IDATS outputs peak current information PCI (e.g., prediction timing information or current quantity information) during the time interval from t1 to t2.

[0160] Because there is no prediction of the peak current in the non-volatile memory starting from time point t2, the internal data signal IDATS outputs a default value or initial value (e.g., where all bits are logic low). The peak current manager can be disabled when the time interval for the internal data signal IDATS to output the default value remains as long as the preset or predefined prediction window PW. That is, after time point t3, the peak current manager is disabled, and the internal data signal IDATS continuously outputs the default value.

[0161] According to some example embodiments, the internal clock signal ICLK may no longer be switched along with the disabling of the peak current manager. That is, the internal clock signal ICLK may output a logic low corresponding to ground (GND), or it may be set to a high impedance state Hi-Z.

[0162] Subsequently, according to the above embodiments, when the ready / busy signal (e.g., reference) is received... Figure 12 When the logic value transitions from high to low, the peak current manager can be reactivated. Additionally, the internal clock signal ICLK can be toggled again.

[0163] According to the above embodiments, when no peak current is predicted within a given time, the non-volatile memory can disable the internal clock signal ICLK and the peak current manager, and thus reduce power consumption.

[0164] Figure 14 This is a flowchart of an operation method for a non-volatile memory according to some example embodiments.

[0165] refer to Figure 14 In operation S1100, the non-volatile memory can obtain internal data signals including prediction timing information of the peak current or current quantity information of the peak current. For example, after a memory access operation to the non-volatile memory is initiated, operation S1100 can be repeated. Alternatively, operation S1100 can be repeated until the ready / busy signal transitions to logic high again after it transitions to logic low.

[0166] In operation S1200, the non-volatile memory can transmit the internal data signals obtained in operation S1100 via internal data lines synchronized with the internal clock line. Operation S1200 can be repeatedly executed within time intervals individually allocated to the non-volatile memory.

[0167] By using the method according to the above embodiments, peak current information shared before the peak current occurs can be provided to each non-volatile memory in advance, and thus peak current can be prepared in advance.

[0168] Figure 15 This is a flowchart of an operational method based on predicted time information, according to some example embodiments.

[0169] refer to Figure 15 Following operation S1200, which transmits internal data signals, in operation S1300, the non-volatile memory can check whether the prediction time information has changed. That is, the non-volatile memory can share a specific occurrence prediction time or a specific remaining period with the remaining non-volatile memory, and can then continuously check whether the shared prediction time information has changed. For example, the prediction time information can change when the predicted value differs from the prediction value at the first shared time. When the prediction time information has not changed, operation S1300 can be repeated.

[0170] When the prediction timing information is changed in operation S1300, in operation S1400, the non-volatile memory can transmit internal data signals including the changed prediction timing information. Therefore, the changed prediction timing information thus shared can be re-provided to the remaining non-volatile memory.

[0171] Figure 16 This is a flowchart of an internal data signal transmission method according to some example embodiments.

[0172] refer to Figure 16 In operation S1210, the non-volatile memory can transmit internal data signals including prediction time information within a first time interval of the allocated time interval.

[0173] In operation S1220, the non-volatile memory can transmit internal data signals including current quantity information within a second time interval following a first time interval in the allocated time intervals. In some example embodiments, operation S1220 can be executed at the occurrence prediction time indicated by the prediction time information transmitted in operation S1210, or before the occurrence prediction time. Therefore, the remaining non-volatile memory having the shared current quantity information can check the peak current.

[0174] Figure 17 This is a flowchart of an internal data signal transmission method according to some example embodiments.

[0175] refer to Figure 17 In operation S2100, the non-volatile memory can buffer prediction timing information. For example, according to the above embodiment, the non-volatile memory can buffer registers (e.g., reference...). Figure 3) Execute buffer.

[0176] In operation of S2200, the non-volatile memory can receive internal data signals through internal data lines.

[0177] In operation S2300, the non-volatile memory can check whether the prediction timing information included in the internal data signal received in operation S2200 overlaps with the buffered prediction timing information.

[0178] When the prediction timing information and the buffered prediction timing information overlap in operation S2300, the non-volatile memory can modify the buffered prediction timing information in operation S2400. Afterwards, the non-volatile memory can transmit an internal data signal including the modified prediction timing information via operation S1200. Alternatively, when the prediction timing information and the buffered prediction timing information do not overlap in operation S2300, the buffered prediction timing information can be transmitted without modification via operation S1200.

[0179] According to this disclosure, a non-volatile memory capable of performing inter-memory communication to share prediction timing information of peak current, a storage device including the non-volatile memory, and a method thereof can be provided.

[0180] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure.

Claims

1. A storage device, the storage device comprising: Multiple non-volatile memories; as well as The storage controller is connected to the plurality of non-volatile memories via data lines. The plurality of non-volatile memories are interconnected via an internal clock line separate from the data line and an internal data line synchronized with the internal clock line. Each of the plurality of non-volatile memories is configured to transmit an internal data signal, including prediction timing information of peak current, via the internal data line.

2. The storage device according to claim 1, wherein, The internal data signal includes a header and a body, and When the header indicates a first logic level, the main body includes the predicted time information.

3. The storage device according to claim 2, wherein, When the header indicates a second logic level, the body includes current quantity information of the peak current.

4. The storage device according to claim 1, wherein, The non-volatile memory among the plurality of non-volatile memories is configured to transmit an internal clock signal via the internal clock line.

5. The storage device according to claim 4, wherein, The prediction time information indicates the predicted time of the peak current occurrence, the number of remaining cycles of the internal clock signal from the transmission time of the internal data signal to the predicted time of occurrence, or the remaining time from the transmission time of the internal data signal to the predicted time of occurrence.

6. The storage device according to claim 1, wherein, One of the plurality of non-volatile memories is configured to transmit the internal data signal to the remaining non-volatile memories during time intervals individually allocated to that non-volatile memory.

7. The storage device according to claim 6, wherein, When the prediction time information changes after the internal data signal is transmitted within a first time interval within the time interval, the non-volatile memory is configured to transmit the internal data signal including the changed prediction time information within a second time interval after the first time interval within the time interval.

8. The storage device according to claim 6, wherein, The remaining non-volatile memory is configured to stop scheduled operations at the predicted time of the peak current occurrence, indicated by the predicted time information.

9. The storage device according to claim 6, wherein, The non-volatile memory is configured as follows: During the first time interval of the time interval, the internal data signal including the predicted time information is transmitted; as well as During the second time interval following the first time interval, the internal data signal including current quantity information of the peak current is transmitted.

10. The storage device according to claim 1, wherein, The first non-volatile memory of the plurality of non-volatile memories is configured as follows: Buffer the predicted timing information regarding the first non-volatile memory; Receive the internal data signal from the second non-volatile memory; as well as When the prediction time information about the second non-volatile memory included in the internal data signal overlaps with the buffered prediction time information, the buffered prediction time information is changed.

11. A method for using a non-volatile memory, the method comprising: An internal data signal is obtained, including prediction timing information of the peak current of the non-volatile memory; as well as The internal data signal is transmitted via an internal data line synchronized with the internal clock line.

12. The method according to claim 11, wherein, The internal data signal includes a header and a body. Wherein, when the header indicates a first logic level, the body includes the predicted time information, and When the header indicates the second logic level, the main body includes the current quantity information of the peak current.

13. The method according to claim 11, further comprising: The internal clock signal is transmitted through the internal clock line.

14. The method according to claim 11, wherein, The transmission of the internal data signal is repeated within a time interval that is separately allocated to the non-volatile memory.

15. The method according to claim 11, further comprising: After transmitting the internal data signal, check whether the prediction time information has changed; as well as When the prediction time information changes, the internal data signal including the changed prediction time information is transmitted.

16. The method of claim 14, wherein, The transmission of the internal data signal also includes: During a first time interval within the time interval, the internal data signal including the predicted time information is transmitted; and During the second time interval following the first time interval, the internal data signal including current quantity information of the peak current is transmitted.

17. The method according to claim 11, further comprising: Buffer the predicted time information; The internal data signal is received via the internal data line; Check whether the prediction time information included in the internal data signal overlaps with the buffered prediction time information; and When the prediction time information included in the internal data signal overlaps with the buffered prediction time information, the buffered prediction time information is changed.

18. A non-volatile memory, the non-volatile memory comprising: Storage cell array; Input / output circuitry, the input / output circuitry being connected to data lines that transmit write or read data associated with the memory cell array, an internal clock line separate from the data lines, and an internal data line synchronized with the internal clock line; and A control logic circuit configured to transmit an internal data signal, including prediction timing information of peak current, via the internal data line based on control of the input / output circuit.

19. The non-volatile memory according to claim 18, further comprising: A clock generator configured to generate an internal clock signal to be transmitted through the internal clock line.

20. The non-volatile memory according to claim 19, wherein, The clock generator is configured to stop generating the internal clock signal if the peak current is not predicted within the prediction window.

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