A hard disk power-off test method based on time sequence control, a computer program product and a system

By adopting a time-based hard drive power failure testing method, a programmable power control unit is used to precisely trigger power failure within a critical operation window. Combined with multi-level data integrity verification, this method solves the problem of missed detection rate in high-risk scenarios in hard drive power failure testing and improves the accuracy of the test.

CN122177196APending Publication Date: 2026-06-09GUANGDONG HANWEI INFORMATION TECH CO LTD

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
GUANGDONG HANWEI INFORMATION TECH CO LTD
Filing Date
2026-02-27
Publication Date
2026-06-09

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Abstract

This invention provides a time-series control-based hard drive power-down testing method, computer program product, and system. The method includes: initializing the hard drive under test and a programmable power control unit; writing benchmark test data to the hard drive under test and generating corresponding data fingerprint information; executing a preset input / output load scenario and monitoring the internal operating state of the hard drive under test in real time; identifying key operation windows based on the internal operating state of the hard drive under test, and triggering a power-down command at a specified delay time within the key operation window to control the programmable power control unit to cut off power supply; after a preset recovery waiting time, controlling the programmable power control unit to restore power supply and monitoring the power-on recovery process of the hard drive under test; performing multi-level data integrity verification, including comparing the recovered data of the hard drive under test with the data fingerprint information; generating a test report based on the multi-level data integrity verification results, and determining that the hard drive power-down test is passed if the verification results are passed.
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Description

Technical Field

[0001] This invention relates to the field of storage device testing technology, and in particular to a hard disk power failure testing method, computer program product, and system based on timing control. Background Technology

[0002] With the rapid development of big data, cloud computing, and artificial intelligence technologies, storage devices, as the core carriers of data, are directly related to the security and stability of information systems. In practical applications, unexpected power outages are one of the main causes of storage device failures. For example, in situations such as data center server crashes, power fluctuations in industrial control systems, depleted mobile device batteries, or accidental power disconnection by users, the hard drive may be performing critical operations such as writing, erasing, mapping table updates, or garbage collection. A power outage at this time can easily lead to data loss, file system corruption, metadata inconsistencies, or even render the hard drive "bricked" (unrecognizable or unable to boot).

[0003] During the research, development, production, and acceptance phases of hard drives, rigorous power loss testing (PLT) is a necessary step in verifying hard drive stability. The main purpose of PLT is to evaluate the effectiveness of the hard drive's data protection mechanisms (such as capacitor power loss protection, log rollback, atomic writes, etc.) under sudden power outages, and whether its self-recovery capability after power-on meets expectations. Most existing PLT strategies employ random or fixed-interval power loss. While these strategies can simulate real-world scenarios, they lack specificity and struggle to accurately capture critical microsecond-level operation windows within the firmware (such as mapping table updates and cache flushing thresholds), resulting in a high rate of missed detections in high-risk scenarios. Summary of the Invention

[0004] The technical problem this invention aims to solve is how to reduce the false negative rate in high-risk scenarios during hard drive power failure testing.

[0005] To address the aforementioned technical problems, this invention provides a hard disk power-loss testing method based on timing control, comprising the following steps: S1. Initialize the hard drive under test and the programmable power control unit that supplies power to it; S2. Write benchmark test data to the hard disk under test and generate corresponding data fingerprint information; S3. Execute a preset input / output load scenario to monitor the internal operating status of the hard disk under test in real time; S4. Based on the internal operating state of the hard drive under test, identify key operation windows, and trigger a power-down command at a specified delay time within the key operation window to control the programmable power control unit to cut off the power supply to the hard drive under test; S5. After a preset recovery waiting time, control the programmable power control unit to restore power supply to the hard drive under test, and monitor the power-on recovery process of the hard drive under test; S6. Perform multi-level data integrity verification, including comparing the recovered data of the tested hard disk with the data fingerprint information; S7. Generate a test report based on the multi-level data integrity verification results. If the verification results are passed, the hard drive power failure test is considered to have passed.

[0006] Furthermore, the real-time monitoring of the internal operating status of the hard drive under test in step S3 specifically includes: obtaining the input / output command type by intercepting the command interface between the host and the hard drive under test; and / or analyzing the current execution stage of the firmware of the hard drive under test by collecting the reserved debugging interface signal or indicator light signal of the hard drive under test; and / or using a high-speed data acquisition card to monitor the power supply current waveform characteristics of the hard drive under test and identify the start and end times of read / write operations, garbage collection operations, or metadata update operations.

[0007] Furthermore, the identification of key operation windows in step S4 specifically includes at least one of the following stages: the stage where data is written to the cache but not yet flushed to the flash memory medium; the stage where cached data is being flushed to the flash memory medium; the stage where the flash memory mapping table is being updated; the stage where garbage collection or wear leveling operations are being performed; the stage where firmware code is being upgraded or initialized; and the stage where specific commands are being executed in multi-queue concurrent processing.

[0008] Furthermore, the specified delay time in step S4 is determined through microsecond-level timing control, specifically including: Obtain the feature parameters of the currently identified operation type; query the preset timing strategy library to obtain the risk time interval corresponding to the operation type; within the risk time interval, determine a delay time value according to a random algorithm or a fixed step size, the precision range of the delay time value is 1 microsecond to 1000 microseconds; after detecting the operation trigger signal, delay the delay time value to trigger a power-down command to execute the power cut-off operation.

[0009] Furthermore, the multi-level data integrity verification in step S6 includes: Physical layer verification: Scan all sectors on the disk, count the number of unreadable sectors and the number of verification errors; Logical layer verification: Check the consistency of file system metadata, verify the integrity of flash mapping tables, and detect whether there are logical address mapping errors; Application layer verification: Read the benchmark test data written in step S2, calculate the current data fingerprint and compare it with the original data fingerprint; Performance layer verification: Measure the power-on recovery time and execute standard performance test scripts to evaluate the impact of power loss on the subsequent read and write performance of the hard drive.

[0010] Furthermore, in step S7, if the multi-level data integrity verification result fails, the hard drive power failure test is determined to have failed, and then the test dynamic adjustment steps are executed: record the power failure timing characteristics and operation types that caused the test failure in historical tests; calculate the fault weight coefficient for each operation type, wherein the fault weight coefficient is positively correlated with the frequency of historical failures of that operation type; based on the fault weight coefficient and the coverage gap of the current test scenario, dynamically adjust the test priority and test frequency of each key operation window in the next round of testing; prioritize the execution of power failure test scenarios corresponding to high-priority key operation windows.

[0011] The present invention also provides a computer program product, comprising a computer program, characterized in that, when the computer program is executed by a processor, it implements the steps in the above-described hard disk power failure test method.

[0012] This invention also provides a hard disk power failure testing system based on timing control, characterized in that it includes: The load generation module is configured to generate various preset input / output load scenarios and send input / output requests to the hard drive under test. The status monitoring module is configured to monitor the internal operating status of the hard drive under test in real time and identify key operation windows. A power-down control module, which is connected to a programmable power control unit, is configured to trigger a power-down command to cut off or restore power supply based on feedback from the status monitoring module. The data verification module is configured to perform multi-level data integrity verification after power is restored. The central controller is communicatively connected to the load generation module, the status monitoring module, the power failure control module, and the data verification module, and includes an interconnected memory and a processor, wherein the memory stores the aforementioned computer program product.

[0013] The present invention has the following beneficial effects: by coordinating the control of the power supply with the programmable power supply, a power-down command is triggered at a specified delay time within the critical operation window to cut off the power supply, and the power supply is restored after a preset recovery waiting time. This can accurately lock the power-down test at critical operation windows such as mapping table update and cache flushing critical point. Compared with random power-down, it can increase the detection rate of problems under the critical operation window by several times and effectively reduce the missed detection rate in high-risk scenarios. Attached Figure Description

[0014] Figure 1 This is a flowchart illustrating a hard drive power failure testing method based on timing control. Detailed Implementation

[0015] The present invention will be further described in detail below with reference to specific embodiments.

[0016] This embodiment provides a hard disk power failure testing system based on timing control, including a load generation module, a status monitoring module, a power failure control module, a data verification module, and a central controller. The load generation module is configured to generate various preset input / output (I / O) load scenarios and send I / O requests to the hard disk under test. The status monitoring module is configured to monitor the internal operating status of the hard disk under test in real time and identify critical operation windows. The power failure control module is connected to a programmable power control unit and is configured to trigger a power failure command to cut off or restore power supply based on feedback from the status monitoring module. The data verification module is configured to perform multi-level data integrity verification after power is restored. The central controller is communicatively connected to the load generation module, status monitoring module, power failure control module, and data verification module, and includes an interconnected memory and processor. The memory stores a computer program product, including a computer program, which, when executed by the processor, implements... Figure 1 The time-series-based hard drive power failure test method shown includes the following steps: S1, S2, S3, S4, S5, S6, and S7.

[0017] S1. Initialize the hard drive under test and the programmable power control unit that supplies power to it.

[0018] In this embodiment, a programmable power control unit (PPU) is used to power the hard drive under test, and the central controller is communicatively connected to the PPU. At the start of the power-down test, the central controller starts the test control software, loads the firmware version information and specifications of the hard drive under test, and then controls the temperature control chamber to set the target temperature (e.g., 25°C, 70°C). After waiting for the hard drive under test to reach thermal equilibrium, a specific "marking command" is sent to the hard drive under test. Simultaneously, a high-speed data acquisition card monitors current changes, calculates the time delay from the software issuing the command to the actual power cut-off, and compensates for this delay in subsequent tests to ensure the accuracy of the power-down timing is within ±10μs.

[0019] A programmable power control unit (PLU) is a precision instrument that transforms a regular power supply into one with fault injection capabilities. Its core strengths lie in its response speed and protection logic configuration. Initializing the PLU involves first setting the precise output voltage according to the hard drive's specifications and enabling remote sensing to compensate for cable voltage drops, ensuring accurate voltage at the hard drive's terminals. Then, the time it takes for the voltage to rise from 0 to the rated value is set to simulate the actual system startup process, preventing instantaneous surges from impacting the hard drive's input capacitors.

[0020] S2. Write benchmark test data to the hard drive under test and generate corresponding data fingerprint information.

[0021] After the power-down test begins, the central controller generates benchmark test data with a specific pattern (such as pseudo-random sequence, alternation of all 0s / all 1s, etc.), covering 10% to 100% of the hard drive capacity. Then, the test data is written to the specified logical block address (LBA) range of the hard drive under test, and the checksum (CRC32 or SHA256) of the written data is calculated to generate the original data fingerprint information and store it in the secure area.

[0022] S3. Execute preset input / output load scenarios to monitor the internal operating status of the hard drive under test in real time.

[0023] The central controller initiates the load generation module to execute preset input / output (IO) load scenarios (such as 4K random write, sequential read, mixed load, background GC trigger, etc.) and monitors the internal operating status of the hard drive under test in real time. Specifically, this includes: obtaining the input / output command types by intercepting the command interface between the host and the hard drive under test; and / or analyzing the current execution stage of the hard drive firmware by collecting the reserved debugging interface signals or indicator light signals of the hard drive under test; and / or using a high-speed data acquisition card to monitor the power supply current waveform characteristics of the hard drive under test and identify the start and end times of read / write operations, garbage collection operations, or metadata update operations.

[0024] S4. Based on the internal operating state of the hard drive under test, identify the key operation window, and trigger a power-down command at a specified delay time within the key operation window to control the programmable power control unit to cut off the power supply to the hard drive under test.

[0025] The central controller, through the status monitoring module, identifies key operation windows based on the internal operating status of the tested hard drive. Specifically, these include at least one of the following stages: the stage where data is written to the cache but not yet flushed to the flash media; the stage where cached data is being flushed to the flash media; the stage where the flash mapping table is being updated; the stage where garbage collection or wear leveling operations are being performed; the stage where firmware code is being upgraded or initialized; and the stage where specific commands are being executed in multi-queue concurrent processing.

[0026] Then, the central controller triggers a power-down command at a specified delay time within the critical operation window, controlling the programmable power control unit to cut off the power supply to the hard drive under test. The specified delay time is determined by microsecond-level timing control, specifically including: acquiring the characteristic parameters of the currently identified operation type; querying the preset timing strategy library to obtain the risk time interval corresponding to the operation type; within the risk time interval, determining a delay time value according to a random algorithm or a fixed step size, with the precision range of the delay time value being 1 microsecond to 1000 microseconds; after detecting the operation trigger signal, delaying the delay time value triggers the power-down command to execute the power cut-off operation.

[0027] S5. After the preset recovery waiting time, control the programmable power control unit to restore power supply to the hard drive under test, and monitor the power-on recovery process of the hard drive under test.

[0028] After a preset recovery waiting time (e.g., 5 seconds), the simulated capacitor discharges completely. The central controller then controls the programmable power control unit to restore power to the hard drive under test and monitors the power-on recovery process of the hard drive, such as monitoring the power-on sequence of the hard drive and recording the time taken from power-on to host recognition and device readiness. If the hard drive under test is not ready within a preset timeout period (e.g., 300 seconds), it is marked as a boot failure.

[0029] S6. Perform multi-level data integrity verification, including comparing the recovered data of the tested hard drive with the data fingerprint information.

[0030] After the tested hard drive is powered on and restored, the central controller performs multi-level data integrity verification, including comparing the restored data of the tested hard drive with the data fingerprint information, specifically including: Physical layer verification: Scan all sectors on the disk, count the number of unreadable sectors and the number of verification errors; Logical layer verification: Check the consistency of file system metadata, verify the integrity of flash mapping tables, and detect whether there are logical address mapping errors; Application layer verification: Read the benchmark test data written in step S2, calculate the current data fingerprint and compare it with the original data fingerprint; Performance layer verification: Measure the power-on recovery time and execute standard performance test scripts to evaluate the impact of power loss on the subsequent read and write performance of the hard drive.

[0031] S7. Generate a test report based on the multi-level data integrity verification results. If the verification results are passed, the hard drive power failure test is considered to have passed.

[0032] After the multi-level data integrity verification is completed, the central controller generates a test report based on the verification results. If the multi-level data integrity verification passes, the hard drive power-down test is deemed to have passed; if the multi-level data integrity verification fails, the hard drive power-down test is deemed to have failed. Then, the test dynamic adjustment steps are executed: recording the characteristics of power-down timing and operation types that led to test failures in historical tests; calculating the fault weight coefficient for each operation type, which is positively correlated with the frequency of historical failures of that operation type; dynamically adjusting the test priority and frequency of each key operation window in the next round of testing based on the fault weight coefficient and the coverage gap of the current test scenario; and prioritizing the execution of power-down test scenarios corresponding to high-priority key operation windows.

[0033] By using programmable power supply control to coordinate the power supply, a power-down command is triggered at a specified delay time within the critical operation window to cut off the power supply. After a preset recovery waiting time, the power supply is restored. This allows the power-down test to be precisely locked in critical operation windows such as mapping table updates and cache flushing critical points. Compared with random power-down, the detection rate of problems under critical operation windows can be increased several times, effectively reducing the missed detection rate in high-risk scenarios.

[0034] The above description is merely an embodiment of the present invention and does not limit the scope of patent protection. Any non-substantial changes or substitutions made by those skilled in the art based on the present invention will still fall within the scope of patent protection.

Claims

1. A hard disk power failure testing method based on timing control, characterized in that, Includes the following steps: S1. Initialize the hard drive under test and the programmable power control unit that supplies power to it; S2. Write benchmark test data to the hard disk under test and generate corresponding data fingerprint information; S3. Execute a preset input / output load scenario to monitor the internal operating status of the hard disk under test in real time; S4. Based on the internal operating state of the hard drive under test, identify key operation windows, and trigger a power-down command at a specified delay time within the key operation window to control the programmable power control unit to cut off the power supply to the hard drive under test; S5. After a preset recovery waiting time, control the programmable power control unit to restore power supply to the hard drive under test, and monitor the power-on recovery process of the hard drive under test; S6. Perform multi-level data integrity verification, including comparing the recovered data of the tested hard disk with the data fingerprint information; S7. Generate a test report based on the multi-level data integrity verification results. If the verification results are passed, the hard drive power failure test is considered to have passed.

2. The hard drive power failure test method according to claim 1, characterized in that, Step S3 involves real-time monitoring of the internal operating status of the hard drive under test, specifically including: obtaining input / output command types by intercepting the command interface between the host and the hard drive under test; and / or analyzing the current execution stage of the firmware of the hard drive under test by collecting the reserved debugging interface signal or indicator light signal of the hard drive under test; and / or using a high-speed data acquisition card to monitor the waveform characteristics of the power supply current of the hard drive under test, and identifying the start and end times of read / write operations, garbage collection operations, or metadata update operations.

3. The hard disk power failure test method according to claim 1, characterized in that, The identification of key operation windows in step S4 specifically includes at least one of the following stages: the stage where data is written to the cache but not yet flushed to the flash memory medium; the stage where cached data is being flushed to the flash memory medium; the stage where the flash memory mapping table is being updated; the stage where garbage collection or wear leveling operations are being performed; and the stage where firmware code is being upgraded or initialized. A specific command execution phase in multi-queue concurrent processing.

4. The hard disk power failure test method according to claim 1, characterized in that, The specified delay time in step S4 is determined by microsecond-level timing control, specifically including: obtaining the feature parameters of the currently identified operation type; querying the preset timing strategy library to obtain the risk time interval corresponding to the operation type; within the risk time interval, determining a delay time value according to a random algorithm or a fixed step size, wherein the precision range of the delay time value is 1 microsecond to 1000 microseconds; after detecting the operation trigger signal, delaying the delay time value to trigger a power-down command to execute the power cut-off operation.

5. The hard disk power failure test method according to claim 1, characterized in that, The multi-level data integrity verification in step S6 includes: Physical layer verification: Scan all sectors on the disk, count the number of unreadable sectors and the number of verification errors; Logical layer verification: Check the consistency of file system metadata, verify the integrity of flash mapping tables, and detect whether there are logical address mapping errors; Application layer verification: Read the benchmark test data written in step S2, calculate the current data fingerprint and compare it with the original data fingerprint; Performance layer verification: Measure the power-on recovery time and execute standard performance test scripts to evaluate the impact of power loss on the subsequent read and write performance of the hard drive.

6. The hard disk power failure test method according to any one of claims 1 to 5, characterized in that, In step S7, if the multi-level data integrity verification result fails, the hard disk power failure test is determined to fail, and then the test dynamic adjustment step is executed: record the power failure timing characteristics and operation type that caused the test failure in historical tests. Calculate the fault weight coefficient for each operation type, which is positively correlated with the frequency of historical faults of that operation type; based on the fault weight coefficient and the coverage gap of the current test scenario, dynamically adjust the test priority and test frequency of each key operation window in the next round of testing; prioritize the execution of power failure test scenarios corresponding to high-priority key operation windows.

7. A computer program product comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps in the hard disk power failure test method according to any one of claims 1 to 6.

8. A hard disk power failure testing system based on timing control, characterized in that, include: The load generation module is configured to generate various preset input / output load scenarios and send input / output requests to the hard drive under test. The status monitoring module is configured to monitor the internal operating status of the hard drive under test in real time and identify key operation windows. A power-down control module, which is connected to a programmable power control unit, is configured to trigger a power-down command to cut off or restore power supply based on feedback from the status monitoring module. The data verification module is configured to perform multi-level data integrity verification after power is restored. The central controller is communicatively connected to the load generation module, the status monitoring module, the power failure control module, and the data verification module, and includes an interconnected memory and a processor, wherein the memory stores the computer program product of claim 7.