An ultra-low ripple power supply regulation system

Abstract

This invention relates to the field of power electronic converter technology, specifically to an ultra-low ripple power supply regulation system to solve technical problems such as phase-cutting decision mismatch, phase-cutting transient ripple surge, and excessive ripple caused by the disconnect between phase-cutting and current-sharing control in existing multi-phase power conversion systems. The technical solution includes: a phase current signal acquisition module, a phase-cutting decision and execution module, and a current-sharing deviation correction module. It acquires the current envelope signals of each phase through a magnetically coupled auxiliary winding and a peak detection circuit; implements gradual phase-cutting control through a window comparison array and an RC power electronic converter charging / discharging network; and achieves linked current-sharing correction through a resistor averaging network and a transconductance amplifier array. This invention can achieve ultra-low ripple output under all operating conditions of a multi-phase power supply, while simultaneously improving power supply efficiency and operational stability.

Description

Technical Field

[0001] This invention relates to the field of power electronic converter technology, and more specifically, to an ultra-low ripple power supply regulation system. Background Technology

[0002] Multiphase parallel DC-DC converters connect multiple power conversion units in parallel, maintaining a fixed phase difference between the switching signals of each phase and operating alternately. This reduces output current ripple and improves dynamic response speed when outputting high power. Such converters are widely used in applications with stringent requirements for power quality and efficiency, such as server power supply, communication base station power supply, electric drive system of new energy vehicles, and power supply of precision instruments.

[0003] In existing technologies, digital control schemes are commonly used to achieve phase-switching control of multiphase converters, i.e., dynamically adjusting the number of phases in operation based on the load current to optimize efficiency. This scheme uses an analog-to-digital converter to periodically sample parameters such as output voltage and inductor current of each phase, runs a phase-switching algorithm in a digital signal processor or microcontroller to determine the number of phases that should be in operation, and then outputs the drive signals for each phase through a pulse width modulation generator. To improve the performance during the phase-switching process, some schemes introduce a PID controller in the digital controller to perform current sharing control of each phase current, or add hysteresis comparison in the phase-switching threshold judgment to avoid repeated switching.

[0004] However, the aforementioned digital control scheme has inherent technical defects due to its discrete characteristics. The digital control link has delays in analog-to-digital conversion, algorithm operation, and pulse width modulation update. These delays are usually on the order of microseconds. When the controller determines that a phase needs to be turned off, the inductor current of the turned-off phase is forced to be released quickly through the freewheeling circuit due to the sudden cutoff of the switching transistor, resulting in a sharp current change. The digital controller cannot synchronously compensate for the duty cycle of the remaining working phases in the same switching cycle, resulting in low-frequency transient ripple at the output that is independent of the switching frequency. Its amplitude can reach tens of millivolts, which seriously damages the output quality of the ultra-low ripple power supply.

[0005] Meanwhile, the digital current sharing algorithm relies on an ideal model with consistent parameters for each phase to perform calculations. It cannot effectively correct the dispersion of physical parameters of each phase power device caused by manufacturing process and temperature characteristics, including differences in the on-resistance of metal oxide semiconductor field-effect transistors, inductance tolerance, and propagation delay of drive circuits. This results in deviations in the actual current of each phase, destroying the ripple cancellation effect of the interleaved parallel connection.

[0006] In addition, the digital controller still needs to keep the analog-to-digital converter, processor core and clock circuit running under light load conditions. Its own power consumption of tens to hundreds of milliwatts increases sharply as a proportion of the total power consumption of the system when the output power drops to a few watts under light load, which partially offsets the power loss saved by the phase-switching operation.

[0007] Therefore, an ultra-low ripple power supply control system is proposed. Summary of the Invention

[0008] The purpose of this invention is to provide an ultra-low ripple power supply regulation system to solve the technical problems existing in the digital control scheme of multi-phase parallel DC-DC converters, such as large phase-cutting transient ripple, current sharing accuracy constrained by the discreteness of device parameters, and the loss of phase-cutting efficiency gain due to the power consumption of the controller itself under light load conditions.

[0009] To address the aforementioned technical problems, the present invention aims to provide an ultra-low ripple power supply regulation system, comprising: The phase current signal acquisition module includes an auxiliary winding magnetically coupled to the main power inductors of each phase in the multiphase power conversion array, and a peak detection circuit connected to the output terminal of the auxiliary winding. The peak detection circuit outputs a current envelope signal characterizing the peak value of the inductor current of each phase. The phase-cutting decision and execution module includes a window comparator array and an RC charge / discharge switching network. The input terminal of the window comparator array receives the current envelope signal, and its reference input terminal is connected to an upper limit reference voltage and a lower limit reference voltage, respectively. When the current envelope signal of any phase is higher than the upper limit reference voltage, it outputs a phase-increasing trigger signal; when it is lower than the lower limit reference voltage, it outputs a phase-decreasing trigger signal. The controlled terminal of the RC charge / discharge switching network receives the phase-increasing trigger signal and the phase-decreasing trigger signal, respectively. Its output terminal is connected to the reference voltage input terminal of the pulse width modulation comparator of the selected phase. When it receives the phase-increasing trigger signal, it outputs a first gradually changing reference voltage with an increasing slope; when it receives the phase-decreasing trigger signal, it outputs a second gradually changing reference voltage with a decreasing slope. The current sharing deviation correction module includes a resistor averaging network and a transconductance amplifier array. The input of the resistor averaging network receives the current sampling signals of each phase, and the output of the average current signal is output. Each transconductance amplifier in the transconductance amplifier array receives the current sampling signal of the corresponding phase and the average current signal, and its output is connected to the reference voltage input of the pulse width modulation comparator of the corresponding phase via an integrating capacitor.

[0010] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This ultra-low ripple power supply control system, through the auxiliary winding magnetically coupled with the main power inductor and the peak detection circuit, directly obtains the envelope signal of the peak current of each phase inductor. It does not require the sampling resistor of the series power circuit, has no additional conduction loss, and can accurately sense the actual operating current peak of each phase. The phase cutting decision is perfectly matched with the real-time operating state of each phase, avoiding transient fluctuations caused by improper phase cutting timing.

[0011] 2. In this ultra-low ripple power supply control system, through the RC power electronic converter charging and discharging switching network, a gradually changing reference voltage with a fixed slope is output during phase-increasing / phase-decreasing triggering, rather than a sudden reference voltage. This causes the duty cycle of the corresponding phase to change slowly, and the inductor current to rise or fall smoothly, avoiding step jumps in the total multi-phase current and suppressing the output ripple of phase-cutting transients at the source.

[0012] 3. In this ultra-low ripple power supply control system, by connecting the output of the current sharing deviation correction module and the phase-cutting gradual reference voltage together to the reference voltage input of the pulse width modulation comparator, the current sharing closed loop and the phase-cutting control are linked. During the phase-cutting process, the current sharing loop can correct the current deviation of each phase in real time, avoid loop oscillation caused by phase-cutting, and at the same time significantly reduce the current imbalance of each phase during steady-state operation, reduce steady-state output ripple, and achieve ultra-low ripple output under all operating conditions. Attached Figure Description

[0013] Figure 1 This is an overall system block diagram of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Examples, such as Figure 1 As shown, this embodiment provides an ultra-low ripple power supply regulation system, including: The phase current signal acquisition module includes an auxiliary winding magnetically coupled to the main power inductors of each phase in the multiphase power conversion array, and a peak detection circuit connected to the output terminal of the auxiliary winding. The peak detection circuit outputs a current envelope signal characterizing the peak value of the inductor current of each phase. The phase-cutting decision and execution module includes a window comparator array and an RC charge / discharge switching network. The input terminal of the window comparator array receives the current envelope signal, and its reference input terminal is connected to an upper limit reference voltage and a lower limit reference voltage, respectively. When the current envelope signal of any phase is higher than the upper limit reference voltage, it outputs a phase-increasing trigger signal; when it is lower than the lower limit reference voltage, it outputs a phase-decreasing trigger signal. The controlled terminal of the RC charge / discharge switching network receives the phase-increasing trigger signal and the phase-decreasing trigger signal, respectively. Its output terminal is connected to the reference voltage input terminal of the pulse width modulation comparator of the selected phase. When it receives the phase-increasing trigger signal, it outputs a first gradually changing reference voltage with an increasing slope; when it receives the phase-decreasing trigger signal, it outputs a second gradually changing reference voltage with a decreasing slope. The current sharing deviation correction module includes a resistor averaging network and a transconductance amplifier array. The input of the resistor averaging network receives the current sampling signals of each phase, and the output of the average current signal is output. Each transconductance amplifier in the transconductance amplifier array receives the current sampling signal of the corresponding phase and the average current signal, and its output is connected to the reference voltage input of the pulse width modulation comparator of the corresponding phase via an integrating capacitor.

[0016] It should be noted that in this embodiment, the input voltage of the multiphase power conversion array is 12 volts, the rated output voltage is 1.0 volts, the rated total output current is 40 amps, the single switching cycle is 1 microsecond, the rated switching frequency is 1 MHz, and the total number of phases is 4. Each phase includes a synchronously configured main power switch, a freewheeling switch, and a main power inductor. The output terminals of the main power inductors of each phase are connected to the output capacitor and the load terminal. The inductance value of the main power inductor is 1 microhenry, the rated current of a single phase is 10 amps, and the maximum peak current of a single phase is 15 amps. Furthermore, the various modules are disclosed.

[0017] Currently, phase current detection in multiphase power supplies typically employs either series sampling resistors or inductor-DC resistance sampling. Series sampling resistors, directly connected in the power circuit, introduce additional conduction losses, which are particularly severe in high-current scenarios, reducing overall power supply efficiency. Inductor-DC resistance sampling requires a parallel RC network across the inductor to indirectly obtain current information through a matching time constant. However, the temperature drift characteristics of the RC parameters are usually inconsistent with those of the inductor-DC resistance, making it difficult to guarantee detection accuracy across the entire temperature range. Furthermore, neither of these methods can directly and accurately extract the peak envelope information of the inductor current for each phase. Phase-cutting decisions precisely rely on the current peak value to determine whether each phase is approaching its upper or lower load limit. Therefore, the phase current signal acquisition module adopts a non-contact magnetic coupling sampling method, which has no additional conduction losses and can accurately acquire the peak envelope of the inductor current for each phase, providing a reliable basis for phase-cutting decisions. The specific implementation method is as follows: For each phase of the multiphase power converter array, an auxiliary winding with the same magnetic core as the main power inductor is configured. The main power inductor serves as the power winding, and the auxiliary winding serves as the sampling winding, forming a coupled inductor. The corresponding terminals of the auxiliary winding and the main power inductor are configured to correspond to each other, so that the induced voltage of the auxiliary winding is linearly related to the rate of change of the current of the main power inductor. When the current of the main power inductor increases, the auxiliary winding generates a positive induced voltage; when the current of the main power inductor decreases, the auxiliary winding generates a negative induced voltage. The amplitude of the induced voltage is proportional to the rate of change of the current, and the proportionality coefficient is determined by the turns ratio of the auxiliary winding to the main power winding.

[0018] The selection of the number of turns in the auxiliary winding must simultaneously meet two constraints: First, under minimum load current, the output voltage value of the induced voltage of the auxiliary winding, after peak detection and signal conditioning, must be higher than the input offset voltage of each comparator in the subsequent window comparator array; otherwise, the current envelope signal will be buried in the noise and offset of the comparator, causing the phase-cutting judgment to fail. Second, under maximum load current, the maximum voltage value of the current envelope signal must be lower than the upper limit of the comparator's input common-mode voltage; otherwise, the comparator will enter the nonlinear operating region, the comparison threshold will shift, and the phase-cutting timing will produce an error. The comparator selected in this embodiment... The typical input offset voltage is 2 mV, and the upper limit of the input common-mode voltage is 4.5 V, while the lower limit is 0.5 V. Considering both signal-to-noise ratio and linear operating range, the auxiliary winding has 1 turn, and the main power inductor has 10 turns, meaning the turns ratio of the auxiliary winding to the main power inductor is 1:10. At this turns ratio, when the main power inductor current changes from 1 amp light load to 15 amp peak, the current envelope signal voltage range after signal conditioning is 0.8 V to 4.0 V, which is completely within the comparator's input common-mode range, and the signal amplitude is much greater than the input offset voltage, ensuring reliable threshold comparison.

[0019] The output terminal of the auxiliary winding is connected to the input terminal of the peak detection circuit. The peak detection circuit extracts the peak value of the high-frequency AC induction signal output by the auxiliary winding and outputs a DC current envelope signal that is linearly related to the peak value of the inductor current of that phase. The discharge time constant of the peak detection circuit needs to take into account two aspects: the time constant should be large enough so that the ripple of the current envelope signal is minimal when the load is stable, ensuring the stability of the phase-cutting judgment; at the same time, the time constant should be small enough so that the circuit can track the rapid changes in the load in a timely manner, ensuring the timeliness of the phase-cutting response. In this embodiment, the discharge time constant is selected as 10 microseconds, which is 10 times the switching cycle of 1 microsecond in this embodiment. This not only can it stably maintain the current peak information in each switching cycle, but it can also follow the changes in the load current on a time scale of tens of microseconds.

[0020] By employing the aforementioned technical means, conduction losses caused by series sampling resistors in the power circuit are avoided, thus improving power supply efficiency; peak information of inductor current can be accurately obtained phase by phase, and phase-switching decisions are perfectly matched to the real-time operating status of each phase, avoiding output fluctuations caused by phase-switching timing being too early or too late.

[0021] Considering that existing phase-switching control of multiphase power supplies is mostly based on total output current or total load power, when using total current as the decision criterion, the controller only knows the total load size and cannot know the specific distribution of current in each phase. When the current imbalance between phases is caused by the discreteness of device parameters, it is possible that one phase is close to overload while other phases still have a large margin, but the total current has not yet reached the phase-increasing threshold. The system does not increase the phase in time, causing that phase to overload and affecting reliability. In terms of phase-switching execution methods, existing digital schemes usually directly abruptly change the pulse width modulation reference voltage and drive enable state, which is selected... The duty cycle of the intermediate phase jumps from zero to the steady-state value or from the steady-state value to zero within a single cycle, causing a step jump in the total multi-phase current. This current step generates transient voltage fluctuations across the equivalent series resistance of the output capacitor, which are superimposed on the steady-state output ripple, forming large transient ripples that degrade the power supply quality of ultra-low ripple. Therefore, the phase-cutting decision and execution module makes phase-cutting decisions based on the phase-by-phase current envelope signal, accurately sensing the operating state of each phase, and achieving a smooth transition in the phase-cutting process through gradual reference voltage adjustment, thereby suppressing transient ripples at the source. The specific implementation method is as follows: The window comparator array contains comparator units that correspond one-to-one with the total number of phases in the multiphase power conversion array, namely four upper limit comparators and four lower limit comparators; the current envelope signal of each phase is connected to the input terminal of the corresponding comparator unit. The reference input terminals of the comparator units are respectively connected to preset upper limit reference voltages and lower limit reference voltages.

[0022] The upper and lower reference voltages are set based on the following: the phase increase threshold should be set around 90% of the single-phase rated current to ensure that the original working phases have a certain current margin before the new phase is put into operation, and to avoid overload of the original working phases due to the lag in phase increase operation; the phase decrease threshold should be set around 30% of the single-phase rated current to ensure that the current of the remaining working phases will not exceed its rated value after a phase is turned off; in this embodiment, when all four phases are working, the rated current of each phase is 10 amps, the upper reference voltage is set to 2.0 volts, which corresponds to about 9 amps, or 90% of the rated current; the lower reference voltage is set to 1.0 volts, which corresponds to about 3 amps, or 30% of the rated current; when the number of working phases decreases, the equivalent rated current of a single phase increases accordingly, and the reference voltage needs to be adjusted synchronously.

[0023] When the current envelope signal of any working phase is higher than the upper limit reference voltage, it indicates that the current of that phase is close to its rated load limit, and the current number of working phases cannot meet the load demand. The corresponding upper limit comparator outputs a high level, which is then combined by an OR gate logic to generate an increasing phase trigger signal. When the current envelope signals of all working phases are lower than the lower limit reference voltage, it indicates that the current total load can be fully borne by fewer phases, and there is redundancy in the current number of working phases. The corresponding lower limit comparator outputs a high level, which is then combined by an OR gate logic to generate a decreasing phase trigger signal. To avoid repeated switching caused by small fluctuations in the current envelope signal near the threshold, each comparator is equipped with a hysteresis function.

[0024] The controlled terminal of the RC charge / discharge switching network receives the phase-increasing trigger signal and the phase-decreasing trigger signal respectively, and its output terminal is connected to the reference voltage input terminal of the pulse width modulation comparator of the selected phase. In this embodiment, the pulse width modulation adopts the trailing edge modulation method, that is, the switch is turned on at the beginning of each switching cycle, and the switch is turned off when the sawtooth wave signal exceeds the reference voltage. The non-inverting input terminal of the pulse width modulation comparator receives the reference voltage, and the inverting input terminal receives the sawtooth wave signal. The higher the reference voltage, the later the comparator output flips and the smaller the duty cycle; the lower the reference voltage, the earlier the comparator output flips and the larger the duty cycle.

[0025] When a phase-increasing trigger signal is received, the capacitor inside the RC charge-discharge switching network enters the charging process; the voltage across the capacitor rises exponentially from zero, with the slope determined by the product of the charging resistor and the capacitor; this voltage is output as the first gradually changing reference voltage to the reference voltage input of the pulse width modulation comparator for the newly selected phase; the duty cycle of the new phase increases smoothly from zero, and the inductor current rises steadily from zero accordingly; when a phase-decreasing trigger signal is received, the capacitor inside the RC charge-discharge switching network enters the discharging process; the voltage across the capacitor decreases exponentially from its steady-state value, with the slope determined by the product of the discharging resistor and the capacitor; this voltage is output as the second gradually changing reference voltage to the reference voltage input of the pulse width modulation comparator for the phase to be turned off; the duty cycle of this phase decreases smoothly to zero, and the inductor current drops steadily to zero.

[0026] Through the above technical means, the phase-cutting decision based on the phase-by-phase current peak value is accurately matched to the actual working state of each phase, and the misjudgment of the phase-cutting timing will not occur due to the imbalance of the current in each phase; through the gradual adjustment of the reference voltage, the current of the new phase is slowly built up from zero, and the current of the turn-off phase is smoothly decayed to zero, avoiding the step jump of the total current during the phase-cutting process, suppressing the output ripple of the phase-cutting transient from the physical principle, and realizing a smooth transition of the phase-cutting process.

[0027] Because existing multiphase power supply current sharing control mostly uses independent average current loops or peak current loops, during phase switching, the sudden change in the number of working phases causes a step jump in the average current reference. This sudden change in the input reference of the current sharing loop triggers loop oscillation, which in turn exacerbates the output ripple during the phase switching transient. Simultaneously, the digital current sharing algorithm relies on an ideal model with consistent parameters for each phase. However, the physical parameters of the actual power devices in each phase exhibit dispersion, including differences in the on-resistance of metal-oxide-semiconductor field-effect transistors, inductance tolerances, and propagation delays in the drive circuit. The digital algorithm cannot effectively correct these physical deviations one by one. Therefore, the current sharing deviation correction module implements phase-by-phase analog closed-loop current sharing correction, and connects the current sharing correction signal and the phase switching gradual reference voltage together to the reference voltage input of the pulse width modulation comparator. This ensures complete linkage between current sharing control and phase switching control, guaranteeing loop stability during phase switching and providing real-time compensation for the dispersion of device parameters in each phase. The specific implementation method is as follows: The input of the resistor averaging network is connected to the current sampling signals of each phase of the multiphase power conversion array. The current sampling signals are led out from the auxiliary winding output of the phase current signal acquisition module and obtained after passing through a first-order low-pass filter. The cutoff frequency of the low-pass filter is set to one-tenth of the switching frequency, i.e., 100 kHz, to filter out high-frequency glitches of the switching frequency and retain the average value and low-frequency variation information of the inductor current, thus meeting the accuracy requirements of the current information of the current sharing loop. The resistor averaging network performs an average calculation on the current sampling signals of each phase and outputs the average current signal of all working phases. This average current signal serves as the reference benchmark for current sharing control, representing the ideal equilibrium value that the current of each phase should reach.

[0028] The transconductance amplifier array contains four transconductance amplifiers, each corresponding to one of the total number of phases. The inverting input of each transconductance amplifier receives the current sampling signal of the corresponding phase, while the non-inverting input receives the average current signal. The transconductance amplifier converts the difference between the two input signals into an output current, which is proportional to the input voltage difference, with the proportionality coefficient being the transconductance value. The output of the transconductance amplifier is connected to the first terminal of an integrating capacitor, and the second terminal of the integrating capacitor is grounded. The integrating capacitor integrates the output current of the transconductance amplifier into a voltage signal, which serves as the duty cycle correction voltage. The first terminal of the integrating capacitor is also connected to the reference voltage input of the pulse width modulation comparator for the corresponding phase.

[0029] The working principle of current sharing correction is as follows: When the current sampling signal of a certain phase is greater than the average current signal, the transconductance amplifier outputs a positive current to charge the integrating capacitor. The voltage across the capacitor rises, the reference voltage of the pulse width modulation comparator for that phase rises, the pulse width modulation duty cycle decreases, and the inductor current of the corresponding phase decreases. When the current sampling signal of a certain phase is less than the average current signal, the transconductance amplifier outputs a negative current, the integrating capacitor discharges, the voltage across the capacitor drops, the reference voltage drops, the pulse width modulation duty cycle increases, and the inductor current of the corresponding phase increases. Through this closed-loop control, the inductor current of all working phases is adjusted to be consistent with the average current.

[0030] The dynamic response speed of the current sharing loop needs to be designed reasonably. If the current sharing loop responds too quickly, it may couple and oscillate with the output voltage regulation loop, leading to system instability. If the response is too slow, it cannot compensate for the current deviation of each phase in time, resulting in poor current sharing accuracy. The crossover frequency of the current sharing loop is set to about one-thirtieth of the switching frequency, i.e., about 30 kHz, which is much lower than the crossover frequency of the voltage loop, ensuring that the two will not interfere with each other. The capacitance value of the integrating capacitor is determined based on the transconductance value of the transconductance amplifier and the target crossover frequency. In this embodiment, the transconductance value is selected as 100 micro Siemens, the integrating capacitor is selected as 100 picofarads, and the crossover frequency is about 16 kHz, which meets the design requirements.

[0031] The current sharing correction signal and the phase-cutting gradual reference voltage are both connected to the reference voltage input of the pulse width modulation comparator. During steady-state operation, the phase-cutting trigger signal is invalid, and the RC charge-discharge switching network outputs a normal steady-state reference voltage. The current sharing correction signal is superimposed with a small correction amount on this steady-state reference voltage. During the phase-cutting transition, the RC charge-discharge switching network outputs a gradual reference voltage, and the current sharing correction signal is adjusted synchronously in real time. The two signals work together at the reference voltage input of the pulse width modulation comparator by summing the voltages. This circuit topology with a shared reference voltage input ensures the physical linkage between phase-cutting control and current sharing control. The phase-cutting action does not interrupt the continuous operation of the current sharing closed loop, and the current sharing correction does not interfere with the smoothness of the phase-cutting soft transition.

[0032] Through the above technical means, phase-by-phase error-free closed-loop current sharing control is achieved, and the current imbalance of each phase can be controlled within 2%, ensuring that the ripple cancellation effect of the interleaved parallel connection is maximized and reducing steady-state output ripple. The current sharing control and phase cutting control are fully linked, and the current sharing loop continues to work stably during the phase cutting process, avoiding loop oscillation and achieving ultra-low ripple output under all operating conditions.

[0033] The auxiliary winding outputs a high-frequency AC inductive signal, with a frequency consistent with the switching frequency of 1 MHz. The peak envelope needs to be extracted from this high-frequency signal to characterize the peak value of the inductor current. Using a conventional passive peak detector circuit, i.e., a detector directly composed of diodes and capacitors, introduces detection errors due to the forward voltage drop of the diodes. The forward voltage drop of a silicon diode is approximately 0.7 volts, which, when superimposed on the inductive signal, produces a significant amplitude error. Furthermore, this forward voltage drop varies with temperature, further degrading the detection accuracy across the entire temperature range. Therefore, the peak detector circuit consists of an operational amplifier, a diode, and a bleeder resistor. The non-inverting input of the operational amplifier is connected to the output of the auxiliary winding, and the output of the operational amplifier is connected to the anode of the diode. The cathode of the diode is connected to the first terminal of the bleeder resistor, serving as the output of the peak detector circuit. The second terminal of the bleeder resistor is grounded. The specific implementation is as follows: The operational amplifier is a rail-to-rail input / output operational amplifier with a bandwidth of 10 MHz. The 10 MHz bandwidth is much larger than the 1 MHz switching frequency, ensuring sufficient response speed and enabling rapid tracking of the inductor current peak change within a switching cycle. Schottky diodes are used, with a forward voltage drop of approximately 0.3 volts and a reverse recovery time of less than 10 nanoseconds. As majority carrier devices, Schottky diodes exhibit virtually no charge extraction process when transitioning from forward conduction to reverse cutoff, resulting in an extremely short reverse recovery time, making them suitable for 1 MHz high-frequency switching scenarios and avoiding peak hold distortion caused by reverse recovery delay. A 100 kΩ bleeder resistor is selected, and a 100 picofarad filter capacitor is connected in parallel with ground at the output of the peak detector circuit. The bleeder resistor and... The discharge time constant formed by the filter capacitor is 100 kΩ multiplied by 100 picofarads, which equals 10 microseconds, ten times the switching cycle of 1 microsecond in this embodiment. The selection of this time constant is based on the following criteria: the discharge time constant needs to be several times greater than the switching cycle so that when the output voltage is maintained due to reverse cutoff of the diodes in a single switching cycle, the discharge amount of the capacitor through the bleed resistor is extremely small, and the drop in output voltage can be ignored, thereby stably maintaining the current peak information of this cycle; however, the time constant cannot be too large, otherwise when the load current changes continuously and slowly, the capacitor voltage cannot follow the decrease in time, causing the current envelope signal to not truly reflect the decreasing trend of the actual current peak, resulting in a delay in phase-cutting decision; a time constant of 10 microseconds can achieve a balance between the above two requirements.

[0034] The peak detection circuit works as follows: When the output voltage of the auxiliary winding rises, the output voltage of the operational amplifier rises synchronously. When its output voltage exceeds the sum of the diode cathode voltage and the diode forward voltage drop, the diode conducts in the forward direction, the operational amplifier charges the filter capacitor, and the output voltage rises with the peak value of the input voltage. During this process, the high open-loop gain of the operational amplifier effectively reduces the diode forward voltage drop to one-half of the open-loop gain, achieving precise tracking. When the output voltage of the auxiliary winding drops, the voltage at the output terminal of the operational amplifier drops accordingly. The diode is reverse-biased because the cathode voltage is higher than the anode voltage, and the filter capacitor discharges slowly through the bleed resistor. The output voltage will maintain the peak level of this cycle. In the next switching cycle, the above charging and discharging process is repeated, and a stable current envelope signal is formed at the output terminal.

[0035] By employing the aforementioned technical means, the high gain of the operational amplifier eliminates the detection error caused by the forward voltage drop of the diode, achieving a peak detection accuracy of less than one percent. The discharge time constant is adapted to the switching frequency, which can both stably maintain the current peak value of each cycle and follow the slow changes in the load current, ensuring the accuracy and response speed of the current envelope signal and providing a stable and reliable basis for subsequent phase-cutting decisions.

[0036] Considering that although the current envelope signal has been smoothed by the peak detection circuit, small ripple fluctuations are still unavoidable in the actual circuit, these fluctuations originate from multiple factors, including the small charging and discharging fluctuations of the filter capacitor in each switching cycle in the peak detection circuit, high-frequency noise mixed in the induced signal of the auxiliary winding, and electromagnetic interference introduced by the circuit board traces. When the average level of the current envelope signal approaches the threshold voltage of the comparator, the small ripple fluctuations superimposed on it will cause the signal to cross the threshold level multiple times, resulting in the comparator output frequently switching within a very short time. In the phase-cutting control scenario, this frequent switching manifests as repeated oscillations of the phase-increasing trigger signal and the phase-decreasing trigger signal, i.e., phase-cutting ringing. Phase-cutting ringing causes the system to perform phase-increasing and phase-decreasing actions multiple times within a very short time. The repeatedly increased and decreased phases generate continuous current impacts, the output ripple deteriorates sharply, and the power switching transistors also bear additional thermal stress. Therefore, a positive feedback resistor is connected between the non-inverting input terminal and the output terminal of each comparator unit in the window comparator array, so that the upper limit reference voltage and the lower limit reference voltage form voltage hysteresis respectively. The specific implementation is as follows: In each comparator unit of the window comparator array, a positive feedback resistor with a resistance of 1 megohm is connected between the non-inverting input and the output terminal; an input resistor with a resistance of 100 kilohm is connected in series between the non-inverting input and the signal input terminal; the comparator is supplied with a power supply voltage of 5 volts, the high-level output voltage is approximately 5 volts, and the low-level output voltage is approximately 0 volts.

[0037] The quantitative analysis of the hysteresis voltage is as follows: When the comparator output is low (0V), the 1-megaohm positive feedback resistor and the 100-kiloohm input resistor form a parallel network. The equivalent voltage at the non-inverting input is the value of the input signal after voltage division by the input resistor. At this time, the threshold voltage is equal to the reference voltage setting itself. When the input signal rises above the threshold and the comparator output flips to a high (5V), the positive feedback resistor is connected between the 5V output and the non-inverting input, forming a voltage divider relationship with the 100-kiloohm input resistor. According to the superposition principle, the voltage at the non-inverting input is equal to the component of the input signal acting alone plus the component of the output feedback acting alone. The output feedback component is equal to 5V multiplied by the input resistance divided by the input resistance plus the positive feedback resistor, which is equal to 5V multiplied by 100-kiloohm divided by... 100 kilohms plus 1 megahm equals approximately 0.45 volts. This means that after the comparator output flips to a high level, the equivalent threshold at the non-inverting input is raised by about 0.45 volts. The current envelope signal needs to drop to a new threshold about 0.45 volts lower than the original threshold before the comparator flips to a low level again. Similarly, when the comparator flips from a high level to a low level, the equivalent threshold at the non-inverting input is lowered by about 0.45 volts, and the signal needs to rise above the raised threshold again before it can flip again. The aforementioned 0.45-volt hysteresis window is much larger than the typical amplitude of tens of millivolts of ripple fluctuation superimposed on the current envelope signal, ensuring that the current envelope signal will not repeatedly cross the threshold due to small ripples. The generation and removal of the phase-triggered signal both have clear hysteresis characteristics.

[0038] By employing the aforementioned technical means, the voltage hysteresis window effectively avoids the frequent phase-cutting ringing phenomenon caused by fluctuations in the current envelope signal near the threshold, thereby improving the system's operational stability and reliability. It also avoids the output ripple degradation and additional thermal stress on the power switching transistors caused by frequent phase-cutting, ensuring the continuous stability of ultra-low ripple output.

[0039] Considering the need to generate a gradually changing reference voltage with a fixed slope through a controllable charging and discharging process, and given that an RC charging and discharging network utilizes the physical charging and discharging characteristics of resistors and capacitors to generate an exponentially changing voltage waveform whose slope is determined only by the resistance and capacitance values, is unaffected by external conditions, and exhibits high stability, analog switches possess the advantages of low on-resistance (typically in the hundreds of ohms), high off-resistance, high switching speed (typically in the nanoseconds), and simple control. Therefore, the RC charging and discharging switching network includes a first analog switch and a second analog switch. When the first analog switch receives an increasing phase trigger signal, it outputs the voltage across the capacitor in the charging process within the RC charging and discharging switching network as the first gradually changing reference voltage. When the second analog switch receives a decreasing phase trigger signal, it outputs the voltage across the capacitor in the discharging process within the RC charging and discharging switching network as the second gradually changing reference voltage. The specific implementation method is as follows: The RC charge / discharge switching network includes a charging resistor, a discharging resistor, a charging / discharging capacitor, a first analog switch, and a second analog switch. One end of the charging resistor is connected to a 5V high-precision reference voltage, and the other end is connected to the input terminal of the first analog switch. One end of the discharging resistor is grounded, and the other end is connected to the input terminal of the second analog switch. The output terminals of the first and second analog switches and the first terminal of the charging / discharging capacitor are connected together, and this common connection node serves as the output terminal of the RC charge / discharge switching network. The second terminal of the charging / discharging capacitor is grounded. The controlled terminal of the first analog switch receives an increasing phase trigger signal, and the controlled terminal of the second analog switch receives a decreasing phase trigger signal.

[0040] The resistance values ​​of both the charging and discharging resistors are selected as 100 kΩ, and the capacitance value of the charging and discharging capacitors is selected as 100 nanofarads. The charging time constant is 100 kΩ multiplied by 100 nanofarads, which equals 10 microseconds, and the discharging time constant is also 10 microseconds. The cutoff frequency corresponding to the 10 microsecond time constant is approximately 16 kHz, which is much lower than the switching frequency of 1 MHz. The low-pass characteristic makes the capacitor voltage unable to respond quickly to changes in the switching frequency. The capacitor voltage is almost constant within each switching cycle, but it can change smoothly over several switching cycles, meeting the requirements of phase-cutting soft transition for gradual change speed.

[0041] When the phase-increase trigger signal is received, the first analog switch closes and the second analog switch opens; the 5-volt reference voltage charges the charging capacitor through the charging resistor, and the voltage across the capacitor rises exponentially; in the first 10 microseconds of the rise process, that is, within one time constant, the capacitor voltage rises from zero to 63% of 5 volts, or about 3.15 volts; after about 2.3 time constants, or 23 microseconds, the capacitor voltage rises to 90% of 5 volts, or 4.5 volts; during this rise process, the capacitor voltage is the first gradually changing reference voltage, which is output to the reference voltage input of the pulse width modulation comparator of the newly selected phase, so that the duty cycle of this phase increases smoothly.

[0042] When the phase reduction trigger signal is received, the second analog switch closes and the first analog switch opens; the charging and discharging capacitor discharges to ground through the discharge resistor, and the voltage across the capacitor decreases exponentially; the time characteristics of the decreasing process are symmetrical to the rising process; the capacitor voltage is the second gradually changing reference voltage, which is output to the reference voltage input of the pulse width modulation comparator of the phase to be turned off, so that the duty cycle of that phase is smoothly reduced to zero.

[0043] In practical circuits, the initial state reset of the capacitor also needs to be considered. When the phase-increasing trigger signal arrives, the charging and discharging capacitor may already be at a non-zero voltage in some previous state. Direct charging at this time will cause the output voltage to rise from zero, thus reducing the soft transition effect. Therefore, before each phase-increasing trigger signal is effective, a narrow pulse reset signal generated by a monostable multivibrator is added. This reset signal controls a reset analog switch connected in parallel with the charging and discharging capacitor to close briefly, discharging the voltage across the capacitor to zero before starting charging. This reset circuit is a conventional design for those skilled in the art and will not be elaborated here.

[0044] The aforementioned techniques allow for precise control of the rising and falling slopes of the gradual reference voltage. Furthermore, the time constants for the rising and falling slopes can be independently set via charging and discharging resistors, adapting to different transition rate requirements for increasing and decreasing phases. The structure is simple and easy to implement; the analog switch has no mechanical contacts, ensuring high reliability and fast switching speed, thus guaranteeing the smoothness of the phase-switching process.

[0045] Considering the need to obtain the arithmetic mean of all operating phase current sampling signals as a reference for current sharing control, and using a resistor averaging network composed of equivalent resistors to perform passive averaging based on Kirchhoff's current law, the structure is the simplest, requiring no additional operational amplifier circuit and avoiding bias voltage errors and temperature drift errors of active devices. As long as the resistance values ​​of each resistor are matched, the average value of the input signal can be accurately obtained. Therefore, the resistor averaging network is composed of multiple equivalent resistors, with one end of each equivalent resistor connected to the current sampling signal of each phase, and the other end connected to a common source to output the average current signal. The specific implementation method is as follows: The resistor averaging network consists of four equal resistors with a resistance of 10 kΩ and a precision of 0.1%. The 0.1% resistor precision ensures that the weights of each branch are completely equal, and the calculation error of the averaging operation is within 0.1%. One end of each resistor is connected to the corresponding phase current sampling signal of the four-phase power conversion array, and the other ends of the four resistors are connected together. This common connection node serves as the output terminal of the average current signal.

[0046] Let the four input voltages be V1, V2, V3, and V4, the common node voltage be Vavg, and the resistance of each resistor be R. According to Kirchhoff's current law, under ideal conditions where no external current flows into or out of the common node, the sum of the currents flowing through the four resistors is zero, i.e., (V1-Vavg) / R + (V2-Vavg) / R + (V3-Vavg) / R + (V4-Vavg) / R = 0. Multiplying both sides of the equation by R, we get: (V1-Vavg)(V2-Vavg) + (V3-Vavg) + (V4-Vavg) = 0. Expanding the parentheses, we get: V1 + V2 + V3 + V4 - 4 × Vavg = 0. Rearranging, we get: 4 × Vavg = V1 + V2 + V3 + V4, i.e., Vavg = (V1 + V2 + V3 + V4) / R. 4) / 4, therefore, the voltage Vavg of the common node is exactly equal to the arithmetic mean of the four input voltages. The above derivation can be extended to any number of phases N. When the number of working phases is N, the resistor averaging network contains N equivalent resistors R. The expression for the voltage Vavg of the common node is: Vavg = (V1 + V2 + ... + VN) / N, where V1 to VN are the voltage values ​​of the current sampling signals of each of the N working phases. This formula shows that the output voltage of the resistor averaging network is exactly equal to the arithmetic mean of each input voltage. As a reference for current sharing control, when the phase switching operation changes the number of working phases, the resistors of the non-working phases are disconnected through the analog switch. N in the formula is automatically updated to the current number of working phases. The average current signal always reflects the average current level of each phase in actual working state.

[0047] When phase-switching reduces the number of operating phases, an analog switch needs to disconnect the resistors corresponding to the non-operating phases to prevent the zero signal of the non-operating phases from lowering the average value. For example, when switching from four-phase to three-phase operation, an analog switch disconnects the connection between the resistor corresponding to the off-phase phase and the common connection node. The voltage of the common connection node is automatically adjusted to the average value of the remaining three operating phase voltages. The gating control signal of the analog switch is generated by a decoder from the phase-switching status signal.

[0048] A voltage follower is connected after the common node. The voltage follower is composed of an operational amplifier. Its non-inverting input is connected to the common node, and its inverting input is directly connected to the output. The high input impedance of the voltage follower ensures that the common node is not affected by the input bias current of the subsequent transconductance amplifier, maintaining the operational accuracy of the resistor averaging network. At the same time, the voltage follower provides low output impedance and can drive the non-inverting inputs of four transconductance amplifiers simultaneously without the average current signal amplitude decreasing due to load effects.

[0049] Using the above-mentioned technical means, the average value of the current sampling signal of each phase can be obtained without error. The calculation accuracy depends only on the resistor matching accuracy and is not affected by temperature changes and active device parameter drift. The structure is simple, the cost is low, no additional active computing devices are required, and the reliability is high, providing a precise and stable reference for current sharing control.

[0050] In a multiphase parallel converter, the turn-on times of the switching signals of each phase must be uniformly staggered in time. If the switching transistors of each phase turn on and off simultaneously, the waveforms of the inductor current ripple of each phase are exactly the same, and the total current ripple at the output terminal is equal to the arithmetic sum of the ripple currents of each phase. The ripple amplitude is proportional to the number of phases. For example, in a four-phase parallel connection, the total output ripple under the same-phase drive is four times that of a single-phase ripple. If the driving signals of each phase are uniformly staggered in phase, that is, the turn-on times of each phase are equally distributed within one switching cycle, then the ripple waveforms of the inductor currents of each phase are staggered in phase. When superimposed at the output terminal, the peaks and valleys of the ripples of each phase fill each other, and the theoretical value of the total output current ripple is zero. In actual circuits, due to the different phases of the switching signals, the ripple waveforms of the inductor currents of each phase are staggered in phase. Even slight differences in phase device parameters will not completely cancel out the ripple to zero. However, staggered parallel connection of phases can reduce the total output ripple to a fraction of the single-phase ripple, resulting in a significant reduction. Therefore, this ultra-low ripple power supply control system also includes a phase reversal circuit. The phase reversal circuit consists of a flip-flop chain composed of multiple cascaded bistable flip-flops. The number of stages in the flip-flop chain corresponds to the total number of phases in the multi-phase power conversion array. The clock input of the flip-flop chain is connected to the master clock signal. The flip-flop chain selects the corresponding bit output based on the current operating phase number signal to provide pulse width modulation enable signals for each phase. There is a phase difference between adjacent output signals determined by the clock frequency and the number of flip-flop stages. The specific implementation is as follows: The phase-out circuit uses a cascaded chain of 4 D-type bistable flip-flops to form a ring counter structure, corresponding to the total number of 4 phases. The D input of each D-type flip-flop is connected to the positive Q output of the previous stage, and the D input of the first stage flip-flop is connected to the inverted Q output of the last stage, forming a closed loop. The clock input of the flip-flop chain is connected to the master clock signal. When the rising edge of the clock arrives, the D-type flip-flop transmits the logic state of the D input to the Q output.

[0051] When the master clock signal is continuously input with rising edges, the Q output terminals of each stage of the flip-flop in the flip-flop chain output high-level pulses in sequence. The width of each pulse is equal to one master clock cycle, and the time interval between the rising edges of adjacent bit output pulses is also equal to one master clock cycle. Let the total number of phases be N and the master clock frequency be fclk. Then the phase difference between adjacent bit output signals is equal to 360 degrees divided by N, and the switching frequency fs is equal to fclk divided by N.

[0052] Under the control of the current number of working phases, the output terminals of the corresponding number of flip-flops are selected by analog switch groups. The selection logic is implemented by a combinational logic circuit or lookup table. When there are 4 working phases, the output terminals of all 4 flip-flops Q1 to Q4 are selected. The phase difference between adjacent output signals is 360 degrees divided by 4, which equals 90 degrees. The switching frequency is fclk divided by 4. When there are 3 working phases, the output terminals of Q1, Q2, and Q3 are selected, and the output of Q4 is shielded. The phase difference between adjacent output signals is 360 degrees divided by 3, which equals 120 degrees. When there are 2 working phases, the output terminals of Q1 and Q2 are selected, and the phase difference is 180 degrees. When there is 1 working phase, only the output terminal of Q1 is selected. There is no concept of phase difference in single-phase operation.

[0053] Each phase's pulse width modulation (PWM) drive signal is enabled by the output signal of the corresponding flip-flop through an AND gate. That is, the flip-flop's output signal and the original drive signal from the PWM circuit are simultaneously input to the two inputs of the AND gate. The output of the AND gate is connected to the gate driver of the power switch. When the flip-flop output is high, the corresponding drive signal can be sent to the power switch through the AND gate, and that phase operates normally. When the flip-flop output is low, the AND gate output is blocked to low, and that phase is turned off. This enabling method ensures that the increase or decrease of phase does not change the phase relationship between the remaining operating phases.

[0054] The phase reordering scheme using the aforementioned hardware trigger chain and ring counter structure allows for the adjustment of the phase relationship to be completed instantly at the hardware level with a nanosecond delay. There is no time overhead for software interrupt response, register configuration, and algorithm operation. When the phase-cutting trigger signal is generated, the system can complete the phase relationship readjustment within the same switching cycle without interrupting the normal operation of the power conversion array.

[0055] Through the above technical means, uniform phase misalignment of the driving signals of each phase under different operating phase numbers is achieved, maximizing the cancellation effect of multi-phase current ripple. The total output current ripple can be reduced to one-Nth of that in single-phase operation, where N is the number of operating phases. The phase relationship switching is completed in real time at the hardware level, without affecting the operation continuity of the power conversion array, and reducing the steady-state output ripple under all operating conditions.

[0056] Considering that the output switching frequency of the trigger chain is equal to the clock frequency divided by the number of operating phases, if the master clock frequency remains constant, the equivalent division ratio of the trigger chain will change when the number of operating phases changes due to phase-switching operations, and the switching frequency will change accordingly. For example, if the master clock frequency is fixed at 4 MHz, the switching frequency is 4 divided by 4 equals 1 MHz when operating in four-phase mode; it becomes 4 divided by 3 approximately equals 1.33 MHz when operating in three-phase mode; it becomes 2 MHz when operating in two-phase mode; and it becomes 4 MHz when operating in single-phase mode. The increase in switching frequency will lead to a proportional increase in the switching losses of the power switching transistors, and the drive losses will also increase accordingly, severely compromising the efficiency gain expected by light-load phase-switching. Therefore, the master clock signal is connected to the trigger chain via a variable frequency divider. The division ratio of the variable frequency divider changes synchronously with the number of power phases currently in operation. The specific implementation method is as follows: The variable frequency divider uses a programmable digital frequency divider. Its input clock is a fixed-frequency master clock signal of 4 MHz. The control terminal of the frequency division coefficient receives the current number of working phases signal. The correspondence between the frequency division coefficient and the number of working phases N is as follows: when N equals 4, the frequency division coefficient is 1, and the output clock frequency is 4 MHz; when N equals 3, the frequency division coefficient is 4 / 3, and the output clock frequency is 3 MHz; when N equals 2, the frequency division coefficient is 2, and the output clock frequency is 2 MHz; when N equals 1, the frequency division coefficient is 4, and the output clock frequency is 1 MHz.

[0057] Verify the above parameters: the output clock frequency divided by the number of working phases N is the switching frequency; when N equals 4, 4 MHz divided by 4 equals 1 MHz; when N equals 3, 3 MHz divided by 3 equals 1 MHz; when N equals 2, 2 MHz divided by 2 equals 1 MHz; when N equals 1, 1 MHz divided by 1 equals 1 MHz; it can be seen that the switching frequency is constant at 1 MHz under any number of working phases.

[0058] The output of the variable frequency divider is connected to the clock input of the flip-flop chain, so that the input clock frequency of the flip-flop chain changes synchronously with the number of working phases. The frequency division factor of the variable frequency divider can be switched by a multiplexer, which selects the corresponding output from multiple pre-divided clocks according to the number of working phases signal. The frequency division factor can also be generated by cascading counters, but the multiplexer scheme has a faster response speed and can complete the clock frequency switching within a few nanoseconds after the phase-cutting trigger signal is valid.

[0059] Through the above technical means, the switching frequency is kept constant under all operating conditions, avoiding the increase in switching and driving losses caused by the increase in switching frequency when the number of working phases decreases. This ensures that the efficiency gain brought by phase switching operation is fully preserved, while ensuring the uniformity of the phase difference of each phase driving signal under different numbers of working phases, and maintaining a stable and reliable ripple cancellation effect.

[0060] Considering the different equivalent rated currents per phase under different numbers of operating phases, taking a total load of 40 amps in this embodiment as an example, when all four phases are operating, each phase is rated to carry 10 amps, and the upper limit of the peak current per phase is approximately 15 amps; when switching to three-phase operation, each phase is rated to carry approximately 13.3 amps, and the upper limit of the peak current per phase is approximately 20 amps; if the phase switching threshold is fixed and set to the level when operating with four phases, the current of each phase when operating with three phases is very likely to exceed the phase increase threshold for a long time. Even if the actual load of the phase is far from the rated level when operating with three phases, the phase increase signal will be triggered, causing the number of phases of the system to be unable to be effectively reduced under light load; conversely, if it is fixed to the higher threshold when operating with three phases... If, during four-phase operation, even if a phase is close to overload, phase increase cannot be triggered, and the protection effect fails. This leads to the most serious problem, namely phase-switching oscillation: after phase decrease, the single-phase current immediately exceeds the phase increase threshold, triggering phase increase; after phase increase, the single-phase current falls below the phase decrease threshold, triggering phase decrease. The system repeatedly switches between the two phase count states, completely losing stability. Therefore, this ultra-low ripple power supply control system also includes a reference voltage adjustment component, including a series resistor chain and an analog switching switch group. The analog switching switch group selects the corresponding taps from multiple voltage divider taps of the series resistor chain according to the current number of operating phases and connects them to the upper limit reference voltage and the lower limit reference voltage respectively. The specific implementation method is as follows: The series resistor chain consists of five 10 kΩ resistors of equal value connected in series with a precision of 1%. The upper end is connected to a 5V high-precision reference voltage, and the lower end is grounded. The five resistors in series form four voltage divider taps, numbered from bottom to top as tap 1 to tap 4. The voltage values ​​of each voltage divider tap are as follows: tap 1 is 5V multiplied by 1 divided by 5 equals 1V, tap 2 is 5V multiplied by 2 divided by 5 equals 2V, tap 3 is 5V multiplied by 3 divided by 5 equals 3V, and tap 4 is 5V multiplied by 4 divided by 5 equals 4V.

[0061] The analog switching group consists of two sets of 4-to-1 analog switches, used to select the upper and lower reference voltages respectively. The selection control terminal of the analog switch receives the current operating phase number signal. The selection logic for the upper and lower reference voltages is as follows: When operating in four phases, the rated current of each phase is 10 amps, the phase increase threshold corresponds to approximately 9 amps, and the phase decrease threshold corresponds to approximately 3 amps; the upper limit reference voltage is selected as 2.0 volts corresponding to tap 2, and the lower limit reference voltage is selected as 1.0 volts corresponding to tap 1.

[0062] When operating in three phases, the rated current of each phase is approximately 13.3 amps, the phase increase threshold corresponds to approximately 12 amps, and the phase decrease threshold corresponds to approximately 4 amps. The upper limit reference voltage is selected as an intermediate value between tap 2 and tap 1, approximately 2.5 volts. This intermediate value can be achieved by adding a fine-tuning resistor between tap 2 and tap 1, or by using a higher precision voltage divider tap scheme. The lower limit reference voltage is selected as approximately 1.25 volts.

[0063] When operating in two phases, the rated current of each phase is 20 amps, the phase increase threshold corresponds to approximately 18 amps, and the phase decrease threshold corresponds to approximately 6 amps; the upper limit reference voltage is selected as 3.0 volts corresponding to tap 3, and the lower limit reference voltage is selected as approximately 1.5 volts.

[0064] When operating in single-phase mode, each phase carries the entire load of 40 amps; the upper limit reference voltage is selected as 4.0 volts corresponding to tap 4, and the lower limit reference voltage is selected as 2.0 volts.

[0065] Through the above dynamic configuration, the fewer the number of working phases, the higher the upper and lower limit reference voltages, and the phase cutting threshold is always matched with the rated current carrying capacity of each phase, thus avoiding phase cutting oscillation caused by threshold mismatch.

[0066] Through the above technical means, the phase-cutting threshold is adaptively adjusted according to the number of working phases, and the phase-cutting judgment standard is always reasonably matched with the current system load sharing capacity, avoiding frequent phase-cutting oscillations under light and heavy load conditions, improving the system's working stability and reliability, and ensuring the accuracy and timeliness of phase-cutting decisions under different numbers of working phases.

[0067] Since the output voltage of the auxiliary winding, after peak detection and signal conditioning, needs to match the input common-mode voltage range of the subsequent window comparator array, if the signal exceeds the upper limit of the comparator's input common-mode voltage, the transistor at the comparator's input terminal enters the saturation region, the gain drops sharply, the comparator cannot switch normally or the switching delay increases significantly, resulting in a delayed or missing phase-cutting trigger signal. If the signal is below the lower limit of the comparator's input common-mode voltage, the transistor at the input terminal enters the cutoff region, and the comparator also cannot respond normally. In either case, it leads to an incorrect phase-cutting decision, and the system cannot perform phase-increasing or phase-decreasing operations at the correct time. Therefore, the voltage swing of the current envelope signal across the full load range must be limited to the linear input range of the comparator. Thus, the turns ratio of the auxiliary winding to the corresponding main power inductor is configured such that the maximum voltage value of the current envelope signal does not exceed the upper limit of the input common-mode voltage of the window comparator array, and the minimum voltage value is not lower than the lower limit of the input common-mode voltage of the window comparator array. The specific implementation method is as follows: In this embodiment, the window comparator array uses a rail-to-rail input complementary metal-oxide-semiconductor comparator with a supply voltage of 5 volts. Its upper limit of input common-mode voltage is the supply voltage minus about 0.5 volts, i.e., 4.5 volts, and the lower limit of input common-mode voltage is about 0.5 volts. That is, the effective linear input range of the comparator is 0.5 volts to 4.5 volts.

[0068] The main power inductor has 10 turns in its main power winding, an inductance of 1 microhenry, and a maximum peak current of 15 amps. The auxiliary winding has 1 turn, meaning the turns ratio of the auxiliary winding to the main power inductor is 1:10. In this configuration, when the inductor current reaches its peak of 15 amps, the maximum voltage of the current envelope signal output after the peak detection circuit and signal conditioning circuit of the auxiliary winding is 4.0 volts, which is lower than the common-mode upper limit of 4.5 volts. When the inductor current is at a light load of about 1 amp, the minimum voltage of the current envelope signal is 0.8 volts, which is higher than the common-mode lower limit of 0.5 volts. Therefore, the current envelope signal is always within the linear input range of the comparator across the entire load range.

[0069] If comparators with different common-mode ranges are selected, the turns ratio needs to be adjusted accordingly. For example, if a comparator with a common-mode upper limit of 3.3 volts is selected, the turns ratio should be adjusted to about 1:15 to reduce the maximum amplitude of the current envelope signal. If a comparator with a higher common-mode lower limit is selected, the turns ratio needs to be appropriately reduced to ensure that the light load signal does not drop below the lower limit. Those skilled in the art can determine the optimal turns ratio through simulation or experiment based on the parameters of the actual selected device.

[0070] The above technical solution ensures that the current envelope signal is always within the linear input range of the comparator across the entire load range, avoiding comparator failure caused by signal saturation or cutoff, and ensuring the reliability and accuracy of phase-cutting decisions. This protection mechanism does not rely on additional limiting circuits and can be achieved simply by adjusting the turns ratio design parameter. The structure is simple and does not increase the number of components or cost.

[0071] Considering that if the rise duration of the gradual reference voltage is shorter than one switching cycle, it means that within a single switching cycle, the reference voltage jumps from zero to its steady-state value. This jump causes a significant change in the pulse width modulation duty cycle within that cycle, resulting in a rapid change in the inductor current within one cycle. According to the basic volt-second balance principle of inductors, the change in inductor current is equal to the time integral of the voltage across the inductor divided by the inductance value. The sudden and significant increase in the duty cycle leads to excessive magnetic energy stored in the inductor during conduction, causing the inductor current to overshoot within this cycle, exceeding the steady-state value. This current overshoot generates a transient voltage spike across the equivalent series resistance of the output capacitor, i.e., a phase-increasing transient ripple. In addition, the current overshoot may also trigger the current protection circuit, causing the newly added phase to be mistakenly turned off, and the system cannot complete the phase-switching operation normally. Therefore, a sufficient rise duration is necessary to ensure that the duty cycle changes slowly and the inductor current is established smoothly. Therefore, the rise duration of the first gradual reference voltage is longer than one complete switching cycle of the multiphase power converter array. The specific implementation method is as follows: In this embodiment, the switching cycle is 1 microsecond, the charging resistor of the RC charging and discharging switching network has a resistance of 100 kiloohms, the charging and discharging capacitor has a capacitance of 100 nanofarads, and the charging time constant is 100 kiloohms multiplied by 100 nanofarads, which equals 10 microseconds. According to the RC circuit charging curve, it takes 1 time constant, or 10 microseconds, for the capacitor voltage to rise from zero to 63% of the steady-state value of 5 volts, about 2.3 time constants, or 23 microseconds, for 90% of the voltage, and about 3 time constants, or 30 microseconds, for 95% of the voltage. Therefore, the duration of the rise of the first gradually changing reference voltage is about 23 to 30 microseconds, which is much longer than the 1-microsecond switching cycle.

[0072] Under the above parameter configuration, the change in the first gradually changing reference voltage within 1 microsecond of a single switching cycle can be estimated by the slope of the RC charging curve. In the initial stage of the charging process, the slope is the highest, approximately 5 volts divided by the time constant 10 microseconds equals 0.5 volts per microsecond. After the first microsecond, the capacitor voltage rises from zero to approximately 0.5 volts, which is only ten percent of the steady-state value of 5 volts. The corresponding pulse width modulation duty cycle of this cycle will not exceed ten percent, and the inductor current slowly builds up from zero. The current increment within one cycle is limited to a safe range. As subsequent cycles progress, the reference voltage increment of each cycle gradually decreases, the duty cycle increases steadily, and the inductor current smoothly climbs to the steady-state value. There is no current overshoot during the entire transition process.

[0073] It should be noted that a longer rise duration is not necessarily better. If the rise duration is too long, for example, reaching hundreds of switching cycles, when the load suddenly increases significantly, the new phase will need a long time to reach the rated output current. The original working phase will be subjected to continuous high current stress during the transition period, which may trigger overcurrent protection or be damaged due to a sharp increase in junction temperature. The choice of rise duration needs to strike a balance between smooth transition and dynamic response speed. It is generally recommended that the rise duration cover 10 to 50 switching cycles. The 23 microseconds in this embodiment corresponds to 23 switching cycles, which is in the middle of this recommended range and can meet the needs of most application scenarios.

[0074] Through the above technical means, the first gradual reference voltage rises slowly during the phase-increasing process, the pulse width modulation duty cycle changes smoothly, and the inductor current is established smoothly without overshoot. This eliminates the current step during the phase-increasing transient and the resulting transient voltage spike at the output terminal, thus suppressing the transient ripple during the phase-increasing process from its source. At the same time, the transition process of the new phase is also kept at a sufficiently fast response speed, so as not to affect the system's timely response to load changes.

[0075] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. An ultra-low ripple power supply regulation system, characterized in that, include: The phase current signal acquisition module includes an auxiliary winding magnetically coupled to the main power inductors of each phase in the multiphase power conversion array, and a peak detection circuit connected to the output terminal of the auxiliary winding. The peak detection circuit outputs a current envelope signal characterizing the peak value of the inductor current of each phase. The phase-cutting decision and execution module includes a window comparator array and an RC charge-discharge switching network. The input terminal of the window comparator array receives the current envelope signal, and its reference input terminal is connected to an upper limit reference voltage and a lower limit reference voltage, respectively. When the current envelope signal of any phase is higher than the upper limit reference voltage, it outputs a phase-increasing trigger signal, and when it is lower than the lower limit reference voltage, it outputs a phase-decreasing trigger signal. The controlled terminal of the RC charge-discharge switching network receives the phase-increasing trigger signal and the phase-decreasing trigger signal respectively. Its output terminal is connected to the reference voltage input terminal of the pulse width modulation comparator of the selected phase. When the phase-increasing trigger signal is received, it outputs a first gradually changing reference voltage with an increasing slope. When the phase-decreasing trigger signal is received, it outputs a second gradually changing reference voltage with a decreasing slope. The current sharing deviation correction module includes a resistance averaging network and a transconductance amplifier array; The input of the resistor averaging network receives the current sampling signals of each phase, and the output of the network outputs the average current signal. Each transconductance amplifier in the transconductance amplifier array receives the corresponding phase current sampling signal and the average current signal, and its output is connected to the reference voltage input of the pulse width modulation comparator of the corresponding phase via an integrating capacitor.

2. The ultra-low ripple power supply control system according to claim 1, characterized in that, The peak detection circuit consists of an operational amplifier, a diode, and a bleed resistor. The non-inverting input of the operational amplifier is connected to the output of the auxiliary winding. The output of the operational amplifier is connected to the anode of the diode. The cathode of the diode is connected to the first end of the bleed resistor and serves as the output of the peak detection circuit. The second end of the bleed resistor is grounded.

3. The ultra-low ripple power supply control system according to claim 1, characterized in that: A positive feedback resistor is connected between the non-inverting input and output terminals of each comparator unit in the window comparator array, causing the upper limit reference voltage and the lower limit reference voltage to form voltage hysteresis respectively.

4. The ultra-low ripple power supply control system according to claim 1, characterized in that, The RC charge / discharge switching network includes a first analog switch and a second analog switch. When the first analog switch receives the phase-increasing trigger signal, it outputs the voltage across the capacitor in the charging process of the RC charge / discharge switching network as the first gradual reference voltage. When the second analog switch receives the phase-decreasing trigger signal, it outputs the voltage across the capacitor in the discharging process of the RC charge / discharge switching network as the second gradual reference voltage.

5. The ultra-low ripple power supply control system according to claim 1, characterized in that, The resistor averaging network consists of multiple equal-value resistors. One end of each equal-value resistor is connected to the current sampling signal of each phase, and the other end is connected to the common resistor to output the average current signal.

6. The ultra-low ripple power supply control system according to claim 1, characterized in that... It also includes a phase reversal circuit, which includes a flip-flop chain composed of multiple cascaded bistable flip-flops. The number of stages of the flip-flop chain corresponds to the total number of phases of the multiphase power conversion array. The clock input of the flip-flop chain is connected to the master clock signal. The flip-flop chain selects the output of the corresponding bit according to the current working phase number signal to provide pulse width modulation enable signals for each phase. There is a phase difference between adjacent bit output signals, which is determined by the clock frequency and the number of flip-flop stages.

7. The ultra-low ripple power supply control system according to claim 6, characterized in that, The master clock signal is connected to the trigger chain via a variable divider, and the division factor of the variable divider changes synchronously with the number of power phases currently in operation.

8. The ultra-low ripple power supply control system according to claim 1, characterized in that, It also includes a reference voltage regulation component, comprising a series resistor chain and an analog switching group, wherein the analog switching group selects corresponding taps from multiple voltage divider taps of the series resistor chain according to the current number of operating phases and connects them to the upper limit reference voltage and the lower limit reference voltage respectively.

9. The ultra-low ripple power supply control system according to claim 1, characterized in that, The turns ratio of the auxiliary winding to the corresponding main power inductor is configured such that the maximum voltage value of the current envelope signal does not exceed the upper limit of the input common-mode voltage of the window comparator array, and the minimum voltage value is not lower than the lower limit of the input common-mode voltage of the window comparator array.

10. The ultra-low ripple power supply control system according to claim 1, characterized in that, The duration of the rise of the first gradually changing reference voltage is longer than one complete switching cycle of the multiphase power conversion array.

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