Low-dropout linear voltage regulator, chip and electronic device

Abstract

The application relates to a low-dropout linear voltage stabilizing circuit, a chip and electronic equipment, wherein the low-dropout linear voltage stabilizing circuit comprises an input end, an output end, an enabling end, an input control module, an output control module, an enabling module and a feedback module; the feedback module is used for outputting a corresponding enabling driving signal according to the size relationship between a preset output voltage and an input voltage; the enabling module is used for inputting an enabling signal and outputting an enabling driving signal according to the enabling signal; the input control module is used for inputting an input voltage and adjusting an output control signal according to the enabling driving signal; and the output control module is used for inputting the input voltage through the input control module and limiting a static current and adjusting an output voltage according to the output control signal and the enabling driving signal, so that the static power consumption performance of the low-dropout linear voltage stabilizing circuit is optimized.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a low dropout linear voltage regulator circuit, chip and electronic device. Background Technology

[0002] A low-dropout linear regulator (LDO) is a low-noise power management chip widely used in electronic systems. Its core function is to provide a stable and clean DC voltage for subsequent circuits. This chip typically consists of basic modules such as an error amplifier, a reference voltage source, a feedback resistor network, and a power transistor as the adjustment element.

[0003] With the increasing prevalence of applications requiring extremely high battery life, such as the Internet of Things (IoT), mobile devices, power tools, and energy storage devices, systems are placing more stringent demands on the energy efficiency of power management chips (PMDs). In battery-powered mobile devices, reducing the power consumption of the LDO itself to extend battery life has become a key research direction. On one hand, reducing power consumption hinges on minimizing the LDO's quiescent current, especially under conditions of high input voltage and large load current, where the shortcomings of traditional LDO architectures in terms of quiescent power consumption become particularly prominent. This type of power consumption deficiency has become a critical bottleneck restricting the overall system energy efficiency and battery life. On the other hand, during operation, if the LDO's input voltage is lower than its set output voltage, a significantly increased quiescent current is typically generated inside the LDO. Therefore, in applications directly powered by batteries, this large quiescent current under abnormal conditions accelerates battery discharge, not only affecting battery life but also potentially damaging battery lifespan and safety. Summary of the Invention

[0004] The purpose of this application is to provide a low dropout linear regulator circuit, chip, and electronic device, which aims to solve the problem of insufficient static power consumption of traditional LDO architecture.

[0005] In a first aspect, embodiments of this application provide a low-dropout linear regulator circuit, including an input terminal, an output terminal, an enable terminal, an input control module, an output control module, an enable module, and a feedback module; The feedback module is connected to the output terminal and the enable module, and is used to output a corresponding enable drive signal according to the relationship between the preset output voltage of the output terminal and the input voltage of the input terminal. When the input voltage is greater than the preset output voltage, a first fixed bias current and a second fixed bias current are output. When the input voltage is less than the preset output voltage, a third bias current is output. The enable drive signal includes the first fixed bias current, the second fixed bias current and the third bias current, and the third bias current is less than the second fixed bias current. The enabling module is connected to the enabling terminal and the feedback module. The enabling module is used to receive the enabling signal and output the enabling drive signal according to the enabling signal. The input control module is connected to the input terminal, the output control module, and the enable module. The input control module is used to receive the input voltage and adjust the output control signal according to the enable drive signal. The output control module is connected to the output terminal, the input control module, and the enable module. The output control module is used to access the input voltage through the input control module and to limit the static current and adjust the output voltage according to the output control signal and the enable drive signal.

[0006] In some embodiments, the feedback module includes: A feedback unit, connected to the output terminal, is used to sample the output voltage and output a feedback voltage; An error amplification unit is connected to the feedback unit and the reference voltage source for the output reference voltage. When the input voltage is greater than the preset output voltage, the error amplification unit outputs a first voltage based on the difference between the feedback voltage and the reference voltage. When the input voltage is less than the preset output voltage, the error amplification unit compares the magnitude of the feedback voltage and the reference voltage and outputs a second voltage representing the magnitude relationship. The reference voltage and the preset output voltage are in a certain proportional relationship. The feedback response unit, connected to the error amplification unit and the enable module, is used to output the first fixed bias current and the second fixed bias current according to the first voltage, and is also used to output the third bias current according to the second voltage.

[0007] In some embodiments, the feedback response unit includes a first switch, a second switch, and a current source; The control terminal of the first switch is connected to the first terminal of the second switch. The first terminal of the first switch is used to output the first fixed bias current, and the second terminal of the first switch is grounded through the current source. The control terminal of the second switch is connected to the output terminal of the error amplification unit. The first terminal of the second switch is used to output the second fixed bias current or the third bias current, and the second terminal of the second switch is grounded.

[0008] In some embodiments, the enabling module includes a third switch and a fourth switch; The control terminals of the third and fourth switches are connected to the enable terminal; the first terminal of the third switch is connected to the input control module, and the second terminal of the third switch is connected to the first terminal of the first switch; the first terminal of the fourth switch is connected to the output control module, and the second terminal of the fourth switch is connected to the first terminal of the second switch.

[0009] In some embodiments, the input control module includes a first resistor, a second resistor, and a fifth switch. A first end of the first resistor is connected to the input terminal, a second end of the first resistor is connected to a first end of the third switch and a control terminal of the fifth switch, a first end of the fifth switch is connected to the input terminal, a first end of the second resistor, and the output control module, and a second end of the fifth switch is connected to a second end of the second resistor and the output control module.

[0010] In some embodiments, the output control module includes a sixth switch, a seventh switch, an eighth switch, a third resistor, and a fourth resistor; The first terminal of the sixth switch is connected to the second terminal of the fifth switch. The second terminal of the sixth switch is connected to the first terminal of the seventh switch and the first terminal of the third resistor. The control terminal of the sixth switch is connected to the control terminal of the eighth switch and the second terminal of the seventh switch. The second terminal of the third resistor is connected to the control terminal of the seventh switch and the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the second terminal of the seventh switch and the first terminal of the fourth switch. The first terminal of the eighth switch is connected to the first terminal of the fifth switch. The second terminal of the eighth switch is connected to the output terminal.

[0011] In some embodiments, the first switch, the second switch, the third switch, and the fourth switch are NMOS transistors; the fifth switch, the sixth switch, the seventh switch, and the eighth switch are PMOS transistors.

[0012] In some embodiments, an output capacitor is further included, wherein a first end of the output capacitor is connected to the output terminal and a second end of the output capacitor is grounded.

[0013] Secondly, embodiments of this application provide a chip including the low-dropout linear regulator circuit described above.

[0014] Thirdly, embodiments of this application provide an electronic device, including the low dropout linear regulator circuit described above or the chip described above.

[0015] The advantages of the embodiments in this application compared with related technologies are: The low-dropout linear regulator circuit of this application includes an input terminal, an output terminal, an enable terminal, an input control module, an output control module, an enable module, and a feedback module. The feedback module is connected to the output terminal and the enable module, and is used to output a corresponding enable drive signal according to the magnitude relationship between the preset output voltage and the input voltage. When the input voltage is greater than the preset output voltage, The system outputs a first fixed bias current and a second fixed bias current. When the input voltage is less than a preset output voltage, it outputs a third bias current. The enable drive signal includes the first fixed bias current, the second fixed bias current, and the third bias current, with the third bias current being less than the second fixed bias current. The enable module is connected to the enable terminal and the feedback module. The enable module is used to receive the enable signal and output an enable drive signal according to the enable signal. The input control module is connected to the input terminal, the output control module, and the enable module. The input control module is used to receive the input voltage and adjust the output control signal according to the enable drive signal. The output control module is connected to the output terminal, the input control module, and the enable module. The output control module is used to receive the input voltage through the input control module and limit the static current and adjust the output voltage according to the output control signal and the enable drive signal. When the input voltage is greater than the preset output voltage, the static current of the input control module and the output control module is set to a fixed value based on the first fixed bias current and the second fixed bias current, so that it does not change with the load. This can effectively reduce the static power consumption of the LDO when the input voltage is greater than the preset output voltage. When the input voltage is less than the preset output voltage, the current from the input control module to the output control module is reduced based on the third bias current, which is less than the second fixed bias current. This can effectively reduce the static power consumption of the LDO when the input voltage is less than the preset output voltage, thereby achieving the static power consumption performance of the wide input range optimized low dropout linear regulator circuit. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a low-dropout linear regulator circuit provided in an embodiment of this application.

[0017] Figure 2 This is a circuit diagram of a low-dropout linear regulator circuit provided in an embodiment of this application. Detailed Implementation

[0018] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0021] like Figure 1 As shown in the figure, this application provides a low dropout linear regulator circuit (hereinafter referred to as LDO), including an input terminal VIN, an output terminal VOUT, an enable terminal EN, an input control module 110, an output control module 120, an enable module 130, and a feedback module 140. VIN, VOUT, and EN also represent the input voltage, output voltage, and enable signal, respectively.

[0022] Feedback module 140 is connected to output terminal VOUT and enable module 130, and is used to output a corresponding enable drive signal according to the relationship between the preset output voltage of output terminal VOUT and the input voltage of input terminal VIN. Specifically, when the input voltage is greater than the preset output voltage, a first fixed bias current I1 and a second fixed bias current I2 are output; when the input voltage is less than the preset output voltage, a third bias current I2' is output. The enable drive signal includes the first fixed bias current I1, the second fixed bias current I2, and the third bias current I2', where the third bias current I2' is less than the second fixed bias current I2. Enable module 130 is connected to enable terminal EN and feedback module 140. Enable module 130 is used to receive an enable signal and output an enable drive signal according to the enable signal. Input control module 110 is connected to input terminal VIN, output control module 120, and enable module 130. Input control module 110 is used to receive the input voltage and adjust the output control signal according to the enable drive signal. The output control module 120 is connected to the output terminal VOUT, the input control module 110 and the enable module 130. The output control module 120 is used to receive the input voltage through the input control module 110, and to limit the static current and adjust the output voltage according to the output control signal and the enable drive signal.

[0023] The enable signal is, for example, a high level (e.g., 5V). It is understood that the LDO operates when the enable terminal EN is high. In this embodiment, when the enable terminal EN is high, the enable module 130 is turned on, transmitting the enable drive signal of the feedback module 140 to the input control module 110 and the output control module 120.

[0024] It is understood that quiescent current includes the enable drive signal and the output control signal, as well as other current signals associated with the enable drive signal. In this embodiment, the magnitude relationship between the preset output voltage and the input voltage is associated with the enable drive signal, and the output control signal is adjusted according to the enable drive signal. While adjusting the output voltage, the quiescent current is regulated and limited. Therefore, it is possible to maintain low quiescent current under a wide input voltage range and full load conditions, thereby reducing the power consumption of the LDO.

[0025] Specifically, when the input voltage is greater than the preset output voltage, the static current of the input control module 110 and the output control module 120 is set to a fixed value according to the first fixed bias current I1 and the second fixed bias current I2, so that it does not change with the load. This can effectively reduce the static power consumption of the LDO when the input voltage is greater than the preset output voltage. When the input voltage is less than the preset output voltage, the current from the input control module 110 to the output control module 120 is reduced according to the third bias current I2' which is less than the second fixed bias current I2. This can effectively reduce the static power consumption of the LDO when the input voltage is less than the preset output voltage, thereby achieving the static power consumption performance of the wide input range optimized low dropout linear regulator circuit.

[0026] like Figure 2 As shown, in some embodiments, the feedback module 140 includes a feedback unit 141, an error amplification unit 142, and a feedback response unit 143. The feedback unit 141 is connected to the output terminal VOUT and is used to sample the output voltage and output a feedback voltage VFB. The error amplification unit 142 is connected to the feedback unit 141 and a reference voltage source (not shown) for the output reference voltage VREF. The error amplification unit 142 outputs a voltage signal EA_OUT to the feedback response unit 143 based on the feedback voltage VFB and the reference voltage VREF. When the input voltage is greater than a preset output voltage, the error amplification unit 142 outputs a first voltage based on the difference between the feedback voltage VFB and the reference voltage VREF. When the input voltage is less than the preset output voltage, the error amplification unit 142 compares the magnitudes of the feedback voltage VFB and the reference voltage VREF and outputs a second voltage representing the magnitude relationship. The reference voltage VREF is proportional to the preset output voltage. The feedback response unit 143 is connected to the error amplification unit 142 and the enable module 130. The feedback response unit 143 is used to output a first fixed bias current I1 and a second fixed bias current I2 according to the first voltage, and is also used to output a third bias current I2' according to the second voltage.

[0027] It is understandable that the reference voltage VREF is proportional to the preset output voltage, meaning that the reference voltage VREF represents the preset output voltage. The first voltage is an amplified signal of the difference between the feedback voltage VFB and the reference voltage VREF. The second voltage is a level signal, such as a high-level signal or a low-level signal. In other words, when the input voltage is greater than the preset output voltage, the error amplification unit 142 operates in error amplification mode or operational amplification mode; when the input voltage is less than the preset output voltage, the error amplification unit 142 operates in comparator mode.

[0028] When the input voltage is greater than the preset output voltage, changes in the LDO's load will cause changes in the output voltage, and consequently, the feedback voltage VFB will also change. In conventional technology, the LDO generates a dynamically changing signal based on this load-dependent feedback voltage VFB to control the output voltage to adapt to the load. However, this dynamically changing signal often leads to changes in the quiescent current, resulting in excessive quiescent power consumption. When the input voltage is less than the preset output voltage, conventional technology typically drives the LDO with a significantly increased quiescent current to raise the input voltage to the preset output voltage. In this case, it also leads to excessive quiescent power consumption.

[0029] In response to this, the technical solution of this application embodiment, when the input voltage is greater than the preset output voltage, the feedback response unit 143 outputs a first fixed bias current I1 and a second fixed bias current I2 based on the first voltage, setting the static current to a fixed value so that it does not change with the load, which can effectively reduce the static power consumption of the LDO when the input voltage is greater than the preset output voltage. When the input voltage is less than the preset output voltage, the feedback response unit 143 outputs a third bias current I2' based on the second voltage, and the third bias current I2' is less than the second fixed bias current I2, which can effectively reduce the static power consumption of the LDO when the input voltage is less than the preset output voltage.

[0030] In some embodiments, a first fixed bias current I1 is used to drive the input control unit, causing the switching transistor of the input control unit to operate in the linear region; a second fixed bias current I2 is used to drive the output control unit, causing the switching transistor of the output control unit to operate in the saturation region, thereby allowing the quiescent current of the LDO to operate at a fixed value as a whole, so that the static power consumption of the LDO is limited when the input voltage is greater than the preset output voltage.

[0031] In some embodiments, the third bias current I2' is used to drive the input control unit, increase the impedance of the input control module 110 to the input control signal, and reduce the current of the input control signal, so that the static power consumption of the LDO is limited when the input voltage is less than the preset output voltage.

[0032] In some embodiments, the error amplification unit 142 includes an error amplification device EA, a feedback voltage VFB connected to the inverting input of the error amplification device EA, and a reference voltage source connected to the non-inverting input of the error amplification device EA.

[0033] In some embodiments, the feedback unit 141 includes a first feedback resistor R5 and a second feedback resistor R6, which are connected in series between the output terminal VOUT and ground. The series connection node of the first feedback resistor R5 and the second feedback resistor R6 serves as a feedback output terminal connected to the inverting input terminal of the error amplification device EA.

[0034] In some embodiments, the feedback response unit 143 includes a first switch MN1, a second switch MN2, and a current source A1.

[0035] The control terminal of the first switch MN1 is connected to the first terminal of the second switch MN2. The first terminal of the first switch MN1 is used to output the first fixed bias current I1, and the second terminal of the first switch MN1 is grounded through the current source A1. The control terminal of the second switch MN2 is connected to the output terminal VOUT of the error amplifier unit 142. The first terminal of the second switch MN2 is used to output the second fixed bias current I2 or the third bias current I2', and the second terminal of the second switch MN2 is grounded.

[0036] Among them, the first switch MN1 and the second switch MN2 are NMOS transistors, and the first terminal, the second terminal, and the control terminal of the first switch MN1 and the second switch MN2 are the drain, source, and gate of the NMOS transistor, respectively.

[0037] In some embodiments, the enabling module 130 includes a third switch MN3 and a fourth switch MN4.

[0038] The control terminals of the third switch MN3 and the fourth switch MN4 are connected to the enable terminal EN; the first terminal of the third switch MN3 is connected to the input control module 110, and the second terminal of the third switch MN3 is connected to the first terminal of the first switch MN1; the first terminal of the fourth switch MN4 is connected to the output control module 120, and the second terminal of the fourth switch MN4 is connected to the first terminal of the second switch MN2.

[0039] Among them, the third switch MN3 and the fourth switch MN4 are NMOS transistors, and the first terminal, the second terminal, and the control terminal of the third switch MN3 and the fourth switch MN4 are the drain, source, and gate of the NMOS transistors, respectively.

[0040] In some embodiments, the input control module 110 includes a first resistor R1, a second resistor R2, and a fifth switch MP5. The first end of the first resistor R1 is connected to the input terminal VIN, the second end of the first resistor R1 is connected to the first end of the third switch MN3 and the control terminal of the fifth switch MP5, the first end of the fifth switch MP5 is connected to the input terminal VIN, the first end of the second resistor R2, and the output control module 120, and the second end of the fifth switch MP5 is connected to the second end of the second resistor R2 and the output control module 120.

[0041] Among them, the fifth switch MP5 is a PMOS transistor, and the first terminal, the second terminal, and the control terminal of the fifth switch MP5 are the source, drain, and gate of the PMOS transistor, respectively.

[0042] In some embodiments, the output control module 120 includes a sixth switch MP6, a seventh switch MP7, an eighth switch MP8, a third resistor R3, and a fourth resistor R4.

[0043] The first terminal of the sixth switch MP6 is connected to the second terminal of the fifth switch MP5. The second terminal of the sixth switch MP6 is connected to the first terminal of the seventh switch MP7 and the first terminal of the third resistor R3. The control terminal of the sixth switch MP6 is connected to the control terminal of the eighth switch MP8 and the second terminal of the seventh switch MP7. The second terminal of the third resistor R3 is connected to the control terminal of the seventh switch MP7 and the first terminal of the fourth resistor R4. The second terminal of the fourth resistor R4 is connected to the second terminal of the seventh switch MP7 and the first terminal of the fourth switch MN4. The first terminal of the eighth switch MP8 is connected to the first terminal of the fifth switch MP5. The second terminal of the eighth switch MP8 is connected to the output terminal VOUT.

[0044] The sixth switch MP6, the seventh switch MP7, and the eighth switch MP8 are PMOS transistors. The first terminal, the second terminal, and the control terminal of the sixth switch MP6, the seventh switch MP7, and the eighth switch MP8 are the source, drain, and gate of the PMOS transistor, respectively.

[0045] In some embodiments, the LDO further includes an output capacitor Cout, with a first terminal of the output capacitor Cout connected to the output terminal VOUT and a second terminal of the output capacitor Cout grounded. The output capacitor Cout is used to filter the output voltage.

[0046] When the input voltage is greater than the preset output voltage: Due to the change in load Rload, the output voltage of the LDO changes, and the feedback voltage VFB also changes accordingly. At this time, the error amplifier EA detects the difference between the feedback voltage VFB and the reference voltage VREF. Therefore, it adjusts the output voltage EA_OUT (i.e., the first voltage) to control the gate voltage of the second switch MN2, so that the second switch MN2 operates in the saturation region. After the gate of the second switch MN2 is adjusted by the output voltage EA_OUT, the voltage at its drain generates a bias voltage on the gate of the first switch MN1, causing the first switch MN1 to conduct. The current source A1 can then flow through the first switch MN1 and through the first resistor R1 in the input control module 110. By setting a reasonable resistance value for the first resistor R1, the reasonable voltage drop generated by the current source A1 across the first resistor R1 is provided to the gate of the high-voltage fifth switch MP5 as the bias voltage of the fifth switch MP5, so that the fifth switch MP5 is in the linear region and operates in the on state of the switch. This causes the second resistor R2 to be short-circuited, pulling the source of the sixth switch MP6 to the input voltage through the fifth switch MP5, so that the input voltage supplies power to the sixth switch MP6 through the sixth switch MP6.

[0047] The second switch MN2, controlled by the first voltage output of the error amplifier EA, will generate a certain second fixed bias current I2. The magnitude of the second fixed bias current I2 is obtained by adding the current through the third resistor R3 and the fourth resistor R4 and the current through the seventh switch MP7. By setting reasonable resistance values ​​for the third resistor R3 and the fourth resistor R4, the seventh switch MP7 is made to operate in the saturation region. The fixed value of the drain voltage V1 of the seventh switch MP7 is used to drive the output adjustment eighth switch MP8, and finally the preset output voltage is obtained.

[0048] By employing the above operating method, when the input voltage is greater than the preset output voltage, reasonable resistance values ​​of the third resistor R3 and the fourth resistor R4 are set. This allows the second fixed bias current I2 generated by the second switch MN2 to pass through the third resistor R3 and the fourth resistor R4, causing the seventh switch MP7 to operate in the saturation region and generate a fixed quiescent current: the second fixed bias current I2. This limits the quiescent current of the sixth switch MP6 from changing with the output current of the eighth switch MP8, effectively reducing the static power consumption of the LDO when the input voltage is greater than the set output voltage.

[0049] When the input voltage is less than the set output voltage: In this case, the feedback voltage VFB output by the feedback unit 141 is less than the reference voltage VREF. The output voltage EA_OUT of the error amplifier EA will be high (i.e., the second voltage). The magnitude of this high voltage is the supply voltage of the error amplifier EA, for example, it will not exceed 5V. The high-level input to the gate of the second switch MN2 makes the second switch MN2 work in the linear region, generating the third bias current I2'. The drain of the second switch MN2 will pull down the gate of the first switch MN1 to ground, thereby turning off the branch from the current source A1, the first switch MN1, and the third switch MN3 to the input control module 110. The current source A1 can no longer generate a voltage drop across the first switch MN1 and the third switch MN3. The gate of the fifth switch MP5 will be pulled up to the input voltage by the first resistor R1, causing the fifth switch MP5 to turn off. The source of the sixth switch, MP6, is pulled up to the input voltage through the second resistor R2. By setting a relatively large resistance value for the second resistor R2, the current flowing through the second resistor R2 can be reduced, thereby limiting the magnitude of the third bias current I2' and thus solving the problem of excessive static power consumption of the LDO when the input voltage is less than the preset output voltage.

[0050] Secondly, embodiments of this application provide a chip including the LDO described above.

[0051] Thirdly, embodiments of this application provide an electronic device, including the LDO or the chip described above.

[0052] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A low-dropout linear voltage regulator circuit, characterized in that, It includes input terminals, output terminals, enable terminals, input control modules, output control modules, enable modules, and feedback modules; The feedback module is connected to the output terminal and the enable module, and is used to output a corresponding enable drive signal according to the relationship between the preset output voltage of the output terminal and the input voltage of the input terminal. When the input voltage is greater than the preset output voltage, a first fixed bias current and a second fixed bias current are output; when the input voltage is less than the preset output voltage, a third bias current is output. The enable drive signal includes the first fixed bias current, the second fixed bias current and the third bias current, and the third bias current is less than the second fixed bias current. The enabling module is connected to the enabling terminal and the feedback module. The enabling module is used to receive the enabling signal and output the enabling drive signal according to the enabling signal. The input control module is connected to the input terminal, the output control module, and the enable module. The input control module is used to receive the input voltage and adjust the output control signal according to the enable drive signal. The output control module is connected to the output terminal, the input control module, and the enable module. The output control module is used to access the input voltage through the input control module and to limit the static current and adjust the output voltage according to the output control signal and the enable drive signal.

2. The low-dropout linear voltage regulator circuit as described in claim 1, characterized in that, The feedback module includes: A feedback unit, connected to the output terminal, is used to sample the output voltage and output a feedback voltage; An error amplification unit is connected to the feedback unit and the reference voltage source for the output reference voltage. When the input voltage is greater than the preset output voltage, the error amplification unit outputs a first voltage based on the difference between the feedback voltage and the reference voltage. When the input voltage is less than the preset output voltage, the error amplification unit compares the magnitude of the feedback voltage and the reference voltage and outputs a second voltage representing the magnitude relationship. The reference voltage and the preset output voltage are in a certain proportional relationship. The feedback response unit, connected to the error amplification unit and the enable module, is used to output the first fixed bias current and the second fixed bias current according to the first voltage, and is also used to output the third bias current according to the second voltage.

3. The low-dropout linear voltage regulator circuit as described in claim 2, characterized in that, The feedback response unit includes a first switch, a second switch, and a current source; The control terminal of the first switch is connected to the first terminal of the second switch. The first terminal of the first switch is used to output the first fixed bias current, and the second terminal of the first switch is grounded through the current source. The control terminal of the second switch is connected to the output terminal of the error amplification unit. The first terminal of the second switch is used to output the second fixed bias current or the third bias current, and the second terminal of the second switch is grounded.

4. The low-dropout linear voltage regulator circuit as described in claim 3, characterized in that, The enabling module includes a third switch and a fourth switch; The control terminals of the third and fourth switches are connected to the enable terminal; the first terminal of the third switch is connected to the input control module, and the second terminal of the third switch is connected to the first terminal of the first switch; the first terminal of the fourth switch is connected to the output control module, and the second terminal of the fourth switch is connected to the first terminal of the second switch.

5. The low-dropout linear voltage regulator circuit as described in claim 4, characterized in that, The input control module includes a first resistor, a second resistor, and a fifth switch. The first end of the first resistor is connected to the input terminal, the second end of the first resistor is connected to the first end of the third switch and the control terminal of the fifth switch, the first end of the fifth switch is connected to the input terminal, the first end of the second resistor, and the output control module, and the second end of the fifth switch is connected to the second end of the second resistor and the output control module.

6. The low-dropout linear voltage regulator circuit as described in claim 5, characterized in that, The output control module includes a sixth switch, a seventh switch, an eighth switch, a third resistor, and a fourth resistor; The first terminal of the sixth switch is connected to the second terminal of the fifth switch. The second terminal of the sixth switch is connected to the first terminal of the seventh switch and the first terminal of the third resistor. The control terminal of the sixth switch is connected to the control terminal of the eighth switch and the second terminal of the seventh switch. The second terminal of the third resistor is connected to the control terminal of the seventh switch and the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the second terminal of the seventh switch and the first terminal of the fourth switch. The first terminal of the eighth switch is connected to the first terminal of the fifth switch. The second terminal of the eighth switch is connected to the output terminal.

7. The low-dropout linear voltage regulator circuit as described in claim 6, characterized in that, The first, second, third, and fourth switching transistors are NMOS transistors; the fifth, sixth, seventh, and eighth switching transistors are PMOS transistors.

8. The low-dropout linear regulator circuit as described in any one of claims 1 to 7, characterized in that, It also includes an output capacitor, the first end of which is connected to the output terminal, and the second end of which is grounded.

9. A chip, characterized in that, Includes the low dropout linear regulator circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the low dropout linear regulator circuit as described in any one of claims 1 to 8 or the chip as described in claim 9.

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