Flyback converter and its sampling fault protection circuit and protection method

Abstract

This application provides a flyback converter and its sampling fault protection circuit and method. The flyback converter incorporates a fault detection and protection strategy for insufficient sampling time. This includes using a time window signal generation circuit to generate a time window signal with a second duration after a predetermined blanking time has elapsed for a first duration. A sampling fault judgment circuit determines a sampling error when both the time window signal and a zero-voltage detection signal are simultaneously valid (i.e., a valid zero-voltage detection signal is detected within the validity period of the time window signal). This generates a sampling fault protection signal to trigger sampling fault protection action on the flyback converter, effectively preventing abnormal output voltage drift, reducing the risk of system damage, and enhancing system robustness.

Description

Technical Field

[0001] This application relates to the field of switching power supply technology, specifically to a flyback converter and its sampling fault protection circuit and protection method. Background Technology

[0002] Switching power supplies are common power supply devices widely used in various electronic devices, such as chargers or adapters. They convert input power into the required output voltage and current to meet the operating requirements of the equipment. Isolated converters are widely used in switching power supply applications because they protect the load from high-voltage surges and damage to the input bus, making them widely applicable in telecommunications wireless networks, automotive, and medical equipment. Among various isolated converter topologies, the flyback converter topology, which eliminates the need for an output filter inductor, has a simple circuit structure, output isolation, and low cost, making it a popular choice for end-device applications. The primary-side feedback (PSR) flyback converter, in particular, eliminates the need for a sampling optocoupler, reduces the number of circuit components, and lowers circuit complexity. Its advantages, including simple structure, low cost, and flexible control, make it widely used in the switching power supply field.

[0003] In PSR feedback, the secondary output voltage can be determined by sampling the plateau portion of the drain-source voltage (or drain voltage) waveform of the primary-side main switch using voltage divider resistors and auxiliary windings, or by directly sampling the plateau portion of the waveform. Accurate sampling of the plateau portion of the drain-source voltage waveform of the auxiliary winding or main switch is crucial for control during actual execution.

[0004] In practical applications, due to the non-ideal characteristics of components in the circuit, the drain voltage waveform of the auxiliary winding or main switch may exhibit voltage spikes and resonances at the beginning of its plateau. Direct sampling at this time would cause significant interference. The current conventional method is to set a blanking time (Tblank) after the main switch is turned off, and to prohibit sampling of the plateau voltage during this blanking time. (Refer to...) Figure 3 and Figure 4 The blanking time Tblank corresponds to the time period t1-t2, and the sampling action of the platform voltage of the flyback converter occurs after time t2.

[0005] Figure 3 A schematic diagram of the auxiliary winding voltage waveform of a flyback converter during normal sampling is shown in the relevant technology. Figure 4 A schematic diagram of the auxiliary winding voltage waveform during abnormal sampling is shown in the related technology. Under normal conditions, reference... Figure 3The flyback converter has a sufficient margin in its freewheeling time to ensure that the secondary-side freewheeling does not end within the blanking time Tblank. In this case, the flyback converter can accurately sample the plateau voltage value of the auxiliary winding voltage waveform after the blanking time Tblank ends (i.e., after time t2). However, with the trend towards miniaturization and higher frequency operation of flyback converters, as the switching frequency increases, the freewheeling time becomes shorter. Dynamically, under conditions such as interference or external voltage injection, the system's freewheeling time may be insufficient (i.e., the freewheeling time is less than the preset blanking time Tblank). (Refer to...) Figure 4 Under this operating condition, sampling the auxiliary winding voltage after the blanking time Tblank ends (i.e. after time t2) will result in a low sampled voltage. Under the action of the control loop, the output voltage is prone to abnormally high, which may cause damage to components such as the main switch, RCD snubber circuit or load in the flyback converter. Summary of the Invention

[0006] In view of the above-mentioned technical problems, the purpose of this application is to provide a flyback converter and its sampling fault protection circuit and protection method. In this application, a fault detection and protection strategy for insufficient sampling time is set in the flyback converter. When the ZCB signal is detected within the corresponding time window, it is considered that there is a sampling error and the fault protection action is triggered, including forcibly reducing the switching frequency of the system to prolong the duration of the switching cycle, reduce the transmission power, and avoid the output voltage from being surged.

[0007] According to a first aspect of this application, a sampling fault protection circuit for a flyback converter is provided, comprising:

[0008] The time window signal generation circuit generates a time window signal with a second duration after the first duration following the end of the predetermined blanking time.

[0009] The sampling fault judgment circuit determines whether a sampling fault has occurred based on the time window signal and the zero voltage detection signal. If both the time window signal and the zero voltage detection signal are detected to be valid, a sampling fault protection signal is generated. The sampling fault protection signal is used to trigger the execution of sampling fault protection action for the flyback converter. The zero voltage detection signal becomes valid when the drain voltage / drain-source voltage of the main switch of the flyback converter drops to a first zero voltage detection threshold, or when the auxiliary winding voltage of the flyback converter drops to a second zero voltage detection threshold.

[0010] Optionally, the first duration is equal to the sum of the sampling time and the fall time;

[0011] The sampling time represents the time required to sample the drain voltage / drain-source voltage / auxiliary winding voltage of the main switch transistor, and the fall time represents the time required for the drain voltage / drain-source voltage of the main switch transistor to drop to the first zero voltage detection threshold from the end of the plateau, or for the auxiliary winding voltage to drop to the second zero voltage detection threshold from the end of the plateau.

[0012] Optionally, the time window signal generation circuit includes:

[0013] The first delay circuit, upon receiving a first transition edge signal representing the end time of the blanking time, delays the first transition edge signal by a first delay time and outputs a first trigger signal.

[0014] The second delay circuit, upon receiving the inverted signal of the first transition edge signal representing the end time of the blanking time, delays the inverted signal of the first transition edge signal by a second delay time and outputs the second trigger signal.

[0015] The first AND logic circuit performs AND logic processing on the first trigger signal and the second trigger signal to generate the time window signal;

[0016] Wherein, the first transition edge signal is a falling edge signal, the first delay time is equal to the sum of the first duration and the second duration, and the second delay time is equal to the first duration;

[0017] Alternatively, the first transition edge signal is a rising edge signal, the first delay time is equal to the first duration, and the second delay time is equal to the sum of the first duration and the second duration.

[0018] Optionally, the time window signal generation circuit includes:

[0019] The first delay circuit, upon receiving the inverted signal of the second transition edge signal representing the end time of the blanking time, delays the inverted signal of the second transition edge signal by a third delay time and outputs a first trigger signal, wherein the third delay time is equal to the sum of the first duration and the second duration.

[0020] The second delay circuit, upon receiving a second edge signal representing the end time of the blanking time, delays the second edge signal by a fourth delay time and outputs a second trigger signal, wherein the fourth delay time is equal to the first duration.

[0021] The first AND logic circuit performs AND logic processing on the first trigger signal and the second trigger signal to generate the time window signal.

[0022] Optionally, the sampling fault determination circuit includes:

[0023] The second AND logic circuit performs AND logic processing on the time window signal and the zero voltage detection signal to generate a sampling fault indication signal. The sampling fault indication signal is in a valid state when both the time window signal and the zero voltage detection signal are valid.

[0024] The latch performs latching processing on the sampling fault indication signal and outputs the sampling fault protection signal.

[0025] Optionally, during normal operation of the flyback converter, the sampling fault protection action includes at least one of the following:

[0026] Reduce the switching frequency of the flyback converter;

[0027] The peak current of the flyback converter is reduced by a step value, and the flyback converter turns off the main switch when the primary side current reaches the peak current.

[0028] Optionally, when the flyback converter is in start-up or short-circuit operation, the sampling fault protection action includes at least one of the following:

[0029] Reduce the switching frequency of the flyback converter;

[0030] The peak current of the flyback converter is reduced by a second step value. When the primary side current of the flyback converter reaches the peak current, the main switch is turned off. The second step value is less than the first step value.

[0031] Lower the first zero voltage detection threshold or the second zero voltage detection threshold.

[0032] According to a second aspect of this application, a flyback converter is provided, including a sampling fault protection circuit as disclosed in any embodiment of this application.

[0033] According to a third aspect of this application, a sampling fault protection method for a flyback converter is provided, comprising:

[0034] After the predetermined blanking time has elapsed for a first duration, a time window signal with a second duration is generated.

[0035] The system determines whether a sampling fault has occurred based on the time window signal and the zero-voltage detection signal. If both the time window signal and the zero-voltage detection signal are detected to be valid, a sampling fault protection signal is generated. The sampling fault protection signal is used to trigger the execution of a sampling fault protection action for the flyback converter. The zero-voltage detection signal becomes valid when the drain voltage / drain-source voltage of the main switch of the flyback converter drops to a first zero-voltage detection threshold, or when the auxiliary winding voltage of the flyback converter drops to a second zero-voltage detection threshold.

[0036] Optionally, the first duration is equal to the sum of the sampling time and the fall time;

[0037] The sampling time represents the time required to sample the drain voltage / drain-source voltage / auxiliary winding voltage of the main switch transistor, and the fall time represents the time required for the drain voltage / drain-source voltage of the main switch transistor to drop to the first zero voltage detection threshold from the end of the plateau, or for the auxiliary winding voltage to drop to the second zero voltage detection threshold from the end of the plateau.

[0038] Optionally, during normal operation of the flyback converter, the sampling fault protection action includes at least one of the following:

[0039] Reduce the switching frequency of the flyback converter;

[0040] The peak current of the flyback converter is reduced by a step value, and the flyback converter turns off the main switch when the primary side current reaches the peak current.

[0041] Optionally, when the flyback converter is in start-up or short-circuit operation, the sampling fault protection action includes at least one of the following:

[0042] Reduce the switching frequency of the flyback converter;

[0043] The peak current of the flyback converter is reduced by a second step value, which is smaller than the first step value;

[0044] Lower the first zero voltage detection threshold or the second zero voltage detection threshold.

[0045] The beneficial effects of this application include at least the following:

[0046] The flyback converter and its sampling fault protection circuit and method provided in this application include a time window signal generation circuit and a sampling fault judgment circuit. The time window signal generation circuit generates a time window signal with a second duration after a first duration following the end of a predetermined blanking time. The sampling fault judgment circuit determines the existence of a sampling fault when both the time window signal and the zero-voltage detection signal are detected to be valid simultaneously, i.e., when a valid zero-voltage detection signal is detected within the validity period of the time window signal. At this time, a sampling fault protection signal is generated to trigger the execution of sampling fault protection action for the flyback converter. Compared with existing solutions, the solution in this application is equivalent to setting a fault detection and protection strategy for insufficient sampling time in the flyback converter, which can effectively avoid abnormal high output voltage, thereby reducing the risk of system damage and enhancing system robustness.

[0047] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit this application. Attached Figure Description

[0048] Figure 1 This diagram illustrates the structure of a flyback converter according to an embodiment of this application.

[0049] Figure 2 This diagram illustrates the structure of a sampling fault detection circuit in the primary-side control circuit of a flyback converter according to an embodiment of this application.

[0050] Figure 3 The diagram shows the waveform of the auxiliary winding voltage of a flyback converter during normal sampling in the relevant technology.

[0051] Figure 4 The diagram shows a waveform of the auxiliary winding voltage of a flyback converter during abnormal sampling in related technologies.

[0052] Figure 5 The diagram shows the waveforms of the auxiliary winding voltage sampling signal and the zero-voltage detection signal of the flyback converter during normal sampling, according to an embodiment of this application.

[0053] Figure 6 The diagram shows the waveforms of the auxiliary winding voltage sampling signal and the zero-voltage detection signal of the flyback converter during abnormal sampling according to an embodiment of this application.

[0054] Figure 7 Show Figure 1 Schematic diagrams of the primary current waveforms of the flyback converter under normal output negative voltage and after insufficient time for triggering sampling fault.

[0055] Figure 8 A schematic flowchart of a sampling fault protection method for a flyback converter provided according to an embodiment of this application is shown. Detailed Implementation

[0056] The preferred embodiments of this disclosure are described in detail below with reference to the accompanying drawings, but this disclosure is not limited to these embodiments. This disclosure covers any alternatives, modifications, equivalent methods, and solutions made within the spirit and scope of this disclosure.

[0057] In order to provide the public with a thorough understanding of this disclosure, specific details are described in detail in the following preferred embodiments of this disclosure, but those skilled in the art can fully understand this disclosure without these details.

[0058] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. It should be noted that the drawings are in a simplified form and use non-precise scales, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0059] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0060] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0061] In the description of this application, words such as "exemplary" or "for example" are used to indicate that they are examples, illustrations, or descriptions. Any embodiment described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments. The term "and / or" in this document describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. "Multiple" refers to two or more. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0062] In addition, the same reference numerals in the figures indicate the same or similar structures, so repeated descriptions of them will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive manner. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referred to each other.

[0063] Figure 1 This paper shows a schematic diagram of the flyback converter provided in an embodiment of this application. Of course, the sampling fault protection scheme disclosed in this application can be applied to other applications as well. Figure 1 Besides the conventional flyback converter shown, it can also be applied to other types of flyback converters such as active clamp flyback converters. Furthermore, Figure 1 The peripheral circuits can also be modified according to the actual application.

[0064] like Figure 1 As shown, the flyback converter 100 provided in this application includes: a transformer TR comprising a primary winding Np, a secondary winding Ns and an auxiliary winding Na, a voltage input circuit connected to the primary winding Np, a voltage output circuit connected to the secondary winding Ns, a main switch Q1, a primary control circuit 10 and a rectifier unit Q2.

[0065] In some examples, the voltage input circuit includes a capacitor C1 connected between the input voltage terminal and the primary-side reference ground, and an energy recovery circuit (e.g., including a resistor R2, capacitor C2, and diode D1) connected between the same-named and opposite-named terminals of the primary winding Np. The input voltage terminal receives the input voltage Vin. The input voltage Vin can be obtained by rectifying alternating current or provided by a network cable (in the case of PoE power supply applications). In some other examples, the voltage input circuit also includes at least one of a rectifier circuit and a power factor correction circuit.

[0066] In some examples, the voltage output circuit includes a capacitor Co connected to the output voltage terminal, and the flyback converter 100 provides the output voltage Vout to the load through the output voltage terminal.

[0067] The main switch Q1 is connected between the primary winding Np and the reference ground. In one possible embodiment, the main switch Q1 may be an NMOS field-effect transistor.

[0068] The rectifier unit Q2 is connected between the secondary winding Ns and the voltage output circuit. Optionally, the rectifier unit Q2 is, for example, a rectifier diode or a synchronous rectifier tube.

[0069] The primary-side control circuit 10 is connected to the control terminal of the main switch transistor Q1 and is used to control the switching state of the main switch transistor Q1.

[0070] Figure 1 In the primary-side control circuit 10, there are four pins: VCC, FB, DRV, CS, and GND. Pin VCC is connected to the cathode of diode D2, the first terminal of resistor R1, and the first terminal of capacitor C3. The second terminal of resistor R1 is connected to the input voltage terminal. The anode of diode D2 is connected to the first terminal of auxiliary winding Na. The second terminal of capacitor C3 is connected to the second terminal of auxiliary winding Na and the reference ground. The primary-side control circuit 10 receives the supply voltage through pin VCC. Pin FB is connected to the common connection node of resistors R3 and R4. Resistors R3 and R4 are connected in series between the first and second terminals of auxiliary winding Na. The primary-side control circuit 10 receives the auxiliary winding voltage sampling signal Vaux_FB, which represents the output voltage Vout, through pin FB. Pin GND is connected to the primary-side reference ground and is used to provide a reference ground potential for the primary-side control circuit 10. Pin CS is connected to reference ground via sampling resistor Rcs, which is connected in series with the main switch Q1. The primary-side control circuit 10 receives the primary-side current of the flyback converter (i.e., the inductor current flowing through the primary winding Np of the transformer TR, denoted as i) through pin CS. L The primary-side current sampling signal is used. The DRV pin is connected to the control terminal of the main switch Q1 and is used to provide a drive signal Vgs1 to the main switch Q1. The main switch Q1 is controlled by the drive signal Vgs1 to perform turn-on / turn-off operations. In this embodiment, the primary-side control circuit 10 generates the drive signal Vgs1 based on the auxiliary winding voltage sampling signal Vaux_FB, which characterizes the output voltage, and the primary-side current sampling signal. This includes, but is not limited to: determining the switching frequency and / or peak current of the flyback converter 100 based on the auxiliary winding voltage sampling signal Vaux_FB, controlling the turn-on time of the main switch Q1 based on the indication signal of the flyback converter's switching frequency, and controlling the turn-off of the main switch Q1 when the indication signal that the primary-side current sampling signal has reached the peak current is detected.

[0071] Figure 2 This diagram illustrates the structure of the sampling fault detection circuit in the primary-side control circuit of the flyback converter provided in an embodiment of this application. Figure 2 As shown, in this embodiment, the primary-side control circuit 10 further includes: a blanking time setting circuit 30, a voltage detection circuit 40, and a sampling fault protection circuit 20.

[0072] The blanking time setting circuit 30 receives the drive signal Vgs1 and uses it to determine the turn-off time of the main switch Q1 based on the drive signal Vgs1. After the main switch Q1 is turned off, it generates a blanking time indication signal Vtb with a predetermined blanking time (denoted as Tblank).

[0073] The voltage detection circuit 40 receives the auxiliary winding voltage sampling signal Vaux_FB and compares it with the second zero-voltage detection threshold Vref_zcb after the blanking time Tblank ends. Based on the comparison result, a zero-voltage detection signal ZCB is generated. The zero-voltage detection signal ZCB switches to an active state at point ZCB. Point ZCB represents the moment when the auxiliary winding voltage drops from its plateau voltage to equal the second zero-voltage detection threshold Vref_zcb (e.g., the zero voltage value; however, in practical applications, considering the influence of device parasitics or other factors, it can be set near the zero voltage value, i.e., slightly equal to the zero voltage value), or the moment when the drain-source voltage or drain voltage of the main switch Q1 drops from its plateau voltage to equal the first zero-voltage detection threshold (e.g., the input voltage; however, in practical applications, considering the influence of device parasitics or other factors, it can be set near the input voltage value, i.e., slightly equal to the input voltage value). Therefore, in other embodiments, the drain voltage / drain-source voltage of the main switch Q1 can be sampled and compared with a corresponding first zero-voltage detection threshold (the input voltage is also scaled accordingly when the sampled drain voltage / drain-source voltage is scaled proportionally to obtain this threshold) to obtain the ZCB point. A ZCB signal is typically implemented in PSR controllers. It can be used as a marker of the end of the plateau voltage. However, its occurrence time is a quarter of a resonant cycle later than the end of the plateau voltage, so compensation is required. The zero-voltage detection signal ZCB is, for example, active when high.

[0074] The sampling fault protection circuit 20 further includes a time window signal generation circuit 21 and a sampling fault judgment circuit 22. The time window signal generation circuit 21 generates a time window signal Tw_zcb with a second duration (T2) after a first duration (T1) following the end of a predetermined blanking time Tblank. The sampling fault judgment circuit 22 determines whether a sampling fault has occurred based on the time window signal Tw_zcb and the zero-voltage detection signal ZCB. If both the time window signal Tw_zcb and the zero-voltage detection signal ZCB are detected to be valid simultaneously, a valid sampling fault protection signal Sfp is generated. When valid, the sampling fault protection signal Sfp triggers the execution of a sampling fault protection action (e.g., insufficient sampling time fault protection action) for the flyback converter 100. For example, when a sampling error is detected, the transmission power of the flyback converter 100 can be reduced by forcibly lowering its switching frequency, thus preventing an abnormal increase in the output voltage of the flyback converter 100. Of course, at different operating stages of the flyback converter 100, other sampling fault protection actions can also be triggered to protect the flyback converter 100 from sampling faults. For details, please refer to the following description.

[0075] In this embodiment, the first duration T1 is equal to the sum of the sampling time (denoted as Tsimple) and the fall time (denoted as Tzcb_delay), where the fall time Tzcb_delay is used to compensate for the delay between the ZCB point and the voltage plateau end point. The sampling time Tsimple represents the time required to sample the auxiliary winding voltage, and the fall time Tzcb_delay represents the time required for the auxiliary winding voltage to drop from the plateau end time to the second zero voltage detection threshold Vref_zcb. In other embodiments, the sampling time Tsimple can also represent the time required to sample the drain voltage / drain-source voltage of the main switch Q1, and the fall time Tzcb_delay can also represent the time required for the drain voltage / drain-source voltage of the main switch Q1 to drop from its plateau end time to the first zero voltage detection threshold. The plateau value described herein (corresponding to the plateau voltage mentioned above) represents the voltage value corresponding to the straight line of the approximately horizontal portion of the auxiliary winding voltage waveform or the drain voltage or drain-source voltage waveform of the main switch Q1 during the secondary freewheeling time of the transformer TR.

[0076] Figure 2In the circuit, the time window signal generation circuit 21 further includes: an inverter 211, a first delay circuit 212, a second delay circuit 213, and a first AND logic circuit 214. The input terminal of the inverter 211 is connected to the input terminal of the first delay circuit 212 to receive the blanking time indication signal Vtb. The output terminal of the inverter 211 is connected to the output terminal of the second delay circuit 213. The first input terminal and the second input terminal of the first AND logic circuit 214 are respectively connected to the output terminals of the first delay circuit 212 and the second delay circuit 213.

[0077] exist Figure 2 In the illustrated embodiment, the first delay circuit 212 is configured to delay the first transition edge signal, representing the end time of the blanking time Tblank, by a first delay time before outputting a first trigger signal upon receiving the first transition edge signal. The second delay circuit 213 is configured to delay the inverted signal of the first transition edge signal, representing the end time of the blanking time Tblank, by a second delay time before outputting a second trigger signal upon receiving the inverted signal of the first transition edge signal, representing the end time of the blanking time Tblank. The first AND logic circuit 214 performs AND logic processing on the first trigger signal and the second trigger signal to generate a time window signal Tw_zcb. The first delay time is equal to the sum of the first duration T1 and the second duration T2, and the second delay time is equal to the first duration T1. For example, when the high-level duration of the blanking time indicator signal Vtb is used to indicate the blanking time Tblank, the falling edge of the blanking time indicator signal Vtb can be used as the first transition edge signal representing the end time of the blanking time Tblank.

[0078] Furthermore, when the low-level duration of the blanking time indicator signal Vtb is used to indicate the blanking time Tblank, the rising edge of the blanking time indicator signal Vtb can also be used as the transition edge signal characterizing the end time of the blanking time Tblank. In this case, the aforementioned first delay time will be set to be equal to the first duration T1, and the aforementioned second delay time will be set to be equal to the sum of the first duration T1 and the second duration T2. ​​Alternatively, it is also possible to... Figure 2The time window signal generation circuit 21 shown is modified into the following structure (not shown): the input terminal of inverter 211 is connected to the input terminal of second delay circuit 213 to receive blanking time indication signal Vtb; the output terminal of inverter 211 is connected to the input terminal of first delay circuit 212; the first input terminal and the second input terminal of first AND logic circuit 214 are respectively connected to the output terminals of first delay circuit 212 and second delay circuit 213. Based on this, first delay circuit 212 is configured to delay the inverted signal of second transition edge signal (such as rising edge) representing the end time of blanking time Tblank by a third delay time before outputting a first trigger signal when receiving the inverted signal of second transition edge signal (such as rising edge) representing the end time of blanking time Tblank; second delay circuit 213 is configured to delay the second transition edge signal (such as rising edge) representing the end time of blanking time Tblank by a fourth delay time before outputting a second trigger signal when receiving the second transition edge signal (such as rising edge) representing the end time of blanking time Tblank; first AND logic circuit 214 performs AND logic processing on the first trigger signal and the second trigger signal to generate time window signal Tw_zcb. The third delay time is equal to the sum of the first duration T1 and the second duration T2, and the fourth delay time is equal to the first duration T1.

[0079] Of course, the time window signal generation circuit 21 in this application is not limited to the embodiments described above. In addition to the embodiments described above, the same function can also be achieved through other modifications.

[0080] Optionally, the first delay circuit 212 and the second delay circuit 213 can be implemented digitally or analogically.

[0081] Further, the sampling fault judgment circuit 22 includes a second AND logic circuit 221 and a latch 222. The first input terminal of the second AND logic circuit 221 is connected to the output terminal of the first AND logic circuit 214, and the second input terminal of the second AND logic circuit 221 is connected to the output terminal of the voltage detection circuit 40. The second AND logic circuit 221 performs AND logic processing on the time window signal Tw_zcb and the zero voltage detection signal ZCB to generate a sampling fault indication signal. This sampling fault indication signal is valid when both the time window signal Tw_zcb and the zero voltage detection signal ZCB are simultaneously valid (e.g., both are valid when they are high). The latch 222 latches the sampling fault indication signal and outputs a sampling fault protection signal SfP.

[0082] In some preferred embodiments, the sampling fault detection circuit 22 further includes: resistor R5, resistor C3, and diode D3. The first end of resistor R5 is connected to the output of the second AND logic circuit 221, and the second end of resistor R5 is connected to the input of latch 222. Capacitor C3 is connected between the second end of resistor R5 and reference ground. The anode of diode D3 is connected to the second end of resistor R5, and the cathode of diode D3 is connected to the first end of resistor R5. Resistor R5 and capacitor C3 are used to filter the sampling fault indication signal output by the second AND logic circuit 221, and diode D3 can prevent the latch from erroneously flipping due to the cumulative effect of continuous pulse interference.

[0083] Figure 5 This shows the normal sampling time. Figure 1 A schematic diagram of the waveforms of the auxiliary winding voltage sampling signal and the zero-voltage detection signal. Figure 6 It shows abnormal sampling. Figure 1 A schematic diagram of the waveforms of the auxiliary winding voltage sampling signal and the zero-voltage detection signal. It should be noted that in this invention... Figures 3-6 The waveform of Vaux_FB is proportional to the voltage wave on the auxiliary winding. In other embodiments, when the voltage on the auxiliary winding is negative, a corresponding clamping circuit can be set in the primary control circuit 10. In this case, when the voltage on the auxiliary winding is negative, Vaux_FB will be clamped to a certain value.

[0084] Under normal operating conditions, when the freewheeling time (denoted as Tsw) of the flyback converter 100 is sufficient, the plateau time of the auxiliary winding voltage sampling signal Vaux_FB will continue until after the blanking time Tblank ends, and the plateau time of the auxiliary winding voltage sampling signal Vaux_FB is greater than the sum of the blanking time Tblank and the sampling time Tsimple, such as... Figure 5 As shown, at this time, the time from time t1 (the start of the blanking time Tblank) to the point where the zero-voltage detection signal ZCB switches from the invalid state to the valid state (i.e., time t3) is greater than Tblank + Tsimple + Tzcb_delay. When the freewheeling time Tsw of the flyback converter 100 is insufficient, the plateau time of the auxiliary winding voltage sampling signal Vaux_FB will be less than the blanking time Tblank. At this time, the end time of the plateau time of the auxiliary winding voltage sampling signal Vaux_FB will be within the blanking time Tblank, as shown. Figure 6 As shown, at this time, the time from time t1, when the blanking time Tblank begins, to the ZCB point (i.e., time t3) when the zero voltage detection signal ZCB switches from the invalid state to the valid state is less than Tblank + Tsimple + Tzcb_delay.

[0085] Based on the above principles, combined with Figure 1 , Figure 2 , Figure 5 and Figure 6 During operation, the main switch Q1 is turned off at time t1. The blanking time setting circuit 30 sets the blanking time Tblank starting from time t1, and the blanking time Tblank ends at time t2. The time window signal generation circuit 21 generates a time window signal Tw_zcb with a second duration T2 after the first duration T1 following the end of the blanking time Tblank, based on the blanking time indication signal Vtb output by the blanking time setting circuit 30. That is, after the main switch Q1 is turned off, the time window signal Tw_zcb with a second duration T2 is generated at the end of Tblank+Tsimple+Tzcb_delay. Based on this, the sampling fault judgment circuit 22 determines whether a sampling fault has occurred by detecting whether the time window signal Tw_zcb and the zero voltage detection signal ZCB are simultaneously in a valid state (e.g., whether they are both in a high-level state).

[0086] For example, when the time window signal Tw_zcb and the zero-voltage detection signal ZCB are not simultaneously valid, that is, when no valid zero-voltage detection signal ZCB is detected within the time window corresponding to the time window signal Tw_zcb, such as Figure 5 As shown, if the sampling is normal, an invalid sampling fault protection signal Sfp is generated. When both the time window signal Tw_zcb and the zero-voltage detection signal ZCB are detected to be valid, that is, when a valid zero-voltage detection signal ZCB is detected within the time window corresponding to the time window signal Tw_zcb, as shown... Figure 6 As shown, if a sampling error is detected, a valid sampling fault protection signal Sfp is generated to trigger the sampling fault protection action of the flyback converter 100. It can be understood that this application uses the time window signal Tw_zcb to determine whether a sampling fault has occurred, rather than using a single time point. This effectively avoids malfunctions caused by interference and improves the accuracy of sampling fault detection.

[0087] Furthermore, during normal operation of the flyback converter 100, the sampling fault protection actions triggered by the valid sampling fault protection signal Sfp include: reducing the switching frequency of the flyback converter 100, thereby extending the switching cycle of the flyback converter 100, reducing the transmission power of the flyback converter 100, and preventing voltage rise. Additionally, the peak current of the flyback converter 100 can be reduced by a step value (i.e., reducing the peak current of the flyback converter 100 by a step value while reducing the switching frequency of the flyback converter 100), thus further reducing the transmission power of the flyback converter 100, resulting in lower output voltage Vout and lower stress on the switching transistors. The primary current i of the flyback converter 100... L When the peak current is reached, the main switch Q1 is turned off. Of course, in some other embodiments, when the sampling fault protection signal Sfp is valid, the sampling fault protection action of reducing the peak current of the flyback converter 100 by the first step can also be triggered independently.

[0088] When the flyback converter 100 is in start-up or short-circuit operation, the output voltage Vout of the flyback converter is low or negative. At this time, the zero-voltage detection signal ZCB output by the voltage detection circuit 40 is always valid. Therefore, after the main switch Q1 is turned off, the sampling fault protection circuit 20 will also detect the zero-voltage detection signal ZCB within the time window corresponding to the time window signal Tw_zcb, thus determining that a sampling fault exists and triggering the sampling fault protection action. At this time, the sampling fault protection actions that can be triggered when the sampling fault protection signal Sfp is valid include: reducing the switching frequency of the flyback converter 100, thereby extending the switching cycle of the flyback converter 100 and increasing the freewheeling time Tsw of the flyback converter, thereby reducing the transmission power of the flyback converter 100 and avoiding voltage rise. (Ref. 7) Figure 7 (a) shows Figure 1 A schematic diagram of the primary-side current waveform of a flyback converter under normal output negative voltage. Figure 7 (b) shows Figure 1 A schematic diagram of the primary-side current waveform of a flyback converter after insufficient time to trigger a fault sampling fault and subsequent fault protection action. Figure 7 (a) The freewheeling time of the flyback converter 100 in each switching cycle is Tsw1. Figure 7(b) The freewheeling time of the flyback converter 100 in each switching cycle is Tsw2, where Tsw2 is greater than Tsw1. By increasing the freewheeling time of the flyback converter, the energy consumed by the flyback converter 100 during the freewheeling time can be increased. Therefore, if the switching cycle of the flyback converter 100 is sufficiently large, the energy consumed by the flyback converter 100 during the freewheeling time will be greater than the energy increased during the minimum conduction time. Consequently, in multiple consecutive switching cycles, the primary current i of the flyback converter 100 will... L The inability to accumulate voltage spikes helps reduce the voltage spikes generated when the main switch Q1 is turned off. At the same time, the lower switching frequency can also reduce the thermal stress on the main switch Q1.

[0089] Furthermore, when the flyback converter 100 is in start-up or short-circuit operation, the peak current of the flyback converter 100 can be reduced by a second step (i.e., while reducing the switching frequency of the flyback converter 100, the peak current of the flyback converter 100 is reduced by a second step). This further reduces the transmission power of the flyback converter 100, resulting in lower output voltage Vout and lower stress on the switching transistors. Specifically, the flyback converter 100 has a primary-side current i L When the peak current is reached, the main switch Q1 is turned off. If a sampling fault is detected at the beginning of startup, the system may fail to start normally due to excessive reduction of the peak current. The second step value can be set to be smaller than the first step value, so that the peak current of the flyback converter 100 during startup is greater than the current required by the normal load. Alternatively, the first zero-voltage detection threshold or the second zero-voltage detection threshold Vref_zcb can be reduced to avoid the phenomenon that the zero-voltage detection signal ZCB clock is valid during startup, thus ensuring that the system can start normally.

[0090] Of course, when the flyback converter 100 is in a start-up or short-circuit condition, the sampling fault protection action that can be triggered when the sampling fault protection signal Sfp is valid is not limited to the implementation methods listed above. It may include performing at least one of the following: reducing the switching frequency of the flyback converter 100; reducing the peak current of the flyback converter 100 by a second step value; and reducing the zero voltage detection threshold Vref_zcb.

[0091] Furthermore, this application also provides a sampling fault protection method for a flyback converter. This method can be applied to the sampling fault protection circuit 20 of the flyback converter disclosed in any of the foregoing embodiments. In specific implementation, such as... Figure 8 As shown, the sampling fault protection method includes the following steps:

[0092] Step 810: After a first duration following the end of the predetermined blanking time, a time window signal with a second duration is generated.

[0093] Step 820: Determine whether a sampling fault has occurred based on the time window signal and the zero-voltage detection signal. If both the time window signal and the zero-voltage detection signal are detected to be valid, generate a sampling fault protection signal. The sampling fault protection signal is used to trigger the execution of sampling fault protection action on the flyback converter. The zero-voltage detection signal becomes valid when the drain voltage / drain-source voltage of the main switch of the flyback converter drops to the first zero-voltage detection threshold, or when the auxiliary winding voltage of the flyback converter drops to the second zero-voltage detection threshold.

[0094] For example, in step 820, the first duration is equal to the sum of the sampling time and the fall time, wherein the sampling time represents the time required to sample the drain voltage / drain-source voltage / auxiliary winding voltage of the main switch, and the fall time represents the time required for the drain voltage / drain-source voltage of the main switch to drop to the first zero voltage detection threshold from the end of the platform, or for the auxiliary winding voltage to drop to the second zero voltage detection threshold from the end of the platform.

[0095] During normal operation of the flyback converter, the sampling fault protection action includes at least one of the following: reducing the switching frequency of the flyback converter; reducing the peak current of the flyback converter by a step value; and turning off the main switch when the primary current of the flyback converter reaches the peak current.

[0096] When the flyback converter is in start-up or short-circuit operation, the sampling fault protection action includes at least one of the following: reducing the switching frequency of the flyback converter; reducing the peak current of the flyback converter by a second step value, wherein the second step value is less than the first step value; or reducing the first zero-voltage detection threshold or the second zero-voltage detection threshold.

[0097] It should be noted that the specific implementation of each step in the flyback converter and its sampling fault protection method of the switching power supply described above, as well as the technical effects that can be brought about after implementation, can be found in the relevant content of the flyback converter and its sampling fault protection circuit described in the foregoing embodiments, and will not be repeated here.

[0098] In summary, the flyback converter and its sampling fault protection circuit and method provided in this application are configured to generate a time window signal with a second duration after a first duration following the end of a predetermined blanking time. When both the time window signal and the zero-voltage detection signal are detected to be valid simultaneously, i.e., when a valid zero-voltage detection signal is detected within the validity period of the time window signal, a sampling fault is determined to exist. At this time, a sampling fault protection signal is generated to trigger the execution of the sampling fault protection action of the flyback converter, which effectively avoids abnormal high output voltage, reduces the risk of system damage, and enhances the robustness of the system. At the same time, the sampling fault protection strategy disclosed in the embodiments of this application can also reduce the short-circuit stress of each switch in the system without increasing the cost of additional components.

[0099] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this application and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A sampling fault protection circuit for a flyback converter, comprising: The time window signal generation circuit generates a time window signal with a second duration after the first duration following the end of the predetermined blanking time. The sampling fault judgment circuit determines whether a sampling fault has occurred based on the time window signal and the zero voltage detection signal. If both the time window signal and the zero voltage detection signal are detected to be valid, a sampling fault protection signal is generated. The sampling fault protection signal is used to trigger the execution of sampling fault protection action for the flyback converter. The zero voltage detection signal becomes valid when the drain voltage / drain-source voltage of the main switch of the flyback converter drops to a first zero voltage detection threshold, or when the auxiliary winding voltage of the flyback converter drops to a second zero voltage detection threshold.

2. The sampling fault protection circuit according to claim 1, wherein, The first duration is equal to the sum of the sampling time and the fall time; The sampling time represents the time required to sample the drain voltage / drain-source voltage / auxiliary winding voltage of the main switch transistor, and the fall time represents the time required for the drain voltage / drain-source voltage of the main switch transistor to drop to the first zero voltage detection threshold from the end of the plateau, or for the auxiliary winding voltage to drop to the second zero voltage detection threshold from the end of the plateau.

3. The sampling fault protection circuit according to claim 1 or 2, wherein, The time window signal generation circuit includes: The first delay circuit, upon receiving a first transition edge signal representing the end time of the blanking time, delays the first transition edge signal by a first delay time and outputs a first trigger signal. The second delay circuit, upon receiving the inverted signal of the first transition edge signal representing the end time of the blanking time, delays the inverted signal of the first transition edge signal by a second delay time and outputs the second trigger signal. The first AND logic circuit performs AND logic processing on the first trigger signal and the second trigger signal to generate the time window signal; Wherein, the first transition edge signal is a falling edge signal, the first delay time is equal to the sum of the first duration and the second duration, and the second delay time is equal to the first duration; Alternatively, the first transition edge signal is a rising edge signal, the first delay time is equal to the first duration, and the second delay time is equal to the sum of the first duration and the second duration.

4. The sampling fault protection circuit according to claim 1 or 2, wherein, The time window signal generation circuit includes: The first delay circuit, upon receiving the inverted signal of the second transition edge signal representing the end time of the blanking time, delays the inverted signal of the second transition edge signal by a third delay time and outputs a first trigger signal, wherein the third delay time is equal to the sum of the first duration and the second duration. The second delay circuit, upon receiving a second edge signal representing the end time of the blanking time, delays the second edge signal by a fourth delay time and outputs a second trigger signal, wherein the fourth delay time is equal to the first duration. The first AND logic circuit performs AND logic processing on the first trigger signal and the second trigger signal to generate the time window signal.

5. The sampling fault protection circuit according to claim 1, wherein, The sampling fault detection circuit includes: The second AND logic circuit performs AND logic processing on the time window signal and the zero voltage detection signal to generate a sampling fault indication signal. The sampling fault indication signal is in a valid state when both the time window signal and the zero voltage detection signal are valid. The latch performs latching processing on the sampling fault indication signal and outputs the sampling fault protection signal.

6. The sampling fault protection circuit according to claim 1, wherein, During normal operation of the flyback converter, the sampling fault protection action includes at least one of the following: Reduce the switching frequency of the flyback converter; The peak current of the flyback converter is reduced by a step value, and the flyback converter turns off the main switch when the primary side current reaches the peak current.

7. The sampling fault protection circuit according to claim 6, wherein, When the flyback converter is in start-up or short-circuit operation, the sampling fault protection action includes at least one of the following: Reduce the switching frequency of the flyback converter; The peak current of the flyback converter is reduced by a second step value. When the primary side current of the flyback converter reaches the peak current, the main switch is turned off. The second step value is less than the first step value. Lower the first zero voltage detection threshold or the second zero voltage detection threshold.

8. A flyback converter, comprising: The sampling fault protection circuit as described in any one of claims 1-7.

9. A sampling fault protection method for a flyback converter, comprising: After the predetermined blanking time has elapsed for a first duration, a time window signal with a second duration is generated. The system determines whether a sampling fault has occurred based on the time window signal and the zero-voltage detection signal. If both the time window signal and the zero-voltage detection signal are detected to be valid, a sampling fault protection signal is generated. The sampling fault protection signal is used to trigger the execution of a sampling fault protection action for the flyback converter. The zero-voltage detection signal becomes valid when the drain voltage / drain-source voltage of the main switch of the flyback converter drops to a first zero-voltage detection threshold, or when the auxiliary winding voltage of the flyback converter drops to a second zero-voltage detection threshold.

10. The sampling fault protection method according to claim 9, wherein, The first duration is equal to the sum of the sampling time and the fall time; The sampling time represents the time required to sample the drain voltage / drain-source voltage / auxiliary winding voltage of the main switch transistor, and the fall time represents the time required for the drain voltage / drain-source voltage of the main switch transistor to drop to the first zero voltage detection threshold from the end of the plateau, or for the auxiliary winding voltage to drop to the second zero voltage detection threshold from the end of the plateau.

11. The sampling fault protection method according to claim 9, wherein, During normal operation of the flyback converter, the sampling fault protection action includes at least one of the following: Reduce the switching frequency of the flyback converter; The peak current of the flyback converter is reduced by a step value, and the flyback converter turns off the main switch when the primary side current reaches the peak current.

12. The sampling fault protection method according to claim 11, wherein, When the flyback converter is in start-up or short-circuit operation, the sampling fault protection action includes at least one of the following: Reduce the switching frequency of the flyback converter; The peak current of the flyback converter is reduced by a second step value, which is smaller than the first step value; Lower the first zero voltage detection threshold or the second zero voltage detection threshold.

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