Low-offset comparator that suppresses attenuation of a sampled signal

Abstract

The application discloses a low-offset comparator for inhibiting sampling signal attenuation, relates to the technical field of analog and mixed signal integrated circuit design, and is used for solving the problems of sampling signal amplitude attenuation caused by input parasitic capacitance and sampling capacitance voltage division of a pre-amplification stage of a comparator in the prior art and deterioration of ADC linearity and dynamic range caused by the problems. The low-offset comparator comprises a sample-and-hold enhancement circuit and a subsequent processing circuit, the sample-and-hold enhancement circuit is connected between a sample-and-hold circuit and the subsequent processing circuit, the subsequent processing circuit comprises a pre-amplification stage with an input transistor pair, the sample-and-hold enhancement circuit comprises an input capacitance neutralization network, the input capacitance neutralization network is connected between a differential input end and a differential output end of the pre-amplification stage, is used for generating a feedback capacitance opposite to inherent gate-drain capacitance effect of the input transistor pair, and thus effectively reduces the input capacitance of the pre-amplification stage at a sampling node of the sample-and-hold circuit.

Description

Technical Field

[0001] This invention relates to the field of analog and mixed-signal integrated circuit design technology, and in particular to a low-offset comparator that suppresses sampling signal attenuation. Background Technology

[0002] In high-speed, high-precision analog-to-digital converters, especially in pipelined analog-to-digital converters, the input load of the sample-and-hold circuit stage is a key factor affecting sampling accuracy.

[0003] The preamplifier stage of the comparator introduces a non-negligible input parasitic capacitance, mainly composed of the transistor gate capacitance and gate-drain capacitance Cgd.

[0004] The sampling capacitor is usually set to a small value, because as the front-end load of the pipelined analog-to-digital converter, a large value would increase the design difficulty of the front-end op-amp.

[0005] This parasitic capacitance will form a voltage divider with the sampling capacitor in the sample-and-hold circuit, causing the actual sampled signal amplitude to attenuate, thereby degrading the linearity and dynamic range of the entire ADC.

[0006] Therefore, while employing advanced comparator techniques (such as offset self-calibration), reducing the load on the preceding sampling circuit and ensuring the integrity of the sampled signal has become a key challenge in improving the overall performance of the ADC.

[0007] Therefore, there is an urgent need to provide a more reliable low-offset comparator that can suppress the attenuation of the sampling signal. Summary of the Invention

[0008] The purpose of this invention is to provide a low-offset comparator that suppresses the attenuation of the sampling signal, thereby solving the problem of sample signal amplitude attenuation caused by the voltage division between the input parasitic capacitance and the sampling capacitance of the comparator preamplifier stage in the prior art, and the resulting degradation of ADC linearity and dynamic range.

[0009] To achieve the above objectives, the present invention provides the following technical solution: In a first aspect, the present invention provides a low-offset comparator that suppresses sampling signal attenuation, comprising: Sample-and-hold enhancement circuit and subsequent processing circuit; The sample-and-hold enhancement circuit is connected between the sample-and-hold circuit and the subsequent processing circuit; The subsequent processing circuitry includes a preamplifier stage with input transistor pairs, and the sample-and-hold enhancement circuitry includes an input capacitor neutralization network. The input capacitor neutralization network is connected between the differential input and differential output of the preamplifier stage to generate a feedback capacitor that is opposite to the inherent gate-drain capacitance effect of the input transistor.

[0010] Optionally, the input capacitor neutralization network includes: The first neutralizing capacitor and the second neutralizing capacitor; The first terminal of the first neutralizing capacitor is connected to the first differential input terminal of the preamplifier stage, and the second terminal of the first neutralizing capacitor is connected to the second differential output terminal of the preamplifier stage. The first end of the second neutralizing capacitor is connected to the second differential input terminal of the preamplifier stage, and the second end of the second neutralizing capacitor is connected to the first differential output terminal of the preamplifier stage.

[0011] Optionally, the subsequent processing circuit is a dynamic comparator with offset self-calibration function; The dynamic comparator includes a preamplifier stage, a latch, and an offset self-calibration module connected in sequence; the preamplifier stage is a static amplifier or a dynamic amplifier. The input capacitor neutralization network is independent of offset self-calibration timing and logic, and is used to optimize the signal transmission path during signal tracking or sampling phase.

[0012] Optionally, the offset self-calibration module operates according to a preset clock. During a specific comparison phase, the calibration switch is closed, and the offset information of the amplifier is stored on the calibration capacitor. During the tracking phase, the stored voltage on the calibration capacitor is used to adjust the bias and compensate for the offset.

[0013] Optionally, two switches controlled by a preset phase can be added between the positive and negative terminals of the differential input to establish a feedback path between the input and output terminals, thereby achieving automatic calibration.

[0014] Optionally, when the preset phase is low, the latch operates to compare the results and the offset voltage is stored. When the preset phase is high, the latch does not work, and the static amplifier and the dynamic amplifier work, subtracting the offset voltage to eliminate the offset voltage.

[0015] Optionally, the capacitance values ​​of the first neutralizing capacitor and the second neutralizing capacitor are approximately equal to or less than the inherent gate-drain capacitance of the corresponding transistor.

[0016] Optionally, if there is a deviation in the input and output common mode of the static amplifier, the circuit will automatically adjust its operating state.

[0017] Optionally, the low offset comparator is applied in an analog-to-digital converter, which is a pipelined ADC, wherein each sub-channel or each stage includes the sample-and-hold enhancement circuit.

[0018] Optionally, the input capacitor neutralization network operates continuously, independent of the control of the calibration clock.

[0019] Compared with the prior art, the present invention provides a low-offset comparator that suppresses the attenuation of the sampling signal.

[0020] The system includes a sample-and-hold enhancement circuit and a subsequent processing circuit. The sample-and-hold enhancement circuit is connected between the sample-and-hold circuit and the subsequent processing circuit. The subsequent processing circuit includes a preamplifier stage with input transistor pairs. The sample-and-hold enhancement circuit includes an input capacitor neutralization network. The input capacitor neutralization network is connected between the differential input and differential output of the preamplifier stage to generate a feedback capacitance that is opposite to the inherent gate-drain capacitance effect of the input transistor pairs, thereby significantly reducing the effective input capacitance seen from the preamplifier stage at the sampling node of the sample-and-hold circuit.

[0021] This invention employs an input capacitance neutralization network technique, which significantly reduces the input parasitic capacitance of the preamplifier stage of the low offset comparator and substantially lowers the total input capacitance to ground, thereby suppressing the attenuation of the sampled signal and ensuring the integrity of the sampled signal amplitude.

[0022] Meanwhile, this input capacitor neutralization network can effectively reduce the back kickback noise of the comparator, and can effectively solve the problems of sampling signal attenuation and comparator misalignment in high-speed pipelined analog-to-digital converters.

[0023] In addition, the offset self-calibration module eliminates the DC offset of the comparator, improving the accuracy of the low offset comparator itself.

[0024] Applying this low offset comparator in a pipelined ADC, with each sub-channel or each stage of sample-and-hold enhancement circuitry working together, can improve the accuracy of the entire data conversion system. Attached Figure Description

[0025] The accompanying drawings, which are provided to further illustrate the invention and constitute a part of this invention, are illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention.

[0026] In the attached diagram: Figure 1 This is a schematic diagram of a traditional comparator structure in the prior art; Figure 2 A schematic diagram of a low-offset comparator for suppressing sampling signal attenuation provided by the present invention; Figure 3 A schematic diagram of the structure of the sampling network provided by the present invention, which incorporates a compensation capacitor; Figure 4 The timing diagram for the low offset comparator provided by this invention is shown.

[0027] Figure label: 1-Static amplifier, 2-Dynamic amplifier, 3-Latch. Detailed Implementation

[0028] To facilitate a clear description of the technical solutions of the embodiments of the present invention, the terms "first" and "second" are used in the embodiments of the present invention to distinguish identical or similar items with essentially the same function and effect.

[0029] For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not restricted.

[0030] Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or the order of execution, and that the words "first" and "second" do not necessarily imply that they are different.

[0031] It should be noted that in this invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions.

[0032] Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs.

[0033] To be precise, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a specific way.

[0034] In this invention, "at least one" means one or more, and "more than one" means two or more.

[0035] "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone. A and B can be singular or plural.

[0036] The character " / " generally indicates that the objects before and after it are in an "or" relationship.

[0037] "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items.

[0038] For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0039] In existing technologies, such as Figure 1 As shown, the traditional comparator structure mainly consists of a preamplifier stage ( Figure 1 (the part within the red dashed box) and latch ( Figure 1The right side of the middle section contains two INV parts.

[0040] In traditional structures, the preamplifier stage has input parasitic capacitance, mainly composed of the gate-source capacitance (Cgs) of the transistor. These parasitic capacitances and the sampling capacitor form a voltage divider network. When the input signal is applied to the comparator, due to the presence of parasitic capacitance, the actual signal amplitude applied to the effective input terminal of the preamplifier stage will be less than the original amplitude of the input signal.

[0041] The voltage division effect between the input parasitic capacitance and the sampling capacitance causes the amplitude of the sampled signal to attenuate. For example, during the sampling stage, the input signal is transmitted to the input of the pre-amplification stage through a switched capacitor network. The parasitic capacitance will divert some of the signal charge, resulting in a reduction in the amplitude of the signal that finally reaches the pre-amplification stage for amplification.

[0042] The attenuation of the sampling signal amplitude directly affects the performance of the analog-to-digital converter (ADC). For the ADC, a reduction in the input signal amplitude will narrow the range of signals that it can accurately convert, thereby reducing the dynamic range of the ADC. At the same time, since the effect of parasitic capacitance may be inconsistent under different input signal amplitudes, it will cause the ADC's conversion characteristics to become nonlinear, that is, the linearity will deteriorate, affecting the ADC's ability to accurately convert signals.

[0043] To address the problems in the prior art, the present invention provides a comparator for a high-speed pipelined analog-to-digital converter, which reduces the effective input capacitance through capacitor neutralization and other techniques to ensure the integrity of the sampled signal amplitude.

[0044] Specifically, a low-offset comparator that suppresses the attenuation of the sampled signal.

[0045] The low offset comparator provided by this invention can be widely used in fields such as analog-to-digital converters. This circuit effectively cancels the parasitic capacitance of the input node of the subsequent circuit (especially the comparator with integrated offset self-calibration function) through innovative capacitance neutralization and technology, thereby significantly reducing its load effect on the sample-and-hold circuit, ensuring the integrity of the sampled signal amplitude, and ultimately improving the accuracy of the entire data conversion system.

[0046] To achieve the above objectives, the following detailed description, with reference to the accompanying drawings, provides a low-offset comparator for suppressing sampling signal attenuation provided by the present invention: like Figure 2 As shown, the low offset comparator may include the following structure: Sample-and-hold enhancement circuit and subsequent processing circuit; The sample-and-hold enhancement circuit is connected between the sample-and-hold circuit and the subsequent processing circuit; The subsequent processing circuitry includes a preamplifier stage with input transistor pairs, and the sample-and-hold enhancement circuitry includes an input capacitor neutralization network. The input capacitor neutralization network is connected between the differential input and differential output of the preamplifier stage to generate a feedback capacitor that is opposite to the inherent gate-drain capacitance effect of the input transistor.

[0047] In the above structure, the sample-and-hold enhancement circuit is located between the sample-and-hold circuit and the subsequent processing circuit. It reduces signal attenuation by optimizing the signal transmission path during the sampling and holding stages.

[0048] In one feasible implementation, in practical applications, the sample-and-hold enhancement circuit may include a gate voltage bootstrap switch, a dual-sampling architecture, and bottom plate sampling; the bootstrap capacitor maintains a constant MOSFET gate-source voltage, reduces on-resistance nonlinearity, and improves sampling accuracy; in the dual-sampling architecture, two sets of alternating capacitor arrays achieve two samplings within a single cycle, increasing the sampling frequency; in bottom plate sampling, adjusting the switching timing ensures that the charge injection effect is evenly distributed to both sides of the differential structure, reducing errors.

[0049] The subsequent processing circuit (preamplifier stage) may include at least an input transistor pair and an input capacitor neutralization network. The input transistor pair may adopt a differential structure to reduce signal loss through high input impedance matching. The input capacitor neutralization network may introduce a compensation capacitor between the differential input terminal and the output terminal to form a negative feedback loop and cancel the parasitic effect of the gate-drain capacitance (Cgd).

[0050] For example, by adjusting the phase characteristics through dynamic compensation capacitors, the phase margin can be increased to above a preset threshold to ensure system stability.

[0051] This low offset comparator effectively suppresses signal attenuation and phase delay caused by gate-drain capacitance through a sample-and-hold enhancement circuit and an input capacitor neutralization network. Combined with the high-precision design of the preamplifier stage, it achieves the performance advantages of low offset, low power consumption, high speed and high precision.

[0052] Its application scenarios can cover fields such as high-speed ADC, precision measurement, and signal processing. Its application potential can be further expanded through technologies such as dynamic compensation, noise suppression, and multi-channel synchronization to meet the high-performance requirements of smart grids, 5G communications, and other applications.

[0053] Figure 2The structure includes a sample-and-hold enhancement circuit and a subsequent processing circuit; the sample-and-hold enhancement circuit is connected between the sample-and-hold circuit and the subsequent processing circuit; the subsequent processing circuit includes a preamplifier stage with input transistor pairs, and the sample-and-hold enhancement circuit includes an input capacitor neutralization network; the input capacitor neutralization network is connected between the differential input and differential output of the preamplifier stage to generate a feedback capacitance that is opposite to the inherent gate-drain capacitance effect of the input transistor pairs, thereby significantly reducing the effective input capacitance seen from the preamplifier stage at the sampling node of the sample-and-hold circuit.

[0054] This invention employs an input capacitance neutralization network technique, which significantly reduces the input parasitic capacitance of the preamplifier stage of the low offset comparator and substantially lowers the total input capacitance to ground, thereby suppressing the attenuation of the sampled signal and ensuring the integrity of the sampled signal amplitude.

[0055] Meanwhile, this input capacitor neutralization network can effectively reduce the back kickback noise of the comparator, and can effectively solve the problems of sampling signal attenuation and comparator misalignment in high-speed pipelined analog-to-digital converters.

[0056] based on Figure 2 The structure, and embodiments of this specification also provide Figure 2 The specific components, connections, and operational processes of each structure are explained below.

[0057] As one implementation method, the present invention adds an input capacitor neutralization network.

[0058] The network is connected between the differential input and differential output of the preamplifier stage to generate a feedback capacitance that is opposite to the inherent gate-drain capacitance (Cgd) effect of the input transistor, thereby significantly reducing the effective input capacitance seen from the preamplifier stage at the sampling node of the sample-and-hold circuit.

[0059] Specifically, the input capacitor neutralization network may include: The first neutralizing capacitor and the second neutralizing capacitor; The first terminal of the first neutralizing capacitor is connected to the first differential input terminal of the preamplifier stage, and the second terminal of the first neutralizing capacitor is connected to the second differential output terminal of the preamplifier stage. The first end of the second neutralizing capacitor is connected to the second differential input terminal of the preamplifier stage, and the second end of the second neutralizing capacitor is connected to the first differential output terminal of the preamplifier stage. This cross-coupling structure can efficiently cancel the Miller effect introduced by Cgd.

[0060] In the specific implementation circuit, such as Figure 3 As shown, Figure 3The circuit in the diagram features differential input and differential output. The input section has two pairs of switches, each corresponding to one of the two sets of input signals. The first set of input signals consists of VINP and REFP, connected to capacitor C via a switch. CS One end, C CS The other end is connected to the non-inverting input terminal VIP of amplifier A; the second set of input signals consists of VINN and REFN, and is also connected to capacitor C via a switch. CS The C CS The other end is connected to the inverting input terminal VIN of amplifier A.

[0061] The capacitor C here CS It serves functions such as sampling and preservation.

[0062] Amplifier section: Includes two amplifiers A, each forming a differential amplifier structure; each amplifier has an input capacitor C. gd and C gs Parasitic capacitances are considered, and the amplifier outputs are cross-connected via capacitors C1 and C2. This connection method is related to the circuit's feedback mechanism or frequency compensation, etc. In addition, each amplifier is also connected to a load capacitor C. pd .

[0063] That is, the differential input pair of the preamplifier stage provided in this invention consists of two transistors.

[0064] One transistor receives a first input signal at its gate and its drain is connected to a first output node; the other transistor receives a second input signal at its gate and its drain is connected to a second output node.

[0065] Its inherent gate-drain capacitance is an important factor causing the load effect.

[0066] refer to Figure 3 The preamplifier stage gain is A. Due to the Miller effect, the parasitic capacitance at the input of the preamplifier stage becomes Equation (1): C i =(1+A)C gd (1) Where C i It is the gate-drain capacitance C of the input transistor. gd The parasitic capacitance equivalent to the amplifier input is such that the input capacitance increases to (1+A) times its original value. Typically, A is a large value, thus greatly increasing the parasitic capacitance.

[0067] Generally, the sampling capacitor of a comparator should not be too large, as it will put pressure on the preceding circuitry, especially in pipelined analog-to-digital converters where the preceding stage is usually an operational amplifier. Excessive load will make the design of the operational amplifier a challenge.

[0068] However, the small sampling capacitor causes the voltage at the comparator input terminal to be not full swing, but depends on the voltage division between the sampling capacitor and the parasitic capacitance, which will have a certain impact on the comparison result of the comparator.

[0069] The input capacitor neutralization network includes a first neutralization capacitor and a second neutralization capacitor.

[0070] The first neutralizing capacitor is connected between the gate of the first transistor and the second output node; the second neutralizing capacitor is connected between the gate of the second transistor and the first output node.

[0071] By precisely designing the capacitance values ​​of these two neutralizing capacitors to be approximately equal to or slightly less than the inherent gate-drain capacitance of the corresponding transistor, the parasitic capacitance at the input of the preamplifier stage becomes Equation (2): C in =(1+A)C gd +(1-A)C1 (2) Let C1 = C gd Then you can get C in =2C gd As can be seen, the amplification effect of the pre-amplification stage gain A on the parasitic capacitance is eliminated. Therefore, the input parasitic capacitance is greatly reduced, thereby significantly reducing the total input capacitance to ground at the input node, which in turn suppresses the attenuation of the sampling signal. In addition, this capacitor can also effectively reduce the kickback noise of the comparator.

[0072] That is, the input terminals of the two amplifiers A can be equivalently considered as consisting of differential input pairs of transistors. Taking the input path connected to VIP and VIN as an example, there are two transistors, one of which receives the signal through C at its gate. CS The coupled signal (related to VINP or REFP) has its drain connected to the corresponding output node (related to the output of subsequent cross-connections); the gate of another transistor receives another signal passing through C. CS The coupled signal (related to VINN or REFN) has its drain connected to another output node.

[0073] C in the diagram gd The gate-drain capacitance is inherent to the differential input pair transistors. Due to the amplifier gain A, according to the Miller effect, the gate-drain capacitance C... gd Equivalent to the input of the amplifier, the capacitance C originally located between the transistor gate and drain... gd After Miller effect conversion, the equivalent parasitic capacitance C seen at the input terminal i It becomes (1 + A)C gd .

[0074] As can be seen from formula (1), the capacitance at the input end increases to (1+A) times the original value.

[0075] In practical preamplifier stage circuits, the amplifier gain A is usually set to a relatively large value.

[0076] The subsequent processing circuit is a dynamic comparator with offset self-calibration function; The dynamic comparator includes a preamplifier stage, a latch 3, and an offset self-calibration module connected in sequence; the preamplifier stage is either a static amplifier 1 or a dynamic amplifier 2. The input capacitor neutralization network is independent of offset self-calibration timing and logic, and is used to optimize the signal transmission path during signal tracking or sampling phase.

[0077] The offset self-calibration module operates according to a preset clock. During a specific comparison phase, the calibration switch is closed, and the offset information of the amplifier is stored on the calibration capacitor. During the tracking phase, the stored voltage on the calibration capacitor is used to adjust the bias and compensate for the offset.

[0078] Two switches controlled by a preset phase are added between the positive and negative terminals of the differential input to establish a feedback path between the input and output terminals, thereby achieving automatic calibration.

[0079] When the preset phase is low, the latch operates and compares the results, storing the offset voltage; when the preset phase is high, the latch 3 does not operate, and the static amplifier 1 and the dynamic amplifier 2 operate, subtracting the offset voltage to eliminate the offset voltage.

[0080] Specifically, such as Figure 2 As shown, the offset self-calibration module operates according to its own predetermined timing sequence (e.g., it compares the phase sampling offset and compensates in the next cycle).

[0081] Independent of the existing offset self-calibration timing and logic, the aforementioned input capacitor neutralization network is introduced, specifically for optimizing the signal transmission path during signal tracking / sampling phase.

[0082] Offset calibration mainly refers to calibrating the offset voltage of static amplifier 1. Specifically, at a certain phase, transistors M4 and M5 will be turned on, and at this time, the offset voltage of static amplifier 1 will be stored on the right plate of capacitor Ccs.

[0083] In the next phase, static amplifier 1 operates in amplification mode with M4 and M5 off and signals VINP and VINN on. The offset voltage stored in capacitor Ccs in the previous moment will act on this signal path, which is equivalent to subtracting an offset voltage in advance. Then, since static amplifier 1 itself has an offset voltage, another offset voltage is added, which can cancel out the offset when static amplifier 1 amplifies.

[0084] By adding two neutralizing capacitors to this, I can reduce the parasitic capacitance on the signal path when the static amplifier 1 amplifies the signal (the Miller effect will greatly increase the parasitic capacitance at the input of the static amplifier). This reduction in parasitic capacitance allows the signal to be transmitted with full swing without loss of amplitude, thus ensuring that the comparator can make correct comparisons.

[0085] In other words, the misalignment self-calibration module operates according to its own clock.

[0086] For example, during a specific comparison phase, the calibration switch closes, storing the amplifier's offset information on the calibration capacitor; in the following tracking phase, this stored voltage is used to adjust the bias to compensate for the offset.

[0087] It is important to emphasize that the input capacitor neutralization network operates continuously and passively, independent of the calibration clock, and is always dedicated to improving the AC impedance characteristics seen from the input port to ensure the integrity of the signal during the sampling phase.

[0088] Regarding the offset self-calibration of the amplifier in the comparator, in specific applications, two switching transistors controlled by the Ф2 phase can be added to the VINP and VINN terminals to establish a feedback path between the input and output terminals to achieve automatic calibration.

[0089] like Figure 4 This is the timing diagram of the comparator. When Ф1 is high, latch 3 works to compare the results. At this time, transistors M4 and M5 are turned on, and the offset voltage is stored.

[0090] When Ф2 is high and Ф1 is low, latch 3 does not work. At this time, static amplifier 1 and dynamic amplifier 2 work, subtracting the previous offset voltage, thereby eliminating the offset voltage.

[0091] Among them, static amplifier 1: if there is a deviation in the input and output common mode, the circuit will automatically adjust the working state instead of the pre-planned working state; the amplified signal can speed up the comparison speed of the latch, and the offset will be much smaller, and the greater the gain, the smaller the offset voltage.

[0092] However, if the gain is too high, the bandwidth will decrease, and the comparator speed will slow down.

[0093] Dynamic Amplifier 2: First of all, Dynamic Amplifier 2 has no static power consumption.

[0094] The sizes of M9 and M10 can be designed to be much smaller than those of M7 / M8, which will further reduce parasitic capacitance and reduce the total capacitance of the output nodes.

[0095] In addition, the larger M9 and M10 sizes provide high gain without increasing latch load.

[0096] In addition, kickback noise can cause large spikes in the sampled signal, which can significantly affect the comparison process of the comparator, leading to errors and unstable output.

[0097] In the design, kickback noise is isolated by the on transistors M9 and M10.

[0098] For static amplifier 1 and dynamic amplifier 2, appropriate operational amplifier chips can be selected according to actual design requirements.

[0099] For example, static amplifier 1 can be a high-precision, low-offset operational amplifier chip, while dynamic amplifier 2 can be a high-speed, low-power operational amplifier chip.

[0100] Furthermore, in a specific application, the analog-to-digital converter is a pipelined ADC, where each sub-channel or stage includes the enhancement circuitry to synergistically improve overall performance.

[0101] To test the performance of the entire data conversion system, different analog signals are input, the digital signal output by the ADC is measured, and the linearity and dynamic range of the system are calculated.

[0102] The effective input capacitance is reduced by the input capacitance neutralization network, which ensures the amplitude integrity of the sampled signal; the offset self-calibration module eliminates DC offset and improves the accuracy of the comparator itself. The two complement each other and jointly solve the problem of sampled signal attenuation.

[0103] In this invention, the components can be selected according to actual application requirements. The selection of components is based on the fact that field-effect transistors have advantages such as high input impedance and low noise, making them suitable as input pairs for preamplifier stages.

[0104] Ceramic capacitors are characterized by high precision and good stability, and can meet the requirements of input capacitance neutralization networks for capacitance value accuracy.

[0105] The stability of the film capacitor ensures the accuracy of the offset self-calibration module.

[0106] D flip-flops are commonly used latching elements that can reliably implement signal latching functions.

[0107] Different types of operational amplifier chips can meet the different requirements of static amplifiers and dynamic amplifiers in terms of accuracy, speed, power consumption, etc.

[0108] As an alternative implementation, in specific applications, the first and second neutralizing capacitors can be replaced with variable capacitors.

[0109] The variable capacitor can be a trimmer capacitor, whose capacitance value can be finely adjusted within a certain range.

[0110] In actual circuits, the gate-drain capacitance C of the input transistor pair gd The capacitance may vary slightly due to factors such as process and temperature. Using a variable capacitor allows for fine-tuning of the capacitance value in the input capacitor and neutralization network according to actual conditions, in order to better offset C. gd The introduced Miller effect further optimizes the neutralization effect of input parasitic capacitance.

[0111] The technical solution provided by this invention has at least the following technical effects: 1) Targeted solution to the sampling attenuation problem: The proposal puts forward the application of capacitor neutralization and technology at key nodes that directly interface with the sample-and-hold circuit. The core goal is to reduce the effective input capacitance and ensure the amplitude integrity of the sampled signal. This is a system-level optimization that is independent of and precedes "comparison accuracy".

[0112] 2) Modular integration: The "input capacitor neutralization network" is used as an independent, modularly designed enhancement unit, which is combined with various existing high-performance comparator circuits (especially complex comparators that integrate offset self-calibration, dynamic amplification and other technologies) to form a better overall solution.

[0113] 3) Clear division of technical roles: In the circuit, the offset self-calibration module is responsible for eliminating DC offset and improving the accuracy of the comparator itself; while the input capacitor neutralization network of this invention is responsible for reducing parasitic load on the signal path and improving sampling accuracy; the two are complementary in function and can be designed and controlled independently in terms of timing and circuit structure.

[0114] 4) This invention addresses the system-level bottleneck of sampled signal attenuation caused by parasitic capacitance in subsequent circuits in high-speed ADCs by introducing a simple yet ingeniously designed input capacitor neutralization network.

[0115] This solution, as a "front-end enhancer," can be combined with a variety of advanced comparator core modules that already have functions such as offset self-calibration, to bring significant performance improvements at minimal cost, and has high practical value and broad application prospects.

[0116] 5) The input capacitance neutralization network technology is adopted, which greatly reduces the input parasitic capacitance of the comparator preamplifier stage and significantly reduces the total input capacitance to ground, thereby suppressing the attenuation of the sampling signal and ensuring the integrity of the sampling signal amplitude.

[0117] Meanwhile, this capacitor neutralization network can also effectively reduce the comparator's kickback noise.

[0118] In addition, the offset self-calibration module eliminates the DC offset of the comparator, improving the accuracy of the comparator itself.

[0119] Applying this comparator in a pipelined ADC, with each sub-channel or each stage of sample-and-hold enhancement circuitry working together, can improve the accuracy of the entire data conversion system.

[0120] Although the invention has been described herein in conjunction with various embodiments, other variations of the disclosed embodiments will be understood and implemented by those skilled in the art in carrying out the claimed invention by reviewing the accompanying drawings, the disclosure, and the appended claims.

[0121] In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components.

[0122] A single processor or other unit can perform several of the functions listed in the claims.

[0123] Although different dependent claims describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0124] Although the invention has been described in conjunction with specific features and embodiments thereof, it is obvious that various modifications and combinations may be made therein without departing from the spirit and scope of the invention.

[0125] Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined in the appended claims, and are to be regarded as covering any and all modifications, variations, combinations or equivalents within the scope of the invention.

[0126] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from the spirit and scope of this invention.

[0127] Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A low-offset comparator for suppressing sampling signal attenuation, characterized in that, include: Sample-and-hold enhancement circuit and subsequent processing circuit; The sample-and-hold enhancement circuit is connected between the sample-and-hold circuit and the subsequent processing circuit; The subsequent processing circuitry includes a preamplifier stage with input transistor pairs, and the sample-and-hold enhancement circuitry includes an input capacitor neutralization network. The input capacitor neutralization network is connected between the differential input and differential output of the preamplifier stage to generate a feedback capacitor that is opposite to the inherent gate-drain capacitance effect of the input transistor.

2. The low offset comparator according to claim 1, characterized in that, The input capacitor neutralization network includes: The first neutralizing capacitor and the second neutralizing capacitor; The first terminal of the first neutralizing capacitor is connected to the first differential input terminal of the preamplifier stage, and the second terminal of the first neutralizing capacitor is connected to the second differential output terminal of the preamplifier stage. The first end of the second neutralizing capacitor is connected to the second differential input terminal of the preamplifier stage, and the second end of the second neutralizing capacitor is connected to the first differential output terminal of the preamplifier stage.

3. The low offset comparator according to claim 1, characterized in that, The subsequent processing circuit is a dynamic comparator with offset self-calibration function; The dynamic comparator includes a preamplifier stage, a latch, and an offset self-calibration module connected in sequence; the preamplifier stage is a static amplifier or a dynamic amplifier. The input capacitor neutralization network is independent of offset self-calibration timing and logic, and is used to optimize the signal transmission path during signal tracking or sampling phase.

4. The low offset comparator according to claim 3, characterized in that, The offset self-calibration module operates according to a preset clock. During a specific comparison phase, the calibration switch is closed, and the amplifier's offset information is stored on the calibration capacitor. In phase tracking, the stored voltage on the calibration capacitor is used to adjust the bias and compensate for the offset.

5. The low offset comparator according to claim 3, characterized in that, Two switches controlled by a preset phase are added between the positive and negative terminals of the differential input to establish a feedback path between the input and output terminals, thereby achieving automatic calibration.

6. The low offset comparator according to claim 5, characterized in that, When the preset phase is low, the latch works to compare the results and the offset voltage is stored. When the preset phase is high, the latch does not work, and the static amplifier and the dynamic amplifier work, subtracting the offset voltage to eliminate the offset voltage.

7. The low offset comparator according to claim 2, characterized in that, The capacitance values ​​of the first neutralizing capacitor and the second neutralizing capacitor are approximately equal to or less than the inherent gate-drain capacitance of the corresponding transistor.

8. The low offset comparator according to claim 3, characterized in that, If there is a deviation in the input and output common mode of the static amplifier, the circuit will automatically adjust its operating state.

9. The low offset comparator according to claim 1, characterized in that, The low offset comparator is used in an analog-to-digital converter (ADC) that is a pipelined ADC, wherein each sub-channel or each stage contains the sample-and-hold enhancement circuit.

10. The low offset comparator according to claim 1, characterized in that, The input capacitor neutralization network operates continuously, independent of the calibration clock control.

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