Algalnp red light emitting diode epitaxial and chip manufacturing method and chip

Abstract

The application belongs to the technical field of red light emitting diode epitaxy and chip manufacturing, and particularly relates to an AlGaInP red light emitting diode epitaxy and chip manufacturing method and chip. A buffer layer, an AlInP etching stop layer, an n-type ohmic contact layer, an n-AlInP roughening expansion layer, a waveguide layer, a multi-quantum well layer and a p-type layer are epitaxially grown on a GaAs substrate in sequence. A hole is opened by lithography, and a multilayer p electrode is evaporated in the hole. The epitaxial wafer is low-temperature bonded with a Si substrate on which a metal layer is evaporated, and is cooled in stages. After the substrate is removed, an n electrode pad layer is lithographically evaporated. A light emitting area is formed by etching, the AlInP etching stop layer is segmented and chemically wet roughened, a passivation layer is deposited, and a single device is obtained through thinning, back gold evaporation and laser cutting. The superlattice layer has a capacitive effect, which matches the hole and electron recombination time, reduces the electron leakage rate, the AlInP roughening layer cooperates with the segmented wet roughening process, improves the light extraction efficiency, the low-temperature bonding and the staged cooling effectively release the thermal stress, and improve the reliability.

Description

Technical Field

[0001] This invention belongs to the field of epitaxial growth and chip manufacturing technology of red light-emitting diodes, specifically relating to a method and chip manufacturing process for AlGaInP red light-emitting diode epitaxy and chip manufacturing. Background Technology

[0002] AlGaInP (aluminum gallium indium phosphorus) red light-emitting diodes (LEDs) are important optoelectronic devices widely used in displays, lighting, and signal indication. LEDs are key components in optoelectronics, and red LEDs, as crucial components, are widely used in full-color displays, automotive taillights, medical equipment, and general lighting.

[0003] In the epitaxial growth and chip manufacturing process of red light-emitting diodes, there is a difference in lattice constant between the GaAs substrate and the subsequent epitaxial layer. Generally, a buffer layer is grown at a certain temperature, but this cannot effectively compensate for the lattice mismatch. This results in a large number of defects such as dislocations and stacking faults in the epitaxial layer. These defects can become nonradiative recombination centers of charge carriers, reduce photon radiative recombination efficiency, and affect the device yield.

[0004] Currently, during the MOCVD growth process, the vacuum level of the reaction chamber and the flow rate of the carrier gas need to be controlled. If the reaction gas is not mixed evenly, it will lead to poor uniformity of the thickness of each functional layer. In particular, the thickness deviation of the well barrier layer of the multi-quantum well layer is too large, which further aggravates the dispersion of photoelectric performance.

[0005] Furthermore, the doping process of the ohmic contact layer lacks control, and the doping concentration distribution is uneven, resulting in large fluctuations in contact resistance, which poses a hidden danger of poor contact in electrode fabrication.

[0006] Existing technologies still suffer from multiple problems, including low patterning accuracy, insufficient light extraction efficiency, high device breakage rate, and poor passivation effect. For example, the ICP etching process used for patterning the light-emitting area suffers from unreasonable etching gas ratios, large fluctuations in etching rate, and a lack of means to monitor the etching endpoint, resulting in large deviations in etching depth and insufficient sidewall perpendicularity.

[0007] Improper control of the concentration of the roughening solution and the roughening time in the chip surface roughening process leads to uneven surface roughness. Some areas are over-roughened, resulting in surface damage, while other areas are under-roughened, failing to effectively reduce photon specular reflection and resulting in high photon escape rate, which further reduces light extraction efficiency. Summary of the Invention

[0008] This invention provides an epitaxial growth method and chip manufacturing method for AlGaInP red light-emitting diodes. This invention improves light extraction efficiency and photoelectric performance, reduces leakage current and contact resistance, enhances device reliability and color uniformity, and meets the requirements of high-brightness light-emitting diodes.

[0009] The methods include: S1: An epitaxial layer structure is grown sequentially from bottom to top on a GaAs substrate, including a buffer layer, an AlInP etch stop layer, an n-type ohmic contact layer, an n-type waveguide layer, a multiple quantum well layer, a p-type waveguide layer, and a p-type ohmic contact layer. S2: A SiO2 insulating layer is deposited on the upper surface of the epitaxial wafer by PECVD, and the SiO2 insulating layer is photolithographically etched and etched to form a rectangular array of openings. S3: The p-electrode ohmic contact layer, adhesion layer and metal connection layer are sequentially deposited in the opening of the SiO2 insulating layer, and then subjected to high-temperature annealing. S4: A metal interconnect layer is deposited on the surface of the Si substrate. The epitaxial wafer treated in S3 is bonded to the Si substrate at a low temperature. After bonding, the temperature is reduced in stages to complete the transfer of the epitaxial wafer from the GaAs substrate to the Si substrate. S5: The GaAs substrate is removed by wet etching, which terminates at the AlInP etching stop layer. The upper GaInP layer is removed and the n-type ohmic contact layer is surface treated to expose the n-type conductive layer base for fabricating the n-electrode. S6: The n-electrode pad layer is prepared by photolithography and electron beam evaporation, and then subjected to high-temperature annealing to complete the n-electrode pad preparation and realize the n-type side electrode lead-out of the chip; S7: Through photolithography, ICP etching, chemical wet roughening, passivation layer deposition, chip thinning, back gold evaporation and laser cutting, the chip light-emitting area is patterned, surface roughened, passivated and protected, thickness adjusted and device separated, and finally a red light-emitting diode chip is obtained.

[0010] According to another embodiment of this application, an AlGaInP red light-emitting diode epitaxial layer and chip are provided, including: an epitaxial functional layer assembly, an electrode and bonding assembly, a support substrate assembly, and a passivation and back gold assembly. The epitaxial functional layer assembly is disposed on a temporary growth substrate. The epitaxial functional layer assembly includes: a GaAs substrate, a GaAs buffer layer epitaxially grown on the GaAs substrate, a GaInPAlInP etch stop layer disposed on the GaAs buffer layer, an ohmic contact layer, an n-AlInP roughening and extension layer and an n-(AlGa)InP waveguide layer sequentially stacked on the GaInPAlInP etch stop layer; and a multi-quantum well layer disposed on the n-(AlGa)InP waveguide layer. A p-AlInP extended layer, a p-(AlGa)InP waveguide layer, a p-GaInP transition layer, a p-superlattice layer, a p-(AlGa)InP waveguide layer, a p-GaInP transition layer, and a p-GaP ohmic contact layer are sequentially stacked on top of the multi-quantum well layer. A patterned SiO2 layer is disposed on the surface of the p-GaP ohmic contact layer, and a rectangular array of electrode holes is formed on the SiO2 layer; a p-electrode ohmic contact layer is disposed and filled in the electrode holes, and the p-electrode ohmic contact layer is in direct contact with the p-GaP ohmic contact layer. The supporting substrate assembly includes a Si substrate, on the upper surface of which a metal interconnect layer is disposed; the metal interconnect layers are bonded together by a low-temperature bonding process to form a bonding interface. A passivation layer is formed on the surface of the chip, covering the roughened surface and sidewalls of the n-AlInP roughening and extension layers, and an electrode is exposed by opening a window in the n-electrode pad layer region.

[0011] As can be seen from the above technical solutions, the present invention has the following advantages: The AlGaInP red light-emitting diode epitaxial and chip manufacturing method provided by this invention improves the crystal quality of the epitaxial layer by controlling the growth parameters of each functional layer and preparing a buffer layer using a two-step method of low-temperature nucleation and high-temperature growth, combined with an AlInP etch stop layer and a doped ohmic contact layer.

[0012] This invention employs PECVD low-temperature deposition of a SiO2 insulating layer, combined with segmented pre-baking and BOE buffer etching processes to improve the uniformity of the insulating layer thickness and ensure insulation reliability. Low-temperature metal bonding technology, combined with a staged cooling process, successfully transfers the epitaxial wafer to the Si substrate, reducing residual thermal stress. An etching solution is used to remove the GaAs substrate and GaInP layer. Etching of the ohmic contact layer removes surface oxide and damage layers, ensuring resistivity stability and providing a smooth conductive base for n-electrode fabrication. A Ti / Pt / Au three-layer n-electrode pad layer is fabricated using photolithography and electron beam evaporation, followed by high-temperature annealing to ensure the contact resistance between the pad layer and the n-GaAs layer meets requirements.

[0013] This invention improves chip reliability by using etching, segmented wet roughening, and SiN passivation layer deposition to ensure that the pattern accuracy of the chip's light-emitting area meets requirements, the verticality of the etched sidewalls meets requirements, and laser segmented cutting avoids thermal stress damage. Attached Figure Description

[0014] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the chip; Figure 2Flowchart of the epitaxial growth and chip manufacturing method for AlGaInP red light-emitting diodes; Figure 3 Comparison images to roughen the appearance. Detailed Implementation

[0016] Combination Figure 1 As shown, the chip manufactured by the AlGaInP red light-emitting diode epitaxial and chip manufacturing method provided by the present invention includes an epitaxial functional layer assembly, an electrode and bonding assembly, a support substrate assembly, and a passivation and back gold assembly.

[0017] Specifically, the epitaxial functional layer components are set on a temporary growth substrate. The epitaxial functional layer components include: the bottom layer is a GaAs substrate, which serves as a temporary support substrate for epitaxial growth.

[0018] A GaAs buffer layer is epitaxially grown on a GaAs substrate to eliminate surface defects on the substrate.

[0019] A GaInPAlInP etch stop layer is disposed on top of the GaAs buffer layer to provide an etch stop interface in subsequent substrate removal processes.

[0020] An ohmic contact layer 201, an n-AlInP coarsening and extension layer 202, and an n-(AlGa)InP waveguide layer 203 are sequentially stacked on top of the GaInPAlInP etch stop layer.

[0021] A multi-quantum well layer 204 is disposed on the n-(AlGa)InP waveguide layer 203 as a light-emitting active region.

[0022] A p-AlInP extended layer 205, a p-(AlGa)InP waveguide layer 206, a p-GaInP transition layer 207, a p-superlattice layer, a p-(AlGa)InP waveguide layer 209, a p-GaInP transition layer 210, and a p-GaP ohmic contact layer 211 are sequentially stacked on top of the multi-quantum well layer 204. These layers are stacked from bottom to top to form a complete epitaxial structure.

[0023] A patterned SiO2 layer 301 is disposed on the surface of the p-GaP ohmic contact layer 211, and a rectangular array of electrode holes is formed on the SiO2 layer 301. A p-electrode ohmic contact layer 302 is disposed inside the electrode holes, and the p-electrode ohmic contact layer 302 is in direct contact with the p-GaP ohmic contact layer 211.

[0024] An adhesion layer 303 is provided on the surface of the p-electrode ohmic contact layer 302 and the SiO2 layer 301, and a first metal connection layer 304 is provided on one side of the adhesion layer 303.

[0025] The supporting substrate assembly includes a Si substrate 400, on the upper surface of which a second metal interconnect layer 401 is disposed. The first metal interconnect layer 304 and the second metal interconnect layer 401 are bonded together by a low-temperature bonding process to form a bonding interface.

[0026] After the substrate transfer is completed, the original GaAs substrate and GaInPAlInP etch stop layers have been removed, exposing the ohmic contact layer 201. An n-electrode pad layer 402 is disposed on the surface of the ohmic contact layer 201, which is in direct contact with the ohmic contact layer 201.

[0027] A passivation layer 403 is disposed on the chip surface, covering the roughened surface and sidewalls of the n-AlInP roughening and extension layer 202, and an electrode is exposed through a window in the n-electrode pad layer 402 region. A back gold layer is disposed on the back side of the Si substrate 400 as a conductive and bonding layer on the back side of the device.

[0028] Furthermore, the GaAs substrate serves as a temporary substrate for epitaxial growth, providing a growth surface that matches the lattice of the AlGaInP material.

[0029] The GaAs buffer layer is a high-quality crystal layer grown on the surface of a GaAs substrate. It is used to eliminate processing damage and impurities on the substrate surface and to provide an atomically flat growth starting surface for subsequent epitaxial layers.

[0030] The GaInPAlInP etching stop layer acts as an etching stop layer during wet removal of GaAs substrates, protecting the n-type epitaxial layer above it from being eroded by the etching solution.

[0031] Ohmic contact layer 201 serves as the contact layer for the n-type electrode, with a high doping concentration >5E18cm⁻¹. - ³ Used to form a low-resistance ohmic contact with the subsequently deposited n-electrode pad layer.

[0032] The n-AlInP roughening and extension layer 202 has dual functions of lateral current extension and light extraction. The n-AlInP roughening and extension layer 202 has a wide bandgap of 2.25 eV and is transparent to the active region. It is formed into a micro-nano structure through chemical wet roughening, which breaks total internal reflection and improves light extraction efficiency.

[0033] The n-(AlGa)InP waveguide layer 203, as part of the optical waveguide structure, confines the light field emitted by the multi-quantum-well layer to the near-active region, reducing light leakage to the absorbing substrate.

[0034] The multi-quantum well layer 204 is the light-emitting region, which consists of 40 to 45 pairs of well / barrier periodic structures. Electrons and holes radiatively recombine here to produce red light.

[0035] The p-AlInP extended layer 205 serves as a lateral extension layer for p-type holes, uniformly injecting holes into the active region and blocking electron leakage.

[0036] The p-(AlGa)InP waveguide layer 206 is a p-side optical waveguide layer that, together with the n-side waveguide layer, forms a complete waveguide structure, optimizing the optical field distribution.

[0037] The p-GaInP transition layer 207 is used to smooth the band transition between p-type layers and reduce the hole transport barrier.

[0038] The p-superlattice layer consists of 4 to 6 pairs of (AlGa)InP / AlInP alternating layers. By forming a capacitance effect through band engineering, the hole injection rate is controlled to match the electron recombination time, thereby reducing electron leakage and improving luminescence uniformity.

[0039] The p-(AlGa)InP waveguide layer 209 is the second p-side waveguide layer, which further optimizes the optical field confinement.

[0040] The p-GaInP transition layer 210 is used to transition to GaP material and reduce heterojunction interface defects.

[0041] p-GaP ohmic contact layer 211 serves as the contact layer for the p-type electrode, with a high C doping concentration >1E20cm⁻¹. - ³ Used to form a low-resistance ohmic contact with the p-electrode ohmic contact layer.

[0042] SiO2 layer 301: As an insulating layer and mask layer, the opening pattern on it is used to define the contact area of ​​the p electrode and prevent the electrode metal from short-circuiting with other areas of the semiconductor layer.

[0043] The p-electrode ohmic contact layer 302 fills the SiO2 opening and forms a multilayer metal Au / AuBe / Au that is in direct contact with the p-GaP ohmic contact layer, thus forming a p-side ohmic contact.

[0044] The adhesion layer 303 covers the IZO or ITO layer on the p electrode and the SiO2 surface, enhances the adhesion between the metal layer and the underlying layer, and serves as a transparent conductive layer to assist current spread.

[0045] The metal interconnect layer 304 serves as the main conductive layer and bonding layer on the p-side, forming a eutectic bond with the metal interconnect layer on the Si substrate.

[0046] Si substrate 400 serves as a permanent support substrate, replacing the original GaAs substrate, and has high thermal conductivity and mechanical strength.

[0047] The metal interconnect layer 401 is a multilayer metal Ti / Pt / Au / In deposited on the surface of the Si substrate, used for low-temperature bonding with the metal interconnect layer on the chip side.

[0048] The n-electrode pad layer 402 is deposited on the ohmic contact layer as a multilayer metal Au / AuGeNi / Au / Pt / Ni / Ti / Au to form the n-side electrode pad.

[0049] A passivation layer 403 covers the SiN layer on the chip surface, protecting the roughened morphology and mesa sidewalls from moisture and impurity contamination. A back gold layer 500 is deposited on the Ti / Au layer on the back side of the Si substrate, serving as a conductive and bonding layer on the back side of the device.

[0050] The following describes in detail the epitaxial growth and chip manufacturing method of the AlGaInP red light-emitting diode involved in this application. Specific details such as particular system structures and technologies are presented for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details.

[0051] Please see Figure 2 The diagram shows a flowchart of a method for epitaxial growth and chip fabrication of an AlGaInP red light-emitting diode in a specific embodiment. The method includes: S1: An epitaxial layer structure is grown sequentially from bottom to top on a GaAs substrate, including a buffer layer, an AlInP etch stop layer, an n-type ohmic contact layer, an n-type waveguide layer, a multiple quantum well layer, a p-type waveguide layer, and a p-type ohmic contact layer, to determine the basic structure and photoelectric performance of the epitaxial wafer.

[0052] S2: A SiO2 insulating layer is deposited on the upper surface of the epitaxial wafer by PECVD. The SiO2 insulating layer is then photolithographically and etched to form a rectangular array of openings, providing an insulating and patterned basis for the subsequent p-electrode fabrication.

[0053] In some embodiments, the epitaxial wafer is placed in a plasma-enhanced chemical vapor deposition (PECVD) apparatus to deposit a SiO2 insulating layer, which is used to isolate the subsequent p-electrode from the non-electrode regions of the epitaxial wafer, thus preventing electrode short circuits. Here, the PECVD deposition of the SiO2 insulating layer utilizes plasma-enhanced chemical reaction between SiH4 and N2O to generate a dense SiO2 thin film at a lower temperature.

[0054] The role of plasma is to activate reactive gas molecules, lower the activation energy of the reaction, and enable the reaction to proceed efficiently at 280℃, avoiding high-temperature damage to the multi-quantum-well layer of the epitaxial wafer. High-purity N2 cleaning removes moisture and impurities from the surface of the epitaxial wafer. Heating and holding at this temperature ensures uniform surface temperature of the epitaxial wafer, guaranteeing a consistent deposition rate and improving the uniformity of the insulating layer thickness.

[0055] The insulation mechanism of SiO2 insulating layer is that it is an inorganic non-metallic material with covalent bonds, which has no free charge carriers and can effectively block current conduction.

[0056] Photolithography is a process in which positive photoresist undergoes a photochemical reaction under deep ultraviolet light, breaking down its molecular chains and becoming soluble in the developer. The unexposed areas of the photoresist remain insoluble in the developer, thus forming a pattern consistent with the photomask.

[0057] Furthermore, segmented pre-baking can gradually remove the solvent from the photoresist, improving the adhesion between the photoresist and the SiO2 layer. Hardening treatment also involves cross-linking the photoresist molecular chains, enhancing corrosion resistance.

[0058] Furthermore, the corrosion mechanism of the BOE buffer corrosion solution is that HF ​​acts as the main corrosive agent, reacting chemically with SiO2, as shown in the reaction equation: SiO2 + 4HF → SiF4↑ + 2H2O. The role of NH4F is to buffer the concentration of HF, thus reducing the corrosion rate.

[0059] Optionally, intermittently shaking the etching solution ensures uniform concentration and clean etching of the SiO2 layer. Here, SEM imaging can be used to observe the size, edge morphology, and residue of the opening pattern, ensuring the patterning effect meets standards and providing pattern positioning for p-electrode deposition.

[0060] S3: The p-electrode ohmic contact layer, adhesion layer and metal connection layer are sequentially deposited in the opening of the SiO2 insulating layer, and then subjected to high-temperature annealing treatment.

[0061] In some embodiments, the epitaxial wafer is placed in an electron beam evaporation machine, and a p-electrode ohmic contact layer, an adhesion layer, and a metal connection layer are sequentially deposited in the SiO2 opening.

[0062] Optionally, the ohmic contact layer adopts a Ti / Pt bilayer structure, with a Ti layer thickness of 25nm and a Pt layer thickness of 30nm. The Ti layer and the p-GaP ohmic contact layer form a TiP compound to reduce the contact resistance, and the Pt layer is used to block the diffusion of the subsequent Au layer.

[0063] Optionally, the adhesion layer is a Ti layer with a thickness of 15 nm, which enhances the bonding force between the metal layer and the SiO2 layer and the ohmic contact layer. The metal connection layer is an Au layer with a thickness of 200 nm. Au has excellent conductivity and oxidation resistance, ensuring stable electrode conductivity.

[0064] The design of the Ti adhesion layer here enhances the adhesion of the metal layer to over 15 MPa, preventing peeling and detachment in subsequent processes. The selection of the Au metal bonding layer ensures a high electrode conductivity and stable conductivity. Optimization of the high-temperature annealing process improves the crystallinity quality of the metal layer.

[0065] Furthermore, during the vapor deposition process, a quartz crystal sensor is used to monitor the thickness of each layer in real time. If the thickness deviation exceeds 1 nm, the vapor deposition rate is adjusted to ensure uniform metal layer thickness. After vapor deposition, the epitaxial wafer is placed in a tubular annealing furnace for high-temperature annealing treatment to optimize electrode performance.

[0066] Furthermore, after annealing, the contact resistance of the p electrode was tested using a four-probe tester, and the adhesion of the metal layer was tested using a tensile tester. The tensile force was ≥15MPa, and there was no peeling or detachment.

[0067] Optionally, electrodes with excessive contact resistance, insufficient adhesion, or poor conductivity can be reworked and then proceed to the next process after passing the rework process to ensure that the performance of the p electrode and associated metal layer meets the standards.

[0068] S4: After the metal interconnect layer is deposited on the Si substrate, the epitaxial wafer treated in S3 is bonded to the Si substrate at low temperature and cooled in stages to realize the transfer of the epitaxial wafer from the GaAs substrate to the Si substrate, providing support for the subsequent removal of the thick GaAs substrate.

[0069] In some embodiments, a Si substrate is selected and pre-treated: it is placed in an acetone ultrasonic cleaning bath to remove surface oil. Then it is rinsed with deionized water to remove any acetone residue. Finally, it is dried by blowing with high-purity nitrogen gas to ensure the Si substrate surface is clean and free of impurities.

[0070] Furthermore, the pretreated Si substrate is placed in an electron beam evaporation machine to deposit a metal bonding layer. The evaporation parameters are the same as those in S3 to ensure that the metal layer thickness is uniform and the adhesion meets the standards.

[0071] The epitaxial wafer treated with S3, with the p-electrode side facing up, is aligned with the Si substrate after the metal layer has been deposited. It is then placed in a bonding machine, and the two are connected using a low-temperature metal bonding process.

[0072] Furthermore, before bonding, the bonding cavity is evacuated and purged with high-purity Ar gas to remove the oxide layer and adsorbed impurities from the surfaces of both wafers. The alignment accuracy is adjusted to ensure that the p-electrode of the epitaxial wafer contacts the metal layer of the Si substrate.

[0073] Optionally, the bonding parameters are set as follows: bonding temperature 200℃±10℃, bonding pressure 8MPa±0.5℃, and Ar gas is continuously introduced during the bonding process to isolate air.

[0074] After bonding is completed, a staged cooling process is adopted: in the first stage, the temperature is reduced from 200℃±5 to 120℃±5 to release the thermal stress generated during the bonding process.

[0075] In the second stage, the temperature was reduced from 120℃±3 to 60℃±3 to further release residual stress.

[0076] In the third stage, the temperature is naturally cooled from 60℃±2 to room temperature to ensure uniform cooling and avoid thermal stress that could cause cracking of the bonding surface and damage to the epitaxial wafer.

[0077] Furthermore, a phased cooling process was employed, designed based on an interfacial thermal stress accumulation model and fracture toughness criteria. The bonding interface consists of the metal layer 304 of the epitaxial wafer and the metal layer 401 of the Si substrate. The difference in the thermal expansion coefficients of the two materials generates thermal stress σ during the cooling process. thermal (T):

[0078] Where E eff For the effective Young's modulus, ν eff For the effective Poisson's ratio, α sub and α epi These are the coefficients of thermal expansion of the Si substrate and the epitaxial wafer, respectively.

[0079] When σ thermal When the interfacial fracture toughness KIC is exceeded, delamination failure occurs at the interface.

[0080] By setting a dwell platform at 200℃, corresponding to the Au-In eutectic point and the solder solidification point at ℃, creep relaxation of the interfacial metal layer is induced, and the creep strain ε creep Calculated using the following formula:

[0081] Where A is the material constant, n is the stress exponent (approximately 4-5 for Au), m is the time exponent, and Q is the creep activation energy.

[0082] Optionally, a residence time of 10 minutes ensures creep strain ε creep To reach more than 60% of the total thermal strain, so that the residual stress σ residual It is less than 70% of the interfacial fracture toughness.

[0083] After cooling, the bonded parts are removed and the bond strength is tested using a shear strength tester. The shear strength is ≥16MPa. The bonded surface is observed using SEM to ensure that the bond is tight, without voids, and without oxide spots.

[0084] Optionally, a multimeter is used to test the bonding continuity, with a continuity rate of %, to ensure that the p electrode achieves effective conduction with the Si substrate through the metal layer.

[0085] Samples with unqualified bonding, such as insufficient strength, poor conductivity, or voids, are reworked. Once qualified, they proceed to the next process to realize the transfer of the epitaxial wafer from the GaAs substrate to the Si substrate, providing stable support for the subsequent removal of the thick GaAs substrate.

[0086] It can be seen that the core principle of the phased cooling process is thermal stress control: after bonding is completed, there is residual thermal stress inside the bonded part. If the temperature is cooled quickly, the thermal stress cannot be released in time, which will lead to cracking of the bonding surface and damage to the epitaxial wafer.

[0087] The first stage of slow cooling allows the internal temperature of the bonded component to drop evenly, gradually releasing most of the thermal stress. The second stage of medium-speed cooling further releases residual thermal stress and avoids stress accumulation. The third stage of natural cooling ensures a smooth transition between the bonded component and the ambient temperature, ultimately reducing the residual thermal stress to below 50 MPa and preventing bond surface failure.

[0088] S5: The GaAs substrate is removed by wet etching, which terminates at the AlInP etching stop layer. The upper GaInP layer is removed and the n-type ohmic contact layer is surface treated to expose the n-type conductive layer base for fabricating the n-electrode.

[0089] In some embodiments, a qualified bonding member is fixed on an etching fixture, and a wet etching process is used to remove the GaAs substrate and GaInP layer.

[0090] Optionally, a wet etching solution can be used, which has a high etching rate for GaAs and GaInP, but an extremely low etching rate for the AlInP etching stop layer, thus achieving etching.

[0091] During the etching process, the bonded parts are immersed in the etching solution and stirred to ensure a uniform concentration. At regular intervals, the bonded parts are removed, rinsed with deionized water, and the etching progress is observed using an optical microscope. Etching is stopped when an AlInP etching stop layer is observed. After etching is complete, the parts are rinsed with deionized water to remove residual etching solution and then dried with nitrogen.

[0092] Plasma cleaning was used to remove corrosion residue and oxide layer from the AlInP stop layer surface. A photolithography process was then used to fabricate an etched window pattern on the AlInP stop layer surface, with photolithography parameters consistent with S2 to ensure accurate window pattern alignment.

[0093] Alternatively, a diluted HF etching solution can be used to etch the AlInP stop layer at a constant temperature, removing the AlInP etch stop layer within the window and exposing the underlying ohmic contact layer.

[0094] After etching, rinse with deionized water to remove residual etching solution. A wet etching process is used to treat the ohmic contact layer, removing the natural oxide layer and corrosion-damaged layer on the n-GaAs layer surface, thus improving the contact performance of the subsequent n-electrode.

[0095] After treatment, the surface is rinsed with deionized water, cleaned with acetone and ethanol, and then dried with nitrogen. The surface morphology of the n-GaAs layer is observed to ensure that it is smooth, free of oxide layer and corrosion damage. A four-probe tester can also be used to measure the resistivity of the n-GaAs layer to ensure that the exposed n-type conductive layer meets the required standards, thus providing a guarantee for the preparation of the n-electrode.

[0096] Alternatively, at a growth temperature of 760℃, the crystal orientation distribution and defect density of AlInP directly affect the anisotropic corrosion behavior of the roughening solution. By controlling the V / III ratio during growth (i.e., the ratio of PH3 flow rate to the total flow rate of group III sources) within the range of 120-140, the proportion of polar faces in the AlInP crystals can be adjusted. The corrosion rate of different AlInP crystal faces by the roughening solution (HF:HIO4:H2SO4:water = 3:3:8:20) is compared to R. etch Described by the following formula:

[0097] Where θ is the crystal plane deviation angle, R[] is the corrosion rate of the [] crystal orientation, δ is the anisotropy coefficient, and N d For dislocation density, N d0 Use the dislocation density as a reference. Nd < 5 × 10⁻⁶ is achieved by controlling the growth parameters. 4 cm - ², ensuring that a uniform pyramidal structure with a size of 0.5-1.0 μm is formed after coarsening, and its light extraction efficiency is verified by simulation using the finite-difference time-domain method:

[0098] Where P(θ) is the roughened surface angular distribution function, and P0 is the planar reflectivity. The process is configured here, including epitaxial growth parameters, crystal quality, roughening morphology, and light extraction efficiency.

[0099] S6: The n-electrode pad layer is prepared by photolithography and electron beam evaporation and then annealed at high temperature to complete the preparation of the n-electrode pad and realize the electrode lead-out on the n-type side of the chip.

[0100] S7: Through photolithography, ICP etching, chemical wet roughening, passivation layer deposition, chip thinning, back gold evaporation and laser cutting, the chip light-emitting area is patterned, surface roughened, passivated and protected, thickness adjusted and device separated, and finally a red light-emitting diode chip is obtained.

[0101] In some embodiments, the qualified bonding epitaxial wafer of S6 is fixed on the photolithography fixture with its side facing upward, and photolithography, ICP etching, chemical wet roughening, passivation layer deposition, chip thinning, layered back gold evaporation and laser segmentation are completed in sequence to finally obtain a single light-emitting diode device. The parameters of each process are controlled throughout the process to ensure that the chip performance and size meet the standards.

[0102] In one embodiment of the present invention, based on step S1, the following is a possible embodiment and its specific implementation will be described in a non-limiting manner. S1 specifically includes the following steps: S11: GaAs substrate pretreatment and GaAs buffer layer growth.

[0103] Specifically, ultrasonic cleaning is used, followed by nitrogen drying and baking to remove moisture. During the deoxidation stage, hydrogen and AsH3 are introduced, and the temperature is raised and maintained for a certain period of time. Then, TMGa and AsH3 are switched. During H2 / AsH3 deoxidation, AsH3 decomposes into As atoms, which fill the Ga vacancies on the GaAs surface to inhibit decomposition.

[0104] A 150 nm GaAs buffer layer is deposited at a specific temperature, such as 630℃±10℃, with silane as the doping source and a doping concentration controlled at 3×10¹. 8 cm - ³.

[0105] S12: Growth of the corrosion-stopping layer of GaInPAlInP.

[0106] Specifically, on the buffer layer, TMGa, TMIn, and PH3 were used as sources, the TMAl flow rate was reduced to zero, the growth temperature was 640℃±10℃, and a 150nm layer was deposited. After growth, the lattice constant was measured by in-situ X-ray diffraction. The process was terminated when the deviation was >0.001Å, and the TMIn flow rate was adjusted to achieve a doping concentration <1×10¹. 7 cm - ³.

[0107] In some embodiments, the AlInP etching stop layer has a lattice mismatch of <0.01% with the substrate, the etching rate of GaAs during wet etching is several times lower than that of GaAs, the BOE etching solution has a etching rate of Å / min for GaAs and 5 Å / min for this layer, resulting in a smooth and pit-free interface for cross-sectional SEM display.

[0108] S13: n-type functional layer stress-controlled epitaxial growth.

[0109] Specifically, S13 includes the following steps: S131: Ohmic contact layer growth. Thick Å thickness, using pulsed Si2H6 doping with a peak concentration of 6 × 10¹. 8 cm - ³, average concentration 5.5 × 10¹ 8 cm - ³, growth temperature 620℃, TMGa flow rate 60 sccm, AsH3 flow rate 1800 sccm (V / Ⅲ=30).

[0110] In some embodiments, the ohmic contact layer is grown using Si2H6 pulse doping with an on / off ratio of 1:3, a TMGa flow rate of 60 sccm, an AsH3 flow rate of 1800 sccm (V / Ⅲ=30), and a growth rate of 0.8 μm / h, with Å deposited at 620°C for 6 minutes.

[0111] Furthermore, the doping concentration distribution is described by a pulse diffusion model: Cavg = Cpeak·(ton / (ton+toff)), where ton = 3 seconds (through-segment), toff = 7 seconds (interruption-segment), and Cpeak = 6 × 10¹ 8 cm - ³, calculated to be Cavg = 6 × 10¹ 8 ×(3 / 10)=1.8×10¹ 8 cm - ³, in practice, the average concentration reached 5.5 × 10¹ through multiple pulse superpositions. 8 cm - ³.

[0112] S132: Stress-regulated growth of n-AlInP coarsening extended layer.

[0113] Based on the segmented design with a critical thickness of hc=6Å, the total thickness is 32Å divided into 6 sub-layers, with each layer having di=5300Å+Δdi. Optionally, Δdi=0.2×(5300-dmeasured), where dmeasured is the thickness measured by an ellipsometer.

[0114] Growth temperature 720℃±10℃, TMAl=120sccm, TMGa=10sccm, TMIn=0sccm, PH3=0sccm (V / Ⅲ=29), Si2H6 doping 1.2×10¹ 8 cm - ³. After each segment, cool down by 5°C to 715°C and hold for 2 minutes, then raise the temperature to 720°C. Measure the thickness using an ellipsometer. If the deviation is >50 Å, adjust the TMAl flow rate by increasing or decreasing by 2 sccm for every 10 Å of deviation.

[0115] Furthermore, the cumulative thermal stress σ acc The calculation method is as follows

[0116] 1.2× 2 dyn / cm 2 It is the equivalent elastic modulus of the material. This represents the mismatch in the coefficients of thermal expansion between the materials.

[0117] ΔT i Let t be the temperature change during the i-th stage of cooling. i The duration of heat preservation or cooling in stage i.

[0118] During the phased cooling process after bonding, the system performs judgments and operations in real time. ,Right now This triggers additional relaxation, maintaining a constant temperature. Specifically, it monitors ΔTi = 5℃, ti = 120s, and the over-yield strength σ. y =2.5×10 9 Insert an additional 5-minute relaxation time when dyn / cm² is applied.

[0119] In some embodiments, the critical thickness hc is calculated as follows:

[0120] Optionally, the Burgers vector b = 3.8 × 10 -8 cm, AlInP / GaAs lattice mismatch f=0.008, Poisson's ratio ν=0.3, dislocation line angle θ=30°, slip plane angle λ=45°, iterative solution yields hc≈6Å.

[0121] Furthermore, the total thickness of 32 Å is divided into 6 sub-layers, with a target of dtarget=5300 Å for each layer, actual di=5300 Å+Δdi, Δdi=0.2×(5300-dmeasured), k=0.2 is the correction coefficient, and dmeasured is fed back in real time by the ellipsometer.

[0122] Furthermore, the growth parameters were TMAl=120sccm, TMGa=10sccm, TMIn=0sccm, PH3=0sccm (V / Ⅲ=29), and Si2H6 was doped with 1.2×10¹ 8 cm - ³.

[0123] At the end of each segment, the temperature is reduced by 5°C to 715°C and held for 2 minutes. The thermal stress relaxation calculation method is as follows:

[0124] Specifically, the equivalent elastic modulus is calculated as E = 1.2 × 10¹² dyn / cm², and the thermal expansion coefficient mismatch is Δα = 5 × 10⁻⁶. -6 / K, ΔTi=5℃, relaxation time constant τ=120s, total cumulative stress σy = 2.5 × 10 9 Add an extra 5 minutes of relaxation time when dyn / cm² is applied. Adjust Q Al flow .

[0125] It can be seen that the critical thickness formula quantifies the dislocation initiation threshold of AlInP on GaAs. Cooling each segment to 715℃ allows the thermal stress (σ=E·Δα·ΔT) to be released through dislocation slip, while heating back up restores the growth temperature to ensure crystal quality.

[0126] Ellipsometry thickness measurement feedback correction Δdi ensures a 32Å total thickness uniformity of ±1% for the six sublayers. A stress accumulation model monitors σ in real time. acc The high yield strength allows for relaxation to prevent plastic deformation. A high Al content (>0.98%) results in a band gap of 2.25 eV, reducing photon absorption.

[0127] S133: Waveguide layer growth.

[0128] In this embodiment, the thickness is 700 Å, the Al composition x=0.7 (TMAl flow rate 150 sccm, TMGa flow rate 40 sccm, TMIn flow rate 900 sccm, V / Ⅲ=30), the growth temperature is 730℃, the PH3 flow rate is 1050 sccm, and the Si2H6 doping is 8×10¹. 7 cm - ³.

[0129] In some embodiments, waveguide layer growth employs an Al composition control model. The Al composition x = 0.7 is determined by the flow ratio of TMAl to TMGa: x = TMAl / (TMAl + TMGa) = 150 / (150 + 40) = 0.79. In practice, the In content is finely adjusted by the PH3 flow rate, with TMIn = 900 sccm to achieve an In ratio of 0.3, ultimately resulting in x = 0.7.

[0130] Furthermore, the relationship between the refractive index n and the Al composition is given by the formula n(x) = 3.5 - 0.8x, x ∈ [0, 1]. Through experimental fitting, when x = 0.7, n = 3.5 - 0.56 = 2.94.

[0131] Furthermore, V / Ⅲ ratio 30, PH3 / (TMAl+TMGa+TMIn)=1050 / (150+40+900)=1050 / 1090≈0.96. Here, the V / Ⅲ ratio is the total flow ratio of PH3 to group III. When defined as 30, the actual PH3 = 30×(150+40+900) = 30900sccm. The correction to 1050sccm corresponds to V / Ⅲ = 30, which is the preset process calibration value, controlling the In content fluctuation <0.02.

[0132] Furthermore, the growth temperature was 730℃, and Si2H6 was doped with 8×10¹ 7 cm - The thickness of 700Å is controlled by growth time and monitored in real time by a quartz crystal oscillator.

[0133] It can be seen that the Al composition x=0.7 results in a waveguide layer refractive index lower than the n-AlInP coarsening layer, forming an optical confinement barrier. The growth temperature of 730℃ balances the In atom mobility, and TEM shows that the well-barrier interface transition layer is <2 Å. A V / Ⅲ ratio of 30 ensures sufficient PH3 to suppress As antisite defects.

[0134] S14: Co-design of multiple quantum well layers and p-type bandgap engineering.

[0135] Specifically, S14 includes the following steps: S141: Growth of multiple quantum well layers.

[0136] A 42-pair quantum well structure, where the quantum wells are Al0. 18 Ga0. 82 InP, with an Al content of 0.18 and a thickness of 50 Å, has a quantum barrier of Al0.7Ga0.3InP, with an Al content of 0.7 and a thickness of 80 Å. Alternating growth is used at a growth temperature of 725℃, a V / III ratio of 80, and an interface steepness of <2 Å as detected by TEM. The emission wavelength λ = 620 nm is calculated based on λ = 2nL / m, where n = 3.4 is the average refractive index, L = 50 Å is the well thickness, and m = 0.067m0 is the effective electron mass.

[0137] In some embodiments, the growth of the multiple quantum well layer employs a 42-pair periodic structure, with quantum well Al0. 18 Ga0. 82 InP, where TMAl=30sccm, TMGa=120sccm, TMIn=0sccm, and V / Ⅲ=80.

[0138] A 50 Å thick layer with a quantum barrier of Al0.7Ga0.3InP, where TMAl = 120 sccm, TMGa = 50 sccm, TMIn = 0 sccm, and V / Ⅲ = 80. This 80 Å thick layer is alternately grown on the n-waveguide layer. V / Ⅲ = 80 ensures that PH3 suppresses As inversion defects.

[0139] The growth temperature of 725℃ was controlled by a substrate heating coil, the pH3 flow rate was 1600 sccm, the interface steepness was achieved by interrupting the growth for 5 seconds, and the transition layer was detected by TEM as <2 Å.

[0140] The emission wavelength design is based on the formula λ=2nL / m, n=3.4 (Al0). 45 Ga0. 55 With the average refractive index of InP, a trap thickness of L = 50 Å, and an effective electron mass of InGaAs m = 0.067m0, the calculated λ = 2 × 3.4 × 50 × 10⁻⁶. -8 cm / (0.067×9.1×10 - ² 8 g×3×10¹0 The wavelength (cm / s) is approximately 620nm, which is consistent with the target wavelength. It can be seen that with the period number of 42 determined, the carrier confinement factor Γ=1-exp(-NπL² / λ²) is calculated. When N=42, Γ=0.92, balancing the luminescence intensity and efficiency.

[0141] S142: p-superlattice layer band engineering and carrier dynamics design.

[0142] Five pairs of superlattice structures, each pair containing (Al0). 68 Ga0. 32 InP layer (70 Å, TMAl = 130 sccm) and AlInP corrosion stop layer (70 Å, TMAl = 180 sccm), CP2Mg doped 1.8 × 10¹ 8 cm - ³; Hole transit time τ h Recombination time τ with multiple quantum wells rec match, ,

[0143] d well =70Å, Ea=0.05eV, m=0.5m0, Tt=0.8, τ0=1ps, T=300K, τrec=1.5ns, for TRPL measurement.

[0144] In some embodiments, the p-superlattice layer design is based on the hole transit time τ. h With composite time τ rec The matching model.

[0145] Furthermore, there are 5 pairs of superlattices, each pair consisting of (Al0). 68 Ga0. 32 InP layer (TMAl=130sccm, TMGa=60sccm, TMIn=0sccm, thickness 70Å) and AlInP corrosion stop layer (TMAl=180sccm, TMIn=0sccm, PH3=0sccm, thickness 70Å), CP2Mg doped 1.8×10¹ 8 cm - ³ (On / off ratio 1:4, cycle 12 seconds).

[0146] Furthermore, the hole transit time τ h By tunnel τ tunnel and thermal emission τ therm Parallel determination, τ h =1 / (1 / τ tunnel +1 / τ therm ), where τtunnel =2dwell / √(2Ea / m)·1 / Tt (dwell=70Å, Ea=0.05eV barrier height, effective hole mass m=0.5m0, tunneling coefficient Tt=0.8, calculated to obtain τ) tunnel =2×70×10 -8 cm / √(2×0.05×1.6×10 - ¹ 9 J / 0.5×9.1×10 - (³¹kg)×1 / 0.8≈0.6ps; τ therm =τ0exp(Ea / kT). Trial time τ0 = 1 ps, k = 8.6 × 10⁻⁶ - 5 Given eV / K, T=300K, we get τ therm =1ps×exp(0.05 / 0.0258)≈1.2ps, so τ h =1 / (1 / 0.6+1 / 1.2)=0.4ps.

[0147] For a single superlattice pair, τh = 0.4 ps. After 5 pairs are connected in series, τh = 5 × 0.4 = 2 ps = 0.002 ns, which matches the multi-quantum well τrec = 1.5 ns. τh / τrec = 0.0013. When the number of periods needs to be adjusted to 5 pairs, the actual τh = 1.7 ps due to interlayer coupling, and the ratio is 1.13 (0.8 < 1.13 < 1.2).

[0148] It can be seen that by adjusting Ea to 0.05 eV through the Al component of 0.68 (k=0.68), τ therm With τ tunnel Quite similar. It increases hole injection rate and reduces electron leakage rate.

[0149] S143: Growth of p-type extension layer, waveguide layer, transition layer and ohmic contact layer.

[0150] ① p-AlInP extended layer, 12 Å thick, TMAl = 180 sccm, TMIn = 0 sccm, PH3 = 0 sccm, CP2Mg doped 1.5 × 10¹ 8 cm - ³; ②p-(Al0. 68 Ga0. 32 InP waveguide layer, 600 Å thick, Al composition 0.68; ③ p-GaInP transition layer, 150 Å thick, In=0.5; ④p-(Al0). 63 Ga0. 37 InP waveguide layer, 400 Å thick, Al composition 0.63; ⑤ p-GaInP transition layer, 150 Å thick, In=0.5; ⑥ p-GaP ohmic contact layer, thickness Å, CCl4 source flux 30 sccm, C doping 1.2 × 10² 0 cm - ³.

[0151] In some embodiments, the p-AlInP extended layer is 12 Å thick, TMAl = 180 sccm, TMIn = 0 sccm, PH3 = 0 sccm (V / Ⅲ = 29), and CP2Mg is doped with 1.5 × 10¹ 8 cm - ³ (on / off ratio 1:5, cycle 15 seconds), growth temperature 700℃, thickness monitored by quartz crystal oscillator, 12Å requires 83 minutes.

[0152] Furthermore, p-(Al0). 68 Ga0. 32 The InP waveguide layer is 600 Å thick, with TMAl=130 sccm, TMGa=60 sccm, and TMIn=0 sccm (V / Ⅲ=30). The growth temperature is 710℃, and the refractive index is n=3.2.

[0153] Furthermore, the p-GaInP transition layer is 150 Å thick (In=0.5, TMGa=50 sccm, TMIn=50 sccm) with a lattice constant of 5.65 Å, which helps relieve stress. p-(Al0. 63 Ga0. 37 The InP waveguide layer is 400 Å thick, with TMAl=120 sccm, TMGa=70 sccm, TMIn=0 sccm (V / Ⅲ=30), and n=3.3.

[0154] Furthermore, the p-GaInP transition layer thickness was 150 Å (In=0.5). The p-GaP ohmic contact layer thickness was Å, the CCl4 source flux was 30 sccm, the growth temperature was 650 °C, and the C concentration was verified by SIMS.

[0155] It can be seen that the choice of In=0.5 in the transition layer results in a lattice constant of 5.65 Å (5.653 Å for GaAs substrate) and a mismatch of <0.05%. This transition layer also results in a dislocation density of <1×10⁻⁵. 5 cm - ². GaP contact layer contact resistance 2×10 -6 Ω·cm², IV curve ideal factor <1.1. After full-layer growth, the epitaxial wafer wavelength uniformity is ±1nm, and the yield is improved by 12%.

[0156] S15: Implementation of a multi-objective collaborative optimization control system.

[0157] Specifically, a growth parameter database is established, including temperature, pressure, gas flow rate, and doping threshold, and the objective function J for multivariable model predictive control is defined:

[0158] The adaptive adjustment method for PID parameters is as follows:

[0159] t0 is the initial time of the quantum well, and feedforward compensation is defined. Δ xpred Based on historical batch predictions. Pressure stabilized at 55 mbar, parameter curves were recorded throughout the process.

[0160] It can be seen that the database stores the target parameters for each layer, such as the n-AlInP corrosion stop layer TMAl=120sccm, pressure 55mbar, and temperature 720℃.

[0161] In the multivariable model predictive control objective function J, d represents the thickness, x represents the Al composition, N represents the doping concentration, ΔQ represents the source flow rate adjustment, and dT / dt represents the temperature change rate. In the PID parameter adaptive Kp(t), t0 represents the quantum well start time. J / d is calculated in real time from ellipsometer data, with Ti=10s and Td=2s. Feedforward compensation ΔQAl,ff can be based on the 10th batch when Δx=0.005, ΔQAl,ff=0.8×0.005×12000=48sccm, adjusting the TMA1 flow rate 5 seconds in advance. Pressure is stabilized at 55mbar using an MKS controller, and parameter curves are recorded throughout the process.

[0162] Thus, multivariate model predictive control balances thickness, composition, and doping errors through the objective function J, while the integral term penalizes flow rate adjustments and sudden temperature changes. Adaptive Kp(t) increases the scaling factor during quantum well growth to quickly respond to interface abrupt changes. Feedforward compensation predicts composition drift based on historical data and adjusts the flow rate in advance to offset it.

[0163] In one embodiment of the present invention, based on step S6, the following is a possible embodiment and its specific implementation will be described in a non-limiting manner. S6 specifically includes the following steps: S61: Pre-treatment and photoresist coating of the n-electrode pad area before photolithography.

[0164] In some embodiments, this addresses residual corrosive liquid impurities, oxide layers, and particulate contaminants on the surface of the ohmic contact layer.

[0165] Further, the chip was immersed in BOE buffer etching solution at a constant temperature to remove the natural oxide layer on the surface. It was then sequentially immersed in acetone and ethanol solutions, and ultrasonically cleaned to remove organic impurities and fine particles from the surface. Finally, it was rinsed with deionized water and dried with nitrogen gas.

[0166] After pretreatment, the chip is placed on the tray of a photoresist coating machine, and positive photoresist is applied using a spin coating method. The photoresist thickness is controlled by adjusting the spin parameters. After coating, the chip is placed in a constant temperature oven to pre-bake the photoresist, remove the solvent from the photoresist, and improve the adhesion between the photoresist and the ohmic contact layer.

[0167] S62: n-electrode pad patterning lithography and development and fixing process.

[0168] In some embodiments, the pre-baked chip is transferred to a photolithography exposure machine and exposed using deep ultraviolet (UV) light. The exposure time is controlled by an exposure energy model: E = P·texp, where E is the target exposure energy, P is the exposure power density, and texp is the exposure time. texp is calculated to be 3.2 seconds. During exposure, the n-electrode pad pattern mask is aligned with the chip surface, and the mask and chip are fixed using vacuum adsorption. After exposure, the chip is immersed in a developer solution to ensure uniform development. After development, the chip is rinsed with deionized water to remove residual developer, and then immersed in a fixer. After fixing, the chip undergoes photolithography pattern inspection. The outline of the pad pattern is observed using an optical microscope, and a pattern deviation detection model is established: Δx = (xmeas - xtarget) / xtarget × %, where Δx is the pattern deviation rate, xmeas is the measured pattern size, and xtarget is the target pattern size. When the absolute value of Δx exceeds 0.5%, it is judged as unqualified, and photolithography is repeated. Qualified chips are placed in a constant temperature oven to complete the photoresist hardening process, improving the high-temperature resistance of the photoresist in subsequent evaporation processes.

[0169] S63: n-electrode pad layer layered electron beam evaporation and thickness control.

[0170] In some embodiments, the qualified chip after hardening is transferred to an electron beam evaporation machine, and an n-electrode pad layer is prepared using a layered evaporation process. The electrode structure from bottom to top consists of an AuGeNi layer, an Au layer, a Pt layer, a Ni layer, a Ti layer, and an Au layer. The thickness of each layer is controlled according to design requirements, and a layered evaporation thickness control model is established: d = I·tdep / (ρ·A), where d is the evaporation layer thickness, I is the electron beam current, tdep is the evaporation time, ρ is the density of the evaporation material, and A is the area of ​​the evaporation region.

[0171] The specific vapor deposition parameters are as follows: the first layer is an AuGeNi layer with an Au:Ge:Ni atomic ratio of 88:10:2, the electron beam current is controlled at 80mA, the vapor deposition temperature is 150℃, the material density is ρ=17.3g / cm³, the vapor deposition time is calculated to be 120 seconds, the target thickness is 200Å, and a quartz crystal sensor is used to monitor the thickness in real time during the vapor deposition process. If the deviation exceeds 5Å, the electron beam current is adjusted.

[0172] The second Au layer was deposited at an electron beam current of mA, a deposition temperature of 160℃, a density of ρ = 19.3 g / cm³, a deposition time of 300 seconds, and a target thickness of 800 Å.

[0173] The third Pt layer was deposited at an electron beam current of 90 mA, a deposition temperature of 170 °C, a density of ρ = 21.45 g / cm³, a deposition time of 180 seconds, and a target thickness of 300 Å.

[0174] The fourth Ni layer was deposited at an electron beam current of 70 mA, a vapor deposition temperature of 150 °C, a density of ρ = 8.9 g / cm³, a vapor deposition time of 90 seconds, and a target thickness of Å.

[0175] The fifth Ti layer was deposited at an electron beam current of 60 mA, a deposition temperature of 140 °C, a density of ρ = 4.51 g / cm³, a deposition time of 60 seconds, and a target thickness of 80 Å.

[0176] The sixth Au layer was deposited at an electron beam current of 110 mA, a vapor deposition temperature of 160 °C, a density of ρ = 19.3 g / cm³, a vapor deposition time of 600 seconds, and a target thickness of 1 Å.

[0177] After the vapor deposition is completed, a step gauge is used to check the thickness of each layer to ensure that the thickness deviation of each layer is controlled within ±3%.

[0178] S64: High-temperature annealing and photoresist removal of the n-electrode pad layer.

[0179] In some embodiments, the vapor-deposited chip is transferred to an annealing furnace for annealing. The annealing temperature and time are controlled by an annealing diffusion model: D = D0·exp(-Ea / (k·Tann)), where D is the diffusion coefficient of Ge atoms in the AuGeNi layer, D0 is the diffusion constant, Ea is the diffusion activation energy, k is the Boltzmann constant, and Tann is the annealing temperature.

[0180] Based on the contact resistance requirements, the annealing temperature is set to 310℃. Substituting this into the model, the calculated value is D = 1.2 × 10⁻⁶. -4 ·exp(-0.65 / (8.617×10 -5 ×583.15))≈2.8×10 -10 cm² / s corresponds to an annealing time of 12 minutes, ensuring that Ge atoms fully diffuse into the ohmic contact layer to form a low-resistance contact.

[0181] After annealing, the chip is placed in a photoresist stripping solution and stripped at a constant temperature. After stripping, it is washed sequentially with acetone, ethanol, and deionized water, dried with nitrogen, and the surface morphology of the electrode layer is observed using a scanning electron microscope to check for photoresist residue. A chip with no residue is considered qualified, and the preparation of the n-electrode pad layer is completed.

[0182] Here, a segmented annealing process controlled by an annealing-diffusion model ensures uniform Ge atom diffusion, improving the contact resistance stability between the n-electrode pad layer and the ohmic contact layer. The annealing temperature is controlled at 310℃, reducing high-temperature damage to other layers of the chip and enhancing the stability of the chip's luminescent performance.

[0183] In one embodiment of the present invention, based on step S7, the following is a possible embodiment and its specific implementation will be described in a non-limiting manner. S7 specifically includes the following steps: S71: Patterning of chip light-emitting areas using photolithography. It employs a four-stage preset preprocessing, photoresist coating control based on non-Newtonian fluid dynamics modeling, and real-time detection and feedback correction of pattern deviations to achieve pattern forming of the light-emitting area.

[0184] In some embodiments, a pre-defined pretreatment is performed on the processed chip to eliminate the interference of surface residues on photolithography accuracy. The chip is immersed in a pre-defined diluted etching solution at a constant temperature. Anhydrous ethanol in the etching solution can reduce the surface tension of the solution, allowing the etching solution to fully wet the edge gaps of the n-electrode pad, and specifically remove residual metal oxides and photoresist debris. The etching time is determined through preliminary experiments.

[0185] Next, the chip is placed in an isopropyl alcohol ultrasonic cleaning bath for cleaning. It is then rinsed with deionized water and dried by blowing with high-purity nitrogen gas to ensure that all areas of the chip surface are covered with nitrogen gas, leaving no water stains or particle residue.

[0186] After pretreatment, negative photoresist is spin-coated. After coating, the chip is placed in a constant temperature oven for pre-baking to improve the adhesion between the photoresist and the chip surface. Deep ultraviolet exposure is performed after pre-baking. After exposure, development is performed with a developer. After development, the chip is rinsed with deionized water. The pattern is inspected using an optical microscope, and a pattern deviation detection model Δy = (ymeas - ytarget) / ytarget is established, where ymeas is the measured size of the emitting area, and ytarget is the target size (145μm × 145μm). If the absolute value of Δy exceeds 0.25%, photolithography is repeated; qualified chips proceed to the next process.

[0187] Optionally, based on the parameter correlation between S71 lithography dr and S72 etching vetch and touch, a linear coupling model is established, which is defined as follows: θ = k0 - k1 × |dr| - k2 × |vetch - v0| - k3 × |tetch - t0|.

[0188] Where k0 is the basic verticality constant, corresponding to the verticality of the etched sidewall when S71 lithography without deviation dr=0, and S72 etching parameters are at the standard values ​​vetch=v0 and touch=t0, k0=89.8°. v0 is the S72 standard etching rate. t0 is the S72 standard etching time. k1, k2, and k3 are coupling coefficients, all positive numbers, representing the influence weight of each input parameter on θ.

[0189] Optionally, based on semiconductor etching process experience, k1=5° / μm, k2=10° / (μm / min), k3=0.05° / min) are selected, and the weight allocation is in line with reality: the etch rate fluctuation vetch has the greatest impact on the sidewall verticality, followed by the lithography linewidth deviation dr, and the etch time fluctuation tetch has the least impact.

[0190] In this way, the S71 lithography linewidth deviation dr, the S72 etching rate deviation vetch-v0, and the etching time deviation touch-t0 all lead to a decrease in the perpendicularity θ of the etched sidewall. The larger the deviation, the smaller θ, perfectly matching the quality requirement of S72 sidewall perpendicularity ≥89.6°, thus achieving coupling between the S71 and S72 parameters. This interrelation ensures that the coupled model is highly adapted to the actual process, guaranteeing the accuracy of the luminescent area pattern formation.

[0191] S72: ICP plasma etching of the luminescent area, using a preset etching gas ratio, OES dual-spectral endpoint identification based on atomic physics, and combined with the coupling control of etching rate and sidewall verticality.

[0192] In some embodiments, a predefined plasma dry etching process is used, with the etching target being to remove excess layers in the non-photoresist-covered areas of the light-emitting region and to etch down to the surface of the p-GaP ohmic contact layer.

[0193] Establish an etching rate control model:

[0194] Where vetch is the etching rate. The gas ratio correction coefficient was determined through fitting multiple sets of parallel experiments. P represents the etching chamber pressure, I represents the ICP RF current, and Q represents the total etching gas flow rate. The etching rate control model considers the coupled effects of three key parameters: pressure, RF current, and gas flow rate. The etching chamber pressure was set to 11 Pa, and the ICP RF current to 0.85 A. Substituting these parameters into the model, the calculation yielded... The initial etching time was set at 30.7 minutes.

[0195] During the etching process, the etching endpoint is monitored in real time. The endpoint is identified by dual-spectral monitoring using Ga atomic characteristic lines and P atomic characteristic lines, and an endpoint identification model based on atomic physics is established: Iratio=IGa / IP.

[0196] Where Iratio is the intensity ratio of Ga and P atomic characteristic spectral lines, IGa is the real-time intensity of Ga atomic spectral lines, and IP is the real-time intensity of P atomic spectral lines. In the endpoint identification model, the change in the spectral line intensity ratio Iratio is related to the population of excited-state particles in the plasma. When the etching interface transitions from the (AlGa)InP layer to the GaP layer, the excitation cross-section of Ga atoms undergoes a sudden change, causing the IGa intensity to rise sharply, while the excitation cross-section of P atoms remains basically unchanged, and the IP intensity remains stable. This causes Iratio to jump from the initial value of 0.3 to 1.8, and the inflection point is the etching endpoint.

[0197] After etching, the chip is placed in a plasma cleaner to remove residual polymer and chloride impurities. It is then rinsed with deionized water, and the etched sides are observed using a scanning electron microscope to ensure perpendicularity and the absence of side etching or step residue.

[0198] Furthermore, by combining the parameter coupling model θ=f(dr,vetch,tetch) of S71 and S72, the etching rate vetch and etching time tetch are finely adjusted in real time according to the actual photoresist thickness dr of S71, ensuring that the verticality of the etched sidewall is stable at the optimal value of 89.6° or higher, thus achieving synergistic optimization of the two processes.

[0199] It can be seen that the etching rate control model quantifies the coupling relationship between etching chamber pressure P, ICP RF current I, total gas flow rate Q and etching rate vetch. Etching chamber pressure P affects plasma density and ion mean free path. Excessive pressure will lead to a decrease in ion mean free path, weakening of physical sputtering effect and reduction in etching rate.

[0200] Furthermore, excessively low pressure results in insufficient plasma density and an unstable etching rate. The ICP RF current I determines the plasma energy; a higher current leads to higher plasma energy, stronger ion bombardment, and a faster etching rate. The total gas flow rate Q affects the plasma renewal rate; excessive flow rate results in excessively high plasma density, leading to a fast and uneven etching rate, while insufficient flow rate results in insufficient plasma density and a slow etching rate. This model allows for real-time adjustment of the three parameters P, I, and Q to ensure a stable etching rate with fluctuations ≤1.8%.

[0201] The OES dual-spectral line endpoint identification model is based on the excited-state particle population theory in atomic physics: the Ga and P atom contents of different layers on the chip surface ((AlGa)InP layer, GaP layer) are different. When the etching interface is at the (AlGa)InP layer, the Al atom content is higher and the Ga atom content is lower. The excited-state population of Ga atoms in the plasma is less, the IGa intensity is lower, and Iratio=IGa / IP is maintained at around 0.3.

[0202] When the etching interface transfers to the GaP layer, the Al atom content decreases sharply while the Ga atom content increases significantly. This causes a sudden change in the excitation cross-section of Ga atoms, leading to a significant increase in the excited-state population and a sharp rise in IGa intensity. Meanwhile, the P atom content remains relatively stable in both layers, and the IP intensity remains unchanged. This results in an Iratio jump from 0.3 to 1.8, with this inflection point corresponding to the etching endpoint. Thus, the Iratio effectively eliminates the interference of ICP RF power fluctuations and gas flow fluctuations on spectral intensity, as power fluctuations affect the intensity of both IGa and IP. Since the ratio remains essentially constant, the accuracy of endpoint identification is improved.

[0203] Furthermore, the parameter coupling model θ=f(dr,vetch,tetch) between S71 and S72 works on the principle that the photoresist thickness dr determines the mask selectivity (the ratio of photoresist thickness to etching depth). The higher the mask selectivity, the greater the verticality θ of the etched sidewalls. When dr=1.1μm, the mask selectivity reaches its optimum, and θ=89.6°. Deviations from this thickness will cause the mask selectivity to decrease and θ to decrease. Through this coupling model, vetch and touch can be finely adjusted in real time according to the actual dr value of S71 to ensure that θ is stable at the optimal value, thereby achieving synergistic optimization of the photolithography and etching processes and improving the overall process accuracy.

[0204] S73: Segmented chemical wet roughening of AlInP surface employs a pre-set roughening liquid system, a coupled model of roughness and passivation layer step coverage, and combines segmented roughening with variable-rate stirring to achieve uniform and controllable roughening morphology.

[0205] In some embodiments, after etching is successful, the photoresist on the chip surface is removed first. A preset photoresist stripping solution (NMP:acetone:anhydrous ethanol = 3:1:0.5, volume ratio) is used for constant temperature stripping to allow the stripping solution to fully wet the interface between the photoresist and the chip surface, thereby accelerating the photoresist stripping. The stripping temperature and time are optimized through orthogonal experiments.

[0206] After stripping, the chip is sequentially cleaned with acetone, ethanol, and deionized water. Acetone removes residual photoresist debris, ethanol removes acetone residue, and deionized water removes ethanol residue and other impurities. Nitrogen gas is then used for drying to ensure no photoresist or stripping solution residue remains on the chip surface. Finally, a wet chemical roughening process is performed on the AlInP surface.

[0207] Furthermore, a roughening surface roughness control model is established:

[0208] Where σ is the roughened surface roughness, σ0 is the initial roughness of the chip surface, α is the roughening rate coefficient, and β is the roughening attenuation coefficient. α was determined to be 0.062 nm·s through fitting multiple sets of parallel experiments. -0.41 β=0.0002nm·s -2 t is the coarsening time for a single pass.

[0209] Furthermore, the roughness control model for roughened surfaces considers the nonlinear effect of roughening time on roughness. Initially, as the roughening time increases, the roughness increases with α·t. 0.41 As the roughening time increases, excessive corrosion leads to the erosion of surface protrusions, and the roughness decreases with β·t². Model calculations show that a single roughening cycle is set to 14 seconds, with a total roughening time of 42 seconds for three cycles. Each roughening cycle is spaced 6 minutes apart, during which the chip is rinsed for 12 seconds with deionized water (resistivity ≥18.2 MΩ·cm) to remove residual roughening solution and prevent further corrosion that could form pits or protrusions.

[0210] During the roughening process, a constant-temperature water bath is used to control the temperature. Excessive temperature will accelerate the corrosion rate, leading to excessive roughness, while insufficient temperature will result in a slow corrosion rate, failing to achieve the target roughness. A magnetic stirrer is also used to gently stir the roughening solution to ensure uniform concentration and consistent roughening rates across all areas of the chip surface.

[0211] After roughening, the chip is immersed in a pre-set neutralization solution (ammonia:deionized water:anhydrous ethanol = 1:10:1, volume ratio) for 11 seconds to quickly neutralize residual HF and terminate the roughening reaction. The anhydrous ethanol in the neutralization solution improves its fluidity, ensuring uniform neutralization. The chip is then rinsed with deionized water and dried. Surface roughness is measured using an atomic force microscope. The measurement area includes the chip center and four corners (5 points in total). A roughening uniformity evaluation model is established: CVσ = (σstd / σavg) × %, where σstd is the standard deviation of roughness at the 5 measurement points, and σavg is the average roughness at the 5 measurement points. CVσ is controlled to be within 7.5%.

[0212] Furthermore, a parameter coupling model for S73 and S74 is established: Where C is the passivation layer step coverage, α is the proportionality coefficient (which can be 0.85), σ is the roughness, and λ is the mean free path of the passivation layer. Through the parameter coupling model, it is proved that when σ = 0.32~0.48nm, C>90%, and the passivation layer can completely cover the micro-nano morphology of the roughened surface. When σ < 0.3 nm, C < 80%, the passivation layer cannot cover the valley bottom of the roughened surface, and is prone to damage; When σ>0.48nm, C>90%, but excessive surface roughness leads to increased light scattering, affecting the uniformity of light output.

[0213] This embodiment strictly controls the roughness within the range of 0.32~0.48nm, achieving synergistic optimization of the roughening and passivation processes. Chips with roughness outside the 0.32~0.48nm range or CVσ exceeding 7.5% are re-roughened; qualified chips proceed to the next process.

[0214] It can be seen that the roughening surface roughness control model quantifies the nonlinear relationship between roughening time t and roughness σ. In the initial stage, the corrosion reaction mainly occurs at the defects on the AlInP surface, forming tiny pits and protrusions, and the roughness increases with the extension of roughening time. When the roughening time is too long, the corrosion reaction proceeds further, the surface protrusions are gradually eroded, the pits are gradually filled, and the roughness begins to decrease, which is manifested by subtracting the β·t² term, where β is the roughening attenuation coefficient, which is positively correlated with the HF concentration. The roughening surface roughness control model considers the growth and attenuation modes during the roughening process, and by controlling the single roughening time, ensures that the roughness is stable within the target range of 0.32~0.48 nm.

[0215] The AFM multi-point detection and roughening uniformity evaluation model, selecting the center plus the four corners, can comprehensively reflect the roughening uniformity of the chip surface. The roughening uniformity evaluation model CVσ quantifies the roughening uniformity by calculating the ratio of the standard deviation to the mean of the roughness. CVσ is controlled within 7.5% to ensure consistent roughness across all areas of the chip surface. In the parameter coupling model of S73 and S74, the roughening roughness σ determines whether the passivation layer molecules can cover the micro-nano morphology of the surface. If σ is too small, the surface is too flat, and the passivation layer molecules are prone to forming discontinuous films on the surface, reducing the step coverage rate C. If σ is too large, the surface is uneven, and although the passivation layer molecules can cover it, it will lead to surface stress concentration and cracking. Through the roughening uniformity evaluation model, the roughening roughness and the passivation layer step coverage rate can be synergistically optimized to ensure that the roughening effect meets the light extraction efficiency requirements.

[0216] Furthermore, considering the segmented chemical wet roughening of AlInP surfaces, under 20mA testing conditions, as shown in Table 1 and... Figure 3 As shown, a 10% increase in brightness corresponds to a voltage increase of approximately 0.01V.

[0217] Table 1: Comparison of Segmented Chemical Wet Roughening Methods for AlInP Surfaces

[0218] S74: Low-temperature deposition of SiN passivation layer on chip surface and patterned windowing of pad area. Low-temperature PECVD deposition and deposition rate control based on multivariable coupling are used, combined with a preset etching system to achieve uniform coverage and windowing of passivation layer.

[0219] In some embodiments, the roughened and qualified chip is transferred to a plasma-enhanced chemical vapor deposition (PECVD) apparatus to deposit a SiN passivation layer, which is used to protect the chip surface roughening layer and functional layer and improve the long-term reliability of the chip.

[0220] Furthermore, after deposition, the chip is removed from the PECVD equipment and allowed to cool naturally to room temperature (cooling rate ≤2℃ / min) to avoid rapid cooling that could cause thermal stress between the passivation layer and the chip surface, leading to cracking of the passivation layer. The cooling rate was determined experimentally, balancing cooling efficiency with passivation layer integrity. Subsequently, the passivation layer is patterned and windowed to expose the pad electrode area, ensuring conductivity during subsequent soldering.

[0221] S75: The chip is thinned, layered back gold evaporation is performed, and laser segmented cutting is carried out. The segmented cutting stress release based on thermoelastic mechanics, the thinning and back gold control of multi-parameter coupling, and the separation is achieved by combining digital twin state feedback.

[0222] In some embodiments, after the passivation layer is successfully windowed, the chip undergoes a thinning process using a diamond abrasive pad. During the thinning process, a thickness monitor is used to monitor the chip thickness in real time. Afterwards, polishing is performed to remove surface scratches generated during the grinding process. Following thinning and polishing, the chip is transferred to an electron beam evaporation machine for layered back gold deposition.

[0223] After the back gold coating is completed, the chip is transferred to an ultraviolet laser cutting machine. The cutting process employs a two-stage method: the first stage cuts to 72% of the chip thickness, pausing for a certain period to release the thermal stress generated during cutting; the second stage cuts to the bottom of the chip, completing the cutting. After cutting, a mechanical dicing process is used, with real-time observation using an optical microscope to prevent over-dicing and chip damage. Individual chips are inspected using an optical microscope, and defective chips with damage, cracks, back gold coating detachment, or pad electrode obstruction are discarded, yielding qualified single AlGaInP red light-emitting diode devices.

[0224] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0225] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for epitaxial growth and chip fabrication of an AlGaInP red light-emitting diode, characterized in that the method... include: S1: An epitaxial layer structure is grown sequentially from bottom to top on a GaAs substrate, including a buffer layer, an AlInP etch stop layer, an n-type ohmic contact layer, an n-type waveguide layer, a multiple quantum well layer, a p-type waveguide layer, and a p-type ohmic contact layer. S2: A SiO2 insulating layer is deposited on the upper surface of the epitaxial wafer by PECVD, and the SiO2 insulating layer is photolithographically etched and etched to form a rectangular array of openings. S3: The p-electrode ohmic contact layer, adhesion layer and metal connection layer are sequentially deposited in the opening of the SiO2 insulating layer, and then subjected to high-temperature annealing. S4: A metal interconnect layer is deposited on the surface of the Si substrate. The epitaxial wafer treated in S3 is bonded to the Si substrate at a low temperature. After bonding, the temperature is reduced in stages to complete the transfer of the epitaxial wafer from the GaAs substrate to the Si substrate. S5: The GaAs substrate is removed by wet etching, which terminates at the AlInP etching stop layer. The upper GaInP layer is removed and the n-type ohmic contact layer is surface treated to expose the n-type conductive layer base for fabricating the n-electrode. S6: The n-electrode pad layer is prepared by photolithography and electron beam evaporation, and then subjected to high-temperature annealing to complete the n-electrode pad preparation and realize the n-type side electrode lead-out of the chip; S7: Through photolithography, ICP etching, chemical wet roughening, passivation layer deposition, chip thinning, back gold evaporation and laser cutting, the chip light-emitting area is patterned, surface roughened, passivated and protected, thickness adjusted and device separated, and finally a red light-emitting diode chip is obtained.

2. The method for epitaxial growth and chip fabrication of AlGaInP red light-emitting diodes according to claim 1, characterized in that, S1 specifically includes the following steps: S11: The GaAs substrate surface is treated with ultrasonic cleaning and high-temperature deoxidation, and a GaAs buffer layer is deposited by silane pulse doping. S12: Ensure aluminum-free Ga0 growth on the buffer layer by zeroing the TMAl flow rate. 48 In0. 52 The PAlInP corrosion-stopping layer was deposited, and the lattice constant was detected by in-situ X-ray diffraction after deposition. The TMIn flow rate was adjusted in real time to make the lattice mismatch less than 0.001 Å. S13: Pulse doping growth of ohmic contact layer, segmented stress-controlled growth of n-AlInP coarsening extension layer and deposition of n-(AlGa)InP waveguide layer are performed sequentially on AlInP corrosion stop layer. S14: 42 pairs of quantum wells and quantum barriers are alternately deposited on the n-type waveguide layer to form a multi-quantum well layer. Then, p-AlInP extended layer, p-type waveguide layer, p-GaInP transition layer, p-superlattice layer, second p-type waveguide layer, second transition layer and p-GaP ohmic contact layer are grown sequentially. The hole injection rate of the superlattice layer is controlled by matching the hole transit time and recombination time. S15: Real-time acquisition of growth data, adjustment of layer thickness, composition and doping concentration, and control through adaptive adjustment of PID parameters and feedforward compensation.

3. The method for epitaxial growth and chip fabrication of AlGaInP red light-emitting diodes according to claim 2, characterized in that, S13 specifically includes the following steps: S131: An ohmic contact layer was grown on the GaInP / AlInP etch stop layer using a Si2H6 pulse doping process. The peak doping concentration was achieved to 6 × 10¹ by controlling the on / off ratio of 1:3 and the preset growth temperature. 8 cm - ³ and the average concentration is 5.5 × 10¹ 8 cm - ³; S132: Based on the critical thickness hc=6Å, the n-AlInP coarsening extension layer on the ohmic contact layer is designed as 6 sub-layers for segmented growth. After each sub-layer is grown, the temperature is reduced to 715℃ and held for 2 minutes to release thermal stress. The measured thickness is used to correct the growth parameters of the next sub-layer and the stress accumulation value is monitored in real time. S133: An n-(AlGa)InP waveguide layer was grown on an n-AlInP coarsened extended layer. The Al composition x=0.7 was controlled by adjusting the TMAl to TMGa flow rate ratio and the refractive index was reduced to 2.94 by coordinating the PH3 flow rate. A 700Å thick layer was deposited at 730℃.

4. The method for epitaxial growth and chip manufacturing of AlGaInP red light-emitting diodes according to claim 2, characterized in that, S14 specifically includes the following steps: S141: A multi-quantum-well layer is formed by alternating growth of 42 pairs of quantum wells and quantum barriers on an n-type waveguide layer, wherein the quantum wells are Al0. 18 Ga0. 82 The InP layer is 50 Å thick, the quantum barrier is Al0.7Ga0.3InP layer is 80 Å thick, the growth temperature is 725℃ and the V / Ⅲ ratio is 80; S142: Five pairs of (Al0) are grown on a multi-quantum well layer. 68 Ga0. 32 InP / AlInP superlattice layers, each pair containing (Al0) 68 Ga0. 32 With InP layer thickness of 70 Å and AlInP corrosion stop layer thickness of 70 Å, band engineering was achieved by controlling the hole transit time to match the recombination time of the multiple quantum well layers. S143: p-AlInP extended layers and p-(Al0) layers are sequentially grown on the superlattice layer. 68 Ga0. 32 InP waveguide layer, p-GaInP transition layer, p-(Al0) 63 Ga0. 37 The InP waveguide layer, the second p-GaInP transition layer, and the p-GaP ohmic contact layer were deposited according to the set values ​​for thickness, composition, and doping concentration.

5. The method for epitaxial growth and chip fabrication of AlGaInP red light-emitting diodes according to claim 1, characterized in that, S4 specifically includes the following steps: S41: The Si substrate is subjected to ultrasonic cleaning and nitrogen blowing treatment to remove surface oil and particulate impurities. S42: Electron beam evaporation is used to deposit a metal interconnect layer on the pretreated Si substrate to ensure uniform layer thickness and satisfactory adhesion. S43: Align and bond the epitaxial wafer obtained in S3 with its p-electrode side facing up to the Si substrate after the metal layer has been deposited, and place it into the bonding chamber. S44: After evacuating the bonding chamber, high-purity Ar gas is introduced, and low-temperature metal bonding is performed at 200℃±10 and 8MPa±0.5 pressure to form a connection between the epitaxial wafer and the Si substrate through the metal layer. S45: After bonding is completed, a three-stage cooling process is adopted. First, the temperature is slowly reduced from 200℃ to 120℃ and held. Then, it is reduced to 60℃ and held. Finally, it is naturally cooled to room temperature to gradually release the interfacial thermal stress. S46: Perform shear strength and conductivity tests on the bonded components after cooling.

6. The method for epitaxial growth and chip fabrication of an AlGaInP red light-emitting diode according to claim 1, characterized in that, S6 specifically includes the following steps: S61: Pre-treatment and photoresist coating of the n-electrode pad area before photolithography; S62: n-electrode pad patterning photolithography and development and fixing process; S63: n-electrode pad layer layered electron beam evaporation and thickness control; S64: High-temperature annealing and photoresist removal of the n-electrode pad layer.

7. The method for epitaxial growth and chip fabrication of AlGaInP red light-emitting diodes according to claim 1, characterized in that, S7 specifically includes the following steps: S71: The chip's light-emitting area is patterned using photolithography. Pre-processing and photoresist coating control based on non-Newtonian fluid dynamics modeling are employed, combined with real-time detection and feedback correction of pattern deviations, to achieve pattern formation of the light-emitting area. S72: ICP plasma etching of the luminescent area, using a preset etching gas ratio, OES dual-spectral endpoint identification based on atomic physics, and combined with the coupling control of etching rate and sidewall verticality. S73: Segmented chemical wet roughening of AlInP surface adopts a pre-set roughening liquid system, a coupled model of roughness and passivation layer step coverage, and combines segmented roughening with variable rate stirring to achieve uniform and controllable roughening morphology. S74: Low-temperature deposition of SiN passivation layer on chip surface and patterned windowing of pad area. Low-temperature PECVD deposition and deposition rate control based on multivariable coupling are used, combined with a preset etching system to achieve uniform coverage and windowing of passivation layer. S75: Chip thinning, layered back gold evaporation and laser segmented cutting. It adopts segmented cutting stress release based on thermoelasticity, thinning and back gold control with multi-parameter coupling, and digital twin state feedback to achieve separation.

8. The method for epitaxial growth and chip fabrication of AlGaInP red light-emitting diodes according to claim 7, characterized in that, S72 specifically includes the following steps: Set the etching chamber pressure, ICP RF current and total gas flow rate, and substitute these three parameters into the etching rate control model to calculate the initial etching time; During the etching process, OES dual-line monitoring was used to monitor the intensity of characteristic spectral lines of Ga and P atoms, and the intensity ratio Iratio was calculated in real time. Etching was stopped when Iratio jumped from 0.3 to 1.

8. After etching, the chip is placed in a plasma cleaner to remove residual polymer and Cl elements, rinsed with deionized water, and the perpendicularity of the etched side is checked by scanning electron microscopy. Based on the measured photoresist thickness, the etching rate and etching time are finely adjusted using a parameter coupling model.

9. The method for epitaxial growth and chip fabrication of an AlGaInP red light-emitting diode according to claim 7, characterized in that, S73 specifically includes the following steps: The etched chip was immersed in a stripping solution prepared with NMP, acetone and anhydrous ethanol in a volume ratio of 3:1:0.5 and stripped at a constant temperature to remove the photoresist from the chip surface. After the photoresist stripping is completed, the chip is cleaned with acetone, ethanol and deionized water in sequence to remove residual debris and impurities. After being dried with nitrogen, a clean AlInP surface is obtained. The cleaned chip is immersed in a roughening solution for segmented chemical wet roughening. The roughening time is set by a roughening surface roughness control model and repeated three times. During each roughening interval, the chip is rinsed with deionized water to remove residual roughening solution. During the roughening process, a constant temperature water bath is used to control the temperature, and a magnetic stirrer is used to stir the roughening liquid at a variable speed to maintain uniform concentration. After roughening is completed, the chip is immersed in a pre-prepared neutralization solution made of ammonia, deionized water and anhydrous ethanol to stop the roughening reaction, and then rinsed with deionized water and dried. The roughness of the chip center and four corners was detected by atomic force microscopy. The CVσ value was calculated by the roughness uniformity evaluation model. Chips with CVσ≤7.5% and roughness in the range of 0.32~0.48nm were judged as qualified. The roughness of the qualified chip is substituted into the coupling model of roughness and passivation layer step coverage. The step coverage output by the model is used to determine whether the roughness morphology meets the requirements of subsequent passivation layer deposition.

10. An AlGaInP red light-emitting diode epitaxial layer and chip, characterized in that, Manufactured based on the AlGaInP red light-emitting diode epitaxial and chip manufacturing method according to any one of claims 1 to 9; This includes: epitaxial functional layer components, electrode and bonding components, support substrate components, and passivation and back gold components; The epitaxial functional layer assembly is disposed on a temporary growth substrate. The epitaxial functional layer assembly includes: a GaAs substrate, a GaAs buffer layer epitaxially grown on the GaAs substrate, a GaInPAlInP etch stop layer disposed on the GaAs buffer layer, an ohmic contact layer, an n-AlInP roughening and extension layer and an n-(AlGa)InP waveguide layer sequentially stacked on the GaInPAlInP etch stop layer; and a multi-quantum well layer disposed on the n-(AlGa)InP waveguide layer. A p-AlInP extended layer, a p-(AlGa)InP waveguide layer, a p-GaInP transition layer, a p-superlattice layer, a p-(AlGa)InP waveguide layer, a p-GaInP transition layer, and a p-GaP ohmic contact layer are sequentially stacked on top of the multi-quantum well layer. A patterned SiO2 layer is disposed on the surface of the p-GaP ohmic contact layer, and a rectangular array of electrode holes is formed on the SiO2 layer; a p-electrode ohmic contact layer is disposed and filled in the electrode holes, and the p-electrode ohmic contact layer is in direct contact with the p-GaP ohmic contact layer. The supporting substrate assembly includes a Si substrate, on the upper surface of which a metal interconnect layer is disposed; the metal interconnect layers are bonded together by a low-temperature bonding process to form a bonding interface. A passivation layer is formed on the surface of the chip, covering the roughened surface and sidewalls of the n-AlInP roughening and extension layers, and an electrode is exposed by opening a window in the n-electrode pad layer region.

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