High-side driver turn-off circuit, chip and electronic device

Abstract

The application discloses a turn-off circuit of a high-side driver, a chip and electronic equipment, and belongs to the field of driving circuits. A detection circuit outputs a first type of control signal in response to a gate-source voltage of a power tube being greater than or equal to a first threshold voltage, outputs a second type of control signal in response to the gate-source voltage of the power tube being less than the first threshold voltage and greater than or equal to a second threshold voltage, and outputs a third type of control signal in response to the gate-source voltage of the power tube being less than the second threshold voltage. A bias output circuit outputs a first bias voltage in response to the first type of control signal, outputs a second bias voltage in response to the second type of control signal, and outputs a third bias voltage in response to the third type of control signal. A driving circuit outputs a pull-down current according to the bias voltages, so as to pull down the gate-source voltage of the power tube. The third bias voltage, the first bias voltage and the second bias voltage decrease in sequence, and the bias voltages are positively correlated with the pull-down current. Therefore, the efficiency, reliability and safety are improved.

Description

Technical Field

[0001] This application belongs to the field of driver circuit technology, and particularly relates to a turn-off circuit, chip and electronic device of a high-side driver. Background Technology

[0002] High-side switches are widely used in automotive electronics and industrial control to drive resistive, capacitive, and inductive loads. During the high-side switch turn-off process, especially when driving inductive loads, if the turn-off rate is too fast and the di / dt change is large, a large voltage spike will be generated in the inductor, potentially damaging the high-side switch. External high-side switches typically have lower on-resistance and higher current-carrying capacity, but their turn-off process may generate even higher voltage spikes. External power transistors offer greater flexibility in device selection, and their parasitic parameters vary, leading to greater uncertainty in turn-off control. Therefore, achieving safe turn-off of external power transistors driving inductive loads has become a key challenge in high-side switch design.

[0003] To achieve safe turn-off of inductive loads, the turn-off circuit of the relevant high-side driver discharges the gate-source voltage of the power transistor with a small current. By controlling the gate-source voltage to decrease at a slow rate, the rate of change of the power transistor current is reduced, thereby reducing the voltage stress generated during the turn-off process. However, turning off the power transistor with a constant small current results in a relatively long turn-off time, significant heat loss in the power transistor, affecting turn-off speed and efficiency, and may even lead to overheating and damage to the power transistor.

[0004] Therefore, the shutdown circuit of the related high-side driver has low efficiency, poor reliability and security. Summary of the Invention

[0005] The purpose of this application is to provide a shutdown circuit, chip, and electronic device for a high-side driver, which aims to solve the problems of low regulation efficiency, poor reliability, and poor security of the shutdown circuit of the related high-side driver.

[0006] This application provides a high-side driver shutdown circuit connected to a power transistor, comprising:

[0007] A detection circuit, connected to the power transistor, is used to output a first type of control signal in response to the gate-source voltage of the power transistor being greater than or equal to a first threshold voltage, and to output a second type of control signal in response to the gate-source voltage of the power transistor being less than the first threshold voltage but greater than or equal to a second threshold voltage, and to output a third type of control signal in response to the gate-source voltage of the power transistor being less than the second threshold voltage. A bias output circuit, connected to the detection circuit, is used to output a first bias voltage in response to a first type of control signal, output a second bias voltage in response to a second type of control signal, and output a third bias voltage in response to a third type of control signal. A driving circuit, connected to the detection circuit, the bias output circuit, and the power transistor, is used to output a pull-down current according to each of the bias voltages to pull down the gate-source voltage of the power transistor. The third bias voltage, the first bias voltage, and the second bias voltage decrease sequentially, and the bias voltage is positively correlated with the pull-down current.

[0008] In one embodiment, the control signal includes a first control signal and a second control signal; the detection circuit includes: A first comparison circuit, connected to the power transistor, is used to compare the gate-source voltage of the power transistor with the first threshold voltage to output a first comparison signal; The second comparison circuit, connected to the power transistor, is used to compare the gate-source voltage of the power transistor with the second threshold voltage to output a second comparison signal; A first logic circuit, connected to the bias output circuit, the first comparison circuit, and the second comparison circuit, is used to perform an OR operation on the first comparison signal and the second comparison signal to output the first control signal. The second logic circuit, connected to the bias output circuit, the first comparison circuit, and the second comparison circuit, is used to invert the first comparison signal and perform an AND operation on the inverted first comparison signal and the second comparison signal to output the second control signal.

[0009] In one embodiment, the driving circuit includes a driving transistor; the bias output circuit includes a first switching circuit, a second switching circuit, a first equivalent resistor assembly, a second equivalent resistor assembly, and a first clamping circuit. The first switching circuit is connected to the first logic circuit, and uses the first control signal in response to the first level to connect the first equivalent resistance component between the gate and the source of the driving transistor. The second switching circuit, connected to the second logic circuit, uses the second control signal in response to the first level to connect the second equivalent resistor component between the gate and the source of the driving transistor; The first clamping circuit is connected to the first equivalent resistor assembly, the second equivalent resistor assembly and the driving transistor, and is used to clamp the gate-source voltage of the driving transistor to the third bias voltage. Wherein, the first equivalent resistance component is used to output the first bias voltage based on the input bias current; the first equivalent resistance component and the second equivalent resistance component connected in parallel are used to output the second bias voltage based on the input bias current.

[0010] In one embodiment, the source of the power transistor is connected to signal ground, and the turn-off circuit of the high-side driver further includes: A first current source is used to provide the bias current; The third switching circuit is connected to the driving circuit, the first clamping circuit, the first current source and the first switching circuit, and is used to transmit the bias current in response to the enable signal, and to disconnect the output of the bias current in response to the disconnection of the enable signal. A pull-down circuit, connected to the third switching circuit, the first clamping circuit, the first switching circuit, and the drive circuit, is used to pull down the gate of the power transistor to signal ground when the bias current is disconnected.

[0011] In one embodiment, it further includes: A negative voltage clamping circuit, connected to the power transistor, the driving circuit, and the bias output circuit, is used to pull down the bias voltage in response to the source voltage of the power transistor being less than a first preset voltage, and to clamp the gate voltage of the power transistor to a second preset voltage. The driving circuit is also used to disconnect the output of the pull-down current based on the bias voltage after pull-down, so as to stop pulling down the gate-source voltage of the power transistor; Wherein, the second preset voltage is greater than the first preset voltage.

[0012] In one embodiment, the negative pressure clamping circuit includes: A translation circuit is used to shift the voltage from the power supply to ground to output a shifted voltage. The termination circuit, connected to the translation circuit, the power transistor, and the bias output circuit, is used to pull down the bias voltage based on the translation voltage in response to the source voltage of the power transistor being less than a first preset voltage.

[0013] In one embodiment, the negative pressure clamping circuit further includes: A source follower circuit, connected to the translation circuit, the termination circuit, the drive circuit, and the power transistor, is used to follow the translation voltage to clamp the gate voltage of the power transistor to a second preset voltage.

[0014] In one embodiment, the negative pressure clamping circuit further includes: The second clamping circuit, connected to the translation circuit and the source follower circuit, is used to clamp the translation voltage.

[0015] This invention also provides a chip that includes the shutdown circuit of the high-side driver described above.

[0016] This invention also provides an electronic device, which includes a power transistor and the shutdown circuit of the high-side driver described above.

[0017] The beneficial effects of this invention compared to the prior art are as follows: The detection circuit responds to the gate-source voltage of the power transistor being greater than or equal to a first threshold voltage, outputting a first type of control signal to cause the bias output circuit to respond to the first type of control signal and output a first bias voltage; the detection circuit responds to the gate-source voltage of the power transistor being less than the first threshold voltage but greater than or equal to a second threshold voltage, outputting a second type of control signal to cause the bias output circuit to respond to the second type of control signal and output a second bias voltage; the detection circuit responds to the gate-source voltage of the power transistor being less than the second threshold voltage, outputting a third type of control signal to cause the bias output circuit to respond to the third type of control signal and output a third bias voltage; the driving circuit outputs a pull-down current according to each bias voltage to pull down the gate-source voltage of the power transistor; wherein, the third bias voltage, the first bias voltage, and the second bias voltage decrease sequentially, and the bias voltage is positively correlated with the pull-down current; therefore, when the gate-source voltage of the power transistor is greater than or equal to the first threshold voltage, a large current is used. Rapidly pulling down the gate-source voltage of the power transistor allows it to quickly enter the saturation region, reducing heat loss during conduction. As the gate-source voltage decreases to the first threshold voltage, the pull-down current decreases, reducing the turn-off rate. Thus, when the gate-source voltage is pulled down to near the Miller plateau, a small current is used to pull it down at a slower rate, ensuring a low current change rate during turn-off and preventing voltage spikes in the drain-source voltage that could damage the power transistor due to overvoltage. When the gate-source voltage decreases to the second threshold voltage, a large current is used to rapidly pull it down again. That is, when the gate-source voltage drops below the Miller plateau, the current has already decreased to a low level. Using a large current to pull the gate-source voltage down to 0 completely turns off the power transistor, improving turn-off efficiency. This improves the efficiency, reliability, and safety of the high-side driver's turn-off circuit. Attached Figure Description

[0018] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a shutdown circuit for a related high-side driver. Figure 2This is a schematic diagram of another structure for the shutdown circuit of the related high-side driver; Figure 3 This is a schematic diagram of another structure for the shutdown circuit of the related high-side driver; Figure 4 A schematic diagram of a high-side driver shutdown circuit provided in an embodiment of this application; Figure 5 A schematic diagram of a detection circuit in the turn-off circuit of a high-side driver provided in an embodiment of this application; Figure 6 A schematic diagram of the bias output circuit in the turn-off circuit of a high-side driver provided in an embodiment of this application; Figure 7 This is a schematic diagram of another structure of the bias output circuit in the shutdown circuit of the high-side driver provided in an embodiment of this application; Figure 8 A schematic diagram of another structure of the high-side driver turn-off circuit provided in an embodiment of this application; Figure 9 This is a schematic diagram of a negative voltage clamping circuit in the turn-off circuit of a high-side driver provided in an embodiment of this application. Figure 10 This is a schematic diagram of a negative voltage clamping circuit in the turn-off circuit of a high-side driver provided in an embodiment of this application. Figure 11 This is a schematic diagram of another structure of the negative voltage clamping circuit in the turn-off circuit of the high-side driver provided in an embodiment of this application; Figure 12 A partial example circuit schematic of a high-side driver shutdown circuit provided in an embodiment of this application; Figure 13 The main signal waveform diagram of the high-side driver shutdown circuit provided in an embodiment of this application. Detailed Implementation

[0020] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0021] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0022] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0024] To achieve different pull-down rates, different currents are needed to discharge the gate-source voltage of the power transistor. The first related high-side driver turn-off circuit is as follows: Figure 1 As shown, by directly controlling current sources of different magnitudes to pull down the gate source voltage, this method requires a large number of components, leading to increased area and cost. The second related high-side driver turn-off circuit is shown below. Figure 2 As shown, the pull-down rate of the gate-source voltage is changed by altering the magnitude of the reference current of the current mirror by using a current mirror to pull down the gate-source voltage of the power transistor. This method is simpler to control, but the reference current flows out from the output terminal, and an increase in the reference current leads to increased leakage current and quiescent power consumption. On the other hand, during the turn-off control process, the turn-off threshold and slope are usually preset fixed values. When driving an external power transistor, due to differences in load characteristics and parasitic parameters, the preset turn-off control may still cause the voltage spike generated during turn-off to exceed the power transistor's withstand voltage, resulting in power transistor damage. To further enhance reliability, a freewheeling diode is usually added between the source of the power transistor and the power supply ground, such as... Figure 3 As shown, when a negative voltage appears at the source of the power transistor, the diode conducts to form a freewheeling circuit, suppressing negative voltage spikes. However, adding a freewheeling diode requires additional cost.

[0025] To address the issues of high cost and static power consumption, the applicant discovered that, in the design, when the gate-source voltage of the power transistor is within a preset threshold range, the detection circuit controls the bias output circuit to reduce the bias voltage, thereby reducing the pull-down current of the drive circuit. This eliminates the need for multiple current sources, reduces the possibility of leakage current, and eliminates the need for freewheeling diodes, thus reducing cost and static power consumption.

[0026] Figure 4A schematic diagram of the high-side driver shutdown circuit provided in a preferred embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below: The shutdown circuit of the high-side driver described above is connected to the power transistor M01 and includes a detection circuit 10, a bias output circuit 20, and a drive circuit 30.

[0027] The detection circuit 10 is connected to the power transistor M01 and is used to output a first type of control signal in response to the gate-source voltage of the power transistor M01 being greater than or equal to the first threshold voltage Vth1, and to output a second type of control signal in response to the gate-source voltage of the power transistor M01 being less than the first threshold voltage Vth1 and greater than or equal to the second threshold voltage Vth2, and to output a third type of control signal in response to the gate-source voltage of the power transistor M01 being less than the second threshold voltage Vth2.

[0028] The bias output circuit 20 is connected to the detection circuit 10 and is used to output a first bias voltage Vgate1 in response to a first type of control signal, output a second bias voltage Vgate2 in response to a second type of control signal, and output a third bias voltage Vgate3 in response to a third type of control signal.

[0029] The driving circuit 30 is connected to the detection circuit 10, the bias output circuit 20 and the power transistor M01, and is used to output pull-down current according to each bias voltage to pull down the gate-source voltage of the power transistor M01. Among them, the third bias voltage Vgate3, the first bias voltage Vgate1, and the second bias voltage Vgate2 decrease sequentially, and the bias voltage is positively correlated with the pull-down current.

[0030] It is understood that the drive circuit 30 is specifically used to output a first pull-down current according to the first bias voltage Vgate1, a second pull-down current according to the second bias voltage Vgate2, and a third pull-down current according to the third bias voltage Vgate3, so as to pull down the gate-source voltage of the power transistor M01; the third pull-down current, the first pull-down current, and the second pull-down current decrease sequentially.

[0031] It is understandable that the drain of power transistor M01 can be connected to the power supply VCC, and the source of power transistor M01 can be connected to the signal ground.

[0032] When the gate-source voltage of power transistor M01 is greater than or equal to the first threshold voltage Vth1, a large current is used to rapidly pull down the gate-source voltage of power transistor M01, causing power transistor M01 to quickly enter the saturation region, reducing heat loss during this conduction process. When the gate-source voltage of power transistor M01 decreases to the first threshold voltage Vth1, the pull-down current decreases, reducing the turn-off rate of power transistor M01. Therefore, when the gate-source voltage of power transistor M01 is pulled down to near the Miller plateau, a small current is used to pull down the gate-source voltage of power transistor M01, controlling the gate-source voltage of power transistor M01 to decrease at a lower rate, ensuring a lower current change rate during this turn-off process, preventing... To prevent voltage spikes in the drain-source voltage of power transistor M01, which could lead to overvoltage damage, a large current is used to rapidly pull down the gate-source voltage of power transistor M01 after the gate-source voltage of power transistor M01 decreases to the second threshold voltage Vth2. That is, when the gate-source voltage of power transistor M01 drops below the Miller plateau, the current of power transistor M01 has already dropped to a low level. Using a large current to pull down the gate-source voltage of power transistor M01 quickly to 0, the gate-source voltage of power transistor M01 is completely turned off, improving the turn-off efficiency. This improves the efficiency, reliability, and safety of the high-side driver's turn-off circuit.

[0033] like Figure 2 As shown, the control signals include a first control signal and a second control signal; the detection circuit 10 includes a first comparison circuit 11, a second comparison circuit 12, a first logic circuit 13, and a second logic circuit 14.

[0034] The first comparison circuit 11 is connected to the power transistor M01 and is used to compare the gate-source voltage of the power transistor M01 with the first threshold voltage Vth1 to output a first comparison signal.

[0035] The second comparison circuit 12 is connected to the power transistor M01 and is used to compare the gate-source voltage of the power transistor M01 with the second threshold voltage Vth2 to output a second comparison signal.

[0036] The first logic circuit 13 is connected to the bias output circuit 20, the first comparison circuit 11, and the second comparison circuit 12, and is used to perform an OR operation on the first comparison signal and the second comparison signal to output the first control signal.

[0037] The second logic circuit 14 is connected to the bias output circuit 20, the first comparison circuit 11, and the second comparison circuit 12. It is used to invert the first comparison signal and perform an AND operation on the inverted first comparison signal and the second comparison signal to output the second control signal.

[0038] It is understood that the detection circuit 10 also includes a first reference circuit 15 and a second reference circuit 16.

[0039] A first reference circuit, connected to a first comparator circuit 11, is used to provide a first threshold voltage Vth1.

[0040] The second reference circuit, connected to the second comparator circuit 12, is used to provide the second threshold voltage Vth2.

[0041] In specific implementation, when the gate voltage of power transistor M01 is greater than or equal to the first threshold voltage Vth1, the first comparator circuit 11 outputs a first comparison signal at a first level; when the gate voltage of power transistor M01 is less than the first threshold voltage Vth1, the first comparator circuit 11 outputs a first comparison signal at a second level. When the gate voltage of power transistor M01 is greater than or equal to the second threshold voltage Vth2, the second comparator circuit 12 outputs a first comparison signal at a first level; when the gate voltage of power transistor M01 is less than the second threshold voltage Vth2, the second comparator circuit 12 outputs a second comparison signal at a second level.

[0042] Through the above technical solution, the first type of control signal to the third type of control signal can be output based on the comparison results of the gate-source voltage of the power transistor M01 with the first threshold voltage Vth1 and the second threshold voltage Vth2. Thus, the gate voltage of the power transistor M01 can be pulled down at different rates according to the comparison results at different stages of turn-off, which improves the efficiency of the turn-off circuit of the high-side driver, while also improving reliability and safety.

[0043] like Figure 3 As shown, the driving circuit 30 includes a driving transistor M02; the bias output circuit 20 includes a first switching circuit 21, a second switching circuit 22, a first equivalent resistor component 23, a second equivalent resistor component 24, and a first clamping circuit 25.

[0044] The first switching circuit 21 is connected to the first logic circuit 13, and uses a first control signal in response to the first level to connect the first equivalent resistor component 23 between the gate and the source of the driving transistor MU2.

[0045] The second switching circuit 22 is connected to the second logic circuit 14, and uses a second control signal in response to the first level to connect the second equivalent resistor component 24 between the gate and the source of the driving transistor MU2.

[0046] The first clamping circuit 25 is connected to the first equivalent resistor component 23, the second equivalent resistor component 24 and the driving transistor M02, and is used to clamp the gate-source voltage of the driving transistor M02 at the third bias voltage Vgate3.

[0047] The first equivalent resistor component 23 is used to output a first bias voltage Vgate1 based on the input bias current; the first equivalent resistor component 23 and the second equivalent resistor component 24 connected in parallel are used to output a second bias voltage Vgate2 based on the input bias current.

[0048] Understandably, when the gate voltage of power transistor M01 is greater than or equal to the first threshold voltage Vth1, the first control signal is at the first level, the second control signal is at the second level, and only the first equivalent resistor component 23 is connected between the gate and source of driving transistor M02; when the gate voltage of power transistor M01 is less than the first threshold voltage Vth1 but greater than or equal to the second threshold voltage Vth2, both the first and second control signals are at the first level, and the first equivalent resistor component 23 and the second equivalent resistor component 24 are connected in parallel between the gate and source of driving transistor M02. Between the source and gate of M02; when the gate voltage of power transistor M01 is less than the second threshold voltage Vth2, both the first and second control signals are at the second level, and no equivalent resistor component is connected between the gate and source of driving transistor M02. At this time, the first clamping circuit 25 clamps the gate-source voltage of driving transistor M02 at the third bias voltage Vgate3; thus, based on the comparison result of the gate-source voltage of power transistor M01 with the first threshold voltage Vth1 and the second threshold voltage Vth2, the first bias voltage Vgate1 to the third bias voltage Vgate3 are output. Among them, the first level and the second level have opposite polarities.

[0049] like Figure 4 As shown, the source of the power transistor M01 is connected to the signal ground. The turn-off circuit of the high-side driver also includes a first current source I1, a third switching circuit 26, and a pull-down circuit 27.

[0050] The first current source I1 is used to provide bias current.

[0051] The third switching circuit 26 is connected to the drive circuit 30, the first clamping circuit 25, the first current source I1 and the first switching circuit 21. It is used to transmit bias current in response to the enable signal and to disconnect the output of bias current in response to the disconnection of the enable signal.

[0052] Pull-down circuit 27 is connected to third switch circuit 26, first clamping circuit 25, first switch circuit 21 and drive circuit 30, and is used to pull down the gate of power transistor M01 to signal ground when the bias current is disconnected.

[0053] The shutdown function is enabled by the third switching circuit 26. When the third switching circuit 26 is open, the current bias of the bias output circuit 20 is disconnected, and the gate voltage of the drive transistor M02 is pulled down to signal ground, thus disabling the shutdown function. When the third switching circuit 26 is closed, the bias output circuit 20 receives the current bias and generates a corresponding bias voltage to control the drive transistor M02, enabling the shutdown function.

[0054] like Figure 5 As shown, the shutdown circuit of the high-side driver also includes a negative pressure clamping circuit 40.

[0055] The negative voltage clamping circuit 40 is connected to the power transistor M01, the drive circuit 30 and the bias output circuit 20. It is used to pull down the bias voltage in response to the source voltage of the power transistor M01 being less than the first preset voltage, and to clamp the gate voltage of the power transistor M01 to the second preset voltage.

[0056] The drive circuit 30 is also used to disconnect the output of the pull-down current based on the bias voltage after pull-down, so as to stop pulling down the gate-source voltage of the power transistor M01.

[0057] The second preset voltage is greater than the first preset voltage. It should be noted that the first preset voltage can be a negative voltage.

[0058] The negative voltage clamping circuit 40 achieves negative voltage detection, pull-down shutdown, and gate voltage clamping functions. When the source voltage of power transistor M01 is lower than the first preset voltage, the gate voltage of power transistor M01 is clamped to near the second preset voltage. This ensures that power transistor M01 will turn on when the source voltage drops, clamping the source voltage and preventing damage from excessive drain-source voltage. During the turn-off process, the negative voltage clamping circuit 40 remains operational to reduce the possibility of damage from excessive drain-source voltage in power transistor M01.

[0059] like Figure 6 As shown, the negative pressure clamping circuit 40 includes a translation circuit 41 and a shutdown circuit 42.

[0060] The translation circuit 41 is used to translate the voltage of the power supply ground to output a translated voltage; The termination circuit 42 is connected to the translation circuit 41, the power transistor M01 and the bias output circuit 20, and is used to pull down the bias voltage based on the translation voltage in response to the source voltage of the power transistor M01 being less than the first preset voltage.

[0061] The above technical solution enables the shutdown function of power transistor M01 to be stopped when the source voltage of power transistor M01 is less than the first preset voltage, thereby reducing the possibility of damage to power transistor M01 due to overvoltage of drain-source voltage.

[0062] like Figure 7 As shown, the negative pressure clamping circuit 40 also includes a source follower circuit 43.

[0063] The source follower circuit 43 is connected to the translation circuit 41, the termination circuit 42, the drive circuit 30 and the power transistor M01, and is used to follow the translation voltage so as to clamp the gate voltage of the power transistor M01 to a second preset voltage.

[0064] When the source voltage of power transistor M01 is less than the first preset voltage, the gate voltage of power transistor M01 is clamped to the second preset voltage, and power transistor M01 will be turned on, thus achieving clamping of the source voltage of power transistor M01.

[0065] like Figure 8 As shown, the negative pressure clamping circuit 40 also includes a second clamping circuit 44.

[0066] The second clamping circuit 44 is connected to the translation circuit 41 and the source follower circuit 43 and is used to clamp the translation voltage.

[0067] The above technical solution reduces the possibility of damage caused by excessive gate-source voltage of the field-effect transistor in the source follower circuit 43 and the gate-source voltage of the power transistor M01.

[0068] Figure 9 The diagram illustrates a partial example circuit structure of the high-side driver shutdown circuit provided in an embodiment of the present invention. For ease of explanation, only the parts relevant to the embodiment of the present invention are shown, and are described in detail below: The first reference circuit 15 includes a second current source I2 and a first resistor R1; the positive terminal of the second current source I2 is connected to the first power supply VAA, the negative terminal of the second current source I2 and the first end of the first resistor R1 are connected and together form the output terminal of the first reference circuit 15, which is connected to the first comparison circuit 11 to output a first threshold voltage Vth1; the second end of the first resistor R1 is connected to the signal ground.

[0069] The second reference circuit 16 includes a third current source I3 and a second resistor R2; the positive terminal of the third current source I3 is connected to the first power supply VAA, the negative terminal of the third current source I3 and the first end of the second resistor R2 are connected and together form the output terminal of the second reference circuit 16, which is connected to the second comparator circuit 12 to output a second threshold voltage Vth2; the second end of the second resistor R2 is connected to the signal ground.

[0070] The first comparison circuit 11 includes a first comparator U1; the inverting input terminal of the first comparator U1 constitutes the first input terminal of the first comparison circuit 11 and is connected to the first reference circuit 15 to receive the first threshold voltage Vth1; the non-inverting input terminal of the first comparator U1 constitutes the second input terminal of the first comparison circuit 11 and is connected to the gate of the power transistor MOSFET MOSFET to receive the gate voltage of the power transistor MOSFET MOSFET; the output terminal of the first comparator U1 constitutes the output terminal of the first comparison circuit 11 and is connected to the first logic circuit 13 and the second logic circuit 14 to output a first comparison signal.

[0071] The second comparator circuit 12 includes a second comparator U2; the inverting input terminal of the second comparator U2 constitutes the first input terminal of the second comparator circuit 12 and is connected to the second reference circuit 16 to receive the second threshold voltage Vth2; the non-inverting input terminal of the second comparator U2 constitutes the second input terminal of the second comparator circuit 12 and is connected to the gate of the power transistor MOSFET MOSFET 1 to receive the gate voltage of the power transistor MOSFET MOSFET 1; the output terminal of the second comparator U2 constitutes the output terminal of the second comparator circuit 12 and is connected to the first logic circuit 13 and the second logic circuit 14 to output the second comparison signal.

[0072] The first logic circuit 13 includes an OR gate U3; the first input terminal of the OR gate U3 constitutes the first input terminal of the first logic circuit 13 and is connected to the first comparison circuit 11 to receive a first comparison signal; the second input terminal of the OR gate U3 constitutes the second input terminal of the first logic circuit 13 and is connected to the second comparison circuit 12 to receive a second comparison signal; the output terminal of the OR gate U3 constitutes the output terminal of the first logic circuit 13 and is connected to the first switching circuit 21 to output a first control signal.

[0073] The second logic circuit 14 includes an inverter U4 and an AND gate U5. The input terminal of the inverter U4 forms the first input terminal of the second logic circuit 14 and is connected to the first comparator circuit 11 to receive a first comparison signal. The output terminal of the inverter U4 is connected to the first input terminal of the AND gate U5. The second input terminal of the AND gate U5 forms the second input terminal of the second logic circuit 14 and is connected to the second comparator circuit 12 to receive a second comparison signal. The output terminal of the AND gate U5 forms the output terminal of the second logic circuit 14 and is connected to the second switch circuit 22 to output a second control signal.

[0074] The first switching circuit 21 includes a first switch K1; the first end of the first switch K1 is connected to the gate of the third switching circuit 26 and the driving transistor MOSFET 02, and the second end of the first switch K1 is connected to the first equivalent resistance component 23 and the second switching circuit 22; the control end of the first switch K1 constitutes the control end of the first switching circuit 21 and is connected to the first logic circuit 13 to receive the first control signal.

[0075] The second switching circuit 22 includes a second switch K2; the first end of the second switch K2 is connected to the first equivalent resistance component 23 and the first switching circuit 21; the second end of the second switch K2 is connected to the second equivalent resistance component 24; the control end of the second switch K2 constitutes the control end of the second switching circuit 22, and is connected to the second logic circuit 14 to receive the second control signal.

[0076] The first equivalent resistance component 23 includes a first field-effect transistor Q1; the gate of the first field-effect transistor Q1 is connected to the gate of the third switching circuit 26 and the driving transistor M02, the drain of the first field-effect transistor Q1 is connected to the first switching circuit 21 and the second switching circuit 22, and the source of the first field-effect transistor Q1 is connected to the signal ground.

[0077] The second equivalent resistance assembly 24 includes a plurality of second field-effect transistors Q2 and a plurality of third switches K3; the gate of each second field-effect transistor Q2 is connected to the gate of the third switch circuit 26 and the drive transistor MO2, the drain of each second field-effect transistor Q2 is connected to the second terminal of the third switch K3 in a one-to-one correspondence, and the source of each second field-effect transistor Q2 is connected to signal ground; the first terminal of each third switch K3 is connected to the second switch circuit 22; the control terminal of each third switch K3 constitutes the adjustment terminal of the second equivalent resistance assembly 24 to receive the adjustment signal.

[0078] The first clamping circuit 25 includes a first Zener diode Z1; the positive terminal of the first Zener diode Z1 is connected to signal ground, and the negative terminal of the first Zener diode Z1 is connected to the gate of the first switching circuit 21 and the drive transistor MOSFET MO2.

[0079] The third switching circuit 26 includes a third switch K3; the pull-down circuit 27 includes a third resistor R3.

[0080] The level shifting circuit includes a first diode D1; the positive terminal of the first diode D1 is connected to the power supply ground, and the negative terminal of the first diode D1 forms the output terminal of the level shifting circuit, which is connected to the turn-off circuit 42 to output a shifted voltage.

[0081] The shutdown circuit 42 includes a third field-effect transistor Q3, a second Zener diode Z2, a fourth resistor R4, and a fifth resistor R5. The drain of the third field-effect transistor Q3 is connected to the bias output circuit 20 and the drive circuit 30. The source of the third field-effect transistor Q3, the positive terminal of the second Zener diode Z2, and the second terminal of the fifth resistor R5 are all connected to the signal ground. The negative terminal of the second Zener diode Z2 is connected to the gate of the third field-effect transistor Q3, the first terminal of the fifth resistor R5, and the second terminal of the fourth resistor R4. The first terminal of the fourth resistor R4 constitutes the input terminal of the shutdown circuit 42 and is connected to the translation circuit 41 to receive the translation voltage.

[0082] The source follower circuit 43 includes a fourth field-effect transistor Q4; the drain of the fourth field-effect transistor Q4 is connected to the first power supply VAA, the gate of the fourth field-effect transistor Q4 constitutes the input terminal of the source follower circuit 43, and is connected to the translation circuit 41 and the turn-off circuit 42 to receive the translation voltage; the gate of the fourth field-effect transistor Q4 constitutes the output terminal of the source follower circuit 43, and is connected to the gate of the power transistor M01, the driving circuit 30 and the detection circuit 10 to output the translation voltage after following.

[0083] The second clamping circuit 44 includes a third Zener diode Z3 and a fourth Zener diode Z4; the negative terminal of the third Zener diode Z3 is connected to the source follower circuit 43, the turn-off circuit 42, and the shift circuit 41, the positive terminal of the third Zener diode Z3 is connected to the negative terminal of the fourth Zener diode Z4, and the positive terminal of the fourth Zener diode Z4 is connected to the signal ground.

[0084] The negative pressure clamping circuit 40 also includes a seventh resistor R7; the first end of the seventh resistor R7 is connected to the second clamping circuit 44, the source follower circuit 43, the turn-off circuit 42, and the translation circuit 41, and the second end of the seventh resistor R7 is connected to the signal ground.

[0085] The negative pressure clamping circuit 40 also includes a sixth resistor R6; the sixth resistor R6 is connected between the translation circuit 41 and the source follower circuit 43 and serves as a current limiter.

[0086] The driving circuit 30 includes a driving transistor M02, which can be a field-effect transistor. The drain of the driving transistor M02 forms the output terminal of the driving circuit 30 and is connected to the gate of the power transistor M01 to output a pull-down current. The gate of the driving transistor M02 forms the input terminal of the driving circuit 30 and is connected to the bias output circuit 20 to apply a bias voltage. The source of the driving transistor M02 is connected to the signal ground.

[0087] The drain of power transistor M01 is connected to the supply voltage VCC, the source of power transistor M01 is connected to signal ground, and the gate of power transistor M01 is used to receive pull-down current and output the gate voltage of power transistor M01. The following is based on the working principle. Figure 9 Further explanation is provided below: The current output from the second current source I2 is injected into the first resistor R1 to generate the first threshold voltage Vth1. The current output from the third current source I3 is injected into the second resistor R2 to generate the second threshold voltage Vth2. The first threshold voltage Vth1 is greater than the second threshold voltage Vth2. It can be understood that by selecting the second current source I2 and the third current source I3, the first threshold voltage Vth1 and the second threshold voltage Vth2 can be configured to adapt to different turn-off conditions.

[0088] The first comparator U1 compares the gate voltage of the power transistor M01 with the first threshold voltage Vth1 to output a first comparison signal, and the second comparator U2 compares the gate voltage of the power transistor M01 with the second threshold voltage Vth2 to output a second comparison signal.

[0089] It should be noted that when the gate voltage of power transistor M01 is greater than or equal to the first threshold voltage Vth1, the first comparator U1 outputs a high-level first comparison signal; when the gate voltage of power transistor M01 is less than the first threshold voltage Vth1, the first comparator U1 outputs a low-level first comparison signal. Similarly, when the gate voltage of power transistor M01 is greater than or equal to the second threshold voltage Vth2, the second comparator U2 outputs a high-level first comparison signal; when the gate voltage of power transistor M01 is less than the second threshold voltage Vth2, the first comparator U1 outputs a low-level second comparison signal. That is, when the gate voltage of power transistor M01 is greater than or equal to the first threshold voltage Vth1, the OR gate U3 performs an OR operation on the high-level first comparison signal and the high-level second comparison signal to output a high-level first control signal; the AND gate U5 performs an AND operation on the inverted first comparison signal (low level) and the high-level second comparison signal to output a low-level second control signal. At this time, the first switch K1 is turned on and the second switch K2 is turned off. The bias current I1 flows through the first field-effect transistor Q1, which will generate a higher first bias voltage Vgate1. That is, the gate of the driving transistor M02 is pulled high, and a larger first pull-down circuit 27 is generated so that the gate voltage of the power transistor M01 is pulled down quickly.

[0090] When the gate voltage of power transistor M01 is less than the first threshold voltage Vth1 and greater than the second threshold voltage Vth2, OR gate U3 performs an OR operation on the low-level first comparison signal and the high-level second comparison signal to output a high-level first control signal; AND gate U5 performs an AND operation on the inverted first comparison signal (high level) and the high-level second comparison signal to output a high-level second control signal. At this time, both the first switch K1 and the second switch K2 are turned on, and the bias current I1 flows through the first field-effect transistor Q1 and the second field-effect transistor Q2, generating a lower second bias voltage Vgate2. Therefore, the driving transistor M02 pulls down the gate voltage of power transistor M01 with a small current (second pull-down circuit 27). By configuring the MOS array (each second field-effect transistor Q2), the magnitude of the pull-down current output by the driving transistor M02 can be controlled, thereby controlling the turn-off rate of power transistor M01. It can be understood that the more parallel second field-effect transistors Q2 are connected in the array, the slower the pull-down rate of power transistor M01.

[0091] When the gate voltage of power transistor M01 is less than the second threshold voltage Vth2, OR gate U3 performs an OR operation on the low-level first comparison signal and the low-level second comparison signal to output a low-level first control signal; AND gate U5 performs an AND operation on the inverted first comparison signal (high level) and the low-level second comparison signal to output a low-level second control signal. At this time, the first switch K1 and the second switch K2 are open, the gate of driving transistor M02 is pulled high to the clamping voltage (first bias voltage Vgate1) of the first Zener diode Z1, driving transistor M02 is in a fully conducting state, and the first pull-down circuit 27 is output to force the gate of power transistor M01 to be pulled down to signal ground. At the same time, the turn-off process of external power transistor M01 is basically completed. It is worth emphasizing that the bias current I1 is only used to maintain the conducting state of driving transistor M02, thereby reducing signal ground leakage current and static power consumption.

[0092] When the signal ground voltage is lower than the first preset voltage, such as below -1.4V, where 1.4V is the sum of the forward voltage drop of the first diode D1 and the threshold voltage at which the third MOSFET Q3 turns on, the first diode D1 and the third MOSFET Q3 conduct. At this time, the gate-source voltage of the driver transistor M02 is pulled low, turning off its pull-down function. Simultaneously, the fourth MOSFET Q4, acting as a source follower, has its gate voltage clamped to around -0.7V, and the gate voltage of the power transistor M01 (the source voltage of the fourth MOSFET Q4) is clamped to around -1.4V (the second preset voltage). This way, when the signal ground voltage drops, the power transistor M01 will turn on, clamping the signal ground and preventing damage from excessive drain-source voltage. When the signal ground voltage is higher than the power supply voltage, the gates of the third MOSFET Q3 and the fourth MOSFET Q4 are pulled down to the signal ground by the fifth resistor R5 and the seventh resistor R7, respectively, and are in the off state, without affecting normal turn-off operation. The second Zener diodes Z2 to Z4 are used for clamping to prevent excessive gate-source voltage of the third MOSFET Q3 and the power transistor M01 from being damaged. During the turn-off process, the negative voltage clamping circuit 40 is always working to reduce the possibility of damage from overvoltage of the drain-source voltage of the power transistor M01.

[0093] This invention also provides a chip that includes the shutdown circuit of the high-side driver described above.

[0094] This invention also provides an electronic device, which includes a power transistor and the shutdown circuit of the high-side driver described above.

[0095] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0096] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A turn-off circuit for a high-side driver, characterized in that, Connected to the power transistor, including: A detection circuit, connected to the power transistor, is used to output a first type of control signal in response to the gate-source voltage of the power transistor being greater than or equal to a first threshold voltage, and to output a second type of control signal in response to the gate-source voltage of the power transistor being less than the first threshold voltage but greater than or equal to a second threshold voltage, and to output a third type of control signal in response to the gate-source voltage of the power transistor being less than the second threshold voltage. A bias output circuit, connected to the detection circuit, is used to output a first bias voltage in response to a first type of control signal, output a second bias voltage in response to a second type of control signal, and output a third bias voltage in response to a third type of control signal. A driving circuit, connected to the detection circuit, the bias output circuit, and the power transistor, is used to output a pull-down current according to each of the bias voltages to pull down the gate-source voltage of the power transistor. The third bias voltage, the first bias voltage, and the second bias voltage decrease sequentially, and the bias voltage is positively correlated with the pull-down current.

2. The turn-off circuit of the high-side driver as described in claim 1, characterized in that, The control signal includes a first control signal and a second control signal; the detection circuit includes: A first comparison circuit, connected to the power transistor, is used to compare the gate-source voltage of the power transistor with the first threshold voltage to output a first comparison signal; The second comparison circuit, connected to the power transistor, is used to compare the gate-source voltage of the power transistor with the second threshold voltage to output a second comparison signal; A first logic circuit, connected to the bias output circuit, the first comparison circuit, and the second comparison circuit, is used to perform an OR operation on the first comparison signal and the second comparison signal to output the first control signal. The second logic circuit, connected to the bias output circuit, the first comparison circuit, and the second comparison circuit, is used to invert the first comparison signal and perform an AND operation on the inverted first comparison signal and the second comparison signal to output the second control signal.

3. The turn-off circuit of the high-side driver as described in claim 2, characterized in that, The driving circuit includes a driving transistor; the bias output circuit includes a first switching circuit, a second switching circuit, a first equivalent resistor assembly, a second equivalent resistor assembly, and a first clamping circuit. The first switching circuit is connected to the first logic circuit, and uses the first control signal in response to the first level to connect the first equivalent resistance component between the gate and the source of the driving transistor. The second switching circuit, connected to the second logic circuit, uses the second control signal in response to the first level to connect the second equivalent resistor component between the gate and the source of the driving transistor; The first clamping circuit is connected to the first equivalent resistor assembly, the second equivalent resistor assembly and the driving transistor, and is used to clamp the gate-source voltage of the driving transistor to the third bias voltage. Wherein, the first equivalent resistance component is used to output the first bias voltage based on the input bias current; the first equivalent resistance component and the second equivalent resistance component connected in parallel are used to output the second bias voltage based on the input bias current.

4. The turn-off circuit of the high-side driver as described in claim 3, characterized in that, The source of the power transistor is connected to signal ground, and the turn-off circuit of the high-side driver further includes: A first current source is used to provide the bias current; The third switching circuit is connected to the driving circuit, the first clamping circuit, the first current source and the first switching circuit, and is used to transmit the bias current in response to the enable signal, and to disconnect the output of the bias current in response to the disconnection of the enable signal. A pull-down circuit, connected to the third switching circuit, the first clamping circuit, the first switching circuit, and the drive circuit, is used to pull down the gate of the power transistor to signal ground when the bias current is disconnected.

5. The turn-off circuit of the high-side driver as described in claim 1, characterized in that, Also includes: A negative voltage clamping circuit, connected to the power transistor, the driving circuit, and the bias output circuit, is used to pull down the bias voltage in response to the source voltage of the power transistor being less than a first preset voltage, and to clamp the gate voltage of the power transistor to a second preset voltage. The driving circuit is also used to disconnect the output of the pull-down current based on the bias voltage after pull-down, so as to stop pulling down the gate-source voltage of the power transistor; Wherein, the second preset voltage is greater than the first preset voltage.

6. The turn-off circuit of the high-side driver as described in claim 5, characterized in that, The negative pressure clamping circuit includes: A translation circuit is used to shift the voltage from the power supply to ground to output a shifted voltage. The termination circuit, connected to the translation circuit, the power transistor, and the bias output circuit, is used to pull down the bias voltage based on the translation voltage in response to the source voltage of the power transistor being less than a first preset voltage.

7. The turn-off circuit of the high-side driver as described in claim 6, characterized in that, The negative pressure clamping circuit also includes: A source follower circuit, connected to the translation circuit, the termination circuit, the drive circuit, and the power transistor, is used to follow the translation voltage to clamp the gate voltage of the power transistor to a second preset voltage.

8. The turn-off circuit of the high-side driver as described in claim 7, characterized in that, The negative pressure clamping circuit also includes: The second clamping circuit, connected to the translation circuit and the source follower circuit, is used to clamp the translation voltage.

9. A chip, characterized in that, The chip includes a shutdown circuit for the high-side driver as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, The electronic device includes a power transistor and a shutdown circuit for a high-side driver as described in any one of claims 1 to 8.

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