A DPLL phase meter lock-loss frequency prediction system and method

Abstract

The application relates to the technical field of digital phase-locked loops, and discloses a DPLL phase meter lock-loss frequency prediction system, which is characterized in that a frequency prediction module is additionally arranged in the DPLL phase meter, historical frequency data output by the DPLL module is analyzed through a polynomial fitting, a frequency difference value at adjacent time points is calculated as an accumulation factor, and a frequency prediction value at the next time point is obtained through updating; in combination with lock-loss detection and reset control, relocking is performed with the prediction value as an initial frequency when lock-loss occurs, and the capture is reset when the accumulated lock-loss reaches a preset threshold. The method adopts polynomial fitting and fixed-point data accumulation operation, realizes fast prediction through the accumulation of the difference value of historical frequency data, solves the problem of long secondary locking time in the phase-locked technology, effectively deals with lock-loss caused by noise disturbance, and significantly improves the measurement efficiency and stability of the phase meter.

Description

Technical Field

[0001] This invention relates to the field of digital phase-locked loop (PLL) technology, specifically to a DPLL phase meter loss-of-lock frequency prediction system and method. Background Technology

[0002] Digital phase-locked loop (DPLL) phase meters, as a high-precision signal measurement device, have the core function of synchronizing the phase of the input signal with the local oscillation signal and accurately measuring the phase difference and frequency between the two. They occupy a key position in many fields such as electronic measurement, communication systems, power electronics, and aerospace, and are widely used in core scenarios such as signal synchronization calibration, dynamic frequency tracking, and high-precision phase measurement. They are an important foundation for ensuring the stable operation of related systems and the reliability of measurement data.

[0003] Existing DPLL phase meters mainly consist of core units such as an error detection module, a loop filter, a digitally controlled oscillator (NCO), and a phase comparator. Their working logic is as follows: the phase comparator acquires the phase error between the input signal and the NCO output signal; the error detection module converts this error signal into a processable error signal; the loop filter smooths the error signal before feeding it back to the NCO to adjust its output frequency and phase, ultimately achieving stable phase-locked tracking between the input signal and the local signal. This original technology can meet basic measurement requirements under ideal conditions with stable signal environments and no sudden disturbances. However, it lacks an effective mechanism to address the loss-of-lock problem under complex conditions, and initially relies on external frequency acquisition methods to assign values ​​to the NCO before initiating the phase-locked tracking process.

[0004] To address the shortcomings of the original technology, various improvement schemes have been proposed in related fields. Among them, the most representative is the traditional relocking method based on FFT + peak lookup + difference algorithm. This scheme achieves initial frequency acquisition and relocking after loss of lock through the acquisition module. Its core logic is as follows: at the initial moment, the acquisition module performs FFT transformation on the input signal, locates the spectral peak corresponding to the main frequency of the signal through the peak lookup algorithm, and then optimizes the frequency calculation accuracy through the difference algorithm. The obtained frequency value is assigned to the NCO, and the frequency and phase tracking of the phase-locked loop are started. When the phase-locked loop suddenly loses lock due to external environmental disturbances, the system resets the acquisition module, re-executes the complete process of FFT transformation → peak lookup → difference calculation, and re-acquires the frequency of the input signal and assigns it to the NCO, so that the phase-locked loop restarts.

[0005] In addition, related technologies include two auxiliary solutions: one is to reduce the probability of loss of lock by expanding the acquisition bandwidth of the phase-locked loop, attempting to adapt to signal frequency fluctuations by widening the adjustment range of the NCO; the other is to achieve re-acquisition after loss of lock by using fixed step size scanning or segmented search.

[0006] However, these solutions all have significant drawbacks. The core problem with existing FFT capture solutions is that the relocking process takes too long. The FFT transformation and peak finding process consume a lot of computing resources and time. Especially when the input signal frequency range is wide, the number of FFT points needs to be increased to ensure capture accuracy, which further prolongs the relocking cycle and cannot meet the fast response requirements of real-time measurement scenarios.

[0007] Meanwhile, the frequency resolution of the FFT algorithm is limited by the sampling rate and data length, the optimization effect of the difference algorithm is limited, and the recaptured frequency accuracy is insufficient, which may lead to a large deviation in the initial value of NCO, causing secondary loss of lock or lock-in oscillation of the phase-locked loop; the scheme of expanding the acquisition bandwidth will reduce the system noise suppression capability and sacrifice the phase measurement accuracy; the fixed step size scanning scheme also has the problems of low efficiency and susceptibility to interference.

[0008] There are still prominent technical problems in the field of DPLL phase meters:

[0009] First, the efficiency of relocking after loss of lock is low. The contradiction between the computation time and accuracy of traditional FFT capture schemes cannot be reconciled, resulting in the relocking speed being far from meeting the requirements of dynamic working conditions.

[0010] Second, the loss of lock judgment lacks a precise triggering mechanism. Existing systems mostly rely on simple error signal thresholds or timeout judgments, which can easily trigger the re-acquisition process due to normal signal fluctuations, or cause delays in the acquisition timing due to the lag in the loss of lock judgment.

[0011] Third, the frequency accuracy of recapture is insufficient. The limitations of the existing algorithm lead to a large deviation in the initial value of NCO, which affects the stability of the phase-locked loop relocking. This sacrifices measurement accuracy or system stability in exchange for loss-of-lock fault tolerance.

[0012] In summary, the current DPLL phase meter field still suffers from problems such as long secondary locking time and low accuracy when the FFT + peak search re-acquisition method is used after the DPLL phase meter loses lock due to noise disturbance, making it difficult to meet the real-time and high-precision requirements of the phase measurement field. Summary of the Invention

[0013] The purpose of this invention is to provide a method for automatic relocking after a DPLL phase meter loses lock, in order to solve the technical problems in the current DPLL phase meter field, such as low relocking efficiency after a loss of lock, lack of accurate triggering mechanism for loss of lock judgment, insufficient accuracy of reacquisition frequency, and some solutions sacrificing measurement accuracy or system stability for loss of lock fault tolerance.

[0014] To solve the above-mentioned technical problems, the present invention specifically provides the following technical solution:

[0015] A method for automatic relocking of a DPLL phase meter after lock-up includes a DPLL module, a frequency prediction module, a lock-up detection module, and a reset control module.

[0016] The DPLL module is used to acquire and output the frequency data of the current signal in real time. ;

[0017] The frequency prediction module is communicatively connected to the DPLL module and is used to receive frequency data output by the DPLL module. Calculate the frequency difference between adjacent time points. And based on current frequency data Frequency difference Update predicted frequency values ;

[0018] The unlock detection module is communicatively connected to the DPLL module and is used to detect the locking status of the DPLL module in real time and output an unlock detection signal.

[0019] The reset control module is communicatively connected to the unlock detection module, the frequency prediction module, and the DPLL module, respectively. It receives and counts unlock detection signals. When the unlock count does not reach a preset threshold, it controls the DPLL module to predict the frequency value. The initial frequency is used to perform a relocking operation; when the unlock count reaches a preset threshold, the DPLL module is controlled to perform a reset initial frequency capture operation.

[0020] As a preferred embodiment of the present invention, the preset threshold is 3 times, the reset control module has a built-in unlock counter, the unlock counter accumulates when it receives the unlock detection signal, and the count is cleared when the DPLL module successfully relocks.

[0021] As a preferred embodiment of the present invention, the frequency prediction module uses a fixed-point data accumulation method to perform calculations, which is compatible with FPGA hardware architecture.

[0022] In a preferred embodiment of the present invention, the operation cycle of the frequency prediction module does not exceed [a certain value]. The predicted frequency value The accuracy is no less than .

[0023] This embodiment provides a method for predicting the unlock frequency of a DPLL phase meter, used to implement the aforementioned DPLL phase meter unlock frequency prediction system, including the following steps:

[0024] Step 100: After the system is powered on, the DPLL module performs an initial frequency acquisition operation until signal lock is achieved, enters normal measurement mode, and continuously outputs frequency data. ;

[0025] Step 200: The frequency prediction module receives the frequency data output by the DPLL module in real time. Calculate the frequency difference between adjacent time points. and update the predicted frequency values. Repeat this step to continuously update the predicted frequency values. ;

[0026] Step 300: The unlock detection module monitors the locking status of the DPLL module in real time. If it detects that the module has not lost its lock, it returns to step 200.

[0027] Step 400: If a loss of lock is detected, the loss of lock handling process is triggered. The reset control module counts the loss of lock status and determines whether the loss of lock count has reached a preset threshold.

[0028] If the preset threshold is not reached, the DPLL module is controlled to use the currently updated predicted frequency value 'a' as the initial frequency and perform a relocking operation; if the relocking is successful, the unlock count is cleared to zero and the process returns to step 200; if the relocking fails, the process returns to this step and the count restarts.

[0029] If the preset threshold is reached, the DPLL module is reset and the initial frequency acquisition operation is re-executed. If the acquisition is successful, the process returns to step 200. If the acquisition continues to fail, it is determined that there is no signal at the signal terminal, and the initial frequency acquisition state is maintained until a signal is detected.

[0030] As a preferred embodiment of the present invention, the preset threshold in step 400 is 3 times. When the count of lost lock reaches 3 times and the lock is still not re-locked, the initial frequency capture operation is reset.

[0031] In a preferred embodiment of the present invention, a first-order polynomial fitting model is used in step 200 to update the predicted frequency values. The expression of the first-order polynomial fitting model is as follows: It is constructed based on the linear characteristics of short-term frequency changes of the signal.

[0032] As a preferred embodiment of the present invention, the triggering condition for the loss of lock detection in step 300 is that the phase error signal output by the DPLL module exceeds a preset threshold or the frequency data fluctuation amplitude exceeds a set range.

[0033] Compared with the prior art, the present invention has the following advantages:

[0034] This invention achieves rapid and accurate prediction of the unlock frequency through a single polynomial fitting and fixed-point data accumulation. It is compatible with FPGA deployment and effectively solves the DPLL phase meter unlock problem caused by noise disturbance. Compared with traditional methods, it significantly shortens the secondary locking time, improves frequency accuracy, enhances anti-interference capability and working stability, and balances real-time performance and engineering practicality. Attached Figure Description

[0035] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the DPLL phase meter loss-of-lock frequency prediction system according to an embodiment of the present invention;

[0037] Figure 2 This is a flowchart of the DPLL phase meter loss-lock frequency prediction method according to an embodiment of the present invention. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] like Figure 1 As shown, this embodiment provides a DPLL phase meter loss-of-lock frequency prediction system, including a DPLL module, a frequency prediction module, a loss-of-lock detection module, and a reset control module.

[0040] The DPLL module is used to acquire and output the frequency data of the current signal in real time. ;

[0041] The frequency prediction module is communicatively connected to the DPLL module and is used to receive frequency data output by the DPLL module. Calculate the frequency difference between adjacent time points. And based on current frequency data Frequency difference Update predicted frequency values ;

[0042] The unlock detection module is communicatively connected to the DPLL module and is used to detect the locking status of the DPLL module in real time and output an unlock detection signal.

[0043] The reset control module is communicatively connected to the unlock detection module, the frequency prediction module, and the DPLL module, respectively. It receives and counts unlock detection signals. When the unlock count does not reach a preset threshold, it controls the DPLL module to predict the frequency value. The initial frequency is used to perform a relocking operation; when the unlock count reaches a preset threshold, the DPLL module is controlled to perform a reset initial frequency capture operation.

[0044] The preset threshold is 3 times. The reset control module has a built-in unlock counter. The unlock counter increments when it receives an unlock detection signal and resets to zero when the DPLL module successfully relocks.

[0045] The frequency prediction module uses a fixed-point data accumulation method for calculation, which is compatible with FPGA hardware architecture.

[0046] The operation cycle of the frequency prediction module does not exceed The predicted frequency value The accuracy is no less than .

[0047] like Figure 2 As shown, this embodiment further provides a DPLL phase meter out-of-lock frequency prediction method for implementing the DPLL phase meter out-of-lock frequency prediction system, including the following steps:

[0048] Step 100: After the system is powered on, the DPLL module performs an initial frequency acquisition operation until signal lock is achieved, enters normal measurement mode, and continuously outputs frequency data. ;

[0049] Step 200: The frequency prediction module receives the frequency data output by the DPLL module in real time. Calculate the frequency difference between adjacent time points. and update the predicted frequency values. Repeat this step to continuously update the predicted frequency values. ;

[0050] Step 300: The unlock detection module monitors the locking status of the DPLL module in real time. If it detects that the module has not lost its lock, it returns to step 200.

[0051] Step 400: If a loss of lock is detected, the loss of lock handling process is triggered. The reset control module counts the loss of lock status and determines whether the loss of lock count has reached a preset threshold.

[0052] If the preset threshold is not reached, control the DPLL module to use the currently updated prediction frequency value. As the initial frequency, perform a relocking operation; if relocking is successful, the unlock count is reset to zero, and return to step 200; if relocking fails, return to this step and start counting again.

[0053] If the preset threshold is reached, the DPLL module is reset and the initial frequency acquisition operation is re-executed. If the acquisition is successful, the process returns to step 200. If the acquisition continues to fail, it is determined that there is no signal at the signal terminal, and the initial frequency acquisition state is maintained until a signal is detected.

[0054] The preset threshold mentioned in step 400 is 3 times. When the count of lost lock reaches 3 times and the lock is still not re-locked, the initial frequency capture operation is reset.

[0055] In step 200, a first-order polynomial fitting model is used to update the predicted frequency values. The expression of the first-order polynomial fitting model is as follows: It is constructed based on the linear characteristics of short-term frequency changes of the signal.

[0056] In step 300, the trigger condition for loss of lock detection is that the phase error signal output by the DPLL module exceeds a preset threshold or the frequency data fluctuation amplitude exceeds a set range.

[0057] This method is particularly suitable for FPGA deployment and can use fixed-point data accumulation for prediction. Because it predicts based on historical signal frequency data, its computational accuracy and speed are significantly improved compared to traditional methods. Current methods using FFT combined with peak lookup have computation times in milliseconds (ms) and accuracy in the hundreds of hertz (Hz). This method is especially suitable for phase lock-up issues caused by noise disturbances during phase meter measurements, greatly improving the time and accuracy of phase meter re-locking.

[0058] This method reduces computational complexity compared to traditional methods, and can reduce the secondary locking time to 100. accuracy the following.

[0059] Furthermore, in the DPLL phase meter automatic relocking method of this embodiment, when the digital phase-locked loop loses lock, the initial NCO frequency of the digital phase-locked loop is directly replaced with the estimated value of the digital phase-locked loop frequency at the next moment, so that the digital phase-locked loop restarts locking.

[0060] In this implementation, a relocking module is added to the DPLL algorithm in the actual time limit. This module sets a threshold and detects whether the phase meter is in a lost-lock state by frequency readout.

[0061] The relocking module uses frequency data from before the lock was lost and a linear fitting algorithm to predict the frequency value at the next moment. This predicted frequency value replaces the calculated value from the traditional restart capture algorithm module. This method surpasses the traditional method in both speed and accuracy of frequency prediction.

[0062] Meanwhile, to verify the accuracy of the relocking module's predicted values, a cross-comparison with the capture module can be performed. The linear fitting algorithm model of the relocking module is updated online in real time.

[0063] Figure 1 The diagram shows the overall phase meter system after the addition of the frequency prediction module. It mainly consists of an ADC module, an acquisition module, a DPLL module, and a frequency prediction module, all of which are implemented inside the FPGA.

[0064] Similar to classic digital phase-locked loops, the digital phase-locked loop in this embodiment is a narrowband loop, consisting of a numerically controlled oscillator, a phase increment register (PIR), a multiplier, a low-pass filter (LPF), and a proportional-integral (PI) controller.

[0065] The difference lies in the low-pass filter cutoff frequency being set to 32kHz and the sampling rate to 80MHz, a setting that allows for higher accuracy under multi-frequency coupling conditions. Frequency and phase fluctuations (referred to as frequency readout and phase accumulator readout, respectively) are obtained by reading the values ​​of the phase increment register and phase accumulator (PA). The feedback frequency is 1MHz, and the output rate is 20Hz. A cascaded integrator comb (CIC) filter is used to perform anti-aliasing processing for downsampling, and the final output frequency fluctuation information is used for error signal acquisition and analysis.

[0066] The above embodiments are merely exemplary embodiments of this application and are not intended to limit this application. The scope of protection of this application is defined by the claims. Those skilled in the art can make various modifications or equivalent substitutions to this application within its substance and scope of protection, and such modifications or equivalent substitutions should also be considered to fall within the scope of protection of this application.

Claims

1. A DPLL phase meter unlock frequency prediction system, characterized in that, It includes a DPLL module, a frequency prediction module, a loss-of-lock detection module, and a reset control module; The DPLL module is used to acquire and output the frequency data of the current signal in real time. ; The frequency prediction module is communicatively connected to the DPLL module and is used to receive frequency data output by the DPLL module. Calculate the frequency difference between adjacent time points. And based on current frequency data Frequency difference Update predicted frequency values ; The unlock detection module is communicatively connected to the DPLL module and is used to detect the locking status of the DPLL module in real time and output an unlock detection signal. The reset control module is communicatively connected to the unlock detection module, the frequency prediction module, and the DPLL module, respectively. It receives and counts unlock detection signals. When the unlock count does not reach a preset threshold, it controls the DPLL module to predict the frequency value. The initial frequency is used to perform a relocking operation; when the unlock count reaches a preset threshold, the DPLL module is controlled to perform a reset initial frequency capture operation.

2. The DPLL phase meter unlock frequency prediction system according to claim 1, characterized in that, The preset threshold is 3 times. The reset control module has a built-in unlock counter. The unlock counter increments when it receives an unlock detection signal and resets to zero when the DPLL module successfully relocks.

3. The DPLL phase meter unlock frequency prediction system according to claim 1, characterized in that, The frequency prediction module uses a fixed-point data accumulation method for calculation, which is compatible with FPGA hardware architecture.

4. The DPLL phase meter unlock frequency prediction system according to claim 1, characterized in that, The operation cycle of the frequency prediction module does not exceed The predicted frequency value The accuracy is no less than .

5. A method for predicting the unlock frequency of a DPLL phase meter, used to implement the DPLL phase meter unlock frequency prediction system according to any one of claims 1-4, characterized in that, Includes the following steps: Step 100: After the system is powered on, the DPLL module performs an initial frequency acquisition operation until signal lock is achieved, enters normal measurement mode, and continuously outputs frequency data. ; Step 200: The frequency prediction module receives the frequency data output by the DPLL module in real time. Calculate the frequency difference between adjacent time points. and update the predicted frequency values. Repeat this step to continuously update the predicted frequency values. ; Step 300: The unlock detection module monitors the locking status of the DPLL module in real time. If it detects that the module has not lost its lock, it returns to step 200. Step 400: If a loss of lock is detected, the loss of lock handling process is triggered. The reset control module counts the loss of lock status and determines whether the loss of lock count has reached a preset threshold. If the preset threshold is not reached, control the DPLL module to use the currently updated prediction frequency value. As the initial frequency, perform a relocking operation; if the relocking is successful, the unlock count is reset to zero, and return to step 200. If relocking fails, return to this step and start counting again; If the preset threshold is reached, the DPLL module is reset and the initial frequency acquisition operation is re-executed. If the acquisition is successful, the process returns to step 200. If the acquisition continues to fail, it is determined that there is no signal at the signal terminal, and the initial frequency acquisition state is maintained until a signal is detected.

6. The method for predicting the unlock frequency of a DPLL phase meter according to claim 5, characterized in that, The preset threshold mentioned in step 400 is 3 times. When the count of lost lock reaches 3 times and the lock is still not re-locked, the initial frequency capture operation is reset.

7. The method for predicting the unlock frequency of a DPLL phase meter according to claim 5, characterized in that, In step 200, a first-order polynomial fitting model is used to update the predicted frequency values. The expression of the first-order polynomial fitting model is as follows: It is constructed based on the linear characteristics of short-term frequency changes of the signal.

8. The method for predicting the unlock frequency of a DPLL phase meter according to claim 5, characterized in that, In step 300, the trigger condition for loss of lock detection is that the phase error signal output by the DPLL module exceeds a preset threshold or the frequency data fluctuation amplitude exceeds a set range.

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