High-precision low-latency exponential increment successive approximation analog-to-digital converter

Abstract

The application belongs to the technical field of digital-analog hybrid integrated circuits, and relates to a high-precision low-latency exponential increment successive approximation analog-digital converter, which comprises an exponential delay integrator module, a multi-bit quantizer and a digital-analog converter module.The exponential delay integrator module is used for amplifying the residual voltage of the last round by using a proportional floating inverting amplifier, and is used for realizing exponential form integration and accumulation of the residual voltage by using a stacked capacitor module to control different stacked capacitors to work alternately in odd and even periods through ping-pong timing to delay and store the amplified residual voltage.The multi-bit quantizer is used for multi-bit quantization of the integrated signal to obtain a multi-bit digital signal.The digital-analog converter module is used for converting the multi-bit digital signal into an analog output signal to realize successive approximation logic.The exponential delay integrator module is realized by using a proportional floating inverting amplifier and a stacked capacitor module, which significantly reduces the circuit complexity and processing delay, and improves the robustness and energy efficiency of the system in high-precision application scenarios.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit technology, specifically relating to a high-precision, low-delay exponential incremental successive approximation analog-to-digital converter. Background Technology

[0002] In ultra-low frequency signal processing scenarios such as portable electronic devices and biomedical sensing, the system places more stringent demands on the noise suppression capability and energy efficiency of analog-to-digital converters (ADCs). Noise-shaping successive approximation register (SAPPRC) ADCs, combining the noise-shaping capability of Delta-Sigma modulators with the high energy efficiency of successive approximation ADCs, are gradually becoming the ideal choice for these applications. However, in existing technologies, achieving higher conversion resolution typically requires high-order loop filters or high oversampling rates, which not only introduces system stability risks but also increases circuit complexity and signal processing delay. Furthermore, while capacitor stacking and dynamic buffer techniques can be used to achieve a steeper noise transfer function, the open-loop amplifier gain is susceptible to process variations, voltage fluctuations, and temperature changes, potentially leading to performance degradation or requiring additional calibration circuitry to maintain accuracy. Summary of the Invention

[0003] To address the aforementioned problems in the existing technology, this invention provides a high-precision, low-delay exponential incremental successive approximation analog-to-digital converter. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a high-precision, low-delay exponential incremental successive approximation analog-to-digital converter, comprising: The exponential delay integrator module is used to amplify the residual voltage of the previous round by a preset factor during the residual voltage storage stage. Then, by controlling different stacked capacitors to work alternately in odd and even cycles through ping-pong timing, the amplified residual voltage is delayed and stored, thereby realizing the exponential integral accumulation of the residual voltage. The amplified residual voltage stored in the delay is used to be superimposed with the input signal of the current round during the quantization stage to obtain the integral signal of the current round. A multi-bit quantizer is used to perform multi-bit quantization on the integral signal of the current round during the quantization stage to obtain a multi-bit digital signal of the current round. The digital-to-analog converter module is used to convert the multi-bit digital signal of the current round into the analog output signal of the current round to realize successive approximation logic. The analog output signal of the current round is used to subtract the input signal of the current round to obtain the margin voltage for noise shaping in the next round.

[0004] In one embodiment of the present invention, the digital-to-analog converter module includes a successive approximation control logic module and a multi-bit CDAC array module; The input terminal of the successive approximation control logic module is connected to the output terminal of the multi-bit quantizer, and the output terminal of the successive approximation control logic module is connected to the lower plate of the multi-bit CDAC array module.

[0005] In one embodiment of the present invention, the exponential delay integrator module includes a stacked capacitor module and a proportional floating inverting amplifier module; The proportional floating inverting amplifier module is used to amplify the residual voltage of the previous round by a preset factor to obtain the amplified residual voltage. The stacked capacitor module is used to control different stacked capacitors to work alternately in odd and even cycles through ping-pong timing to delay and store the amplified margin voltage, and to receive a reset signal after a preset period to clear the charge stored on the stacked capacitors.

[0006] In one embodiment of the present invention, the stacked capacitor module includes: a first stacked capacitor and a second stacked capacitor; During odd-numbered periods, the second stacked capacitor interacts with multiple bits of C in the digital-to-analog converter module. DAC The array modules are stacked, and the amplified margin voltage is stored on the first stacked capacitor; During even-numbered periods, the first stacked capacitor interacts with multiple C bits in the digital-to-analog converter module. DAC The array modules are stacked, and the amplified margin voltage is stored on the second stacked capacitor.

[0007] In one embodiment of the present invention, the stacked capacitor module further includes: a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a sixth control switch, a seventh control switch, an eighth control switch, a ninth control switch, a tenth control switch, and an eleventh control switch; The first terminal of the first control switch is connected to the second terminal of the eleventh control switch and the first terminal of the seventh control switch; the first terminal of the third control switch is used to input the first feedback voltage; the second terminal of the first control switch is connected to the second terminal of the third control switch, the negative terminal of the first stacked capacitor, and the first terminal of the ninth control switch. The first terminal of the eleventh control switch is connected to the multi-position C DAC The upper electrode plate of the array module; The first terminal of the fifth control switch is used to input the first feedback voltage; the second terminal of the fifth control switch is connected to the second terminal of the seventh control switch, the negative terminal of the second stacked capacitor, and the first terminal of the tenth control switch. The first terminal of the second control switch is connected to the second terminal of the ninth control switch, the positive terminal of the first stacked capacitor, and the first terminal of the fourth control switch; the second terminal of the second control switch is connected to the second terminal of the eighth control switch, the input terminal of the proportional floating inverting amplifier module, and the input terminal of the multi-bit quantizer. The second terminal of the fourth control switch is used to input the second feedback voltage; The first terminal of the sixth control switch is connected to the positive terminal of the second stacked capacitor, the first terminal of the eighth control switch, and the second terminal of the tenth control switch; the second terminal of the sixth control switch is used to input the second feedback voltage.

[0008] In one embodiment of the present invention, the proportional floating inverting amplifier module includes: a driver-stage floating inverting amplifier and a load-stage floating inverting amplifier, wherein the device size ratio of the driver-stage floating inverting amplifier and the load-stage floating inverting amplifier is N:1; The driver-stage floating inverting amplifier includes: a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first capacitor, and a second capacitor; the load-stage floating inverting amplifier includes: a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a third capacitor, and a fourth capacitor. The gate of the first NMOS transistor is connected to the gate of the first PMOS transistor and receives a positive terminal integration signal. The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, the gate of the third NMOS transistor, the gate of the third PMOS transistor, the drain of the third NMOS transistor, and the drain of the third PMOS transistor and outputs a first feedback voltage. The gate of the second NMOS transistor is connected to the gate of the second PMOS transistor and receives a negative terminal integration signal. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, the gate of the fourth NMOS transistor, the drain of the fourth NMOS transistor, the gate of the fourth PMOS transistor, and the drain of the fourth PMOS transistor and outputs a second feedback voltage. The source of the first NMOS transistor is connected to the source of the second NMOS transistor, the lower plate of the first capacitor, and the upper plate of the second capacitor. The source of the third NMOS transistor is connected to the source of the fourth NMOS transistor, the lower plate of the third capacitor, and the upper plate of the fourth capacitor. The source of the first PMOS transistor is connected to the source of the second PMOS transistor, the upper plate of the first capacitor, and the lower plate of the second capacitor. The source of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the upper plate of the third capacitor, and the lower plate of the fourth capacitor.

[0009] In one embodiment of the present invention, the proportional floating inverting amplifier module further includes: a twelfth control switch, a thirteenth control switch, a fourteenth control switch, a fifteenth control switch, a sixteenth control switch, a seventeenth control switch, an eighteenth control switch, and a nineteenth control switch; The twelfth control switch is connected between the upper plate of the fourth capacitor and the source of the third NMOS transistor; the thirteenth control switch is connected between the lower plate of the fourth capacitor and the source of the third PMOS transistor; the fourteenth control switch is connected between the lower plate of the first capacitor and the source of the second NMOS transistor; and the fifteenth control switch is connected between the upper plate of the first capacitor and the source of the second PMOS transistor. The first terminal of the sixteenth control switch is connected to the power supply voltage, and the second terminal is connected between the lower plate of the third capacitor and the upper plate of the fourth capacitor; the first terminal of the seventeenth control switch is connected between the upper plate of the third capacitor and the lower plate of the fourth capacitor, and the second terminal is grounded; the first terminal of the eighteenth control switch is connected to the power supply voltage, and the second terminal is connected between the lower plate of the first capacitor and the upper plate of the second capacitor; the first terminal of the nineteenth control switch is connected between the upper plate of the first capacitor and the lower plate of the second capacitor, and the second terminal is grounded.

[0010] In one embodiment of the invention, the multi-bit quantizer includes a comparator.

[0011] In one embodiment of the present invention, the digital-to-analog converter module includes a successive approximation control logic module and a multi-bit C... DAC Array module; The input of the successive approximation control logic module is connected to the output of the multi-bit quantizer, and the output of the successive approximation control logic module is linked to the multi-bit C... DAC The input terminal of the array module; The multiple C DAC The array module includes several capacitors, several multi-directional switches, and a twentieth control switch; the first end of the twentieth control switch is used to receive the input signal, and the second end is connected to the upper plate of several capacitors; the lower plates of several capacitors are connected to the common terminal of several multi-directional switches one by one; the first selection terminal of each multi-directional switch is used to input a common-mode voltage, the second selection terminal is used to input a non-inverting reference voltage, and the third selection terminal is used to input an inverting reference voltage.

[0012] In one embodiment of the present invention, the relationship between the analog output signal and the input signal is as follows: Q, in which For the analog output signal of the i-th round, Let i be the input signal for the i-th round. Q is the noise transfer function. These are noise shaping parameters. Q represents the quantization error resulting from quantization by a multi-bit quantizer. As a delay factor, This is the preset multiplier.

[0013] In one embodiment of the present invention, it further includes: a low-delay digital decimation filter, used to perform digital filtering on the multi-bit digital signal of the current round to obtain a Nyquist rate output signal, and to receive a reset signal to periodically clear the signal on the low-delay digital decimation filter.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The analog-to-digital converter of the present invention has a working cycle divided into sampling, quantization and margin voltage storage stages. In the margin voltage storage stage, the exponential delay integrator module amplifies the margin voltage of the previous round to achieve noise transmission through an exponential incremental noise shaping mechanism according to a preset multiple. The margin voltage is delayed and stored by controlling different stacked capacitors to work alternately in odd and even cycles through ping-pong timing control. The exponential incremental noise shaping mechanism is highly sensitive to the margin voltage, which accelerates the accumulation of margin voltage and significantly enhances the suppression of quantization noise in a short time. The analog-to-digital converter significantly reduces circuit complexity and processing delay while improving the robustness and energy efficiency of the system in high-precision application scenarios, effectively overcoming the dependence of traditional solutions on high-order loop filters or high-rate oversampling. 2. In the analog-to-digital converter of the present invention, the proportional floating inverting amplifier module includes a driver-stage floating inverting amplifier and a load-stage floating inverting amplifier, and the device size ratio of the driver-stage floating inverting amplifier and the load-stage floating inverting amplifier is N:1, which ensures the stability of the gain under process, voltage and temperature fluctuations. 3. The stacked capacitor module of the present invention receives a reset signal to clear the charge stored on the stacked capacitor, and the low-delay digital decimation filter receives a reset signal to periodically clear the signal on the low-delay digital decimation filter, which can effectively eliminate the influence of idle tone and simplify the structure of digital filter. Attached Figure Description

[0015] Figure 1 A signal flow diagram of a high-precision, low-delay exponential incremental successive approximation analog-to-digital converter provided in an embodiment of the present invention; Figure 2 A single-ended circuit connection diagram of a high-precision, low-delay exponential incremental successive approximation analog-to-digital converter provided in an embodiment of the present invention; Figure 3 A schematic diagram of the clock signal for a high-precision, low-delay exponential incremental successive approximation analog-to-digital converter provided in an embodiment of the present invention; Figure 4 The circuit connection diagram is provided for a proportional floating inverting amplifier module according to an embodiment of the present invention. Detailed Implementation

[0016] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0017] Example 1 Please see Figure 1 , Figure 1 The present invention provides a signal flow diagram of a high-precision, low-delay exponential incremental successive approximation analog-to-digital converter.

[0018] This embodiment of a high-precision, low-delay exponential incremental successive approximation analog-to-digital converter includes: an exponential delay integrator module 10, a multi-bit quantizer 20, and a digital-to-analog converter module 30. The exponential delay integrator module 10, during the margin voltage storage stage, amplifies the margin voltage from the previous round by a preset factor, and then uses ping-pong timing control to alternate the operation of different stacked capacitors in odd and even cycles to delay the storage of the amplified margin voltage, achieving exponential integral accumulation of the margin voltage. The delayed storage of the noise-shaping signal is then superimposed on the input signal of the current round during the quantization stage to obtain the integral signal of the current round. The multi-bit quantizer 20 performs multi-bit quantization on the integral signal of the current round during the quantization stage to obtain the multi-bit digital signal of the current round. The digital-to-analog converter module 30 converts the multi-bit digital signal of the current round into an analog output signal to implement successive approximation logic. The analog output signal of the current round is subtracted from the input signal of the current round to obtain the margin voltage for noise shaping in the next round.

[0019] Specifically, in the analog domain, the input signal V in the (i-1)th round IN [i-1] and analog output signal V OUT [i-1] The difference is used to form the residual voltage V in the (i-1)th round. RES [i-1], the exponential delay integrator module 10 will convert the residual voltage V of the (i-1)th round. RES [i-1] Amplify by a preset factor and delay and store it in the exponential delay integrator module 10 for the i-th round, and according to the reset signal CLK RST The signal on the exponential delay integrator module 10 is cleared periodically. The preset multiplier is... In the i-th round, the signal stored in the exponential delay integrator module 10 and the input signal V are multiplied. IN [i] Sum to form the current round integral signal V NS[i], The multi-bit quantizer 20 will integrate the current round signal V. NS [i] Quantize multiple times to generate the multi-bit digital signal D for the current round. OUT，nbit [i]. The digital-to-analog converter module 30 converts the multi-bit digital signal D of the current round... OUT，nbit [i] is converted into the analog output signal V of the current round. OUT [i], where nbit represents the number of bits in the digital signal. For example, the multi-bit quantizer 20 is a 7-bit quantizer; correspondingly, the 7-bit quantizer quantizes 7 times to generate a 7-bit digital signal D. OUT，7bit [i].

[0020] The analog-to-digital converter (ADC) of this invention operates in three stages: sampling, quantization, and margin voltage storage. In the margin voltage storage stage, the exponential delay integrator module amplifies the margin voltage from the previous cycle using an exponential incremental noise shaping mechanism, thus transmitting noise. Furthermore, it uses ping-pong timing control to alternate the operation of different stacked capacitors in odd and even cycles to achieve delayed margin voltage storage. This exponential incremental noise shaping mechanism is highly sensitive to margin voltage, accelerating its accumulation and significantly enhancing the suppression of quantization noise in a short time. This ADC significantly reduces circuit complexity and processing delay while improving the system's robustness and energy efficiency in high-precision applications, effectively overcoming the reliance on high-order loop filters or high-rate oversampling in traditional solutions.

[0021] Please see Figure 2 , Figure 2 This is a single-ended circuit connection diagram of a high-precision, low-delay exponential incremental successive approximation analog-to-digital converter provided in an embodiment of the present invention.

[0022] In one specific embodiment, the exponential delay integrator module 10 includes a stacked capacitor module 101 and a proportional floating inverting amplifier module 102. The proportional floating inverting amplifier module 102 is used to multiply the residual voltage V from the previous cycle by a preset factor. RES [i-1] Amplification to obtain the amplified margin voltage; the stacked capacitor module 101 is used to control different stacked capacitors to work alternately in odd and even cycles through ping-pong timing to delay and store the amplified margin voltage, and receive the reset signal CLK after a preset period. RST This is to clear the charge stored on the stacked capacitors.

[0023] Specifically, the stacked capacitor module 101 includes: a first stacked capacitor C E Second stacked capacitor C O In odd-numbered periods, the second stacked capacitor C O With the multi-bit C in the digital-to-analog converter module 30 DAC The array modules 302 are stacked, and the amplified margin voltage is stored in the first stacked capacitor C. EAbove; in even-numbered periods, the first stacked capacitor C E With the multi-bit C in the digital-to-analog converter module 30 DAC The array modules 302 are stacked, and the amplified margin voltage is stored in the second stacked capacitor C. O superior.

[0024] Furthermore, the stacked capacitor module 101 also includes: a first control switch CLK. E11 Second control switch CLK E12 Third control switch CLK O21 Fourth control switch CLK O22 Fifth control switch CLK E21 The sixth control switch CLK E22 Seventh control switch CLK O11 Eighth control switch CLK O12 Ninth control switch CLK RST1 10th control switch CLK RST2 and the eleventh control switch .

[0025] First control switch CLK E11 The first end is connected to the eleventh control switch. The second and seventh control switches CLK O11 The first terminal; the third control switch CLK O21 The first terminal is used to input the first feedback voltage V FB- First control switch CLK E11 The second end is connected to the third control switch CLK O21 The second end, the first stacked capacitor C E The negative terminal and the ninth control switch CLK RST1 First terminal; Eleventh control switch The first end connects to multiple C bits DAC The upper plate of array module 302; the fifth control switch CLK E21 The first terminal is used to input the first feedback voltage V FB- Fifth control switch CLK E21 The second end is connected to the seventh control switch CLK O11 The second terminal, the second stacked capacitor C O The negative terminal and the tenth control switch CLK RST2 The first terminal; the second control switch CLK E12 The first end is connected to the ninth control switch CLK RST1 The second end, the first stacked capacitor C E The positive terminal and the fourth control switch CLK O22 The first terminal; the second control switch CLK E12The second end is connected to the eighth control switch CLK O12 The second terminal, the input terminal of the proportional floating inverting amplifier module 102, and the input terminal of the multi-bit quantizer 20; the fourth control switch CLK O22 The second terminal is used to input the second feedback voltage V. FB+ Sixth control switch CLK E22 The first end is connected to the second stacked capacitor C O The positive terminal, the eighth control switch CLK O12 The first and tenth control switches CLK RST2 The second end; the sixth control switch CLK E22 The second terminal is used to input the second feedback voltage V. FB+ .

[0026] In one specific implementation, the multi-bit quantizer 20 includes a comparator. The multi-bit quantizer 20 is implemented by performing multiple quantization operations through the comparator.

[0027] In one specific embodiment, the digital-to-analog converter module 30 includes a successive approximation control logic module 301 and a multi-bit C... DAC Array module 302. The input of successive approximation control logic module 301 is connected to the output of multi-bit quantizer 20, and the output of successive approximation control logic module 301 is connected to multi-bit C DAC The lower electrode plate of array module 302.

[0028] Multiple C DAC Array module 302 includes several capacitors, several multi-directional switches, and a twentieth control switch CLK. S The twentieth control switch CLK S The first end is used to receive the input signal, and the second end is connected to the upper plates of several capacitors; the lower plates of the capacitors are connected one-to-one to the common terminal of several multi-directional switches; the first selection terminal of each multi-directional switch is used to input the common-mode voltage V. CM The second selection terminal is used to input the in-phase reference voltage V. REFP The third selection terminal is used to input the inverting reference voltage V. REFN .

[0029] For example, multiple C DAC Array module 302 is a 7-bit C DAC The array module, correspondingly, has 64 capacitors and 64 multi-directional switches.

[0030] This embodiment describes the operation of a high-precision, low-delay exponential incremental successive approximation analog-to-digital converter as follows. For ease of understanding, this embodiment uses the first control switch CLK... E11 Second control switch CLK E12The clock signal is denoted as CLK. E1 Set the third control switch CLK O21 and the fourth control switch CLK O22 The clock signal is denoted as CLK. O2 Set the fifth control switch CLK E21 and the sixth control switch CLK E22 The clock signal is denoted as CLK. E2 Set the seventh control switch CLK O11 and the eighth control switch CLK O12 The clock signal is denoted as CLK. O1 Set the ninth control switch CLK RST1 and the tenth control switch CLK RST2 The reset signal is denoted as CLK. RST , eleventh control switch The clock signal is denoted as Set the twentieth control switch CLK S The clock signal is denoted as CLK. S , For CLK S The inverted signal, the clock signal of the proportional floating inverting amplifier module 102 is CLK. BUF .

[0031] In the simulation domain, when CLK S When the signal is high, the input signal hits multiple C bits. DAC Array module 302, the circuit samples the input signal. When CLK... S Inverted signal When CLK is high, during odd-numbered cycles... O1 Change to high level, multiple C DAC Array module 302 stacks second stacked capacitor C O The comparator quantizes seven times, and the resulting multi-bit digital signal controls a multi-bit C. DAC Array module 302 provides feedback to subtract the input signal from the quantization result, obtaining a residual voltage V. RES Appeared in multiple C DAC On the upper electrode plate of array module 302, subsequently, CLK BUF and CLK O2 The signal V becomes high. NS The differential storage is achieved through the proportional floating inverting amplifier module 102 and the first stacked capacitor C. E Above; during even-numbered periods, the second stacked capacitor C O and the first stacked capacitor C E Swap positions, CLK E1 Change to high level, multiple C DACArray module 302 stacks first stacked capacitor C E The comparator quantizes 7 times, and the resulting multi-bit digital signal controls a multi-bit C. DAC The array module 302 provides feedback, performing a subtraction operation between the input signal and the quantization result, resulting in a residual voltage V. RES Appeared in multiple C DAC On the upper electrode plate of array module 302, then CLK BUF and CLK E2 The signal V becomes high. NS The differential storage is achieved through the proportional floating inverting amplifier module 102 and the second stacked capacitor C. O Up. Every 10 cycles, the ninth control switch CLK... RST1 and the tenth control switch CLK RST2 Receive reset signal CLK RST To stack the second capacitor C O and the first stacked capacitor C E The stored charge is cleared.

[0032] Please see Figure 3 , Figure 3 This is a schematic diagram of the clock signal for a high-precision, low-delay exponential incremental successive approximation analog-to-digital converter (ADC) provided in an embodiment of the present invention. One operating cycle of this ADC is sequentially divided into three stages: sampling stage, quantization stage, and margin voltage storage stage. During the sampling stage of this cycle, CLK... S Rise to high level, multiple C DAC The capacitors in array module 302 begin sampling. During the quantization phase... Rise to high level, CLK S The signal drops to a low level, followed by the comparator's clock signal CLK. SAR After seven consecutive cycles, the comparator quantizes a seven-bit digital signal and sends it to multiple C bits. DAC On the lower electrode plate of array module 302. During the margin voltage storage phase, CLK BUF Rise to high level, timing CLK O1 and CLK O2 and CLK E1 and CLK E2 The timing sequence is configured to operate in both odd and even periods. To ensure effective noise shaping for exponential noise shaping, the reset signal CLK is used. RST Every 10 working cycles (i.e., one conversion cycle), the charge stored on the stacked capacitor module 101 is reset. This operation can effectively eliminate the influence of idle tones and simplify the digital filter structure.

[0033] Please see Figure 4 , Figure 4The circuit connection diagram is provided for a proportional floating inverting amplifier module according to an embodiment of the present invention.

[0034] The proportional floating inverting amplifier module 102 includes: a driver-stage floating inverting amplifier and a load-stage floating inverting amplifier.

[0035] The driver-stage floating inverting amplifier includes: a first NMOS transistor M N11 The second NMOS transistor M N12 The first PMOS transistor M P11 The second PMOS transistor M P12 A first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 and the second capacitor C2 constitute N. C RES Module. The load-stage floating inverting amplifier includes: a third NMOS transistor M N21 The fourth NMOS transistor M N22 The third PMOS transistor M P21 The fourth PMOS transistor M P22 The third capacitor C3 and the fourth capacitor C4, wherein the third capacitor C3 and the fourth capacitor C4 constitute C RES Module. N C RES Modules and C RES Each module uses two identical capacitors connected in parallel, and the capacitor plates are connected with the upper and lower plates interchanged.

[0036] The device size ratio of the driver-stage floating inverting amplifier and the load-stage floating inverting amplifier is N:1, that is: the first NMOS transistor M N11 With the third NMOS transistor M N21 The channel width-to-length ratio, the second NMOS transistor M N12 With the fourth NMOS transistor M N22 The channel width-to-length ratio, the first PMOS transistor M P11 With the third PMOS transistor M P21 The channel width-to-length ratio, the second PMOS transistor M P12 With the fourth PMOS transistor M P22 The width-to-length ratio of the channels is N:1, N C RES Modules and C RES The capacitor ratio of the module is N:1.

[0037] First NMOS transistor M N11 The gate of the first PMOS transistor M P11 The gate is connected and the positive input terminal integration signal V is applied. NSP The first NMOS transistor M N11 The drain of the first PMOS transistor M P11 The drain of the third NMOS transistor MN21 The gate of the third PMOS transistor M P21 The gate of the third NMOS transistor M N21 The drain of the third PMOS transistor M P21 The drain is connected and the first feedback voltage V is output. FB- ; Second NMOS transistor M N12 The gate of the second PMOS transistor M P12 The gate is connected and the negative input terminal is integrated with the signal V. NSN The second NMOS transistor M N12 The drain of the second PMOS transistor M P12 The drain of the fourth NMOS transistor M N22 The gate of the fourth NMOS transistor M N22 The drain of the fourth PMOS transistor M P22 The gate of the fourth PMOS transistor M P22 The drain is connected and the second feedback voltage V is output. FB+ ; First NMOS transistor M N11 The source of the second NMOS transistor M N12 The source of the first NMOS transistor is connected to the lower plate of the first capacitor C1 and the upper plate of the second capacitor C2; the third NMOS transistor M... N21 The source and the fourth NMOS transistor M N22 The source of the first PMOS transistor is connected to the lower plate of the third capacitor C3 and the upper plate of the fourth capacitor C4; the first PMOS transistor M... P11 The source and the second PMOS transistor M P12 The source of the first capacitor C1, the upper plate of the second capacitor C2, and the lower plate of the third PMOS transistor M are connected. P21 The source and the fourth PMOS transistor M P22 The source of the capacitor is connected to the upper plate of the third capacitor C3 and the lower plate of the fourth capacitor C4.

[0038] The proportional floating inverting amplifier module 102 also includes: a twelfth control switch CLK BUF1 Thirteenth control switch CLK BUF2 Fourteenth control switch CLK BUF3 The fifteenth control switch CLK BUF4 Sixteenth control switch CLK S1 Seventeenth control switch CLK S2 Eighteenth control switch CLK S3 and the nineteenth control switch CLK S4 .

[0039] Twelfth control switch CLK BUF1 Connected to the upper plate of the fourth capacitor C4 and the third NMOS transistor M N21 Between the source and the source; the thirteenth control switch CLKBUF2 Connected to the lower plate of the fourth capacitor C4 and the third PMOS transistor M P21 Between the source and the source; the fourteenth control switch CLK BUF3 Connected to the lower plate of the first capacitor C1 and the second NMOS transistor M N12 Between the source and the source; the fifteenth control switch CLK BUF4 Connected to the upper plate of the first capacitor C1 and the second PMOS transistor M P12 Between the source and the source; the sixteenth control switch CLK S1 The first terminal is connected to the power supply voltage, and the second terminal is connected between the lower plate of the third capacitor C3 and the upper plate of the fourth capacitor C4; the seventeenth control switch CLK S2 The first terminal is connected between the upper plate of the third capacitor C3 and the lower plate of the fourth capacitor C4, and the second terminal is grounded; the eighteenth control switch CLK S3 The first terminal is connected to the power supply voltage, and the second terminal is connected between the lower plate of the first capacitor C1 and the upper plate of the second capacitor C2; the nineteenth control switch CLK S4 The first end is connected between the upper plate of the first capacitor C1 and the lower plate of the second capacitor C2, and the second end is grounded.

[0040] In this embodiment, the proportional floating inverting amplifier module 102 has two phases within one cycle: a charging phase and an amplification phase. During the charging phase, the sixteenth control switch CLK... S1 Seventeenth control switch CLK S2 Eighteenth control switch CLK S3 and the nineteenth control switch CLK S4 clock signal CLK S When it rises to a high level, N C RES Modules and C RES One end of the module is connected to the power supply voltage VDD, and the other end is connected to GND. N C RES Modules and C RES The module is charged to the power supply voltage VDD. During the amplification stage, the sixteenth control switch CLK... S1 Seventeenth control switch CLK S2 Eighteenth control switch CLK S3 and the nineteenth control switch CLK S4 clock signal CLK S When the signal drops to a low level, the twelfth control switch CLK... BUF1 Thirteenth control switch CLK BUF2 Fourteenth control switch CLK BUF3 The fifteenth control switch CLK BUF4 clock signal CLK BUFWhen the signal rises to a high level, the amplifier begins to operate. Since the component size ratio of the driver-stage floating inverting amplifier to the load-stage floating inverting amplifier is N:1, the output of this op-amp is (V... FB+ -V FB -)=N (V NSP -V NSN The design selects noise shaping parameters. Since the differential proportional floating inverting amplifier module 102 is used to charge the stacked capacitor module 101, N=1 is chosen to achieve the storage of twice the margin voltage.

[0041] In the analog-to-digital converter of this embodiment, the proportional floating inverting amplifier module includes a driver-stage floating inverting amplifier and a load-stage floating inverting amplifier, and the device size ratio of the driver-stage floating inverting amplifier and the load-stage floating inverting amplifier is N:1, which ensures the stability of the gain under process, voltage and temperature fluctuations.

[0042] Given that exponential noise shaping technology is highly sensitive to margin voltage, this embodiment employs a gain-stable proportional floating inverting amplifier module, which significantly enhances circuit robustness while reliably improving system accuracy.

[0043] It should be noted that this embodiment Figure 2 The high-precision, low-delay exponential incremental successive approximation analog-to-digital converter shown is a single-ended circuit diagram. "Single-ended" means that, due to the input signal V... IN It is a differential signal, including the in-phase input signal V. INP and inverted input signal V INP , Figure 2 The signal shown in V NS The generation of this is only one of the differential signals. In the actual circuit layout, there is a stacked capacitor module 101, a successive approximation control logic module 301, and multiple C-bit capacitors. DAC Array module 302 generates positive terminal integral signal V NSP The inputs are fed into the proportional floating inverting amplifier module 102 and the multi-bit quantizer 20, and there is another stacked capacitor module 101, successive approximation control logic module 301, and multi-bit C... DAC Array module 302 generates negative-end integral signal V NSN The input is fed into the proportional floating inverting amplifier module 102 and the multi-bit quantizer 20.

[0044] In one specific embodiment, the delay integration is based on the exponential delay integrator module. The analog output signal V can be obtained. OUT [i] and input signal V IN The relationship of [i] is: Q, in which For the analog output signal of the i-th round, Let i be the input signal for the i-th round. Q is the noise transfer function. These are noise shaping parameters. Q represents the quantization error resulting from quantization by a multi-bit quantizer. As a delay factor, This is the preset multiplier.

[0045] Compared to traditional noise shaping parameters This embodiment introduces an exponential incremental noise shaping mechanism, which implements the noise transfer function through a proportional floating inverting amplifier module. Q, and select This accelerates the accumulation of margin voltage and strengthens the suppression of quantization noise in a shorter time, effectively replacing the traditional noise-shaping analog-to-digital converter that relies on high-order filters or high oversampling rates.

[0046] Please see again Figure 1 and Figure 2 The high-precision, low-delay exponential incremental successive approximation analog-to-digital converter of this embodiment further includes: a low-delay digital decimation filter 40, located in the digital domain, used to convert the multi-bit digital signal D of the current round... OUT，nbit [i] Perform digital filtering to obtain the Nyquist rate output signal D. OUT，Col and receive the reset signal CLK RST The signal on the low-delay digital decimation filter 40 is periodically cleared.

[0047] The low-delay digital decimation filter in this embodiment receives a reset signal to periodically clear the signal on the low-delay digital decimation filter, which can effectively eliminate the influence of idle tones and simplify the structure of the digital filter.

[0048] The high-precision, low-delay exponential incremental successive approximation analog-to-digital converter of this embodiment achieves high-order noise shaping capabilities with minimal hardware overhead and simplifies circuit complexity.

[0049] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-precision, low-delay exponential incremental successive approximation analog-to-digital converter, characterized in that, include: The exponential delay integrator module (10) is used to amplify the residual voltage of the previous round by a preset multiple during the residual voltage storage stage, and then use ping-pong timing control to control different stacked capacitors to work alternately in odd and even cycles to delay the storage of the amplified residual voltage, thereby realizing the exponential integration accumulation of the residual voltage; wherein, the amplified residual voltage stored in the delay is used to be superimposed with the input signal of the current round during the quantization stage to obtain the integral signal of the current round; A multi-bit quantizer (20) is used to perform multi-bit quantization on the integral signal of the current round during the quantization stage to obtain a multi-bit digital signal of the current round; The digital-to-analog converter module (30) is used to convert the multi-bit digital signal of the current round into the analog output signal of the current round to realize successive approximation logic. The analog output signal of the current round is used to subtract the input signal of the current round to obtain the margin voltage for noise shaping in the next round.

2. The high-precision, low-delay exponential incremental successive approximation analog-to-digital converter according to claim 1, characterized in that, The digital-to-analog converter module (30) includes a successive approximation control logic module (301) and a multi-bit C DAC Array module (302); The input terminal of the successive approximation control logic module (301) is connected to the output terminal of the multi-bit quantizer (20), and the output terminal of the successive approximation control logic module (301) is connected to the multi-bit quantizer (20). DAC The lower electrode plate of the array module (302).

3. The high-precision, low-delay exponential incremental successive approximation analog-to-digital converter according to claim 2, characterized in that, The exponential delay integrator module (10) includes a stacked capacitor module (101) and a proportional floating inverting amplifier module (102); The proportional floating inverting amplifier module (102) is used to amplify the residual voltage of the previous round by a preset factor to obtain the amplified residual voltage. The stacked capacitor module (101) is used to control different stacked capacitors to work alternately in odd and even cycles through ping-pong timing to delay and store the amplified margin voltage, and to receive a reset signal after a preset period to clear the charge stored on the stacked capacitors.

4. The high-precision, low-delay exponential incremental successive approximation analog-to-digital converter according to claim 3, characterized in that, The stacked capacitor module (101) includes: a first stacked capacitor (C E ) and second stacked capacitors (C O ); In odd-numbered periods, the second stacked capacitor (C) O ) and the multi-bit C in the digital-to-analog converter module (30) DAC The array modules (302) are stacked, and the amplified margin voltage is stored in the first stacked capacitor (C). E )superior; In even-numbered periods, the first stacked capacitor (C) E ) and the multi-bit C in the digital-to-analog converter module (30) DAC The array modules (302) are stacked, and the amplified margin voltage is stored in the second stacked capacitor (C). O )superior.

5. The high-precision, low-delay exponential incremental successive approximation analog-to-digital converter according to claim 4, characterized in that, The stacked capacitor module (101) also includes: multiple control switches; The first terminal of the first control switch is connected to the second terminal of the eleventh control switch and the first terminal of the seventh control switch; the first terminal of the third control switch is used to input the first feedback voltage; the second terminal of the first control switch is connected to the second terminal of the third control switch and the first stacked capacitor (C E The negative terminal of the 11th control switch is connected to the first terminal of the 9th control switch; the first terminal of the 11th control switch is connected to the multi-bit C DAC The upper plate of the array module (302); the first terminal of the fifth control switch is used to input the first feedback voltage; the second terminal of the fifth control switch is connected to the second terminal of the seventh control switch and the second stacked capacitor (C O The negative terminal of the first control switch and the first terminal of the tenth control switch; the first terminal of the second control switch is connected to the second terminal of the ninth control switch and the first stacked capacitor (C). E The positive terminal of the second control switch is connected to the first terminal of the fourth control switch; the second terminal of the second control switch is connected to the second terminal of the eighth control switch, the input terminal of the proportional floating inverting amplifier module (102), and the input terminal of the multi-bit quantizer (20); the second terminal of the fourth control switch is used to input the second feedback voltage; the first terminal of the sixth control switch is connected to the second stacked capacitor (C O The positive terminal of the sixth control switch, the first terminal of the eighth control switch, and the second terminal of the tenth control switch; the second terminal of the sixth control switch is used to input the second feedback voltage.

6. The high-precision, low-delay exponential incremental successive approximation analog-to-digital converter according to claim 3, characterized in that, The proportional floating inverting amplifier module (102) includes: a driver-stage floating inverting amplifier and a load-stage floating inverting amplifier with a device size ratio of N:1; the driver-stage floating inverting amplifier includes: a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first capacitor, and a second capacitor; the load-stage floating inverting amplifier includes: a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a third capacitor, and a fourth capacitor; The gate of the first NMOS transistor is connected to the gate of the first PMOS transistor and receives a positive integration signal. The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, the gate and drain of the third NMOS transistor, and the gate and drain of the third PMOS transistor, and outputs a first feedback voltage. The gate of the second NMOS transistor is connected to the gate of the second PMOS transistor and receives a negative integration signal. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, the gate and drain of the fourth NMOS transistor, and the gate and drain of the fourth PMOS transistor. And output a second feedback voltage; the source of the first NMOS transistor is connected to the source of the second NMOS transistor, the lower plate of the first capacitor, and the upper plate of the second capacitor; the source of the third NMOS transistor is connected to the source of the fourth NMOS transistor, the lower plate of the third capacitor, and the upper plate of the fourth capacitor; the source of the first PMOS transistor is connected to the source of the second PMOS transistor, the upper plate of the first capacitor, and the lower plate of the second capacitor; the source of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the upper plate of the third capacitor, and the lower plate of the fourth capacitor.

7. The high-precision, low-delay exponential incremental successive approximation analog-to-digital converter according to claim 6, characterized in that, The proportional floating inverting amplifier module (102) further includes: a twelfth control switch, a thirteenth control switch, a fourteenth control switch, a fifteenth control switch, a sixteenth control switch, a seventeenth control switch, an eighteenth control switch and a nineteenth control switch; The twelfth control switch is connected between the upper plate of the fourth capacitor and the source of the third NMOS transistor; the thirteenth control switch is connected between the lower plate of the fourth capacitor and the source of the third PMOS transistor; the fourteenth control switch is connected between the lower plate of the first capacitor and the source of the second NMOS transistor; and the fifteenth control switch is connected between the upper plate of the first capacitor and the source of the second PMOS transistor. The first terminal of the sixteenth control switch is connected to the power supply voltage, and the second terminal is connected between the lower plate of the third capacitor and the upper plate of the fourth capacitor; the first terminal of the seventeenth control switch is connected between the upper plate of the third capacitor and the lower plate of the fourth capacitor, and the second terminal is grounded; the first terminal of the eighteenth control switch is connected to the power supply voltage, and the second terminal is connected between the lower plate of the first capacitor and the upper plate of the second capacitor; the first terminal of the nineteenth control switch is connected between the upper plate of the first capacitor and the lower plate of the second capacitor, and the second terminal is grounded.

8. The high-precision, low-delay exponential incremental successive approximation analog-to-digital converter according to claim 2, characterized in that, The multiple C DAC The array module (302) includes several capacitors, several multi-directional switches, and a twentieth control switch; The first end of the twentieth control switch is used to receive the input signal, and the second end is connected to the upper plate of several capacitors; the lower plates of the several capacitors are connected to the common terminal of the several multi-directional switches in a corresponding manner; the first selection terminal of each multi-directional switch is used to input the common-mode voltage, the second selection terminal is used to input the in-phase reference voltage, and the third selection terminal is used to input the in-phase reference voltage.

9. The high-precision, low-delay exponential incremental successive approximation analog-to-digital converter according to claim 1, characterized in that, The relationship between the analog output signal and the input signal is as follows: Q, in which For the analog output signal of the i-th round, Let i be the input signal for the i-th round. Q is the noise transfer function. These are noise shaping parameters. Q represents the quantization error resulting from quantization by a multi-bit quantizer. As a delay factor, This is the preset multiplier.

10. The high-precision, low-delay exponential incremental successive approximation analog-to-digital converter according to claim 1, characterized in that, Also includes: The low-delay digital decimation filter (40) is used to perform digital filtering on the multi-bit digital signal of the current round to obtain the Nyquist rate output signal, and to receive a reset signal to periodically clear the signal on the low-delay digital decimation filter (40).

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