Satellite communication high-speed decoder with ARM-FPGA hybrid architecture and decoding method

Abstract

This invention discloses a high-speed satellite communication decoder and decoding method based on an ARM-FPGA hybrid architecture, belonging to the field of satellite communication technology. The invention employs an ARM-FPGA heterogeneous platform to achieve hardware and software collaboration. The software subsystem runs on the ARM and is responsible for packet loss detection and flow control; the hardware subsystem is a freely running decoding IP core on the FPGA, executing a real-time Gaussian elimination algorithm, and using a dual-half-table architecture multiplier and parallel computing module to accelerate Galois domain operations; high-speed data and configuration information interaction is achieved through the AXI4 bus. This decoder distributes latency, reducing the average decoding latency by 57.44%, and increasing throughput to more than twice that of traditional solutions, significantly improving the real-time performance and reliability of satellite communication.

Description

Technical Field

[0001] This invention relates to the field of satellite communication technology, specifically to a high-speed satellite communication decoder and decoding method based on an ARM-FPGA hybrid architecture. Background Technology

[0002] 6G's key to seamless global connectivity and the integrated air-space-ground network are attracting worldwide attention. However, the inherent long latency and high packet loss rate of transmission control protocols pose a serious challenge to traditional protocols. The widely used TCP protocol heavily relies on acknowledgment and retransmission mechanisms, which are inefficient in this dynamic and unstable environment, often leading to throughput fluctuations. To address this issue, forward erasure coding (FEC) inserts redundant packets, enabling the receiver to directly recover the original data from packet loss, thereby reducing frequent retransmissions and significantly improving end-to-end performance. However, its inherently complex computation (heavy Galois domain computation) introduces new burdens. Furthermore, the decoder may need to wait for a sufficient number of packets before starting decoding, resulting in additional latency. Attempting to simply accelerate computation by using a more powerful CPU is not a viable strategy, as it would lead to a significant increase in the power consumption, cost, and size of the terminal device, contradicting the core requirement for lightweight devices in practice. Summary of the Invention

[0003] The technical problem to be solved by this invention is to address the shortcomings of existing technologies by proposing a high-speed satellite communication decoder and decoding method based on an ARM-FPGA hybrid architecture. A hardware and software co-designed decoding system is designed and implemented, and a real-time Gaussian elimination algorithm is used to eliminate traditional waiting delays. The control-intensive workload is distributed to the ARM core, while the computationally intensive tasks are offloaded to the FPGA, leveraging its parallel computing capabilities to reduce decoding delays and fully utilizing the comprehensive advantages of heterogeneous architectures.

[0004] To solve the above problems, the present invention adopts the following technical solution:

[0005] First, this invention proposes a high-speed satellite communication decoder with an ARM-FPGA hybrid architecture, comprising:

[0006] The software subsystem, running on an ARM processor, is used to analyze received data packets, determine whether packet loss has occurred based on the continuity of the received data packet sequence, and activate the decoder when packet loss is detected; it is also used to deactivate the decoder and read back the data after decoding is completed by detecting the state of the decoding window.

[0007] The hardware subsystem, deployed on an FPGA, is designed as a decoder IP core operating in free mode. This IP core begins running immediately upon power-up, with its internal state machine monitoring the input data stream in real time. Upon activation, it automatically executes an instantaneous Gaussian elimination algorithm for real-time matrix solving, outputting the final decoding result. The hardware subsystem also includes a parallel computing module to accelerate complex calculations in the Galois field, and an automatic zeroing operation on its own storage matrix and important registers after the decoder is deactivated.

[0008] The ARM processor and the FPGA communicate and exchange data via a hierarchical AXI4 standard bus.

[0009] Preferably, the AXI4 standard bus includes:

[0010] The AXI-Stream bus is used for high-speed, streaming data transfer between ARM and FPGA, and its data bit width is set to match the degree of parallelism.

[0011] The AXI-Lite bus provides a control interface for the ARM processor to configure the parameters of the decoder IP core and regulate the direct memory access controller.

[0012] Preferably, the software subsystem is further configured to configure parameters of the direct memory access controller and decoder IP core via the AXI-Lite bus, the parameters including packet ID, packet type and packet length.

[0013] Preferably, the software subsystem is configured as follows:

[0014] Whether a packet is lost is determined by detecting the continuity of the received source packet ID sequence;

[0015] When the received source packet ID is m, if the next received source packet ID is m+w and w>1, it is determined that packet loss has occurred, the decoder is activated, and the decoding window size is updated to w, the starting index is m+1, and the ending index is m+w.

[0016] Preferably, the hardware subsystem is configured to execute the real-time Gaussian elimination algorithm OF-GE, the process of which includes:

[0017] Each received data packet is processed immediately, distributing the decoding delay throughout the entire decoding cycle. A linear equation system AX=B is constructed within the decoding window, and the coefficient matrix A is always maintained as an upper triangular matrix. When A reaches full rank, the lost source packet is recovered by back-substitution based on the values ​​of its corresponding matrix B and the source packet matrix X.

[0018] Preferably, the parallel computing module includes a Galois field multiplier based on a dual-half-table architecture.

[0019] Preferably, the Galois field multiplier of the dual-half-table architecture is configured as follows:

[0020] Decompose operand a into:

[0021] ;

[0022] in, The high 4 bits of 'a' For the lower 4 bits of 'a', shift the higher 4 bytes left by four bits and add the lower 4 bytes; transform the result of multiplying operands 'a' and 'b' into:

[0023] ;

[0024] Construct two new lookup tables respectively and To calculate, and The lookup table results are the products of the high and low four digits of b and a, i.e. ;

[0025] The lookup table and XOR the output to get the final result a * b.

[0026] Preferably, based on the lookup table, the Galois domain multiplier based on the double-half-table architecture is specifically a three-stage pipelined multiplication unit, which executes sequentially:

[0027] The shift register splits 'a' into high and low 4 bits, which serve as indices for two lookup tables.

[0028] Using the high 4 bits, low 4 bits, and operand b as indexes, parallel queries are performed to obtain... and value;

[0029] The outputs of the two lookup tables are combined into the final result using the XOR module.

[0030] Preferably, the parallel computing module further includes a parallel multiply-accumulate computing module, which is constructed by replicating the three-stage pipelined multiplication unit, and the overall output result... Represented as:

[0031] ;

[0032] in, and For an n-byte vector, It is a scalar.

[0033] Meanwhile, this invention proposes a high-speed forward erasure decoding method for satellite communication, applied to the ARM-FPGA hybrid architecture proposed in the aforementioned high-speed satellite communication decoder, comprising the following steps:

[0034] The ARM processor analyzes the received data packets, determines whether there is packet loss based on the continuity of the data packet sequence, and activates the decoding process when packet loss is detected.

[0035] The FPGA operates in free mode, responding to the activation by monitoring the data flow through a state machine and executing a real-time Gaussian elimination algorithm for decoding calculation, and outputting the result.

[0036] The ARM processor and the FPGA communicate and exchange data via an AXI bus.

[0037] The present invention adopts the above technical solution and has the following technical effects compared with the prior art:

[0038] (1) By adopting the real-time Gaussian elimination algorithm OF-GE and implementing it in hardware, the instant processing of each received data packet is realized, and the waiting delay concentrated before the decoding starts in the traditional scheme is distributed to the entire data packet reception cycle.

[0039] (2) Based on the ARM-FPGA hybrid architecture, the hardware and software co-design allocates control-intensive tasks to the ARM processor, while offloading computationally intensive tasks to the FPGA for parallel execution. Combined with the bit-width matched AXI-Stream high-speed data stream interface, the data processing bottleneck is effectively eliminated.

[0040] (3) The Galois domain multiplier with a dual half-table architecture reduces the storage resources required by the traditional GF(2^8) complete multiplication lookup table from 64KB to only 8KB, reducing resource usage to 1 / 8 of the original. This allows for the integration of more parallel multiply-accumulate computation units within the limited BRAM resources of the FPGA, thereby achieving an order-of-magnitude improvement in computational performance without increasing hardware costs. Attached Figure Description

[0041] Figure 1 This is a flowchart illustrating the principle of the OF-GE algorithm involved in this invention.

[0042] Figure 2 This invention relates to a block diagram of a high-speed satellite communication decoder with an ARM-FPGA hybrid architecture.

[0043] Figure 3 This is the winning architecture of the MulU computing unit and parallel multiply-accumulate module involved in the embodiment.

[0044] Figure 4This is a comparison chart of decoding latency and throughput between the new scheme and the traditional scheme involved in the embodiment under different data packet sizes K. Detailed Implementation

[0045] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

[0046] Example 1: This example proposes a high-speed satellite communication decoder based on an ARM-FPGA hybrid architecture. The core of the technical solution lies in constructing a hardware-software collaborative computing architecture, rationally dividing tasks, and improving decoding efficiency through hardware parallelization and resource optimization techniques. This invention uses an ARM-FPGA heterogeneous computing platform, represented by the Xilinx ZYNQ SoC, as the hardware carrier. The system architecture clearly defines the functions of software and hardware to achieve collaborative computing.

[0047] 1. Working principle and hardware implementation of real-time decoding:

[0048] To facilitate understanding of the decoding algorithm and its hardware implementation, we will first briefly introduce the sliding window forward erasure coding (FEC) process. The core idea of ​​FEC is to add a certain frequency ( ) to the data packet transmission stream. Insert repair package group Its composition is as follows:

[0049] ,

[0050] in, The data packets that need to be transmitted are referred to hereafter as source packets, and each source packet is K bytes in size; To generate GF (Galois field) numbers using pseudo-random numbers, GF(2^8) is used here, meaning that each number is exactly 1 byte in size; , These are the start and end indices of the encoding window, respectively. ; * represents multiplication in GF(2^8). All arithmetic operations such as multiplication and addition mentioned in subsequent articles are calculated in GF(2^8).

[0051] The pseudo-random number generator uses the repair packet ID as a seed to generate pseudo-random numbers; therefore, it is not necessary to transmit the specific ID during the transmission of the repair packet. Only the repair package ID needs to be transmitted. When the receiving end needs to use it, the repair package ID can be directly used as a seed to generate repair coefficients through the same pseudo-random number generator.

[0052] The receiver determines whether a packet has been lost by detecting the continuity of the received source packet ID sequence. When the received source packet ID is m, if the next received source packet ID is m+w and w>1, that is, the source packet with ID m+1 has been lost. At this time, the decoder is activated, the decoding window size is updated to w, the start index is m+1, and the end index is m+w. The entire decoding process of the decoder is carried out in the FPGA. The ARM only needs to provide data and key parameters to the FPGA.

[0053] The FPGA internally uses the real-time Gaussian elimination algorithm OF-GE to build a hardware decoding pipeline. The OF-GE algorithm principle and flow are as follows: Figure 1 As shown. The core of the OF-GE algorithm is to process each received data packet immediately, thereby distributing the decoding delay over the entire decoding cycle. Essentially, it constructs a system of linear equations AX=B within the decoding window, and always maintains the coefficient matrix A as an upper triangular matrix. After A reaches full rank, the lost source packet is recovered by back-substitution based on the values ​​of its corresponding matrix B and the source packet matrix X.

[0054] When a data packet is received, the first step is to determine whether real-time elimination should be performed based on the packet type (source packet or repair packet). Real-time elimination is only required for repair packets. When a repair packet... When it arrives, if its If the value is greater than the end index of the decoding window, the decoding window needs to be expanded to... The repair package coefficients are then obtained using a pseudo-random number generator seeded by the repair package ID. , Next, in the stored matrix, starting from the first row, search downwards for an empty row, denoted by index h. The first h-1 elements are eliminated. To perform synchronization operations, please refer to the algorithm diagram for the calculation method. The calculated... , The corresponding data is stored in row h of matrices A and B. If a source packet is detected... Upon arrival, similar to a repair packet, the decoding window is updated based on the sequence number i. Then, the position of the source packet in the storage matrix is ​​determined using sequence number i, p=im. At this point, A[p][p]=1, and all other values ​​in row p are set to 0. The data from the source packet is stored unchanged in row p of B. The linear equation system AX=B is maintained according to this algorithm, with its coefficient matrix A always remaining an upper triangular matrix. When A reaches full rank, a backward substitution is performed to solve for X, thus obtaining the data from the lost source packet. After decoding, the decoder is deactivated, and subsequent updates are performed. This is the end index of the decoding window.

[0055] 2. Parallelization of key computing units:

[0056] Complex Galois field multiplication operations are repeatedly performed during decoding, consuming a significant amount of decoding time. The parallel computing capabilities of an FPGA can be leveraged to execute these operations multiple times simultaneously. However, traditional lookup table methods pre-compute the products between all GF(2^8) operands, resulting in a multiplication table that occupies 256*256 bytes (64KB). This consumes a large amount of BRAM resources in the FPGA, hindering highly parallel computation. Therefore, a double-half-table architecture is adopted. In this architecture, the linearity of Galois field computation allows 'a' to be decomposed into...

[0057] ,

[0058] in, The high 4 bits of 'a' Given the lower 4 bits of 'a', the final result is obtained by shifting the higher 4 bytes left by four bits and adding the lower 4 bytes. Addition in the Galois field is essentially a bitwise AND operation. Based on this, the multiplication result of 'a' and 'b' can be transformed into:

[0059] ,

[0060] At this point, the product of the two expressions is transformed into the XOR of the two new expressions. To compute the two decomposed expressions, two new lookup tables are now constructed respectively. and To calculate, construct and The lookup table results are the products of the high and low four digits of b and a, i.e. Since b is taken from GF (2^8), the two newly constructed lookup tables occupy a total of 256*16*2 bytes, or 8KB, which significantly reduces resource consumption compared to the traditional 64KB lookup table.

[0061] Based on the above lookup table, such as Figure 3 As shown, a MulU (Multiply Unit, a three-stage pipelined multiplication unit) was designed. First, a was split into high / low 4 bits using a shift register to serve as indices for two lookup tables. Then, both bits were simultaneously used with b as lookup table indices to obtain the result. and The value is then processed by an XOR module to obtain the final calculation result.

[0062] Based on the MulU module, a parallel multiply-accumulate computation module was designed. Essentially, it replicates the MulU module to enable simultaneous operations. During computation, the n-byte vector `src` is first multiplied by a scalar using the MulU module, and then its output is added to a vector `dst` of the same size, completing the multiply-accumulate operation. The final output can be represented as...

[0063] .

[0064] 3. Top-level architecture functional division as follows: Figure 2 As shown, where:

[0065] The ARM processor (software subsystem) is responsible for computationally intensive tasks, scheduling and controlling the entire decoding process. This includes analyzing received data packets, determining packet loss based on the continuity of the received packet sequence, activating the decoder, configuring important parameters (packet ID, packet type, packet length) in the DMA and IP cores via the AXI-Lite bus, and determining whether to deactivate the decoder and read back data by detecting the status of the decoding window. Leveraging the advantages of the ARM processor in complex logic control and system management, it serves as the system's control core, enabling flexible scheduling of computational tasks and efficient management of the entire decoding process.

[0066] FPGA Section (Hardware Subsystem): The decoder IP core is designed for free-running mode. After power-on setup, the IP core immediately begins operation. The state machine monitors the input data stream in real time. When a data packet is received from the ARM via DMA and the AXI-Stream high-speed interface, it automatically executes the instantaneous Gaussian elimination algorithm to perform real-time matrix solving and output the final decoding result. It also accelerates complex GF(2^8) calculations through a high-efficiency parallel computing module. After deactivating the decoder, the IP core automatically performs a zeroing operation, clearing its own storage matrix and important registers to prevent data contamination during subsequent decoding calculations.

[0067] The ARM processor and the FPGA communicate and exchange data via a hierarchical AXI4 standard bus, wherein:

[0068] AXI-Stream bus: Used for high-speed, streaming data transfer between ARM and FPGA. Its data bit width is set to match the degree of parallelism. It provides a high-bandwidth data channel, ensuring a continuous flow of data from memory to the FPGA computing units, avoiding idle computing units due to insufficient data supply, and is the foundation for achieving high throughput.

[0069] The AXI-Lite bus consists of two AXI-Lite interfaces: one for configuring key IP core parameters, such as packet sequence (i.e., source packet or repair packet ID), packet size, and packet type; and the other Lite interface for controlling DMA, including data start location, data transfer length, and data transfer direction. This mechanism provides the ARM processor with a standard and simple control interface for starting, configuring, and monitoring the hardware modules on the FPGA side, and is crucial for achieving hardware-software co-control.

[0070] Compared with existing traditional software decoders, the performance improvement of this invention is as follows: Figure 4 As shown:

[0071] With 32-bit parallelism and a matching 256-bit AXI-Stream interface, our decoder architecture achieves an average latency reduction of 57.44% across multiple different packet sizes (K), with the improvement becoming more pronounced as K increases, reaching a maximum reduction of 77.43%. Correspondingly, throughput also shows a significant improvement, with the proposed decoder achieving an average throughput more than twice that of conventional solutions. As the packet size K increases, the speedup reaches 3.4 times due to parallel computation, demonstrating the advantages of hardware-software co-computing using an ARM-FPGA heterogeneous decoder architecture.

[0072] Example 2: This example proposes a high-speed forward erasure decoding method for satellite communication, applied to an ARM-FPGA hybrid architecture, including the following steps:

[0073] The ARM processor analyzes the received data packets, determines whether there is packet loss based on the continuity of the data packet sequence, and activates the decoding process when packet loss is detected.

[0074] The FPGA operates in free mode, responding to the activation by monitoring the data flow through a state machine and executing a real-time Gaussian elimination algorithm for decoding calculation, and outputting the result.

[0075] The ARM processor and the FPGA communicate and exchange data via an AXI bus.

[0076] It should be noted that the processing flow of Embodiment 2 corresponds to the specific steps of the module provided in Embodiment 1 of the present invention, and has the corresponding functional modules and beneficial effects of the execution method. Technical details not described in detail in this embodiment can be found in Embodiment 1 of the present invention.

[0077] The specific implementation schemes described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific implementation schemes of the present invention and are not intended to limit the scope of the present invention. Any equivalent changes and modifications made by those skilled in the art without departing from the concept and principles of the present invention should fall within the scope of protection of the present invention.

Claims

1. A high-speed satellite communication decoder with an ARM-FPGA hybrid architecture, characterized in that, include: The software subsystem, running on the ARM processor, is used to analyze the received data packets, determine whether there is packet loss based on the continuity of the received data packet sequence, and activate the decoder when packet loss is determined. And to deactivate the decoder and read back the data after decoding is complete by detecting the state of the decoding window; The hardware subsystem, deployed on an FPGA, is designed as a decoder IP core in free-running mode. This IP core starts running as soon as it is powered on. Its internal state machine monitors the input data stream in real time and automatically executes the instantaneous Gaussian elimination algorithm to solve the matrix in real time after being activated, and outputs the final decoding result. The hardware subsystem also includes a parallel computing module for accelerating the computation of the Galois field; and an automatic zeroing operation for its own storage matrix and important registers after the decoder is deactivated. The ARM processor and the FPGA communicate and exchange data via a hierarchical AXI4 standard bus.

2. The high-speed satellite communication decoder with an ARM-FPGA hybrid architecture according to claim 1, characterized in that, The AXI4 standard bus includes: The AXI-Stream bus is used for high-speed, streaming data transfer between ARM and FPGA, and its data bit width is set to match the degree of parallelism. The AXI-Lite bus provides a control interface for the ARM processor to configure the parameters of the decoder IP core and regulate the direct memory access controller.

3. A high-speed satellite communication decoder with an ARM-FPGA hybrid architecture according to claim 2, characterized in that, The software subsystem is also used to configure parameters of the direct memory access controller and decoder IP core via the AXI-Lite bus, including packet ID, packet type and packet length.

4. A high-speed satellite communication decoder with an ARM-FPGA hybrid architecture according to claim 1, characterized in that, The software subsystem is configured as follows: Whether a packet is lost is determined by detecting the continuity of the received source packet ID sequence; When the received source packet ID is m, if the next received source packet ID is m+w and w>1, it is determined that packet loss has occurred, the decoder is activated, and the decoding window size is updated to w, the starting index is m+1, and the ending index is m+w.

5. A high-speed satellite communication decoder with an ARM-FPGA hybrid architecture according to claim 4, characterized in that, The hardware subsystem is configured to execute the real-time Gaussian elimination algorithm OF-GE, the process of which includes: Each received data packet is processed immediately, distributing the decoding delay throughout the entire decoding cycle. A linear equation system AX=B is constructed within the decoding window, and the coefficient matrix A is always maintained as an upper triangular matrix. When A reaches full rank, the lost source packet is recovered by back-substitution based on the values ​​of its corresponding matrix B and the source packet matrix X.

6. A high-speed satellite communication decoder with an ARM-FPGA hybrid architecture according to claim 1, characterized in that, The parallel computing module includes a Galois field multiplier based on a dual-half-table architecture.

7. A high-speed satellite communication decoder with an ARM-FPGA hybrid architecture according to claim 6, characterized in that, The Galois field multiplier of the dual-half-table architecture is configured as follows: Decompose operand a into: ； in, The high 4 bits of 'a' For the lower 4 bits of 'a', shift the higher 4 bytes left by four bits and add the lower 4 bytes; transform the result of multiplying operands 'a' and 'b' into: ； Construct two new lookup tables respectively and To calculate, and The lookup table results are the products of the high and low four digits of b and a, i.e. ; The lookup table and XOR the output to get the final result a * b.

8. A high-speed satellite communication decoder with an ARM-FPGA hybrid architecture according to claim 7, characterized in that, Based on the aforementioned lookup table, the Galois field multiplier with a double-semi-table architecture is specifically a three-stage pipelined multiplication unit, which executes sequentially: The shift register splits 'a' into high and low 4 bits, which serve as indices for two lookup tables. Using the high 4 bits, low 4 bits, and operand b as indexes, parallel queries are performed to obtain... and value; The outputs of the two lookup tables are combined into the final result using the XOR module.

9. A high-speed satellite communication decoder with an ARM-FPGA hybrid architecture according to claim 8, characterized in that, The parallel computing module also includes a parallel multiply-accumulate computing module, which is constructed by replicating the three-stage pipelined multiplication unit, and the overall output result is... Represented as: ； in, and For an n-byte vector, It is a scalar.

10. A high-speed forward erasure decoding method for satellite communication, characterized in that, The high-speed satellite communication decoder described in any one of claims 1-9 comprises the following steps: The ARM processor analyzes the received data packets, determines whether there is packet loss based on the continuity of the data packet sequence, and activates the decoding process when packet loss is detected. The FPGA operates in free mode, responding to the activation by monitoring the data flow through a state machine and executing a real-time Gaussian elimination algorithm for decoding calculation, and outputting the result. The ARM processor and the FPGA communicate and exchange data via an AXI bus.

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