Hash algorithm data padding IP core based on FPGA

Abstract

This invention discloses a hash algorithm data filling IP core based on FPGA, comprising: an end-to-end conversion module, a bit-width conversion module, a message processing module, a splicing module, and a FIFO module. This invention divides large functional modules into numerous smaller, single-function modules, which are connected via stream interfaces, thereby changing centralized control to distributed control. This simplifies inter-module interaction, reduces signal propagation delay, facilitates expansion and maintenance, and provides good fault tolerance. Parametric design increases adaptability.

Description

Technical Field

[0001] This invention relates to the field of information security, and in particular to an IP core for data filling using a hash algorithm based on FPGA. Background Technology

[0002] A hash algorithm is an algorithm that transforms input data of arbitrary length (usually called a message) into fixed-length output data (hash value) using a hash function. Hash algorithms have wide applications in computer science and information security, such as data verification, password storage, digital signatures, and database indexing. Common international hash algorithms are primarily the Secure Hash Algorithm (SHA), including SHA-1, SHA-256, SHA-384, and SHA-512. Domestically, the main hash algorithm is the SM3 cryptographic hash algorithm released by the State Cryptography Administration of China.

[0003] The workflow of a general hash algorithm mainly consists of two parts: data filling and iterative compression. For example... Figure 1 and Figure 2 The diagram illustrates the working principle of data padding, with block lengths of 512 bits and 1024 bits respectively. Assuming message M has a length of L bits, first, one bit "1" is appended to the end of the message, followed by K bits "0", and finally a 64-bit bit string is added, which is the binary representation of message length L. Here, K should satisfy equation (1-1). L + 1 + K ≡ 448 mod 512 (1-1) K is the smallest non-negative integer that satisfies equation (1-1).

[0004] Figure 2 The case of a block length of 1024 bits is given. In this case, a 128-bit string needs to be added at the end, and K should satisfy equation (1-2). L + 1 + K ≡ 896 mod 1024 (1-2) K is the smallest non-negative integer that satisfies equation (1-2).

[0005] The iterative compression part of a hash algorithm varies in its specific implementation depending on the algorithm, but its basic principles and processes are similar. Iterative compression is the key step in progressively compressing input data into a fixed-length hash value, typically involving operations such as nonlinear functions, modulo addition, XOR, and circular shifting. Different algorithms mainly differ in the number of iterations, the selection and use of nonlinear functions, and the implementation of specific operations. Figure 3 and Figure 4 The diagram illustrates the specific process of SM3 compression iteration. Figure 3 In it, the padded message is expanded to generate 132 characters (32 bits). The expansion process includes operations such as circular left shift and exclusive OR to enhance the diffusion and randomness of the message. The message expansion provides input for the subsequent compression process. Figure 4 The specific process of SM3 compression is given. The compression function processes the message block and the intermediate state value through 64 rounds of iteration. Each round of iteration includes: the selection of message words, selecting message words WJ and W’J from the expanded message words; non-linear transformation, performing a series of non-linear transformations on the intermediate state value, including logical operations such as exclusive OR, AND, OR, NOT, and circular shift operations, as Figure 4 shown. The FF, GG, and P0 functions are also non-linear transformations, specifically as shown in equations (1-3), (1-4), and (1-5); state update, updating the intermediate state value with the result of the non-linear transformation. Finally, after processing all the block messages, the intermediate state value is the final hash value.

[0006] (1-3) (1-4) (1-5) In the formula: ⊕: Exclusive OR operation ∧: AND operation ∨: OR operation ¬: NOT operation <<<k: Circular left shift k-bit operation In general hash algorithms, the data padding part usually remains the same, while the compression iteration part varies according to the specific algorithm. However, when implementing these algorithms using FPGAs, problems will occur in the data padding part. When the output bit width is large (such as 512 bits or 1024 bits), the data padding process will consume a large amount of FPGA resources, including Lookup Table (LUT) and RAM resources. This makes the implementation of the data padding part not very applicable in resource-constrained scenarios. In addition, the large output bit width will also cause timing tightness problems in FPGA synthesis. These problems limit the application of general hash algorithms in resource-constrained FPGA environments. How to further optimize or improve to enhance its applicability is an urgent problem to be solved. Summary of the Invention

[0007] In view of the above problems, the present invention proposes a data padding IP core for hash algorithms based on FPGA.

[0008] To achieve the objectives of this invention, an FPGA-based hash algorithm data filling IP core is provided, comprising: an end-to-end conversion module, a bit-width conversion module, a message processing module, a splicing module, and a FIFO module; The end-to-end conversion module is used to: perform end-to-end conversion on the data input to the end-to-end conversion module; The bit width conversion module is used to: perform operations on the data input to the bit width conversion module to convert large bit width to small bit width, or small bit width to large bit width; The message processing module is used to: perform byte statistics on the data input to the message processing module, and fill the last byte of the data input to the message processing module based on the result of the byte statistics and a preset grouping mode; The splicing module is used to: splice the data input to the splicing module into a preset bit width; The end-to-end conversion module receives user input data, performs end-to-end conversion on it, and then stores the end-to-end converted user input data into the FIFO module. The bit-width conversion module reads the end-to-end converted user input data from the FIFO module, performs bit-width conversion on it, and then stores the bit-width converted user input data into the FIFO module. The message processing module reads the bit-width converted user input data from the FIFO module, performs a padding operation on the last data segment of the bit-width converted user input data, and then stores the padded user input data into the FIFO module. The splicing module reads the padded user input data from the FIFO module, performs a splicing operation on it, and then stores the spliced ​​user input data into the FIFO module.

[0009] Furthermore, the bit-width conversion module includes: a first register module; the first register module is used to: cache temporary data when converting the input data to the bit-width conversion module from small bit-width to large bit-width; The splicing module includes a second register module; the second register module is used to cache temporary data when splicing the data input to the splicing module.

[0010] Furthermore, the end-to-end conversion module includes: a first input bit width setting parameter and an input data end-to-end identifier parameter; The first input bit width setting parameter is used to: set the bit width of the input data to the end-to-end conversion module based on the data of the input end-to-end conversion module; The input data end-order identifier parameter is used to: set the end-order format of the input end-order conversion module based on the data of the input end-order conversion module.

[0011] Furthermore, the bit width conversion module also includes: a second input bit width setting parameter and a first output bit width setting parameter; The second input bit width setting parameter is used to: set the bit width of the input data to the bit width conversion module; The first output bit width setting parameter is used to: set the bit width of the output bit width conversion module data.

[0012] Furthermore, the message processing module includes two byte modes: a 512-byte mode and a 1024-byte mode.

[0013] The input and output bit widths of the message processing module are both 64 bits.

[0014] Furthermore, the splicing module includes two grouping modes: 512-bit mode and 1024-bit mode.

[0015] Furthermore, the specific process of converting the large-bit-width data to small-bit-width data input to the bit-width conversion module includes: the bit-width conversion module converts the large-bit-width data into several small-bit-width data; the bit-width conversion module then inputs the several small-bit-width data into the FIFO module one by one; The specific process of converting the input data of the bit-width conversion module from small bit-width to large bit-width includes: the bit-width conversion module stores several small bit-width data into the first register module one by one; the bit-width conversion module concatenates several small bit-width data in the first register module into large bit-width data, and then stores the large bit-width data into the FIFO module.

[0016] Furthermore, the specific process of concatenating the data input to the concatenation module into a preset bit width includes: the concatenation module storing several pieces of data input to the concatenation module into the second register module one by one; the concatenation module performing a concatenation operation on several pieces of data stored in the second register module based on the preset grouping mode, and obtaining data with the corresponding bit width; and the concatenation module storing the data with the corresponding bit width into the FIFO module.

[0017] Furthermore, the AXI4 stream interface is used as the data transmission interface between the modules.

[0018] Compared with the prior art, the present invention has the following beneficial technical effects: This invention employs a distributed control architecture. Compared to traditional centralized control, distributed control can distribute tasks across multiple modules, each operating independently, thus significantly improving system flexibility and scalability. This architecture allows the system to dynamically adjust the working state of each module according to actual needs, reducing dependence on global resources and lowering system complexity and failure risk. Secondly, this invention utilizes parametric design, greatly enhancing the system's versatility and user-friendliness. Users can flexibly select input bit width, endianness (big-endian or little-endian), and data grouping mode (512 or 1024) according to their needs. This parametric design not only meets diverse requirements in different application scenarios but also simplifies system configuration and development processes, improving development efficiency. Users do not need to make large-scale hardware modifications; they can achieve customized functions simply through parameter settings, reducing development costs and time. In terms of data processing, this invention adopts a segmentation strategy, where data is first segmented and then concatenated. The core of this design lies in directly utilizing registers to complete data concatenation, rather than relying on traditional FIFO buffers. In this way, this invention avoids the additional resource overhead of FIFOs, significantly reducing hardware resource consumption. Meanwhile, the use of registers ensures the efficiency and accuracy of data concatenation, enabling rapid data storage and retrieval operations. This design is particularly suitable for resource-constrained scenarios, such as platforms with limited hardware resources like FPGAs, effectively optimizing resource utilization and improving overall system performance. Attached Figure Description

[0019] Figure 1 This is a diagram of the padding format for a block length of 512 in the hash algorithm workflow; Figure 2 This is a diagram of the padding format for a block length of 1024 in the hash algorithm workflow; Figure 3 This is a diagram of the SM3 message extension structure in the hash algorithm workflow; Figure 4 This is a diagram of the SM3 compression function in the hash algorithm workflow; Figure 5 A schematic diagram of a module for filling IP cores with hash algorithm data based on an FPGA according to one embodiment; Figure 6 A flowchart illustrating the module workflow for filling an IP core with data using an FPGA-based hash algorithm, as described in one embodiment. Figure 7 This is a schematic diagram of a little-endian structure in one embodiment; Figure 8 This is a schematic diagram of a big-endian structure in one embodiment; Figure 9 Here is a diagram of the end-order conversion module structure for one embodiment; Figure 10 This is a structural diagram of a bit-width conversion module according to one embodiment; Figure 11 This is a structural diagram of a message processing module in one embodiment. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0021] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] refer to Figure 5 As shown, Figure 5 A schematic diagram of a module for filling IP cores with hash algorithm data based on an FPGA in one embodiment.

[0023] An FPGA-based hash algorithm data filling IP core includes: an end-to-end conversion module, a bit-width conversion module, a message processing module, a splicing module, and a FIFO module; The end-to-end conversion module is used to: perform end-to-end conversion on the data input to the end-to-end conversion module; The bit width conversion module is used to: perform operations on the data input to the bit width conversion module to convert large bit width to small bit width, or small bit width to large bit width; The message processing module is used to: perform byte statistics on the data input to the message processing module, and fill the last byte of the data input to the message processing module based on the result of the byte statistics and a preset grouping mode; The splicing module is used to: splice the data input to the splicing module into a preset bit width; The end-to-end conversion module receives user input data, performs end-to-end conversion on it, and then stores the end-to-end converted user input data into the FIFO module. The bit-width conversion module reads the end-to-end converted user input data from the FIFO module, performs bit-width conversion on it, and then stores the bit-width converted user input data into the FIFO module. The message processing module reads the bit-width converted user input data from the FIFO module, performs a padding operation on the last data segment of the bit-width converted user input data, and then stores the padded user input data into the FIFO module. The splicing module reads the padded user input data from the FIFO module, performs a splicing operation on it, and then stores the spliced ​​user input data into the FIFO module.

[0024] In one embodiment, such as Figure 6 As shown, the FPGA adopts distributed control, with a clear top-level design and defined individual... The module's functions and top-level signals are shown in Table 1: Table 1 Top-level signal list In one embodiment, such as Figure 7 As shown, if the user-side data is little-endian, the endianness conversion module will not process the data and will pass it through to the subsequent bit-width conversion module. If the user-side data is big-endian, the endianness conversion module will convert the big-endian data to little-endian and send it to the subsequent bit-width conversion module. The bit-width conversion module will convert the user-side bit width into a 64-bit output. If the user-side bit width is 128 bits, the bit-width conversion module will divide the bit width from the original 128 bits into two 64-bit outputs. The message processing module receives the message from the bit-width conversion module and performs corresponding padding according to the grouping mode setting (512 or 1024). It should be noted that the message processing output is 64 bits. The processed message will be transmitted to the concatenation module, which will concatenate the input message into 512 bits or 1024 bits for output. The specific number of bits depends on the grouping mode configured by the user.

[0025] like Figure 8 The diagram shown illustrates a big-endian data structure for one embodiment. `s_axis_tdata` identifies the input data, and `s_axis_tkeep` indicates whether the corresponding bit of the input data is valid. Figure 8In the first group of data, there is a 32-bit hexadecimal number 12345678, of which 4 bytes are valid data. The second group of data is also a 32-bit hexadecimal number with the value abcdef12. Since s_axis_tkeep is 1110, 1 indicates that the corresponding byte is valid and 0 indicates that the corresponding byte is invalid. Therefore, the valid data in the second group of data is abcdef.

[0026] In one embodiment, the bit-width conversion module includes: a first register module; the first register module is used to: cache temporary data when converting the input data to the bit-width conversion module from small bit-width to large bit-width; The splicing module includes a second register module; the second register module is used to cache temporary data when splicing the data input to the splicing module.

[0027] In one embodiment, the end-to-end conversion module includes: a first input bit width setting parameter and an input data end-to-end identifier parameter; The first input bit width setting parameter is used to: set the bit width of the input data to the end-to-end conversion module based on the data of the input end-to-end conversion module; The input data end-order identifier parameter is used to: set the end-order format of the input end-order conversion module based on the data of the input end-order conversion module.

[0028] In one embodiment, the bit width conversion module further includes: a second input bit width setting parameter and a first output bit width setting parameter; The second input bit width setting parameter is used to: set the bit width of the input data to the bit width conversion module; The first output bit width setting parameter is used to: set the bit width of the output bit width conversion module data.

[0029] In one embodiment, the message processing module includes two byte modes: a 512-byte mode and a 1024-byte mode. The message processing module has an input and output bit width of 64 bits.

[0030] In one embodiment, the splicing module includes two grouping modes: a 512-bit mode and a 1024-bit mode.

[0031] In one embodiment, the specific process of converting the data input to the bit-width conversion module from large bit-width to small bit-width includes: the bit-width conversion module converts the large bit-width data into several small bit-width data; the bit-width conversion module then inputs the several small bit-width data into the FIFO module one by one; The specific process of converting the input data of the bit-width conversion module from small bit-width to large bit-width includes: the bit-width conversion module stores several small bit-width data into the first register module one by one; the bit-width conversion module concatenates several small bit-width data in the first register module into large bit-width data, and then stores the large bit-width data into the FIFO module.

[0032] In one embodiment, the specific process of concatenating the data input to the concatenation module into a preset bit width includes: the concatenation module storing several pieces of data input to the concatenation module into the second register module one by one; the concatenation module performing a concatenation operation on several pieces of data stored in the second register module based on the preset grouping mode, and obtaining data with a corresponding bit width; and the concatenation module storing the data with the corresponding bit width into the FIFO module.

[0033] In one embodiment, the AXI4 stream interface is used as the data transmission interface between the modules.

[0034] In one embodiment, the endianness conversion module supports parameterized design to meet the needs of different users. The input bit width of the endianness conversion module can be parameterized, allowing users to select an appropriate bit width according to their actual needs, thereby improving the module's versatility and flexibility. Simultaneously, the parameterized endianness design allows users to explicitly identify the endianness of the input data, supporting both big-endian and little-endian formats. In this way, the module can automatically complete the endianness conversion of data according to the endianness requirements on the user side, ensuring correct data transmission and processing across different data bit widths.

[0035] In one embodiment, parameterization of input and output bit widths is supported. The bit width conversion module internally contains two logics: large bit width to small bit width and small bit width to large bit width. Users can flexibly set the input and output bit widths according to their needs, and the module automatically completes the corresponding bit width conversion. When converting from large to small bit width, it is achieved through segmented transmission; for example, when converting 64 bits to 32 bits, the lower 32 bits are transmitted first, followed by the higher 32 bits, divided into two segments for transmission. When converting from small to large bit width, it is completed through FIFO buffering and concatenation. In one embodiment, the message processing module employs a parameterized design, supporting two grouping modes: 512 bytes and 1024 bytes. The module performs byte counting on the input data and processes the last data segment according to the set grouping mode. The module fills in "1"s and "0"s according to the data length until the group size is reached, appending the actual data length information after padding. When data enters the module, it automatically counts internally. After data transmission, the module pads according to the selected grouping length (512 or 1024). If 320 bytes are transmitted and the grouping length parameter is 512, the number of zeros padded will be calculated. It is important to note that both the module's input and output are 64 bits wide.

[0036] In one embodiment, the present invention is implemented based on an FPGA in a programmable device, and the hardware description language or hardware design language used is Verilog HDL. The specific implementation process is as follows: First, assume the user-side input width is 128 bits and the endianness is little-endian. In this case, the relevant parameters of the endianness conversion module need to be set, specifically setting the data width to 128 bits and the endianness to little-endian. When the input of the endianness conversion module is ready to receive data, its `s_axis_tready` signal will be pulled high. At this time, if the user-side data valid signal `s_axis_tvalid` is also pulled high simultaneously, indicating that the user side has data ready to send and the endianness conversion module is also ready to receive data, then the endianness conversion module will begin working. It will receive the 128-bit little-endian data from the user side and convert it to big-endian. After the conversion is complete, the module writes the converted data into its internal FIFO module. Figure 9 As shown, as data is continuously written to the FIFO module, when the FIFO module reaches full capacity, the s_axis_tready signal is pulled low. This indicates that the end-to-end conversion module will no longer receive new data from the user side. At this time, the user side needs to pause data transmission until the data in the FIFO module is retrieved by a subsequent module. Once the data in the FIFO module is read and processed, the s_axis_tready signal will go high again, and the end-to-end conversion module will resume receiving data and continue end-to-end conversion and data writing to the FIFO module. In this way, the end-to-end conversion module can efficiently process user-side data, ensuring the correctness and integrity of data during transmission.

[0037] The input and output bit widths of the bit-width conversion module are set to 128 bits and 64 bits, respectively. Since the input bit width is greater than the output bit width, the conversion module automatically enables the large-to-small bit-width conversion logic based on the parameter configuration. Specifically, the conversion module divides the 128-bit input data into two 64-bit data segments. Within two consecutive clock cycles, these two 64-bit data segments are output sequentially and written into the internal first register module, as shown in the specific structure below. Figure 10 As shown in the diagram. This design ensures the integrity and accuracy of data during bit-width conversion through time-sharing processing, while utilizing the first register module to solve the problem of input / output bit-width mismatch, thus improving the efficiency and flexibility of data transmission.

[0038] The message processing module's grouping mode is set to 512 bytes. When the s_axis_tready signal goes high, the message processing module begins receiving data from the bit-width conversion module. For data that is not in the last frame, the message processing module directly passes it through to the FIFO module. When the last frame of data is detected (i.e., s_axis_tlast goes high), the keep_num module inside the module counts the number of "1"s in the s_axis_tkeep signal to determine the position of the valid byte in the last frame of data. Subsequently, according to the grouping mode, the module processes the last frame of data according to the preset hash algorithm data filling rules. The specific structure of the message processing module is as follows: Figure 11 As shown. If the grouping mode is 512 bytes, then according to... Figure 1 Data is filled according to the rules shown; if the grouping mode is set to 1024 bytes, then according to... Figure 2 The padding rules are shown below. These rules involve adding 1s and several zeros to the end of the data to ensure it conforms to the packet requirements. This design ensures data integrity and consistency during transmission while supporting flexible packet modes, commonly 512-bit and 1024-bit, to meet the needs of different application scenarios.

[0039] The grouping mode of the splicing module is set to 512 bits. Since the message processing module identifies all valid bytes on the data bus as 1 after processing the data (meaning the last data iteration was valid), it removes the keep signal from the valid byte list. This means the splicing module receives data that no longer contains keep signals, only valid data. Based on the grouping mode parameters, the splicing module generates a second register with a width of 512 bits. This register temporarily stores 64 bits of input data from the message processing module for splicing. Specifically, the splicing module needs to receive 8 sets of 64-bit data to splice a complete 512-bit message. During splicing, the s_axis_tready signal output by the splicing module is pulled high whenever it is ready to receive data. When the message processing module detects s_axis_tready going high, it sends 64 bits of data and pulls s_axis_tvalid high. After receiving the 64 bits of data, the splicing module stores it in the 512-bit register and waits for the next data iteration. Once the register has received eight data entries, signifying the completion of a full 512-bit message, the concatenation module pulls `s_axis_tready` low, indicating that it will no longer receive new data. At this point, the concatenation module passes the 512-bit message to subsequent modules. Once the 512-bit message has been successfully transmitted, the concatenation module pulls `s_axis_tready` high again to continue receiving and concatenating new data. In this way, the concatenation module can efficiently complete the data concatenation task while avoiding the use of a FIFO buffer, thus significantly reducing resource consumption.

[0040] In one embodiment, the data padding portion of the Chinese national cryptographic algorithm SM3 is taken as the specific object of analysis. First, the top-level signal of SM3 data padding is identified, as shown in Table 2: Table 2 SM3 Data Fill Top Layer Signal List The end-to-end conversion module changes its bit width parameter, setting its input bit width to 128 bits. Assuming the input signal... If the endianness is little-endian, then set the endianness parameter of the endianness module to little-endian; The bit width conversion module changes the bit width parameters, setting its input bit width to 128 bits and its output bit width to 64 bits; The message processing module has a fixed input width of 64 bits; the module mode parameter is set to 512 groups. The splicing module is set to a 512-bit grouping mode. In this case, the output 64 bits will be spliced ​​into 512 bits and then output to the subsequent compression iteration function for processing.

[0041] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0042] It should be noted that the terms "first," "second," and "third" used in the embodiments of this application are merely to distinguish similar objects and do not represent a specific order of objects. It is understood that "first," "second," and "third" can be interchanged in a specific order or sequence where permitted. It should be understood that the objects distinguished by "first," "second," and "third" can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in an order other than those illustrated or described herein.

[0043] The terms "comprising" and "having," and any variations thereof, in this application are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product, or device that includes a series of steps or modules is not limited to the steps or modules listed, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to such processes, methods, products, or devices.

[0044] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A hash algorithm data filling IP core based on FPGA, characterized in that, include: Ending order conversion module, bit width conversion module, message processing module, splicing module, and FIFO module; The end-to-end conversion module is used to: perform end-to-end conversion on the data input to the end-to-end conversion module; The bit width conversion module is used to: perform operations on the data input to the bit width conversion module to convert large bit width to small bit width, or small bit width to large bit width; The message processing module is used to: perform byte statistics on the data input to the message processing module, and fill the last byte of the data input to the message processing module based on the result of the byte statistics and a preset grouping mode; The splicing module is used to: splice the data input to the splicing module into a preset bit width; The end-to-end conversion module accepts user input data, performs end-to-end conversion on it, and then stores the end-to-end converted user input data into the FIFO module; the bit-width conversion module reads the end-to-end converted user input data from the FIFO module, performs bit-width conversion on it, and then stores the bit-width converted user input data into the FIFO module; the message processing module reads the bit-width converted user input data from the FIFO module, performs a padding operation on the last data of the bit-width converted user input data, and then stores the padded user input data into the FIFO module. The splicing module reads the user input data after the filling operation from the FIFO module, performs a splicing operation on it, and then stores the spliced ​​user input data into the FIFO module.

2. The FPGA-based hash algorithm data filling IP core according to claim 1, characterized in that, The bit-width conversion module includes: a first register module; the first register module is used to: cache temporary data when converting the input data to the bit-width conversion module from a small bit-width to a large bit-width; The splicing module includes a second register module; the second register module is used to cache temporary data when splicing the data input to the splicing module.

3. The FPGA-based hash algorithm data filling IP core according to claim 2, characterized in that, The end-to-end conversion module includes: a first input bit width setting parameter and an input data end-to-end identifier parameter; The first input bit width setting parameter is used to: set the bit width of the input data to the end-to-end conversion module based on the data of the input end-to-end conversion module; The input data end-order identifier parameter is used to: set the end-order format of the input end-order conversion module based on the data of the input end-order conversion module.

4. The FPGA-based hash algorithm data filling IP core according to claim 3, characterized in that, The bit width conversion module further includes: a second input bit width setting parameter and a first output bit width setting parameter; The second input bit width setting parameter is used to: set the bit width of the input data to the bit width conversion module; The first output bit width setting parameter is used to: set the bit width of the output bit width conversion module data.

5. The FPGA-based hash algorithm data filling IP core according to claim 4, characterized in that, The message processing module includes two byte modes: 512-byte mode and 1024-byte mode; The input and output bit widths of the message processing module are both 64 bits.

6. The FPGA-based hash algorithm data filling IP core according to claim 5, characterized in that, The splicing module includes two grouping modes: 512-bit mode and 1024-bit mode.

7. The FPGA-based hash algorithm data filling IP core according to claim 6, characterized in that, The specific process of converting large-bit-width data to small-bit-width data input to the bit-width conversion module includes: the bit-width conversion module converts the large-bit-width data into several small-bit-width data; the bit-width conversion module then inputs the several small-bit-width data into the FIFO module one by one; The specific process of converting the input data of the bit-width conversion module from small bit-width to large bit-width includes: the bit-width conversion module stores several small bit-width data into the first register module one by one; the bit-width conversion module concatenates several small bit-width data in the first register module into large bit-width data, and then stores the large bit-width data into the FIFO module.

8. The FPGA-based hash algorithm data filling IP core according to claim 7, characterized in that, The specific process of concatenating the data input to the concatenation module into a preset bit width includes: the concatenation module storing several pieces of data input to the concatenation module into the second register module one by one; the concatenation module performing a concatenation operation on several pieces of data stored in the second register module based on the preset grouping mode, and obtaining data with the corresponding bit width; and the concatenation module storing the data with the corresponding bit width into the FIFO module.

9. The FPGA-based hash algorithm data filling IP core according to claim 8, characterized in that, The AXI4 stream interface is used as the data transmission interface between the modules.

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