Power control system and system-on-chip device comprising the same

Abstract

The present invention relates to a power control system and a system-on-chip device including the same, which controls power of a plurality of power domains constituting the system-on-chip device by performing power control decisions at a software level and power control execution at a hardware level in parallel. The power control system according to the present invention includes a central processor configured to make decisions on power-up or power-down of at least one target power domain among a plurality of power domains included in the system-on-chip device, and transmit at least one domain power control command among a domain power-up command and a domain power-down command based on the domain power-up / power-down decisions, and a domain power manager configured to receive the domain power control command and execute at least one of a power-up sequence and a power-down sequence for the target power domain.

Description

Technical Field

[0001] This invention relates to power control of a system-on-a-chip (SoC), and more specifically, to a power control system and an SoC including the system, which controls the power of multiple power domains constituting the SoC by executing software-level power control decisions and hardware-level power control execution in parallel. Background Technology

[0002] A System-on-Chip (SoC) is a technology that integrates various functional blocks, such as a Central Processing Unit (CPU), memory, interface, digital signal processing circuitry, and analog signal processing circuitry, into a single semiconductor integrated circuit to realize a computer system or other electronic system, or an integrated circuit (IC) integrated based on this technology. Currently, SoCs are evolving into more complex systems that incorporate various functional blocks such as processors, multimedia, graphics, interfaces, and security.

[0003] A SoC requires a power management unit for the proper management of SoC power consumption. This power management unit may include a power controller for performing power-on / power-off sequences for each power domain.

[0004] Power control for each power domain of the SoC employs either hardware-based or software-based power control. Hardware-based power control refers to controlling the power domain's power at the hardware level within the SoC without software intervention. Software-based power control refers to controlling the power domain's power through software within the SoC. Here, software refers to the operating system (OS), firmware, device drivers, applications, etc., while hardware can refer to the next level down.

[0005] As a typical example of hardware-based power control, there is power control that employs state machines. Traditional hardware-based power controllers are designed as fixed sequencers that execute predetermined sequences based on state machines. State machines have the advantages of simplicity and speed, but on the other hand, they have the disadvantage of reduced flexibility because they only execute predetermined sequences.

[0006] In recent years, as SoCs have become increasingly complex, the power-on / power-off sequences of various power domains have also become very complex. As a result, various abnormal cases may occur after SoC design and during actual silicon chip fabrication (Fab-out). When these abnormal cases occur, the power-on / power-off sequences need to be changed. However, state machines designed to operate with traditional fixed sequencers have the problem of not being able to flexibly handle various abnormal cases.

[0007] Therefore, software-based power control has been the primary approach adopted in recent years. In software-based power control, a central processing unit (CPU) is used to design the power controller, primarily employing the commercially available MCU (Micro Processing Unit) Cortex-M developed by ARM Holdings. The CPU sends power control signals to various power domains at the software level to execute power control.

[0008] Because commercial MCUs are expensive, matching and deploying separate power controllers for each individual power domain would significantly increase the price of the system-on-chip. Therefore, it is designed with a single CPU performing power-on / power-down sequences for multiple power domains. Since the CPU performs software-based power control, it offers greater flexibility in adapting to post-fab-out anomalies; however, because a single CPU can only sequentially control one power domain at a time, it introduces a problem of increased latency.

[0009] Furthermore, the CPU itself consumes a significant amount of power, yet it cannot power down due to the need for power control within its own power domain. In extreme cases, this can be ironically problematic: to control a power domain with a power consumption of only 0.1mW, a CPU with a power consumption of 1000mW might be required. Moreover, since there's no way to power up the SoC if the CPU powers down, the CPU cannot power down on its own. Considering that approximately 60% of the SoC's total power consumption is used to power the CPU, and about 40% is consumed by other power domains, the CPU can only control approximately 40% of the SoC's total power consumption.

[0010] A System-on-a-Chip (SoC) can be divided into a computing area that performs computations or operations, and a non-computing area that presents other functions or elements that do not involve computation or operations. The computing area contains components related to program execution, data processing, and computational operations, such as the Central Processing Unit (CPU), Graphics Processing Unit (GPU), and computing accelerators. The non-computing area includes various functions such as communication interfaces, sensor interfaces, power management and battery management, audio and video interfaces, input / output interfaces, security elements, and clock and timing circuits. The CPU, located in the computing area, has difficulty performing power control on non-computing components. Furthermore, because the CPU performs non-real-time operations, it is difficult to control the power of real-time peripheral devices (such as audio, displays, modems, cameras, and sensors) in real time.

[0011] Existing patent literature (Patent Document 001) Korean Patent Registration No. 10-1861743 (Patent Document 002) Korean Patent Registration No. 10-1835615 Detailed description of the invention Technical issues The purpose of this invention is to provide a power control system that makes power control decisions at the software level and executes power control at the hardware level, with both actions occurring in parallel to control the power of multiple power domains constituting a system-on-a-chip.

[0012] Another object of the present invention is to provide a system-on-a-chip device, the device comprising a power control decision unit operating at the software level and a power control execution unit operating at the hardware level.

[0013] Technical solutions The power control system according to the present invention includes: a central processing unit, which makes a decision on powering on or off at least one of a plurality of power domains included in a system-on-a-chip device, and sends at least one of a domain power control command, namely a domain power-on command and a domain power-off command, based on the domain power-on / power-off decision; and a domain power manager, which receives the domain power control command and executes at least one of a power-on sequence and a power-off sequence on the controlled object power domain.

[0014] Preferably, the central processing unit makes a decision on powering on or off the system, which includes at least a portion of multiple power domains, and sends at least one system power control command, either a system power-on command or a system power-off command, based on the system power-on / power-off decision. The power control system further includes a root power manager, which receives the system power control command and executes at least one power-on sequence or power-off sequence on the domain power managers.

[0015] Preferably, the power management system further includes a memory storing at least one instruction required by the domain power manager to execute domain power control commands, and at least one instruction required by the root power manager to execute system power control commands.

[0016] More preferably, the domain power manager includes: a processing unit that receives domain power control commands from a central processing unit and accesses a memory storing at least one instruction required to execute the domain power control commands, so as to execute at least one instruction stored in the memory; and a register group that changes the value of at least one register field through the processing unit, thereby sending power control signals to the controlled power domain.

[0017] More preferably, the domain power manager also includes a power manager interface that receives signals from the power domain of the controlled object to change the values ​​of specific register fields in the register set.

[0018] More preferably, the root power manager includes: a processing unit that receives system power control commands from the central processing unit, accesses a memory storing at least one instruction for executing the system power control commands, and executes at least one instruction stored in the memory; and a register set that sends power control signals to the domain power manager by changing the value of at least one register field through the processing unit.

[0019] More preferably, the root power manager also includes a power manager interface that receives signals from the domain power manager to change the value of a specific register field in the register set.

[0020] More preferably, the instructions include instructions for changing the value of a specific register field in the register set.

[0021] More preferably, the instructions also include instructions to wait until the value of a specific register field in the register set changes.

[0022] More preferably, the instructions also include instructions to wait for a specific period of time.

[0023] More preferably, the instructions further include at least one of the following: an instruction to write the value of the internal register of the processing unit to a specific register field of the register group; an instruction to write the value of a specific register field of the register group to the internal register of the processing unit; and an instruction to write a user-input constant value to the internal register of the processing unit.

[0024] More preferably, the instructions also include instructions for determining the execution order of the instructions stored in the memory.

[0025] More preferably, the domain power manager is configured in the non-power gating area of ​​the power domain of the controlled object.

[0026] More preferably, the domain power manager and the root power manager are configured in a normally open domain.

[0027] More preferably, the power domain of the controlled object is the central processing unit.

[0028] The system-on-a-chip device according to the present invention includes: a plurality of power domains; a first subsystem including at least a portion of the plurality of power domains; and a second subsystem including at least another portion of the plurality of power domains. The system-on-a-chip (SoC) includes: a central processing unit (CPU) that makes decisions on power-on or power-off of at least one first controlled object power domain among a plurality of power domains included in a first subsystem, and sends a first domain power control command based on the power domain power-on / power-off decision; a CPU that makes decisions on power-on or power-off of at least one second controlled object power domain among a plurality of power domains included in a second subsystem, and sends a second domain power control command based on the power domain power-on / power-off decision; a CPU that makes decisions on power-on or power-off of the first subsystem, and sends a first system power control command based on the first subsystem power-on / power-off decision; a CPU that makes decisions on power-on or power-off of the second subsystem, and sends a second system power control command based on the second subsystem power-on / power-off decision; a first power management unit that receives the first domain power control command and the first system power control command, and performs power control on the plurality of power domains included in the first subsystem; and a second power management unit that receives the second domain power control command and the second system power control command, and performs power control on the plurality of power domains included in the second subsystem.

[0029] Preferably, the first power management unit includes: a domain power manager that receives a first domain power control command and executes at least one of a power-on sequence and a power-off sequence on a first controlled object power domain; a root power manager that receives a first system power control command and executes at least one of a power-on sequence and a power-off sequence on the domain power manager; and a memory that stores at least one instruction required by the domain power manager to execute the first domain power control command and at least one instruction required by the root power manager to execute the first system power control command.

[0030] Preferably, the second power management unit includes: a domain power manager that receives a second domain power control command and executes at least one of a power-on sequence and a power-off sequence on the second controlled object power domain; a root power manager that receives a second system power control command and executes at least one of a power-on sequence and a power-off sequence on the domain power manager; and a memory that stores at least one instruction required by the domain power manager to execute the second domain power control command, and at least one instruction required by the root power manager to execute the second system power control command.

[0031] More preferably, the domain power manager includes: a processing unit that receives domain power control commands from a central processing unit and accesses memory to execute at least one instruction required to execute the received domain power control commands; and a register set that, through the processing unit, modifies the values ​​of at least one register field to send power control signals to the controlled power domain.

[0032] More preferably, the root power manager includes: a processing unit that receives system power control commands from the central processing unit and accesses memory to execute at least one instruction required to execute the received system power control commands; and a register set that sends power control signals to the domain power controller by changing the values ​​of at least one register field through the processing unit.

[0033] More preferably, the domain power manager and the root power manager are configured in a normally open domain.

[0034] More preferably, at least one of the multiple power domains is a central processing unit.

[0035] More preferably, at least one of the multiple power domains is a real-time peripheral device.

[0036] Invention Effects According to the present invention, the following effects can be achieved.

[0037] The present invention can provide a power control system that implements a power control decision unit running at the software level through a central processing unit and configures a programmable sequencer for a power control execution unit running at the hardware level, thereby enabling software-based power control and hardware-based power control to run in parallel.

[0038] This invention implements a power controller for power control in the power domain as a programmable sequencer that operates at the hardware level and can change the power-on / power-off sequence, thereby flexibly addressing defects discovered after fabrication (Fab-out).

[0039] This invention utilizes a microprocessor unit to implement a programmable sequencer, thereby shortening the operation delay time of the power domain and the idle state entry time of the programmable sequencer, thus improving the speed of the system-on-chip device and reducing power consumption.

[0040] This invention employs a programmable sequencer designed individually for each power domain for power control, thus enabling efficient and rapid control of each power domain.

[0041] This invention utilizes a programmable sequencer running at the hardware level to control the power supply of the upper-level central processing unit (CPU) running at the software level, thereby enabling the CPU to be powered on / off and significantly reducing SoC power consumption.

[0042] This invention can match a separate programmable sequencer to each real-time peripheral device to control the power supply of the real-time peripheral device, thereby enabling real-time control of the power supply of each real-time peripheral device.

[0043] The effects of this invention are not limited to those mentioned above. Those skilled in the art to which this invention pertains (referred to as "ordinary skill persons") can clearly understand other effects not mentioned in the claims. Attached Figure Description

[0044] Embodiments of the present invention will be described with reference to the accompanying drawings, wherein similar reference numerals denote similar elements, but are not limited thereto.

[0045] Figure 1 is a structural diagram of a system-on-a-chip device according to an embodiment of the present invention; Figure 2 is a structural diagram of a domain power manager according to an embodiment of the present invention; Figure 3 is a power state transition diagram of the power domain of the present invention; Figure 4 is an example diagram of the power-on sequence and power-off sequence executed by the domain power manager of the present invention; Figure 5 is a structural diagram of a root power manager according to an embodiment of the present invention; Figure 6 is a structural diagram of a system-on-a-chip device according to another embodiment of the present invention.

[0046] Embodiments of the present invention will be described with reference to the accompanying drawings described below, wherein similar reference numerals denote elements, but are not limited thereto.

[0047] Symbol Explanation 100: System-on-Chip (SoC) 110: Central Processing Unit (CPU) 120: Power Management Unit (PMU) 130, 140: Power Domain (PD) 121: Power Management for Root (PMR) 122, 123, 124: Domain Power Manager (PMD) 125: Memory 126: Internal Bus Detailed Implementation The specific implementation of the present invention will now be described in detail with reference to the accompanying drawings. However, in the following description, specific descriptions of well-known functions or configurations will be omitted if there is any possibility of unnecessarily obscuring the spirit of the present invention.

[0048] In the accompanying drawings, the same or corresponding components are given the same reference numerals. Furthermore, in the following description of embodiments, repeated descriptions of the same or corresponding components may be omitted. However, even if a description of a component is omitted, it is not intended that such component is not included in any embodiment.

[0049] The advantages and features of the embodiments disclosed in this specification, as well as the methods for achieving these advantages and features, will become apparent from the following embodiments in conjunction with the accompanying drawings. However, the invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. These embodiments are provided merely to fully inform those skilled in the art of the scope of the invention.

[0050] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the meaning that would be commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, unless explicitly defined otherwise, terms as defined in common dictionaries shall not be idealized or over-interpreted.

[0051] For example, the term "technology" can refer to systems, methods, computer-readable instructions, modules, algorithms, hardware logic, and / or operations permitted by the context and described in the overall documentation.

[0052] In this specification, the singular includes the plural unless the context explicitly indicates that it is singular. Furthermore, plural expressions include singular expressions unless the context explicitly indicates that they are plural. Throughout this specification, when a part is described as including a constituent element, it means, unless otherwise expressly stated to the contrary, that other constituent elements are not excluded, but may be further included.

[0053] In this invention, the terms "comprising," "including," etc., may be used to indicate the presence of features, steps, operations, elements, and / or constituent elements, but these terms do not preclude the addition of one or more other functions, steps, operations, elements, constituent elements, and / or combinations thereof.

[0054] In this invention, when referring to a specific constituent element being "combined," "connected," "associated," or "reacted" with any other constituent element, the specific constituent element may be directly combined, combined, connected, and / or associated with or reacted with another constituent element, but is not limited thereto. For example, one or more intermediate constituent elements may exist between the specific constituent element and other constituent elements. Furthermore, in this invention, "and / or" may include each of one or more of the listed items, or a combination of at least a portion of one or more of them.

[0055] In this invention, the terms "first," "second," etc., are used to distinguish a specific constituent element from other constituent elements, but these terms do not limit the aforementioned constituent elements. For example, a "first" constituent element can be used to refer to an element that is the same as or similar in form to a "second" constituent element.

[0056] Figure 1 is a structural diagram of a system-on-a-chip device (100) according to an embodiment of the present invention.

[0057] The system-on-a-chip device (100) according to the present invention refers to a device having a fully driven product and system in an integrated circuit, which can be implemented as a chip, module or system, etc.

[0058] The system-on-a-chip device (100) according to the present invention includes a power control decision unit operating at the software level and a power control execution unit operating at the hardware level under the control of the power control decision unit to perform power control on at least one power domain (PD).

[0059] The power control decision unit may include a central processing unit (CPU) (110) that controls the power control execution unit at the software level. The power control execution unit may include a power management unit (PMU) (120) that executes power-on / power-off sequences for at least one or more power domains under the control of the central processing unit (110).

[0060] The central processing unit (110) controls the power management unit (120) at the software level and may be a power domain (110) constituting the system-on-chip device. Therefore, in this specification, the reference numeral "110" is named as the central processing unit (110) when it is used to control the power control decision unit of the power management unit (120) to perform its function; and as a power domain (110) when it refers to one of the power domains.

[0061] The central processing unit (110) makes a decision at the software level on whether to perform power-on / power-off on the on-chip system device, the subsystem consisting of multiple power domains and individual power domains, and outputs system power-on / power-off commands and domain power-on / power-off commands to the power management unit (120) based on the decision.

[0062] The power management unit (120) can correspond to at least one power domain (110, 130, 140) and execute a power-on / power-off sequence. Each power domain (110, 130, 140) can handle the power-on / power-off sequence and switch to a power-on or power-off state. The system-on-chip device may include at least one power management unit (120).

[0063] A power domain may include a core domain containing a central processing unit (110), a storage domain containing a memory subsystem such as main memory or cache, a graphics and video domain containing multimedia elements such as graphics processing devices or video encoding / decoding devices, and an input / output domain containing input / output interface elements for external communication. Each power domain may contain lower-level sub-power domains, and at least two power domains may be combined into a subsystem.

[0064] The power management unit (120) corresponds to each power domain (110, 130, 140) and may include: at least one domain power manager (PMD) (122, 123, 124) for power control of the corresponding power domain (110, 130, 140); a root power manager (PMR) (121) for managing at least one domain power manager (122, 123, 124); and a memory (125) for storing programs for operating the root power manager (121) and at least one domain power manager (122, 123, 124). At least one domain power manager (122, 123, 124), the root power manager (121), and the memory (125) can be interconnected via an internal bus (126). The programs stored in the memory (125) may contain instructions and data.

[0065] The root power manager (121) and the domain power managers (122, 123, 124) can be implemented as programmable sequencers that run at the hardware level.

[0066] The root power manager (121) can receive system power-on / power-off commands from the central processing unit (110). System power-on / power-off commands may include power-on / power-off commands for on-chip system devices and power-on / power-off commands for subsystems composed of more than one power domain. In this invention, power-on / power-off commands for on-chip system devices and power-on / power-off commands for subsystems are collectively referred to as system power-on / power-off commands.

[0067] When the root power manager (121) receives a system power-on / power-off command from the central processing unit (110), it will control at least one or more domain power managers (122, 123, 124) based on the instructions and data required to execute the command, thereby enabling the startup / shutdown of the system-on-chip device (100) or a subsystem consisting of multiple power domains.

[0068] Furthermore, when the root power manager (121) starts the system-on-chip device, it runs at least one or more domain power managers (122, 123, 124) based on the instructions and data required for startup to perform the startup of the system-on-chip device (100). The root power manager (121) can also run at the hardware level when starting the system-on-chip device without commands from the central processing unit (110).

[0069] When at least one or more domain power managers (122, 123, 124) receive a domain power-on / power-off command from the central processing unit (110) for power control of an individual power domain, they will perform power-on / power-off sequence control on the corresponding power domain based on the instructions and data required to execute the command.

[0070] The first domain power manager (122) outputs a power control signal to the power domain (110), which is the central processing unit (110), and executes the power-on / power-off sequence; the second domain power manager (123) outputs a power control signal to the first power domain (130) and executes the power-on / power-off sequence; the third domain power manager (124) outputs a power control signal to the second power domain (140) and executes the power-on / power-off sequence.

[0071] The present invention includes a first domain power manager (122) for power control of a central processing unit (110) to enable the central processing unit (110) to switch to a power-down state, thereby reducing the power consumption of the on-chip system device. Furthermore, separate domain power managers (122, 123, 124) can be matched to each power domain (110, 130, 140), allowing power control of each power domain (110, 130, 140) to be performed in parallel, thus enabling efficient and fast processing.

[0072] The root power manager (121), the first domain power manager (122), the second domain power manager (123), and the third domain power manager (124) can each be implemented as the programmable sequencer of the present invention.

[0073] The memory (125) can store the instructions and data required by the root power manager (121) to execute system power-on / power-off commands, the instructions and data to be executed when the root power manager (121) starts up, and the instructions and data required by each domain power manager (122, 123, 124) to execute domain power-on / power-off commands. In this case, the memory (125) can be partitioned according to address space and allocate independent address regions to each manager (121, 122, 123, 124). Furthermore, if the same program needs to run in at least two of the multiple managers (121, 122, 123, 124), the multiple managers (121, 122, 123, 124) can share the same address region.

[0074] This embodiment illustrates a system-on-a-chip device consisting of three power domains and three domain power managers. However, the invention is not limited to this. The number of power domains can be designed to vary depending on the complexity of the system-on-a-chip device, and the number of domain power managers can also be changed according to the number of power domains.

[0075] The root power manager (121) and the domain power managers (122, 123, 124) can be programmable sequencers implemented using microprocessor units (MCUs). Commercially available MCUs primarily used in system-on-chip devices include the Cortex-M developed by ARM Holdings, which is a widely applicable commercial MCU. The programmable sequencer of this invention can be implemented using a general-purpose MCU. However, these general-purpose MCUs include unnecessary components for the operation of the programmable sequencer, such as cache, interrupt handlers, arithmetic units, debugger interfaces, and breakpoint units. These unnecessary components lead to a large size and slow operation.

[0076] This invention does not use a general-purpose MCU, but rather preferably designs a dedicated MCU required for operation as a programmable sequencer to constitute the programmable sequencer in this invention.

[0077] Figure 2 is a structural diagram of a domain power manager (210) according to an embodiment of the present invention; The domain power manager (210) can be an embodiment of a programmable sequencer.

[0078] The domain power manager (210) sends power control signals to the power domain (220) and executes the power-on / power-off sequence of the power domain (220), causing the power domain (220) to transition from a power-on state to a power-off state, or from a power-off state to a power-on state. The power control signals required to execute the power-on / power-off sequence may include reset signals, isolation signals, switch control signals, retention signals, etc. These power control signals can be added / deleted / modified according to the power domain (220) specifications.

[0079] The domain power manager (210) shown in Figure 2 can be one of the first domain power manager (122), the second domain power manager (123), and the third domain power manager (124) shown in Figure 1. The power domain (220) shown in Figure 2 can be one of the power domains (110, 130, 140) shown in Figure 1. The central processing unit (110) can store the program containing the instructions and data to be executed by the domain power manager (210) in the memory (125). The central processing unit (110) can modify and store the instructions and data stored in the memory (125). Therefore, the content and order of the instructions executed by the domain power manager (210) may be changed, thus the domain power manager (210) can become a programmable sequencer.

[0080] The central processing unit (110) makes a decision on whether to power on / off the power domain (220) and outputs a domain power-on command or a domain power-off command to the domain power manager (210) based on the decision.

[0081] When the domain power manager (210) receives a domain power-on command or a domain power-off command, it sends a power control signal to the corresponding power domain (220) to execute the power-on sequence or power-off sequence. The power domain (220) processes the corresponding power-on sequence or power-off sequence to enter the power-on state or power-off state.

[0082] The domain power manager (210) includes: a processing unit (211) that receives commands related to power control of the power domain (220), namely domain power-on / power-off commands, from the central processing unit (110), and accesses a memory (125) storing instructions required to execute the commands, and executes the instructions stored in the memory (125); and a register group (212) by which the processing unit (211) changes the value of at least one field to send power control signals to the power domain (220).

[0083] The register group (212) includes multiple register fields corresponding to each power control signal, and sends the values ​​recorded in the register fields as the corresponding power control signals to the power domain (220). For example, the register group (212) includes a register field corresponding to a reset signal, a register field corresponding to an isolation signal, a register field corresponding to a switch control signal, and a register field corresponding to a hold signal, and sends the corresponding power control signal 0 or 1 according to the corresponding register field value (0 or 1).

[0084] The instructions stored in memory (125) include instructions to write a specific register field value of register group (212) to 0 and instructions to write a specific field value of register group (212) to 1. The processing unit (211) can change the specific register field value of register group (212) to 0 or 1 by executing the corresponding instructions. At this time, the corresponding power control signal value can be changed to 0 or 1 and transmitted to the power domain (220).

[0085] The domain power manager (210) may also include a power manager interface (213) that receives signals from the power domain (220) and transmits them to at least one of the processing unit (211) and the register group (212). Power control signals transmitted from the register group (212) to the power domain (220) may be transmitted to the power domain (220) via the power manager interface (213).

[0086] As one embodiment of the domain power manager (210), the domain power manager (210) can be arranged in the non-power gating region of the power domain (220).

[0087] As another embodiment of the domain power manager (210), the domain power manager (210) can be configured together with the root power manager (121), other domain power managers, and memory in an "always-on domain" of the system-on-chip device. In this case, the power manager interface (213) can be configured in a non-power-gated region of the corresponding power domain (220), rather than an always-on domain. When the root power manager and multiple domain power managers are clustered and configured in such an always-on domain of the system-on-chip device, they can share memory and perform power-on / power-off control of the central processing unit and real-time power-on / power-off control of real-time peripherals at the hardware level.

[0088] In power control signals, there are many signals formed through handshakes. For example, after issuing a power switch enable signal, it is necessary to wait until a corresponding feedback signal is received. At this time, the feedback signal output by the power domain is recorded as a specific register field value of register group (212) through the power manager interface (213), and the processing unit (211) waits until the corresponding register field value records the corresponding specific value. For this purpose, the instructions stored in memory (125) may include instructions to wait until the specific register field value of register group (212) becomes 0, and instructions to wait until the specific register field value of register group (212) becomes 1.

[0089] Furthermore, in power control signals, it is sometimes necessary to wait for a certain period of time after sending a signal before performing the next operation. For example, if the power domain (220) is reset and released, it is necessary to wait until the power domain (220) is reset and begins normal operation.

[0090] Therefore, the instructions stored in the memory (125) can include instructions that wait for a specific period of time, and the wait time information can be stored in a specific register field of the register group (212), or the constant value input by the user can be stored in the internal register of the processing unit (211).

[0091] Furthermore, the instructions stored in the memory (125) may include: an instruction to write the internal register value of the processing unit (211) to a specific register field of the register group (212); an instruction to write the value of a specific register field of the register group (212) to the internal register of the processing unit (211); and an instruction to write a user-input constant value to the internal register of the processing unit (211).

[0092] Furthermore, the instructions stored in the memory (125) may include instructions that determine the execution order of the instructions stored in the memory (125), such as instructions that jump to a specific address, instructions that return to a previous address, instructions that move to a specific address based on the result of instruction execution, etc.

[0093] Figure 3 is a power state transition diagram of the power domain of the present invention; Assuming that in the power-on state of the power domain (220), when the reset signal changes from 1 to 0, the isolation signal changes from 0 to 1, and the switch control signal changes from 0 to 1, the corresponding power domain will enter the power-off state. The power control signals that cause the power domain (220) to change from the power-on state to the power-off state are called the power-off sequence. Furthermore, assuming that in the power-off state of the power domain (220), when the switch control signal changes from 1 to 0, the isolation signal changes from 1 to 0, and the reset signal changes from 0 to 1, the power domain will enter the power-on state. The power control signals that cause the power domain (220) to change from the power-off state to the power-on state are called the power-on sequence.

[0094] Figure 4 is an example diagram of the power-on sequence and power-off sequence executed by the domain power manager of the present invention; The domain power manager (210) executes power-on and power-off sequences on the power domain (220), and the power domain (220) can be switched to power-on and power-off states by executing the power-on and power-off sequences.

[0095] The central processing unit (110) stores the instructions required by the domain power manager (210) to control the power of the power domain (220) in the memory (125). After making a decision on whether to power on or power off the power domain (220), it sends a domain power-on command or a domain power-off command to the domain power manager (210).

[0096] When the domain power manager (210) receives a domain power-down command from the central processing unit (110), it reads from memory (125) and executes the instructions required to perform a power-down sequence on the power domain (220). These instructions include instructions to set the value of a specific register field in the register set (212) to 0 or 1, and as shown in FIG4, by executing these instructions, a power-down sequence can be performed on the power domain (220).

[0097] Additionally, when the domain power manager (210) receives a domain power-on command from the central processing unit (110), it reads from memory (125) and executes the instructions required to perform the power-on sequence on the power domain (220), thereby, as Figure 4 As shown, a power-on sequence can be performed on the power domain (220).

[0098] When at least a portion of the power-down sequence and power-up sequence is changed, the central processing unit (110) can modify the instruction execution order and data stored in memory (125). When the instruction execution order and data stored in memory (125) are modified in this way, the domain power manager (210) that subsequently receives a domain power-up command or domain power-down command will execute the power-up / power-down sequence according to the changed instruction execution order and data. In this way, the domain power manager (210) will operate as a programmable sequence.

[0099] In this invention, when a change in the power-down sequence is required, the central processing unit (110) can modify the instruction execution order and data stored in the memory (125). The programmable sequencer according to this invention can flexibly handle various abnormal situations that occur after chip fabrication.

[0100] Figure 5 is a structural diagram of a root power manager (510) according to an embodiment of the present invention.

[0101] The root power manager (510) can be another embodiment of a programmable sequencer.

[0102] The root power manager (510) can be as follows: Figure 1 The root power manager (PMR) shown is (121).

[0103] The central processing unit (110) can store a program containing instructions and data that the root power manager (510) needs to execute into memory (125). The central processing unit (110) can modify and store the program containing instructions and data stored in memory (125). Therefore, the content and order of instructions executed by the root power manager (510) can be changed, thereby the root power manager (510) can operate as a programmable sequencer.

[0104] The central processing unit (110) can make decisions on powering on or off a system-on-chip device or a subsystem consisting of multiple power domains, and send system power-on / power-off commands to the root power manager (510) based on the decisions. These system power-on / power-off commands may include power-on / power-off commands for the system-on-chip device (100), or power-on / power-off commands for any subsystem consisting of multiple power domains.

[0105] The root power manager (510) includes: a processing unit (511) that receives system power-on / power-off commands from the central processing unit (110) and accesses a memory (125) storing instructions required to execute the corresponding commands, to execute the instructions stored in the memory (125); and a register set (712) through which the processing unit (511) modifies at least one or more field values ​​and sends power control signals to at least one or more domain power managers (122, 123, 124). The root power manager (510) may also include a power manager interface (not shown) that receives signals from at least one or more domain power managers (122, 123, 124) and transmits these signals to at least one of the processing unit (511) and the register set (512). The domain power managers (122, 123, 124) may be as follows: Figure 1 The domain power managers shown are (122, 123, 124).

[0106] The memory (125) stores instructions that need to be executed by the root power manager (510) based on the command input from the central processing unit (110). When the root power manager (510) receives a system power-on / power-off command from the central processing unit (510), it will execute the instructions stored in the memory (125) and send power control signals to at least one domain power manager (122, 123, 124) to control the power.

[0107] That is, when the root power manager (510) receives a system power-on / power-off command from the central processing unit (110), it will run at least one or more domain power managers (122, 123, 124) based on the instructions and data required to execute the corresponding command, thereby enabling the system-on-chip device (100) or a subsystem consisting of multiple power domains to perform startup / shutdown.

[0108] After tape-out, situations may arise where it is necessary to change the power-on sequence or power-off sequence of the domain power managers. In such cases, the central processing unit (110) can change the execution order of the instructions and data stored in the memory (125). Subsequently, the root power manager (510) can execute the startup / shutdown sequence of the system-on-chip device (100) or a subsystem composed of multiple power domains in the changed order. Therefore, according to the present invention, various abnormal situations that occur after tape-out can be flexibly addressed.

[0109] Figure 6 is a structural diagram of a system-on-a-chip device (600) according to another embodiment of the present invention.

[0110] The system-on-chip device (600) may include multiple subsystems (610, 620). The first subsystem (610) may be a CPU subsystem containing a central processing unit (611), and may include multiple power domains other than the central processing unit (611), such as an eleventh power domain (612) and a twelfth power domain (613). The second subsystem (620) may be a GPU subsystem containing a graphics processing unit (GPU) or a camera subsystem, and may include multiple power domains, such as a twenty-first power domain (621), a twenty-second power domain (622), and a twenty-third power domain (623). The system-on-chip device (600) may also include multiple subsystems in addition to the two subsystems.

[0111] The system may include power management units (PMUs) (630, 640) that correspond to multiple subsystems (610, 620) and execute power-on / power-off sequences for at least one power domain contained in each subsystem (610, 620). For example, a first power management unit (630) may execute power-on / power-off sequences for each power domain contained in a first subsystem (610), and a second power management unit (640) may execute power-on / power-off sequences for each power domain contained in a second subsystem (620).

[0112] The first power management unit (630) corresponds to the power domains (611, 612, 613) included in the first subsystem (610), and may include: at least one or more domain power managers (632, 633, 634) for power control of the corresponding power domains (611, 612, 613); a root power manager (PMR; PowerManagement for Root) (631) for managing at least one or more domain power managers (632, 633, 634); and a memory (635) for storing the programs required to run the root power manager (631) and at least one or more domain power managers (632, 633, 634). At least one or more domain power managers (632, 633, 634), the root power manager (631), and the memory (635) may be interconnected via an internal bus (636).

[0113] The second power management unit (640) corresponds to the power domains (621, 622, 623) included in the second subsystem (620), and may include: at least one domain power manager (PMD) (642, 643, 644) for power control of the corresponding power domain (621, 622, 623); a root power manager (PMR) (641) for managing at least one domain power manager (642, 643, 644); and a memory (645) for storing the programs required to run the root power manager (641) and at least one domain power manager (642, 643, 644). At least one domain power manager (642, 643, 644), the root power manager (641), and the memory (645) may be interconnected via an internal bus (646).

[0114] Each root power manager (631, 641) and each domain power manager (632, 633, 634, 642, 643, 644) can be implemented as a programmable sequencer running at the hardware level.

[0115] The central processing unit (611) makes decisions on the power-on / power-off of the on-chip system device, the first subsystem (610), the second subsystem (620), and individual power domains (611, 612, 613, 621, 622, 623) at the software level, and sends system power-on / power-off commands and domain power-on / power-off commands to the first power management unit (630) and the second power management unit (640) based on the decisions.

[0116] When making a power-down decision for the system-on-chip device, the central processing unit (611) sends a system power-down command for the system-on-chip device to the first power management unit (630) and the second power management unit (640). The system power-down command is transmitted to the root power manager (631) of the first power management unit (630) and the root power manager (641) of the second power management unit (640) so that each root power manager (631, 641) executes the instructions required to implement the power-down command for the system-on-chip device, thereby controlling the power supply of each domain power manager (632, 633, 634, 642, 643, 644).

[0117] When the central processing unit (611) makes a power-on or power-off decision for the first subsystem (610), it sends a system power-on / power-off command for the first subsystem (610) to the first power management unit (630); when it makes a power-on or power-off decision for the second subsystem (620), it sends a system power-on / power-off command for the second subsystem (620) to the second power management unit (640). The root power manager (631) of the first power management unit (630) that receives the system power-on / power-off command for the first subsystem (610) will control at least one upper domain power manager (632, 633, 634) based on the instructions and data required to execute the corresponding command; the root power manager (641) of the second power management unit (640) that receives the system power-on / power-off command for the second subsystem (620) will control at least one or more domain power managers (642, 643, 644) based on the instructions and data required to execute the corresponding command.

[0118] In addition, when the central processing unit (611) makes a power-on or power-off decision for an individual power domain, it sends a domain power-on / power-off command to the domain power manager (632, 633, 634, 642, 643, 644) that matches the corresponding power domain. The corresponding domain power manager (632, 633, 634, 642, 643, 644) will send a power control signal to the corresponding power domain based on the instructions and data required to execute the corresponding command.

[0119] Any conventional descriptions, elements, or modules in the flowcharts described in this specification and / or the accompanying drawings should be understood as potentially representing code, modules, fragments, or portions containing more than one implementable instruction required to implement a particular logic function or element. At a conventional level, alternatives to the present invention are all covered within the scope of the examples described herein, and based on the functionality understood herein, the deletion, illustration, or discussion of elements or functions can be performed synchronously or in reverse order.

[0120] Various modifications and variations can be made to the embodiments described above, and it should be understood that these elements are merely one of other acceptable examples. All such modifications and variations are included within the scope of this invention and are intended to be protected by the following claims. The embodiments of the invention described above can be implemented in the form of program instructions executable by various computer components and recorded in a computer-readable recording medium. The computer-readable recording medium may include program instructions, data files, data structures, etc., in individual or combined forms. The program instructions recorded on the computer-readable recording medium may be instructions specifically designed and configured for this invention, or instructions known and usable by those skilled in the art of computer software. Examples of computer-readable recording media include: magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floppy disks; and hardware devices specifically configured to store and execute program instructions such as ROMs, RAMs, and flash memory. In examples of program instructions, not only machine language code generated by a compiler are included, but also high-level language code that can be run by a computer using an interpreter, etc. The hardware device can be configured to run as one or more software modules to perform the processing according to the present invention, and vice versa.

[0121] Although the present invention has been described above with reference to specific structural elements and other specific content, limited embodiments, and accompanying drawings, these are only provided to help to fully understand the present invention. The present invention is not limited to the described embodiments, and those skilled in the art can make various modifications and variations based on these descriptions.

[0122] Therefore, the concept of the present invention should not be limited to the embodiments described above. All claims, equivalents or modifications thereof, should fall within the scope of the present invention.

Claims

1. A power management system, comprising: A central processing unit that makes a decision on power-on or power-off of at least one control object power domain among a plurality of power domains included in a system-on-chip device, and sends at least one domain power control command among a domain power-on command and a domain power-off command based on the power domain power-on / power-off decision. A domain power manager receives the domain power control command and executes at least one of a power-on sequence and a power-off sequence on the controlled object power domain.

2. The power management system according to claim 1, in, The central processing unit makes a decision on powering on or off the system comprising at least a portion of the plurality of power domains, and sends at least one system power control command, either a system power-on command or a system power-off command, based on the system power-on / power-off decision. The power management system further includes a root power manager, which receives the system power control command and executes at least one of a power-on sequence or a power-off sequence on the domain power managers.

3. The system-on-a-chip device according to claim 2, The memory is used to store at least one instruction required by the domain power manager to execute the domain power control command, and at least one instruction required by the root power manager to execute the system power control command.

4. The power management system according to claim 3, in, The domain power manager includes: A processing unit receives the domain power control command from the central processing unit, accesses the memory storing at least one instruction for executing the domain power control command, and executes at least one instruction stored in the memory. The register group is configured by the processing unit to change the value of at least one register field in order to send a power control signal to the power domain of the controlled object.

5. The power management system according to claim 4, in, The domain power manager also includes: A power manager interface that receives signals from the power domain of the controlled object to change the values ​​of specific register fields in the register group.

6. The power management system according to claim 3, in, The root power manager includes: A processing unit receives the system power control command from the central processing unit and accesses the memory storing at least one instruction for executing the system power control command to execute at least one instruction stored in the memory. The register group, wherein the processing unit modifies the value of at least one register field to send a power control signal to the domain power manager.

7. The power management system according to claim 6, in, The root power manager also includes: A power manager interface that receives signals from the domain power manager to change the value of a specific register field in the register group.

8. The power management system according to claim 4 or claim 6, in, The instructions include those for changing the values ​​of specific register fields in the register set.

9. The power management system according to claim 4 or claim 6, in, The instructions also include instructions to wait until the value of a specific register field in the register set changes.

10. The power management system according to claim 4 or claim 6, in, The instructions also include instructions to wait for a specific period of time.

11. The power management system according to claim 4 or claim 6, in, The instructions further include at least one of the following: an instruction to write the value of the internal register of the processing unit to a specific register field of the register group, an instruction to write the value of a specific register field of the register group to the internal register of the processing unit, and an instruction to write a user-input constant value to the internal register of the processing unit.

12. The power management system according to claim 4 or claim 6, in, The instructions also include instructions for determining the execution order of instructions stored in the memory.

13. The power management system according to claim 2, Configure the domain power manager in the non-power gating region of the power domain of the controlled object.

14. The power management system according to claim 2, Configure the domain power manager and the root power manager in the normally open domain.

15. The power management system according to claim 2, The power domain of the controlled object is the central processing unit.

16. A system-on-a-chip device, comprising: Multiple power domains; The first subsystem includes at least a portion of the plurality of power domains; The second subsystem includes at least a portion of the plurality of power domains. This includes: The central processing unit (CPU) makes decisions on power-on or power-off of at least one first control object power domain among multiple power domains included in the first subsystem, and sends a first domain power control command based on the domain power-on / power-off decision; it makes decisions on power-on or power-off of at least one second control object power domain among multiple power domains included in the second subsystem, and sends a second domain power control command based on the domain power-on / power-off decision; it makes decisions on power-on or power-off of the first subsystem, and sends a first system power control command based on the first subsystem power-on / power-off decision; it makes decisions on power-on or power-off of the second subsystem, and sends a second system power control command based on the second subsystem power-on / power-off decision. A first power management unit receives power control commands for the first domain and power control commands for the first system, and performs power control on multiple power domains included in the first subsystem; and The second power management unit receives the second domain power control command and the second system power control command, and performs power control on the multiple power domains included in the second subsystem.

17. The system-on-a-chip device according to claim 16, in, The first power management unit includes: A domain power manager receives the first domain power control command and executes at least one of a power-on sequence and a power-off sequence on the first controlled object power domain. A root power manager that receives the first system power control command and executes at least one of a power-on sequence and a power-off sequence on the domain power manager; and The memory stores at least one instruction required by the domain power manager to execute the first domain power control command, and at least one instruction required by the root power manager to execute the first system power control command.

18. The system-on-a-chip device according to claim 16, in, The second power management unit includes: A domain power manager that receives the second domain power control command and executes at least one of a power-on sequence and a power-off sequence on the power domain of the second controlled object. A root power manager that receives the second system power control command and executes at least one of a power-on sequence and a power-off sequence on the domain power manager; and The memory stores at least one instruction required by the domain power manager to execute the second domain power control command, and at least one instruction required by the root power manager to execute the second system power control command.

19. The system-on-a-chip device according to claim 17 or claim 18, in, The domain power manager includes: A processing unit that receives a domain power control command from the central processing unit and accesses the memory to execute at least one instruction required to implement the received domain power control command. The register group, through the processing unit, changes the value of at least one register field, thereby sending a power control signal to the power domain of the controlled object.

20. The system-on-a-chip device according to claim 17 or claim 18, in, The root power manager includes: A processing unit that receives system power control commands from the central processing unit and accesses the memory to execute at least one instruction required to implement the received system power control commands; The register group, wherein the processing unit modifies the value of at least one register field to send a power control signal to the domain power manager.

21. The system-on-a-chip device according to claim 17 or claim 18, Configure the domain power manager and the root power manager in the normally open domain.

22. The system-on-a-chip device according to claim 21, At least one of the plurality of power domains is the central processing unit.

23. The system-on-a-chip device according to claim 21, At least one of the multiple power domains is a real-time peripheral device.

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