Reduced gate edge capacitance

Abstract

A field effect transistor (FET) device is provided. The FET device includes an active region and a gate. The active region includes a source at a first end thereof and a drain at a second end thereof. The gate extends across the active region and includes at least one end that extends beyond a corresponding edge of the active region by a sub-lithographic dimension.

Description

Background Technology

[0001] This invention generally relates to methods for manufacturing semiconductor devices and the resulting structures. More specifically, this invention relates to a semiconductor device structure with reduced gate-edge capacitance.

[0002] Transistors are semiconductor devices used to amplify or switch electrical signals and power, and are one of the fundamental building blocks of modern electronics. A field-effect transistor (FET) is a type of transistor that uses an electric field to control the flow of current in a semiconductor. An FET has three terminals: source, gate, and drain. An FET controls the current flow by applying a voltage to the gate, thereby changing the conductivity between the drain and source. Summary of the Invention

[0003] According to one aspect of the present invention, a field-effect transistor (FET) device is provided. The FET device includes an active region and a gate. The active region includes a source at a first end of the active region and a drain at a second end of the active region. The gate extends across the active region and includes at least one end extending beyond a corresponding edge of the active region at a sub-lithographic scale. Therefore, the FET device provides a reduction in the gate's extension beyond the active region (PC extending beyond RX).

[0004] According to one aspect of the present invention, a field-effect transistor (FET) device is provided, comprising an active region, a gate, a contact, and first and second spacers. The active region includes a source at a first end and a drain at a second end. The gate extends across the active region and includes a first end and an opposing second end, respectively extending beyond corresponding edges of the active region at a sub-photolithographic scale. The contact is configured to contact the gate within a coverage area of ​​the active region. The first and second spacers contact the first and second ends of the gate, respectively. Therefore, the FET device provides a reduction in the gate's extension beyond the active region (PC extending beyond RX).

[0005] According to one aspect of the present invention, a field-effect transistor (FET) device is provided, comprising an active region, a gate, a contact, and a spacer. The active region includes a source at a first end and a drain at a second end. The gate extends across the active region and includes a first end and an opposing second end, the first end extending beyond a first corresponding edge of the active region at a sub-lithographic dimension, and the second end extending beyond a second corresponding edge of the active region at an dimension exceeding the sub-lithographic dimension. The contact is configured to contact the second end of the gate outside the active region. The spacer contacts the first end of the gate. Therefore, the FET device provides a reduction in the gate's extension beyond the active region (PC extending beyond RX).

[0006] According to one aspect of the present invention, a field-effect transistor (FET) device is provided, comprising first and second active regions, first and second gates, contacts, a first spacer, and a second spacer. Each of the first and second active regions includes a source at a first end and a drain at a second end. The first and second gates extend across the first and second active regions, respectively. Each of the first and second gates includes a complementary first end extending beyond a first corresponding edge of the first and second active regions at a sub-lithographic dimension, and a complementary second end extending beyond a second corresponding edge of the first and second active regions at a dimension exceeding the sub-lithographic dimension. The contacts are configured to contact the complementary first ends of the first and second gates and the first and second corresponding edges of the first and second active regions. The first spacer contacts the complementary first ends of the first and second gates. The second spacer contacts the complementary second ends of the first and second gates. Therefore, the FET device provides a reduction in the gate extent (PC extent RX) of the FET beyond the active region.

[0007] According to one aspect of the invention, a method for assembling a field-effect transistor (FET) device is provided. The method includes: forming an active region having a gate extending across an active region; forming a trench along one end of the gate; performing cyclic metal oxidation and etching to progressively reshape the end of the gate inward toward a corresponding edge of the active region; and forming a spacer in the trench at the end of the gate once the end of the gate extends beyond the corresponding edge of the active region at a sub-lithographic scale. Therefore, the method provides a reduction in the gate extending beyond the active region (PC extending beyond RX) of the FET.

[0008] Additional technical features and benefits are achieved through the technology of this invention. Embodiments and aspects of the invention are described in detail herein and are considered part of the claimed subject matter. For a better understanding, reference can be made to the specific embodiments and accompanying drawings. Attached Figure Description

[0009] The specific details of the proprietary rights described herein are specifically pointed out and explicitly claimed in the claims. The foregoing and other features and advantages of the embodiments of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0010] Figure 1 This is a schematic top view of a FET device according to one or more embodiments of the present invention, wherein a reduced gate material (e.g., PC) extends beyond the active region / area (e.g., RX) at both edges of the active region.

[0011] Figure 2 This is a schematic top view of a FET device having a reduced PC past RX at one edge of the active region, according to one or more embodiments of the present invention.

[0012] Figure 3 This is a schematic top view of a FET device having a reduced PC exceeding RX at the two edges of the first and second active regions according to one or more embodiments of the present invention.

[0013] Figure 4 This is a flowchart illustrating a method for assembling a FET device according to one or more embodiments of the present invention;

[0014] Figure 5 This is a schematic top view of the initial structure of a FET device assembly according to one or more embodiments of the present invention;

[0015] Figure 6 This is a schematic top view of a first intermediate structure for FET device assembly according to one or more embodiments of the present invention;

[0016] Figure 7 This is a schematic top view of a second intermediate structure assembled with FET devices according to one or more embodiments of the present invention;

[0017] Figure 8 This is a schematic top view of a third intermediate structure assembled with FET devices according to one or more embodiments of the present invention;

[0018] Figure 9 This is a schematic top view of the late-stage structure of a FET device assembly according to one or more embodiments of the present invention.

[0019] The illustrations depicted herein are illustrative. Many variations can be made to the illustrations or the operations described therein without departing from the scope of the invention. For example, actions can be performed in a different order, or actions can be added, deleted, or modified. Furthermore, the term "coupling" and its variations describe a communication path between two elements, but do not imply a direct connection between the elements without intermediate elements / connections. All such variations are considered part of the specification.

[0020] In the accompanying drawings and the following detailed description of the described embodiments, the various elements shown in the drawings are labeled with two- or three-digit reference numerals. With a few exceptions, the leftmost digit of each reference numeral(s) corresponds to the drawing number in which its element first appears. Detailed Implementation

[0021] According to one aspect of the present invention, a field-effect transistor (FET) device is provided. The FET device includes an active region and a gate. The active region includes a source at a first end of the active region and a drain at a second end of the active region. The gate extends across the active region and includes at least one end extending beyond a corresponding edge of the active region at a sub-lithographic scale. Therefore, the FET device provides a reduction in the gate's extension beyond the active region (PC extending beyond RX).

[0022] In an additional or alternative embodiment, the gate includes at least one end extending beyond the corresponding edge of the active region at a sub-lithographic scale, and a contact is configured to contact a second end of the gate outside the active region. Therefore, the FET device provides a reduction in the gate extending beyond the active region (PC extending beyond RX) on one side of the active region.

[0023] In an additional or alternative embodiment, the spacer contacts one end of the gate. Therefore, this FET device provides a reduction in the gate's extension beyond the active region (PC extends beyond RX) on one side of the active region.

[0024] In an additional or alternative embodiment, the gate includes opposite ends extending beyond corresponding edges of the active region at a sub-lithographic scale, and contacts are configured to contact the gate within the coverage area of ​​the active region. Therefore, this FET device provides a reduction in the gate's extension beyond the active region (PC extending beyond RX) at opposite sides of the active region.

[0025] In additional or alternative embodiments, spacers contact opposite ends of the gate. Therefore, this FET device provides a reduction in the gate's extension beyond the active region (PC extending beyond RX) on opposite sides of the active region.

[0026] In additional or alternative embodiments, the sub-lithography dimension along the longitudinal axis of the gate is 5 nm or smaller. Therefore, this FET device provides a complementary metal-oxide-semiconductor (CMOS) compatible approach to achieve a reduction in the gate beyond the active region (PC beyond RX).

[0027] In additional or alternative embodiments, the gate comprises an alternative metal gate, and the alternative metal gate comprises either tungsten or aluminum. Therefore, this FET device provides a complementary metal-oxide-semiconductor (CMOS) compatible approach to reduce the portion of the gate extending beyond the active region (PC beyond RX).

[0028] According to one aspect of the present invention, a field-effect transistor (FET) device is provided, comprising an active region, a gate, a contact, and first and second spacers. The active region includes a source at a first end and a drain at a second end. The gate extends across the active region and includes a first end and an opposing second end, respectively extending beyond corresponding edges of the active region at a sub-photolithographic scale. The contact is configured to contact the gate within a coverage area of ​​the active region. The first and second spacers contact the first and second ends of the gate, respectively. Therefore, the FET device provides a reduction in the gate's extension beyond the active region (PC extending beyond RX).

[0029] In additional or alternative embodiments, the sub-lithography dimension along the longitudinal axis of the gate is 5 nm or smaller. Therefore, this FET device provides a complementary metal-oxide-semiconductor (CMOS) compatible approach to achieve a reduction in the gate beyond the active region (PC beyond RX).

[0030] In additional or alternative embodiments, the gate includes an alternative metal gate, and the alternative metal gate includes one of tungsten and aluminum. Therefore, this FET device provides a complementary metal-oxide-semiconductor (CMOS) compatible approach to achieve a reduction in the gate over the active region (PC over RX).

[0031] According to one aspect of the present invention, a field-effect transistor (FET) device is provided, comprising an active region, a gate, a contact, and a spacer. The active region includes a source at a first end and a drain at a second end. The gate extends across the active region and includes a first end and an opposing second end, the first end extending beyond a first corresponding edge of the active region by a sub-lithographic dimension, and the second end extending beyond a second corresponding edge of the active region by a dimension exceeding the sub-lithographic dimension. The contact is configured to contact the second end of the gate outside the active region. The spacer contacts the first end of the gate. Thus, the FET device achieves a reduction in the gate extending beyond the active region (PC extending beyond RX).

[0032] In additional or alternative embodiments, the sub-lithography dimension along the longitudinal axis of the gate is 5 nm or smaller. Therefore, this FET device provides a complementary metal-oxide-semiconductor (CMOS) compatible approach to achieve a reduction in the gate beyond the active region (PC beyond RX).

[0033] In additional or alternative embodiments, the gate includes an alternative metal gate, and the alternative metal gate includes one of tungsten and aluminum. Therefore, this FET device provides a complementary metal-oxide-semiconductor (CMOS) compatible approach to achieve a reduction in the gate over the active region (PC over RX).

[0034] According to one aspect of the present invention, a field-effect transistor (FET) device is provided, comprising a first active region and a second active region, a first gate and a second gate, a contact, a first spacer, and a second spacer. Each of the first and second active regions includes a source at a first end and a drain at a second end. The first gate and the second gate extend across the first and second active regions, respectively. Each of the first and second gates includes complementary first and second ends, the complementary first ends extending beyond a first corresponding edge of the first and second active regions by a sub-lithographic dimension, and the complementary second ends extending beyond a second corresponding edge of the first and second active regions by a dimension exceeding the sub-lithographic dimension. The contact is configured to contact the complementary first ends of the first and second gates and the first and second corresponding edges of the first and second active regions. The first spacer contacts the complementary first ends of the first and second gates. The second spacer contacts the complementary second ends of the first and second gates. Therefore, this FET device achieves a reduction in the gate extension beyond the active region (PC extending beyond RX).

[0035] In additional or alternative embodiments, the sub-lithography dimension is 5 nm or less along each longitudinal axis of each of the first and second gates. Therefore, this FET device provides a complementary metal-oxide-semiconductor (CMOS) compatible approach to achieve a reduction in the gate beyond the active region (PC beyond RX).

[0036] In additional or alternative embodiments, the first gate and the second gate each include an alternative metal gate, and the alternative metal gate includes one of tungsten and aluminum. Therefore, this FET device provides a complementary metal-oxide-semiconductor (CMOS) compatible approach to achieve a reduction in the gate over the active region (PC over RX).

[0037] According to one aspect of the present invention, a method for assembling a field-effect transistor (FET) device is provided. The method includes: forming an active region having a gate extending across an active region; forming a trench along one end of the gate; performing cyclic metal oxidation and etching to progressively reshape the end of the gate inward toward a corresponding edge of the active region; and forming a spacer in the trench at the end of the gate once the end of the gate extends beyond the corresponding edge of the active region at a sub-lithographic dimension. Therefore, this method achieves a reduction in the gate extension beyond the active region (PC extending beyond RX) of the FET.

[0038] In additional or alternative embodiments, the sub-lithography dimension along the longitudinal axis of the gate is 5 nm or smaller. Therefore, this FET device provides a complementary metal-oxide-semiconductor (CMOS) compatible approach to achieve a reduction in the gate beyond the active region (PC beyond RX).

[0039] In an additional or alternative embodiment, the method includes forming a trench at one end of the gate; performing cyclic metal oxidation and etching includes progressively reshaping one end of the gate inward toward the corresponding edge of the active region; forming includes forming a spacer in the trench at one end of the gate once the one end of the gate extends beyond the corresponding edge of the active region at a sub-lithographic dimension; and the method further includes configuring contacts to contact the gate outside the active region. Therefore, this method provides a complementary metal-oxide-semiconductor (CMOS) compatible approach to achieve a reduction in gate overreach (PC over RX).

[0040] In an additional or alternative embodiment, the method includes forming trenches at opposite ends of the gate; performing cyclic metal oxidation and etching includes progressively reshaping the opposite ends of the gate toward corresponding edges of the active region; forming includes forming spacers at opposite ends of the gate once the opposite ends of the gate extend beyond the corresponding edges of the active region at a sub-photolithographic scale; and the method further includes configuring contacts to contact the gate within a coverage area of ​​the active region. Therefore, this method provides a complementary metal-oxide-semiconductor (CMOS) compatible approach to reduce the gate-to-active-region (PC-to-RX) overlap.

[0041] In an additional or alternative embodiment, the method includes forming a first active region and a second active region, and a first gate and a second gate extending across the first active region and the second active region, respectively; forming trenches at complementary first and second ends of the first gate and the second gate; performing cyclic metal oxidation and etching including progressively reshaping the complementary first ends of the first gate and the second gate toward first corresponding edges of the first active region and the second active region; forming spacers at the complementary first ends of the first gate and the second gate once the complementary first ends of the first gate and the second gate extend beyond the first corresponding edges of the first active region and the second active region at a sub-lithographic scale; and the method further includes configuring contacts to contact the complementary first ends of the first gate and the second gate and the first corresponding edges of the first active region and the second active region. Therefore, this method provides a complementary metal-oxide-semiconductor (CMOS) compatible approach to achieve a reduction in gate beyond the active region (PC beyond RX).

[0042] For the sake of brevity, conventional techniques related to the manufacture of semiconductor devices and integrated circuits (ICs) may not be described in detail herein. Furthermore, the various tasks and process steps described herein can be incorporated into more comprehensive procedures or processes with additional steps or functions not described in detail herein. Specifically, the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well-known; therefore, for the sake of brevity, many conventional steps will only be briefly mentioned or omitted entirely without providing well-known process details.

[0043] Turning now to a more specific technical overview related to aspects of the invention, a FET includes a source, a drain, and a gate, and a voltage applied to the gate alters the conductivity between the source and drain. FETs can be formed and assembled using various processes, such as photolithography. As semiconductor device dimensions continue to shrink, the limitations of photolithography become increasingly apparent. Specifically, when assembling FETs using photolithography, the gate material typically extends beyond the edge of the active region defined by the source, drain, and the area between the source and drain. This extension of the gate beyond the active region (i.e., PC extending beyond RX) can be significant and may result in edge capacitance, thereby degrading FET performance.

[0044] Therefore, a complementary metal-oxide-semiconductor process compatible with lithography that can reduce the PC of FETs beyond the RX is still needed.

[0045] Turning now to an overview of various aspects of the invention, one or more embodiments of which address the aforementioned drawbacks of the prior art by providing a FET device comprising an active region and a gate. The active region includes a source at a first end and a drain at a second end. The gate extends across the active region and includes at least one end extending beyond a corresponding edge of the active region at a sub-lithographic scale.

[0046] The above aspects of the present invention reduce the edge capacitance (C) by minimizing the PC beyond the RX to a sub-lithographic size, and then by utilizing cyclic metal oxidation and etching. edge This addresses the shortcomings of existing technologies. For FETs, the gate edge outside the RX is exposed through a trench opening, and cyclic metal oxidation (i.e., plasma oxidation) and etching (i.e., reactive ion etching or wet etching, e.g., DHF) are performed. The trench is then refilled with a spacer material (e.g., SiN).

[0047] We now turn to a more detailed description of various aspects of the invention. Figure 1 FET 101 is depicted, comprising an active region 110 and a gate 120. The active region 110 includes a source 111 at a first end and a drain 112 at a second end opposite to the first end. The active region 110 also includes a first edge 113, a second edge 114 opposite to the first edge 113, and a cover region 115 partially defined by the first edge 113 and the second edge 114. The gate 120 extends across the active region 110 and has a longitudinal axis A1. The gate 120 includes a first end 121 and a second end 122 opposite to the first end 121. The first end 121 extends beyond the first edge 113 by a sub-lithographic dimension D1, and the second end 122 extends beyond the second edge 114 by a sub-lithographic dimension D1. The gate 120 may be provided as an alternative metal gate and may comprise one or more low-resistivity metallic materials, such as tungsten and aluminum.

[0048] According to an embodiment, the sub-lithographic dimension D1 defined along the longitudinal axis A1 is approximately 5 nm or smaller. Since the first end 121 and the second end 122 extend beyond the first edge 113 and the second edge 114 only by the sub-lithographic dimension D1, respectively, the edge capacitance between the first end 121 and the second end 122 and the source 111 and drain 112 of the active region 110 is significantly reduced. This improves the performance factor of the FET device 101.

[0049] like Figure 1 As shown, the FET device 101 also includes a contact 130, a first spacer 141, and a second spacer 142. The contact 130 is disposed between a first edge 113 and a second edge 114 and contacts the gate 120, thus being located within the coverage area 115 of the active region 110. The first spacer 141 contacts or abuts a first end 121 of the gate 120, and the second spacer 142 contacts or abuts a second end 122 of the gate 120.

[0050] Figure 2 A FET device 201 is depicted, comprising an active region 210 and a gate 220. The active region 210 includes a source 211 at a first end and a drain 212 at a second end, the second end being opposite to the first end. The active region 210 also includes a first edge 213, a second edge 214 opposite to the first edge 213, and a cover region 215 partially defined by the first edge 213 and the second edge 214. The gate 220 extends across the active region 210 and has a longitudinal axis A2. The gate 220 includes a first end 221 and a second end 222 opposite to the first end 221. The first end 221 extends beyond the first edge 213 by a sub-lithographic dimension D2, and the second end 222 extends beyond the second edge 214 by a distance exceeding the sub-lithographic dimension D2. The gate 220 may be provided as an alternative metal gate and may comprise one or more low-resistivity metallic materials, such as tungsten and aluminum.

[0051] According to an embodiment, the sub-lithographic dimension D2 defined along the longitudinal axis A2 is approximately 5 nm or smaller. Since the first end 221 extends beyond the first edge 213 only by the sub-lithographic dimension D2, the edge capacitance between the first end 221 and the source 211 and drain 212 of the active region 210 is significantly reduced. This improves the performance factor of the FET device 201.

[0052] like Figure 2As shown, the FET device 201 also includes a contact 230 and a spacer 241. The contact 230 is configured to contact the second end 222 of the gate 220 between the second edge 214 and the distal end of the second end 222, and is outside the coverage area 215 of the active region 210. The spacer 241 contacts or abuts the first end 221 of the gate 220.

[0053] Figure 3 A FET device 301 is depicted, including a first active region 3101 and a second active region 3102, as well as a first gate 3201 and a second gate 3202. The first active region 3101 includes a source 3111 at a first end and a drain 3121 at a second end, wherein the second end is opposite to the first end. The first active region 3101 also includes a first edge 3131, a second edge 3141 opposite to the first edge 3131, and a coverage region 3151 partially defined by the first edge 3131 and the second edge 3141. The second active region 3102 includes a source 3112 at a first end and a drain 3122 at a second end, wherein the second end is opposite to the first end. The second active region 3102 also includes a first edge 3132, a second edge 3142 opposite to the first edge 3132, and a coverage area 3152 partially defined by the first edge 3132 and the second edge 3142. A first gate 3201 extends across the first active region 3101 and has a longitudinal axis A3. The first gate 3201 includes a first end 3211 and a second end 3221 opposite to the first end 3211. The first end 3211 extends beyond the first edge 3131 at a sub-lithographic dimension D3, and the second end 3221 extends beyond the second edge 3141 at a sub-lithographic dimension D3. The first gate 3201 may be provided as an alternative metal gate and may include one or more low-resistivity metallic materials, such as tungsten and aluminum. The second gate 3202 extends across the second active region 3102 and has a longitudinal axis A3. The second gate 3202 includes a first end 3212 and a second end 3222 opposite to the first end 3212. The first end 3212 extends beyond the first edge 3132 with a sub-lithographic dimension D3, and the second end 3222 extends beyond the second edge 3142 with a sub-lithographic dimension D3. The second gate 3202 may be provided as an alternative metal gate and may include one or more low-resistivity metal materials, such as tungsten and aluminum.

[0054] According to an embodiment, the sub-lithographic dimension D3 defined along the longitudinal axis A3 is approximately 5 nm or smaller. Since the first ends 3211 and 3212 extend beyond the first edges 3131 and 3132 only by the sub-lithographic dimension D3, the edge capacitance between the first ends 3211 and 3212 and the source electrodes 3111, 3112 and drain electrodes 3121, 3122 of the first active region 3101 and the second active region 3102 is significantly reduced. Simultaneously, since the second ends 3221 and 3222 extend beyond the second edges 3141 and 3142 only by the sub-lithographic dimension D3, the edge capacitance between the second ends 3221 and 3222 and the source electrodes 3111, 3112 and drain electrodes 3121, 3122 of the first active region 3101 and the second active region 3102 is also significantly reduced. Thus, the performance factor of the FET device 301 is improved.

[0055] like Figure 3 As shown, the FET device 301 also includes a contact 330, first spacers 3411 and 3412, and second spacers 3421 and 3422. The contact 330 is configured to contact complementary first ends 3211 and 3212 of the first gate 3201 and the second gate 3202, and corresponding first edges 3131 and 3132 of the first active region 3101 and the second active region 3102. The first spacers 3411 and 3412 contact the complementary first ends 3211 and 3212 of the first gate 3201 and the second gate 3202. The second spacers 3421 and 3422 contact the complementary second ends 3221 and 3222 of the first gate 3201 and the second gate 3202.

[0056] refer to Figure 4 A method 400 for assembling a FET device is provided. Method 400 includes: forming an active region and having a gate across the active region (box 401); forming a trench along one end of the gate (box 402); performing cyclic metal oxidation and etching to progressively reshape the end of the gate inward toward a corresponding edge of the active region (box 403); and forming a spacer in the trench at the end of the gate once the end of the gate extends along the longitudinal axis of the gate beyond the corresponding edge of the active region by approximately 5 nanometers or less of a sub-lithographic dimension (box 404). Method 400 may further include providing contacts (box 405).

[0057] According to one or more embodiments of the present invention, and as Figure 1As shown, the formation of frame 402 may include creating trenches at opposite ends of the gate; the execution of cyclic metal oxidation and etching in frame 403 may include progressively reshaping the opposite ends of the gate toward the corresponding edges of the active region; and the formation of frame 404 may include forming spacers at the opposite ends of the gate once the opposite ends of the gate extend beyond the corresponding edges of the active region at a sub-lithographic scale. In these or other cases, the arrangement of contacts in frame 405 may include configuring contacts to contact the gate within the coverage area of ​​the active region.

[0058] According to one or more embodiments of the present invention, and as Figure 2 As shown, the formation of frame 402 may include forming a trench at one end of the gate; the execution of cyclic metal oxidation and etching in frame 403 may include progressively reshaping that end of the gate inward toward the corresponding edge of the active region; and the formation of frame 404 may include forming spacers in the trench at that end of the gate once that end of the gate extends beyond the corresponding edge of the active region at a sub-lithographic scale. In these or other cases, the arrangement of the contacts in frame 405 may include arranging the contacts to contact the gate outside the active region.

[0059] According to one or more embodiments of the present invention, and as Figure 3 As shown, the formation of frame 401 may include forming a first active region and a second active region, and having a first gate and a second gate extending across the first active region and the second active region, respectively. The opening of frame 402 may include forming trenches at complementary first and second ends of the first gate and the second gate. The execution of cyclic metal oxidation and etching of frame 403 may include progressively reshaping the complementary first ends of the first gate and the second gate inward toward first corresponding edges of the first active region and the second active region. The formation of frame 404 may include forming spacers at the complementary first ends of the first gate and the second gate once the complementary first ends of the first gate and the second gate extend beyond the first corresponding edges of the first active region and the second active region at a sub-lithographic scale. In these or other cases, the arrangement of contacts in frame 405 may include configuring contacts to contact the complementary first ends of the first gate and the second gate and the first corresponding edges of the first active region and the second active region.

[0060] refer to Figures 5-9 Now we will describe it further. Figure 4 Method 400. It's important to understand that... Figures 5-9 Typically involves Figure 1 The embodiments described herein are for clarity and brevity and should not be construed as limiting the scope of the specification or claims in any way. In fact, those skilled in the art will readily understand without excessive experimentation. Figure 4 Method 400 and Figures 5-9 The diagram is applicable Figure 2 and Figure 3 Various embodiments.

[0061] like Figure 5 As shown, an active region 501 is formed using a standard process (POR), and a gate 502 extends across the active region 501. The gate 502 can be provided as a plurality of gates, and can be provided as an alternative metal gate, and can be formed of a low-resistivity metal material, such as one or more of tungsten and aluminum. Spacers 503 are provided on the sidewalls of the gate 502. At this point, the ends 504 and 505 of the gate 502 extend beyond the corresponding edges of the active region 501 by a distance D51 exceeding the sub-photolithography dimension (i.e., 5 nm or less).

[0062] like Figure 6 As shown, trenches 506 and 507 are cut along ends 504 and 505 of gate 502 to expose ends 504 and 505. Subsequently, as... Figure 7 As shown, cyclic metal oxidation and etching are performed via trenches 506 and 507 to gradually reshape the ends 504 and 505 inward toward the corresponding edges of the active region 501. This cyclic metal oxidation and etching can be repeated iteratively until the ends 504 and 505 extend beyond the corresponding edges of the active region 501 at a sub-lithographic dimension D52 (i.e., 5 nm or less along the longitudinal axis of the gate 502).

[0063] like Figure 8 and Figure 9 As shown, once the ends 504 and 505 of the gate 502 extend beyond the corresponding edge of the active region 501 at a sub-lithographic dimension D52 (see... Figure 7 Spacers 508 and 509 are then formed in trenches 506 and 507 and at the ends 504 and 505 of gate 502. The remaining portions of trenches 506 and 507 are then filled with an interlayer dielectric (ILD), and chemical mechanical planarization (CMP) is performed to planarize the ILD. At this point, a contact 510 that contacts gate 502 can be formed within the coverage area of ​​active region 501.

[0064] Various embodiments of the invention have been described herein with reference to the accompanying drawings. Alternative embodiments may be devised without departing from the scope of the invention. Although various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are set forth in the specification and drawings, those skilled in the art will recognize that many of the positional relationships described herein are orientation-independent, provided that the described functionality is maintained after a change in orientation. Unless otherwise stated, these connections and / or positional relationships may be direct or indirect, and this disclosure is not intended to be limiting in this respect. Thus, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect. As an example of an indirect positional relationship, references in this specification to the formation of layer "A" on layer "B" include the case where one or more intermediate layers (e.g., layer "C") may exist between layer "A" and layer "B," provided that the relevant characteristics and functions of layer "A" and layer "B" are not substantially altered by (a plurality of) intermediate layers (e.g., layer "C").

[0065] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms “comprise,” “include,” “have,” “containing,” or any other variations thereof are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or other elements inherent to such composition, mixture, process, method, article, or apparatus.

[0066] Additionally, the term "exemplary" as used herein means "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as being more preferred or advantageous than other embodiments or designs. The terms "at least one" and "one or more" should be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "multiple" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0067] References to "an embodiment," "an embodiment," "an example embodiment," etc., in the specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment must include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, it should be understood that, whether explicitly described or not, implementing that feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0068] For the purposes of this description, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall refer to the structures and methods described in the orientation shown in the accompanying drawings. The terms “on,” “on top of,” “on the top of,” “placed on,” or “placed on top of” mean that a first element (such as a first structure) is present on a second element (such as a second structure), wherein an intermediate element (such as an interface structure) may exist between the first and second elements. The term “direct contact” means that the first element (such as a first structure) and the second element (such as a second structure) are connected at their interface without any intermediate conductive, insulating, or semiconductor layer.

[0069] Spatial relative terms (e.g., "below," "below," "lower," "above," "upper," etc.) are used herein to simplify the description of the relationship between one element or feature shown in the accompanying drawings and another element(s). It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as "below" or "below" other elements or features would be "above" other elements or features. Thus, the term "below" can encompass both above and below orientations. Devices may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0070] The phrase “selective relative to…” (e.g., “the first element is selective relative to the second element”) means that the first element can be etched while the second element can act as an etch stop layer.

[0071] The terms “about,” “basically,” “approximately,” and their variations are intended to include the degree of error associated with measuring a particular quantity based on the equipment available at the time of application submission. For example, “about” could include a range of ±8%, 5%, or 2% for a given value.

[0072] The term "conformal" (e.g., conformal layer) means that the thickness of the layer is substantially the same on all surfaces, or the thickness varies by less than 15% of the nominal thickness of the layer.

[0073] The terms "epitaxygrowth and / or deposition" and "epitaxygrowth formation and / or growth" refer to the growth of a semiconductor material (crystal material) on a deposition surface of another semiconductor material (crystal material), wherein the grown semiconductor material (crystal capping layer) has substantially the same crystal properties as the semiconductor material on the deposition surface (seed crystal material). In the epitaxial deposition process, the chemical reactants provided by the source gas can be controlled, and system parameters can be set such that the deposited atoms reach the deposition surface of the semiconductor substrate with sufficient energy, thereby moving on the surface and aligning their own orientation with the crystal arrangement of the atoms on the deposition surface. The epitaxially grown semiconductor material can have substantially the same crystal properties as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a {100} oriented crystal surface can exhibit a {100} orientation. In some embodiments of the invention, the epitaxial growth and / or deposition process can selectively form on a semiconductor surface, rather than depositing material on exposed surfaces (such as silicon dioxide or silicon nitride surfaces).

[0074] As mentioned above, for the sake of brevity, this document may not describe in detail conventional techniques associated with the manufacture of semiconductor devices and integrated circuits (ICs). However, as background, a more general description of semiconductor device manufacturing processes that can be used to implement one or more embodiments of the present invention will now be provided. Although specific manufacturing operations for implementing one or more embodiments of the present invention may be known individually, the described combinations of operations and / or the structures resulting from the present invention are unique. Thus, the unique combinations of operations described in conjunction with the manufacture of semiconductor devices according to the present invention utilize a variety of known physical and chemical processes performed on semiconductor (e.g., silicon) substrates, some of which will be described in the following paragraphs.

[0075] Generally, the various processes used to form microchips that will be packaged into ICs can be categorized into four main types: thin film deposition, removal / etching, semiconductor doping, and patterning / photolithography. Deposition is any process that grows, coats, or otherwise transfers material on a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry), chemical mechanical planarization (CMP), etc. Semiconductor doping alters electrical properties by doping (e.g., the source and drain of a transistor), typically through diffusion and / or ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing is used to activate the implanted dopant. Thin films of conductors (e.g., polycrystalline silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of different regions of a semiconductor substrate allows for alteration of the substrate's conductivity as voltage is applied. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of modern microelectronic devices. Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate so that the pattern can be subsequently transferred onto the substrate. In semiconductor lithography, the pattern is formed from a photosensitive polymer called photoresist. To build the complex structure that constitutes the transistors and the many wires that connect millions of transistors, the photolithography and etching pattern transfer steps are repeated multiple times. Each pattern printed on the wafer is aligned with the previously formed pattern, and conductors, insulators, and selectively doped regions are gradually built up to form the final device.

[0076] The flowcharts and block diagrams in the accompanying drawings illustrate possible implementations of the manufacturing and / or operating methods according to various embodiments of the present invention. Various functions / operations of the methods are represented by boxes in the flowcharts. In some alternative implementations, the functions indicated in the boxes may not occur in the order shown in the drawings. For example, two consecutively shown boxes may actually be executed substantially simultaneously, or sometimes they may be executed in reverse order depending on the functions involved.

[0077] The description of various embodiments of the invention is presented for illustrative purposes and is not intended to be exhaustive or limited to the described embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is intended to best explain the principles of the embodiments, their practical application, or improvements to the prior art, or to enable others skilled in the art to understand the embodiments described herein.

Claims

1. A field-effect transistor (FET) device, comprising: The active region includes a source electrode located at a first end of the active region and a drain electrode located at a second end of the active region; as well as A gate extending across the active region and including at least one end extending beyond a corresponding edge sub-lithographic dimension of the active region.

2. The FET device according to claim 1, wherein: The gate includes at least one end, the at least one end extending beyond the corresponding edge of the active region of the sub-lithographic dimension, and The contact is configured to contact the second end of the gate outside the active region.

3. The FET device of claim 2, further comprising a spacer in contact with one end of the gate.

4. The FET device according to claim 1, wherein: The gate includes two opposing ends, each extending beyond the corresponding edge of the active region of the sub-lithographic dimension. The contact is configured to contact the gate within the coverage area of ​​the active region.

5. The FET device of claim 4, further comprising spacers respectively contacting the opposite ends of the gate.

6. The FET device of claim 1, wherein the sub-lithography dimension along the longitudinal axis of the gate is 5 nm or less.

7. The FET device of claim 1, wherein the gate comprises an alternative metal gate.

8. The FET device of claim 7, wherein the alternative metal gate comprises one of tungsten and aluminum.

9. The FET device of claim 1, comprising: A contact element, the contact element being configured to contact the gate within the coverage area of ​​the active region; as well as A first spacer and a second spacer are respectively in contact with a first end and a second end of the gate.

10. The FET device of claim 9, wherein the sub-lithography dimension along the longitudinal axis of the gate is 5 nm or less.

11. The FET device of claim 9, wherein the gate comprises an alternative metal gate.

12. The FET device of claim 11, wherein the alternative metal gate comprises one of tungsten and aluminum.

13. The FET device of claim 1, wherein the gate extends laterally across the active region and includes a first end and an opposing second end, the first end extending beyond a first corresponding edge sub-lithographic dimension of the active region, and the second end extending beyond a second corresponding edge sub-lithographic dimension of the active region; Furthermore, the device further includes: A contact element configured to contact the second end of the gate outside the active region; And a spacer that contacts the first end of the gate.

14. The FET device of claim 13, wherein the sub-lithographic dimension along the longitudinal axis of the gate is 5 nm or less.

15. The FET device of claim 13, wherein the gate comprises an alternative metal gate.

16. The FET device of claim 15, wherein the alternative metal gate comprises one of tungsten and aluminum.

17. The FET device of claim 1, comprising: The first active region and the second active region, each active region including a source at its first end and a drain at its second end; as well as A first gate and a second gate extend laterally across the first active region and the second active region, respectively. Each of the first gate and the second gate includes a complementary first end and a complementary second end. The complementary first end extends beyond the sub-lithographic dimension of a first corresponding edge of the first active region and the second active region, and the complementary second end extends beyond the sub-lithographic dimension of a second corresponding edge of the first active region and the second active region. A contact element, the contact element being configured to contact the complementary first ends of the first gate and the second gate, and the first corresponding edge and the second corresponding edge of the first active region and the second active region; A first spacer is in contact with the complementary first ends of the first gate and the second gate; as well as A second spacer is in contact with the complementary second ends of the first gate and the second gate.

18. The FET device of claim 17, wherein the sub-lithographic dimension is 5 nm or less along each longitudinal axis of each of the first gate and the second gate.

19. The FET device of claim 17, wherein the first gate and the second gate each comprise an alternative metal gate.

20. The FET device of claim 19, wherein the alternative metal gate comprises one of tungsten and aluminum.

21. A method for assembling a field-effect transistor (FET) device, the method comprising: An active region is formed, the active region having a gate extending across the active region; A trench is formed along one end of the gate; Perform cyclic metal oxidation and etching to gradually reshape one end of the gate inward toward the corresponding edge of the active region; as well as Once one end of the gate extends beyond the corresponding edge sub-lithographic dimension of the active region, a spacer is formed in the trench at one end of the gate.

22. The method of claim 21, wherein the sub-lithography dimension along the longitudinal axis of the gate is 5 nm or less.

23. The method according to claim 21, wherein: The trench is formed at one end of the gate. Performing the cyclic metal oxidation and etching includes progressively reshaping one end of the gate inward toward the corresponding edge of the active region. The formation includes forming the spacer in the trench at one end of the gate once the one end of the gate extends beyond the corresponding edge of the active region at the sub-lithographic dimension, and The method further includes providing a contact element that contacts the gate outside the active region.

24. The method of claim 21, wherein: The process includes creating trenches at opposite ends of the gate. Performing the cycle of metal oxidation and etching involves progressively reshaping the opposite ends of the gate inward toward the corresponding edges of the active region. The formation includes forming spacers at the opposite ends of the gate once the opposite ends of the gate extend beyond the corresponding edge of the active region at the sub-lithographic dimension, and The method further includes providing a contact element that contacts the gate within the coverage area of ​​the active region.

25. The method according to claim 21, wherein: The formation includes forming a first active region and a second active region, wherein the first active region and the second active region respectively have a first gate and a second gate spanning the first active region and the second active region. The process includes creating trenches at complementary first and second ends of the first and second gates. Performing the cyclic metal oxidation and etching includes progressively reshaping the complementary first ends of the first gate and the second gate inward toward the first corresponding edges of the first active region and the second active region. The formation includes forming a spacer at the complementary first ends of the first gate and the second gate once the complementary first ends of the first gate and the second gate extend beyond the sublithographic dimension of the first corresponding edge of the first active region and the second active region, and The method further includes providing a contact element that contacts the complementary first ends of the first gate and the second gate, as well as the first corresponding edge of the first active region and the second active region.

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