A method for manufacturing a double-trench MOS field effect transistor and application thereof
By introducing a double trench structure and a heavily p-type doped layer into the silicon carbide MOSFET, the problem of low gate trench reliability is solved, high current conduction capability and gate trench protection are achieved, and device performance is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN ZHIXIN MICROELECTRONICS CO LTD
- Filing Date
- 2023-01-16
- Publication Date
- 2026-07-03
AI Technical Summary
In existing silicon carbide MOSFETs, the reliability of the gate trench is relatively low, especially under high electric fields where it is prone to breakdown, and increasing the gate oxide thickness will affect the device performance.
The fabrication method of dual-trench MOS field-effect transistors is adopted, which involves forming virtual trenches on both sides of the gate trench, injecting P-type heavily doped layers at the bottom and sidewalls of the virtual trenches, and filling the virtual trenches with oxides to shield strong electric fields.
It improves the reliability of the gate trench, avoids breakdown caused by high electric field, and does not significantly increase the channel resistance, thus maintaining high current conduction capability.
Smart Images
Figure CN116053140B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, specifically relating to a method for fabricating and applying a dual-trench MOS field-effect transistor. Background Technology
[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are core devices in next-generation high-efficiency power electronic technology. The breakdown critical electric field of silicon carbide (SiC) MOSFETs is approximately 10 times that of silicon-based MOSFETs. Compared to high-voltage silicon IGBTs, SiC MOSFETs offer higher bandwidth, lower losses, and higher operating temperatures, thus attracting widespread attention. In conventional trench-type SiC MOSFETs, the gate oxide thickness of the gate trench is uniform, especially on the two sidewalls, which exhibit better consistency due to their co-orientation. To achieve higher on-current capability, the gate oxide thickness is typically relatively thin. However, high electric fields tend to appear at trench corners, reducing the reliability of the gate oxide and potentially leading to breakdown. Simply increasing the gate oxide thickness significantly increases the channel's on-resistance, severely impacting device performance.
[0003] Therefore, it is necessary to provide a fabrication method that enables the MOS field-effect transistors fabricated according to the method to have high current conduction capability and high gate trench reliability. Summary of the Invention
[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. To this end, the present invention proposes a method for fabricating a dual-trench MOS field-effect transistor. The dual-trench MOS field-effect transistor fabricated according to the method does not significantly change the gate trench and channel that affect the current conduction capability, thus the channel resistance does not increase, and the reliability of the gate trench structure is improved.
[0005] The present invention also proposes an electronic device.
[0006] According to one aspect of the present invention, a method for fabricating a dual-trench MOS field-effect transistor is provided, comprising the following steps:
[0007] S1: Provide a semiconductor substrate layer, and form a semiconductor epitaxial layer on the semiconductor substrate layer;
[0008] S2: A well region is formed above the semiconductor epitaxial layer;
[0009] S3: Etch the middle region of the upper surface of the well region, implant N-type impurities into the middle region to form an N-type heavily doped region; etch the regions on both sides of the upper surface of the well region and the N-type heavily doped region, implant P-type impurities into the regions to form a P-type heavily doped region; the N-type heavily doped region and the P-type heavily doped region constitute a doped region;
[0010] S4: Etch a virtual trench on each side of the heavily doped N-type region, extending the virtual trench from the top of the doped region to the semiconductor epitaxial layer; implant P-type impurities into the bottom and sidewalls of the virtual trench to form a heavily doped P-type layer; fill the interior of the virtual trench with oxide; etch a gate trench in the middle region of the heavily doped N-type region, extending the gate trench from the top of the heavily doped N-type region to the semiconductor epitaxial layer; at this time, the following trench is formed: one gate trench, and a virtual trench is formed on each side of the gate trench;
[0011] S5: A metal layer is formed on the side of the doped region away from the semiconductor epitaxial layer.
[0012] According to a preferred embodiment of the present invention, at least the following beneficial effects are achieved:
[0013] In the dual-trench MOS field-effect transistor of the present invention, the gate trench and channel structure, which affect current conduction capability, are not significantly changed, and the channel resistance does not increase. Furthermore, because the present invention forms two virtual trenches on both sides of the gate trench, fills the virtual trenches with oxide, and forms a P-type heavily doped layer (containing P-type oxides) at the bottom and sidewalls of the virtual trenches... + It can shield the strong electric field near the gate trench, providing good protection for the gate trench and improving the reliability of the gate oxide.
[0014] In some embodiments of the present invention, the raw materials for preparing the semiconductor substrate include silicon carbide and silicon.
[0015] In some preferred embodiments of the present invention, the raw material for preparing the semiconductor substrate is selected from silicon carbide.
[0016] In some embodiments of the present invention, the raw materials for preparing the semiconductor epitaxial layer include silicon carbide and silicon.
[0017] In some preferred embodiments of the present invention, the raw material for preparing the semiconductor epitaxial layer is selected from silicon carbide.
[0018] In some preferred embodiments of the present invention, the raw material for preparing the semiconductor epitaxial layer is selected from N-type silicon carbide.
[0019] Specifically, N-type materials are electronically conductive and have lower hole-conducting resistance than P-type materials, hence the choice of N-type silicon carbide.
[0020] Specifically, the P-type heavily doped layer in the virtual trench + The N-type silicon carbide epitaxial layer forms a PN junction. The presence of the PN junction can change the distribution of the electric field. At the same time, the oxide filling the virtual trench acts as a field plate. The combination of the two can shield the strong electric field near the gate trench, thus providing good protection for the gate trench.
[0021] In some embodiments of the present invention, the voltage subjected to the semiconductor epitaxial layer is 650 to 1700V.
[0022] In some embodiments of the present invention, the concentration of the semiconductor epitaxial layer is 1×10⁻⁶. 15 ~1×10 17 cm -3 Thickness < 20 μm.
[0023] In some embodiments of the present invention, step S2 uses ion implantation to form the well region above the semiconductor epitaxial layer.
[0024] In some embodiments of the present invention, step S2 forms a P-well region by implanting a P-type impurity over the semiconductor epitaxial layer.
[0025] Specifically, the injection dosage, injection energy, and number of injections are arranged as needed and are not limited here.
[0026] In some embodiments of the present invention, the P-type impurity is either aluminum or boron.
[0027] In some preferred embodiments of the present invention, the P-type impurity is aluminum because aluminum has a higher activation rate.
[0028] In some embodiments of the present invention, the depth of the well region is 0.7 to 1.1 μm.
[0029] In some embodiments of the present invention, the N-type impurity is either nitrogen or phosphorus.
[0030] In some preferred embodiments of the present invention, the N-type impurity is nitrogen.
[0031] In some embodiments of the present invention, the depth of the N-type heavily doped region is 0.3 to 0.6 μm.
[0032] In some embodiments of the present invention, the depth of the P-type heavily doped region is between the depth of the N-type heavily doped region and the depth of the well region.
[0033] In some embodiments of the present invention, before the etching, step S3 requires the deposition of a hard mask, specifically including: depositing a first hard mask in the edge region (i.e., the part other than the middle region) of the upper surface of the well region, etching the middle region of the upper surface of the well region, opening a window, and injecting N-type impurities into the window to form the heavily doped N-type region (source); using an etching process to remove the first hard mask, depositing a second hard mask above the heavily doped N-type region, etching the region on the upper surface of the well region and the regions on both sides of the heavily doped N-type region, opening a window, and injecting P-type impurities into the window to form the heavily doped P-type region.
[0034] Specifically, the first hard mask is deposited to block and protect against N-type impurity implantation, and the second hard mask is deposited to block and protect against P-type impurity implantation.
[0035] In some embodiments of the present invention, the hard mask is deposited using chemical vapor deposition (CVD).
[0036] In some embodiments of the present invention, the deposition method of the hard mask is any one of low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD).
[0037] In some preferred embodiments of the present invention, the hard mask is deposited using low-pressure chemical vapor deposition.
[0038] In some embodiments of the present invention, the thickness of the hard mask is 1.5 to 2 μm.
[0039] In some embodiments of the present invention, step S3 involves ion implantation to implant the N-type impurity and the P-type impurity.
[0040] In some embodiments of the present invention, two virtual trenches are symmetrically formed on both sides of the gate trench.
[0041] In some embodiments of the present invention, the upper part of the virtual trench is located between the heavily doped N-type region and the heavily doped P-type region. That is, when etching the virtual trench, a portion of the heavily doped N-type region and a portion of the heavily doped P-type region are etched in the doped region, and the portion of the heavily doped N-type region is the area on both sides of the heavily doped N-type region.
[0042] In some embodiments of the present invention, the ratio of the depth to the width of the trench is 1 to 2:1.
[0043] In some preferred embodiments of the invention, the ratio of the depth to the width of the trench is 1:1.
[0044] In some embodiments of the present invention, the depth of the trench is 1 to 2 μm.
[0045] In some embodiments of the present invention, before forming each trench, step S4 requires the deposition of a hard mask, specifically including: removing the second hard mask in step S3 using an etching process; depositing a third hard mask above the doped region; etching both sides of the heavily doped N-type region to open a first window on each side to form the virtual trench; injecting P-type impurities into the bottom of the virtual trench to form a bottom P-type heavily doped layer; removing the third hard mask using an etching process; depositing a fourth hard mask above the doped region and the bottom P-type heavily doped layer; further etching the portion of the virtual trench corresponding to the doped region and the well region to form a second window; and injecting P-type impurities into the second window to form a sidewall P-type heavily doped layer.
[0046] In some embodiments of the present invention, the second window is located above the first window.
[0047] In some embodiments of the present invention, the width of the second window is greater than the width of the first window, the depth of the second window is less than the depth of the first window, and greater than the depth of the well region.
[0048] In some embodiments of the present invention, the sidewall P-type heavily doped layer and the bottom P-type heavily doped layer are connected to form the P-type heavily doped layer.
[0049] In some embodiments of the present invention, the width of the sidewall P-type heavily doped layer does not exceed 0.5 μm.
[0050] In some embodiments of the present invention, the sidewall P-type heavily doped layer does not extend beyond the top of the semiconductor epitaxial layer in the depth direction.
[0051] In some embodiments of the present invention, step S4 involves implanting the P-type impurity using ion implantation.
[0052] In some embodiments of the present invention, the oxide filled into the interior of the virtual trench in step S4 is silicon dioxide.
[0053] In some embodiments of the present invention, the method for filling the oxide in step S4 is chemical vapor deposition.
[0054] Specifically, the fourth hard mask is removed by an etching process, and then the oxide is filled in.
[0055] In some embodiments of the invention, step S4 further includes etching away the oxide beyond the virtual trench and the doped region.
[0056] In some embodiments of the present invention, in step S4, a fifth hard mask is first deposited in the doped region, and then the gate trench is etched to form it.
[0057] In some embodiments of the present invention, after the gate trench is formed, step S4 involves removing the fifth hard mask using an etching process.
[0058] In some embodiments of the present invention, step S4 further includes forming a gate oxide layer on the sidewalls and bottom of the gate trench. The specific method includes: first performing sacrificial oxidation, and then growing the gate oxide layer using a thermal oxidation process.
[0059] In some embodiments of the present invention, the gate oxide layer is a silicon dioxide layer.
[0060] In some embodiments of the present invention, the thickness of the gate oxide layer may be adjusted as needed, and no limitation is made here.
[0061] In some embodiments of the present invention, after forming the gate oxide layer, step S4 further includes depositing a polysilicon layer inside the gate trench.
[0062] In some embodiments of the present invention, step S4, after depositing the polysilicon layer, further includes etching away the gate oxide layer and the polysilicon layer that extend beyond the trench and the doped region.
[0063] In some embodiments of the present invention, the hard mask mentioned above comprises any one of silicon dioxide, silicon nitride, and polycrystalline silicon.
[0064] In some embodiments of the present invention, step S5 further includes depositing a dielectric layer over the gate trench before forming the metal layer.
[0065] In some embodiments of the present invention, the width of the dielectric layer is greater than the width of the gate trench.
[0066] In some embodiments of the present invention, the material for depositing the dielectric layer includes any one of doped silicon dioxide, undoped silicon dioxide, and silicon nitride.
[0067] In some embodiments of the present invention, step S5 uses a sputtering process to form the metal layer.
[0068] In some preferred embodiments of the present invention, step S5 uses a front-side metal sputtering process and a photolithography process to form the metal layer.
[0069] In some embodiments of the present invention, the material of the metal layer includes either aluminum or tungsten.
[0070] In some preferred embodiments of the present invention, the material of the metal layer is aluminum.
[0071] The dual-trench MOS field-effect transistor fabricated according to the above method includes:
[0072] A semiconductor substrate layer and a semiconductor epitaxial layer are stacked sequentially.
[0073] Well regions, which are stacked on the semiconductor epitaxial layer;
[0074] The doped region is disposed on the well region; the doped region includes an N-type heavily doped region and a P-type heavily doped region, with the P-type heavily doped region disposed on both sides of the N-type heavily doped region;
[0075] The trench includes a gate trench and two dummy trenches. The gate trench is located at the center and extends from the top of the N-type heavily doped region to the semiconductor epitaxial layer. A dummy trench is provided on each side of the gate trench. The dummy trench extends from the top of the doped region to the semiconductor epitaxial layer. The sidewalls and bottom of the dummy trench are provided with P-type heavily doped layers. The interior of the dummy trench is filled with oxide.
[0076] A metal layer located on the side of the doped region away from the semiconductor epitaxial layer.
[0077] In some embodiments of the present invention, the sidewalls and bottom of the gate trench are provided with a gate oxide layer, and a polysilicon layer is deposited inside.
[0078] In some embodiments of the present invention, the dual-trench MOS field-effect transistor further includes a dielectric layer disposed above the gate trench.
[0079] According to a second aspect of the present invention, an electronic device is provided, comprising a dual-trench MOS field-effect transistor fabricated according to the fabrication method. Attached Figure Description
[0080] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein:
[0081] Figure 1 This is a flowchart illustrating the fabrication of a dual-trench MOS field-effect transistor in Embodiment 1 of the present invention;
[0082] Figure 2 This is a schematic diagram of the structure of the MOS field-effect transistor prepared in Comparative Example 1 of the present invention.
[0083] Figure label:
[0084] 1-Silicon carbide substrate; 2-N-type silicon carbide epitaxial layer; 3-P-well region; 4-First hard mask; 5-N-type heavily doped region; 6-Second hard mask; 7-P-type heavily doped region; 8-Third hard mask; 9-Virtual trench; 10-Bottom P-type heavily doped layer; 11-Fourth hard mask; 12-Sidewall P-type heavily doped layer; 13-Silicon dioxide; 14-Fifth hard mask; 15-Gate trench; 16-Silicon dioxide layer; 17-Polysilicon layer; 18-Dielectric layer; 19-Metal layer. Detailed Implementation
[0085] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0086] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.
[0087] In the description of this invention, terms such as greater than, less than, and exceeding are understood to exclude the stated number, while terms such as above, below, and within are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.
[0088] In the description of this invention, unless otherwise explicitly defined, terms such as etching and deposition should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.
[0089] In the description of this invention, references to terms such as "one embodiment," "some embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments.
[0090] Unless otherwise specified, the experimental methods used in the examples are conventional methods; unless otherwise specified, the materials and reagents used are commercially available.
[0091] Example 1
[0092] This embodiment fabricates a dual-trench MOS field-effect transistor. The specific process is detailed in (see [link to documentation]). Figure 1 The a~r) are:
[0093] (1) A silicon carbide substrate 1 is provided, and an N-type silicon carbide epitaxial layer 2 is formed on the silicon carbide substrate 1. The concentration of the N-type silicon carbide epitaxial layer 2 is 1×10⁻⁶. 16 cm -3 The thickness is 15μm.
[0094] (2) P-type aluminum impurities are implanted above the N-type silicon carbide epitaxial layer 2 by ion implantation to form a P-well region 3 with a depth of 1 μm.
[0095] (3) A first hard mask 4 (1.5 μm thick) is deposited on the edge region (i.e., the part outside the middle region) of the upper surface of the P-well region 3 using low-pressure LPCVD to block and protect against N-type impurity implantation. The middle region of the upper surface of the P-well region 3 is photolithographically etched to open the window. A high concentration of N-type impurity nitrogen is implanted into the window using ion implantation to form an N-type heavily doped region 5 with a depth of 0.5 μm. The first hard mask 4 is stripped by etching. A second hard mask 6 (1.5 μm thick) is deposited on the N-type heavily doped region 5 using LPCVD to block and protect against P-type impurity implantation. The regions on the upper surface of the P-well region 3 and on both sides of the N-type heavily doped region 5 are photolithographically etched to open the window. A high concentration of P-type impurity aluminum is implanted into the window using ion implantation to form a P-type heavily doped region 7 with a depth of 0.7 μm. The N-type heavily doped region 5 and the P-type heavily doped region 7 together constitute the doped region.
[0096] (4) The second hard mask 6 is removed using an etching process. A third hard film 8 (1.5 μm thick) is deposited above the doped region using LPCVD. Photolithography is performed on both sides of the heavily doped N-type region 5 to create a first window on each side, followed by etching to form virtual trenches 9 (two virtual trenches 9 are symmetrical). The virtual trenches 9 extend from the top of the doped region to the N-type silicon carbide epitaxial layer 2 (specifically, the upper part of the virtual trenches 9 is located between the heavily doped N-type region 5 and the heavily doped P-type region 7; that is, when etching the virtual trenches 9, a portion of the heavily doped N-type region 5 and a portion of the heavily doped P-type region 7 are etched in the doped region). A high concentration of P-type aluminum impurities is implanted into the bottom of the virtual trenches 9 using ion implantation to form a bottom heavily doped P-type layer 10. The third hard mask 8 is removed using an etching process. A fourth hard mask 11 (1.5 μm thick) is deposited above the doped region and the bottom P-type heavily doped layer 10. Further photolithography and etching are performed on the portion of the virtual trench 9 corresponding to the doped region and P-well region 3 to form a second window (located above the first window; the width of the second window is greater than the width of the first window, and its depth is less than the depth of the first window but greater than the depth of the P-well region 3). High-concentration P-type aluminum impurities are implanted into the second window using ion implantation to form a sidewall P-type heavily doped layer 12. The sidewall P-type heavily doped layer 12 does not extend beyond the top of the N-type silicon carbide epitaxial layer 2 in the depth direction. The sidewall P-type heavily doped layer 12 (0.1 μm wide) and the bottom P-type heavily doped layer 10 are connected to form a P-type heavily doped layer. The fourth hard mask 11 is removed using an etching process. Silicon dioxide 13 is filled inside the virtual trench 9 using a CVD process. The silicon dioxide 13 extending beyond the virtual trench 9 and the doped region is etched away.
[0097] A fifth hard mask 14 (2 μm thick) is deposited in the doped region using LPCVD. A gate trench 15 is formed by photolithography and etching processes. The gate trench 15 extends from the top of the N-type heavily doped region 5 to the N-type silicon carbide epitaxial layer 2. The fifth hard mask 14 is removed by etching. Sacrificial oxidation is performed first, and then thermal oxidation is used to grow a silicon dioxide layer 16 (gate oxide layer) on the sidewalls and bottom of the gate trench 15. A polysilicon layer 17 is deposited inside the gate trench 15 so that the polysilicon layer 17 fills the interior of the gate trench 15. The silicon dioxide layer 16 and the polysilicon layer 17 that extend beyond the trench and the doped region are removed by etching.
[0098] The two virtual trenches 9 are symmetrically formed on both sides of the gate trench 15, and the virtual trenches 9 and the gate trench 15 together constitute the trench structure.
[0099] (5) A dielectric layer 18 (material is doped silicon dioxide) is deposited above the gate trench 15, the width of which is greater than the width of the gate trench 15; lead holes are formed by photolithography above the P-type heavily doped region 7 and the N-type heavily doped region 5.
[0100] A metal layer 19 (made of aluminum) is formed on the side of the doped region and dielectric layer 18 away from the N-type silicon carbide epitaxial layer 2 using front-side metal sputtering and photolithography. The metal layer 19 is then annealed in a furnace tube at 400°C to allow the metal in the lead hole to form a good ohmic contact with the semiconductor. Then, the silicon carbide substrate layer 1 is thinned on the back side and metallized on the back side.
[0101] The above steps form a dual-trench MOS field-effect transistor, including: a silicon carbide substrate layer 1 and an N-type silicon carbide epitaxial layer 2 stacked sequentially;
[0102] P-well region 3 is stacked on N-type silicon carbide epitaxial layer 2;
[0103] The doped region is disposed on the P-well region 3; including the N-type heavily doped region 5 and the P-type heavily doped region 7, with the P-type heavily doped region 7 disposed on both sides of the N-type heavily doped region 5.
[0104] The trench includes a gate trench 15 and two dummy trenches 9. The gate trench 15 is located at the center and extends from the top of the N-type heavily doped region 5 to the N-type silicon carbide epitaxial layer 2. The sidewalls and bottom of the gate trench 15 are provided with silicon dioxide layers 16 (gate oxide layers), and a polysilicon layer 17 is deposited inside. A dummy trench 9 is provided on each side of the gate trench 15. The dummy trench 9 extends from the top of the doped region to the N-type silicon carbide epitaxial layer 2. The dummy trench 9 includes a bottom P-type heavily doped layer 10 and a sidewall P-type heavily doped layer 12. The interior of the dummy trench 9 is filled with silicon dioxide 13.
[0105] The dielectric layer 18 is located above the gate trench 15;
[0106] Metal layer 19 is located on the side of the doped region and dielectric layer 18 away from N-type silicon carbide epitaxial layer 2.
[0107] In the aforementioned dual-trench MOS field-effect transistor, the gate trench and channel structure that affect current conduction capability are not significantly changed, and the channel resistance does not increase. Meanwhile, since this embodiment forms two virtual trenches on both sides of the gate trench, fills the virtual trenches with oxide, and forms a P-type heavily doped layer at the bottom and sidewalls of the virtual trenches, it can shield the strong electric field near the gate trench, providing good protection for the gate trench and improving the reliability of the gate oxide.
[0108] Comparative Example 1
[0109] This comparative example fabricates a MOS field-effect transistor. The difference between this example and Example 1 is that the MOS field-effect transistor in Comparative Example 1 does not have two virtual trenches.
[0110] The specific preparation process is the same as in Example 1.
[0111] The structure of the MOS field-effect transistor in Comparative Example 1 is as follows: Figure 2 As shown, the MOS field-effect transistor comprises: a silicon carbide substrate layer and a silicon carbide epitaxial layer stacked sequentially.
[0112] P-well regions are stacked on silicon carbide epitaxial layers;
[0113] The doped region is located on the P-well region; it includes an N-type heavily doped region and a P-type heavily doped region, with the P-type heavily doped region located on both sides of the N-type heavily doped region.
[0114] The trench includes a gate trench located at the center, extending from the top of the N-type heavily doped region to the silicon carbide epitaxial layer, with silicon dioxide (gate oxide) layers disposed on the sidewalls and bottom of the gate trench, and a polysilicon layer deposited inside.
[0115] The dielectric layer is located above the gate trench;
[0116] The metal layer is located on the side of the doped region and dielectric layer away from the silicon carbide epitaxial layer.
[0117] This MOS field-effect transistor does not have a virtual trench, only a gate trench. The gate oxide layer of the gate trench has a uniform thickness, especially on the two sidewalls; and to obtain a higher conduction current capability, the gate oxide layer is usually relatively thin. However, high electric fields tend to appear at the corners of the gate trench, which reduces the reliability of the gate oxide layer under high electric field conditions, and may even cause it to break down directly. Simply increasing the thickness of the gate oxide layer would significantly increase the on-resistance of the gate trench, severely affecting device performance.
[0118] It is evident that the MOS field-effect transistor in Comparative Example 1 has certain drawbacks.
[0119] The embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof can be combined with each other unless otherwise specified.
Claims
1. A method for fabricating a dual-trench MOS field-effect transistor, characterized in that, Includes the following steps: S1: Provide a semiconductor substrate layer, and form a semiconductor epitaxial layer on the semiconductor substrate layer; S2: A well region is formed above the semiconductor epitaxial layer; S3: Etch the middle region of the upper surface of the well region and implant N-type impurities into the middle region to form an N-type heavily doped region; The upper surface of the well region and the areas on both sides of the N-type heavily doped region are etched, and P-type impurities are implanted into the region to form a P-type heavily doped region; the N-type heavily doped region and the P-type heavily doped region constitute a doped region; S4: Etch a virtual trench on each side of the heavily doped N-type region, so that the virtual trench extends from the top of the doped region to the semiconductor epitaxial layer, and inject P-type impurities into the bottom and sidewalls of the virtual trench to form a heavily doped P-type layer. The interior of the virtual trench is filled with oxide; a gate trench is etched in the middle region of the heavily doped N-type region, such that the gate trench extends from the top of the heavily doped N-type region to the semiconductor epitaxial layer; at this time, the following trench is formed: a gate trench, and a virtual trench is formed on each side of the gate trench; S5: A metal layer is formed on the side of the doped region away from the semiconductor epitaxial layer.
2. The preparation method according to claim 1, characterized in that, In step S4, when etching the virtual trench, a portion of the heavily doped N-type region and a portion of the heavily doped P-type region are etched in the doped region.
3. The preparation method according to claim 1, characterized in that, In step S4, the oxide filled into the interior of the virtual trench is silicon dioxide.
4. The preparation method according to claim 3, characterized in that, The method for filling the oxide is chemical vapor deposition.
5. The preparation method according to claim 1, characterized in that, Step S4 further includes forming a gate oxide layer on the sidewalls and bottom of the gate trench. The specific method includes: first performing sacrificial oxidation, and then growing the gate oxide layer using a thermal oxidation process.
6. The preparation method according to claim 5, characterized in that, The gate oxide layer is a silicon dioxide layer.
7. The preparation method according to claim 5, characterized in that, Step S4, after forming the gate oxide layer, also includes depositing a polysilicon layer inside the gate trench.
8. The preparation method according to claim 1, characterized in that, The raw materials for preparing the semiconductor substrate include silicon carbide and silicon.
9. The preparation method according to claim 8, characterized in that, The raw materials for preparing the semiconductor epitaxial layer include either silicon carbide or silicon.
10. The preparation method according to claim 8, characterized in that, The concentration of the semiconductor epitaxial layer is 1×10⁻⁶. 15 ~1×10 17 cm -3 Thickness < 20 μm.
11. The preparation method according to claim 1, characterized in that, Step S2 involves forming the well region above the semiconductor epitaxial layer using ion implantation.
12. The preparation method according to claim 11, characterized in that, Step S2 forms a P-well region by implanting a P-type impurity over the semiconductor epitaxial layer.
13. The preparation method according to claim 12, characterized in that, The P-type impurity is either aluminum or boron.
14. The preparation method according to claim 11, characterized in that, The depth of the well region is 0.7~1.1μm.
15. The preparation method according to claim 1, characterized in that, The N-type impurity mentioned in step S3 is either nitrogen or phosphorus.
16. The preparation method according to claim 15, characterized in that, The depth of the N-type heavily doped region is 0.3~0.6μm.
17. The preparation method according to claim 15, characterized in that, The depth of the P-type heavily doped region is between the depths of the N-type heavily doped region and the well region.
18. The preparation method according to claim 1, characterized in that, Step S5 further includes depositing a dielectric layer over the gate trench before forming the metal layer.
19. The preparation method according to claim 18, characterized in that, The width of the dielectric layer is greater than the width of the gate trench.
20. The preparation method according to claim 18, characterized in that, The material used to deposit the dielectric layer includes any one of doped silicon dioxide, undoped silicon dioxide, and silicon nitride.
21. The preparation method according to claim 1, characterized in that, Step S5 uses a sputtering process to form the metal layer.
22. The preparation method according to claim 21, characterized in that, The material of the metal layer includes either aluminum or tungsten.
23. An electronic device, characterized in that, The electronic device includes a dual-trench MOS field-effect transistor prepared by the preparation method according to any one of claims 1 to 22.