Characteristic current transmission circuit based on primary and secondary fusion equipment graphic model checking system

Abstract

The application belongs to the technical field of accurate checking of power distribution lines, and particularly relates to a characteristic current sending circuit based on a primary and secondary fusion equipment graph model checking system, comprising an isolation DC-DC power supply circuit, a characteristic current signal sending circuit and a PT overvoltage protection circuit. The application is suitable for high-precision automatic topology and checking of power distribution lines. The circuit has the functions of inhibiting PT overvoltage pulses and adjusting the frequency of characteristic current sending, ensures accurate and reliable sending of characteristic current signals, and improves the accuracy and reliability of topology identification.

Description

Technical Field

[0001] This invention belongs to the field of power distribution line precision verification technology, specifically relating to a characteristic current sending circuit based on a primary and secondary fusion equipment diagram verification system. Background Technology

[0002] In power systems, accurate verification of distribution lines is crucial for ensuring the safe and stable operation of the power grid. Traditional verification methods often suffer from insufficient accuracy and operational complexity. In recent years, with the development of power automation technology, verification methods based on characteristic current signals have gradually gained attention. However, existing technologies still have many shortcomings in the generation and control of characteristic current signals, such as: It requires signal strength analysis or algorithm processing, is greatly affected by changes in line load, and has poor signal stability.

[0003] Most filters suppress harmonics, but high-frequency signals are susceptible to power grid fluctuations and attenuate quickly. The verification range is usually less than 5km, resulting in a short transmission distance.

[0004] It needs to integrate feedback acquisition modules, signal processing modules, communication modules, etc., and the equipment is relatively large. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the inventors, through long-term practical research, designed a characteristic current transmission circuit based on a primary and secondary fusion equipment pattern verification system. The aim is to provide an efficient and stable characteristic current transmission circuit for power distribution line topology identification, suitable for high-precision automated topology verification of power distribution lines. This circuit has the functions of suppressing PT overvoltage pulses and adjustable characteristic current transmission frequency, ensuring accurate and reliable transmission of characteristic current signals and improving the accuracy and reliability of topology identification.

[0006] The characteristic current transmitting circuit of the primary and secondary fusion equipment pattern verification system of the present invention includes an isolated DC-DC power supply circuit, a characteristic current signal transmitting circuit, and a PT overvoltage protection circuit. The isolated DC-DC power supply circuit includes an input power processing module, a chip enable control module, a transformer isolation module, and an output rectification and filtering module. The characteristic current signal transmitting circuit consists of a signal input section, a power drive section, and a signal transmitting section. The PT overvoltage protection circuit consists of an optocoupler isolation module, a power control and overvoltage absorption module, and an overvoltage rectification and filtering module.

[0007] Signal input section: The PWM signal from the MCU is used as the input and is connected to the anode of the photodiode of the optocoupler O1 through resistor R8. The cathode of the photodiode of the optocoupler O1 is grounded to GND.

[0008] Power drive section: The collector of the optotransistor in optocoupler O1 is connected to the gate of field-effect transistor VT1. The emitter of the optotransistor in optocoupler O1 is grounded to GNDP. The gate of field-effect transistor VT1 is connected to a +12V power supply through resistor R4. Zener diode VP1 is connected in reverse parallel across field-effect transistor VT1. The drain of field-effect transistor VT1 is connected to the cathode of Zener diode VP1. The anode of Zener diode VP1 and the source of field-effect transistor VT1 are both grounded to GNDP.

[0009] Signal transmission section: Rectifier bridge BR1 is connected between the L line and the N line. The positive output terminal of rectifier bridge BR1 is connected to the drain of the field-effect transistor VT1, and the negative output terminal of rectifier bridge BR1 is grounded to GNDP. Capacitor C7 is connected in series between rectifier bridge BR1 and the L line of PT.

[0010] Furthermore, in the isolated DC-DC power supply circuit: Input power processing module: It takes +5V power as input, one end is connected to the VIN pin of the chip, and the other end is grounded to GND through capacitor C5.

[0011] Chip enable control module: The EN pin of the chip is connected to the +5V power supply through resistor R3, and the EN pin of the chip is grounded to GND through resistor R7. A capacitor C8 is connected in parallel across resistor R7.

[0012] Transformer isolation module: Pin 4 of transformer BT1 is connected to the SW pin of the chip, and pin 5 is connected to the node after resistor R5 of the FB pin of the chip.

[0013] Output rectifier and filter module: Pin 3 of transformer BT1 is connected to the anode of diode VD1. The cathode of diode VD1 is connected in parallel with capacitors C3 and C4, and resistor R2 and capacitor C2. Pin 1 of transformer BT1, the other end of capacitor C3, and the other end of capacitor C4 are all grounded to GNDP. The other end of resistor R2 and the other end of capacitor C2 are also grounded to GNDP.

[0014] Furthermore, the isolated DC-DC power supply circuit also includes a bootstrap circuit, consisting of capacitor C1 and resistor R1. The BST pin of the chip is connected to the SW pin of the chip through the bootstrap circuit consisting of capacitor C1 and resistor R1.

[0015] Furthermore, the isolated DC-DC power supply circuit also includes a feedback network consisting of resistors R5 and R6 and capacitor C6. The FB pin of the chip is connected to pin 5 of the transformer BT1 through resistor R5, and resistor R6 and capacitor C6 are connected in parallel between the FB pin of the chip and ground GND.

[0016] Furthermore, the optocoupler isolation module includes an optocoupler O2. One end of the TM_BH pin in the optocoupler isolation module is connected to the MCU, and the other end of the TM_BH pin is connected to the collector of the optotransistor of the optocoupler O2. The emitter of the optotransistor of the optocoupler O2 is grounded to GND. A +5V power supply is connected to the collector of the optotransistor of the optocoupler O2 through a resistor R11, and a +12V power supply is connected to the anode of the photodiode of the optocoupler O2 through a resistor R12. The cathode of the photodiode of the optocoupler O2 is connected to the drain of the field-effect transistor VT3.

[0017] Furthermore, the power control and overvoltage absorption module includes a field-effect transistor VT3, a field-effect transistor VT2, a Zener diode VD2, resistors R9, R10, R13, and R14.

[0018] The gate of the field-effect transistor VT3 is connected to resistors R9 and R14 through resistor R13. The other end of resistor R14 is grounded to GNDP at the same time as the source of the field-effect transistor VT3.

[0019] The gate of the field-effect transistor VT2 is connected in parallel with a Zener diode VD2 and a resistor R10, and then connected between resistors R13 and R14. The cathode of the Zener diode VD2 is connected to the gate of the field-effect transistor VT2. The anode of the Zener diode VD2, the resistor R10, and the source of the field-effect transistor VT2 are all grounded to GNDP. The drain of the field-effect transistor VT2 is connected to a resistor RL.

[0020] Furthermore, the overvoltage rectification and filtering module includes a rectifier bridge BR2, which is connected between the L line and the N line. The positive output terminal of the rectifier bridge BR2 is connected in sequence to a capacitor C9, a resistor R9, and then to a resistor RL. The negative output terminal of the rectifier bridge BR2 and the other end of the capacitor C9 are simultaneously grounded to GNDP. A capacitor C10 is connected in series with the resistor R9, and the other end of the capacitor C10 is grounded to GNDP.

[0021] Furthermore, the capacitor C7 is a load capacitor with a capacitance range of 2μF to 20μF.

[0022] Furthermore, the L line and N line are connected to the AC 220V, 50Hz power supply from the PT, and the characteristic current signal is coupled to the 10KV side through the PT.

[0023] 1) By coordinating the design of safety capacitors (2μF~20μF) and the secondary side of PT (voltage transformer), a low-frequency characteristic current in the range of 100Hz~1KHZ is generated. Taking advantage of the physical characteristic that the current tends to the point of lowest impedance, no complex algorithm is required.

[0024] 2) Low-frequency current has stronger anti-harmonic interference capability, less waveform distortion, and longer transmission distance; and low-frequency current transmission attenuation is small, extending the verification range to 10-15km, covering complex urban and rural networks.

[0025] 3) The characteristic current generation circuit is integrated inside the primary and secondary fusion terminal or other network-connected equipment, without the need for external devices, resulting in lower overall hardware costs. Attached Figure Description

[0026] Figure 1 This is the overall schematic diagram of the characteristic current transmitting circuit of the present invention.

[0027] Figure 2 This is a schematic diagram of the isolated DC-DC power supply circuit of the characteristic current transmission circuit of the present invention.

[0028] Figure 3 This is a schematic diagram of the characteristic current signal transmission circuit of the characteristic current transmission circuit of the present invention.

[0029] Figure 4 This is a schematic diagram of the PT overvoltage protection circuit of the characteristic current transmitting circuit of the present invention. Detailed Implementation

[0030] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. These embodiments are described in sufficient detail to enable those skilled in the art to understand and practice the invention. Logical, implementation, and other changes may be made to the embodiments without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the invention is defined solely by the claims.

[0031] See Figure 1 This invention proposes a characteristic current transmitting circuit based on a primary and secondary fusion equipment pattern verification system, including an isolated DC-DC power supply circuit, a characteristic current signal transmitting circuit, and a PT overvoltage protection circuit. In this circuit, the power extraction coil of the PT is connected to a 220V voltage, and the characteristic current PWM signal is generated by the MCU (microcontroller) and the protection signal is processed.

[0032] See Figure 2 The schematic diagram of the isolated DC-DC power supply circuit of the current transmission circuit of the present invention shows the power conversion and output structure. The isolated DC-DC power supply circuit provides 12V power to the subsequent circuits.

[0033] The isolated DC-DC power supply circuit includes an input power processing module, a chip enable control module, a transformer isolation module, and an output rectification and filtering module.

[0034] Input power processing module: It uses a +5V power supply as input, with one end connected to the chip's VIN pin (pin 3), and the other end grounded to GND through capacitor C5. Capacitor C5 acts as a filter, removing high-frequency noise from the input power supply to ensure its purity and provide a good power environment for stable chip operation.

[0035] Chip enable control module: The chip's EN pin (pin 5) is connected to a +5V power supply via resistor R3, and pulled up to +5V through resistor R3. Simultaneously, the chip's EN pin is pulled down to ground (GND) through resistor R7. A capacitor C8 is connected in parallel across resistor R7. This configuration ensures a stable enable signal to the chip's EN pin, guaranteeing the chip's operation under appropriate conditions. Resistors R3 and R7 form a voltage divider circuit, and capacitor C8 further stabilizes the EN pin voltage, preventing voltage fluctuations from interfering with the chip's enable state.

[0036] The isolated DC-DC power supply circuit also includes a bootstrap circuit, consisting of capacitor C1 and resistor R1. The chip's BST pin (pin 6) is connected to the chip's SW pin (pin 2) through the bootstrap circuit composed of capacitor C1 and resistor R1. The function of the bootstrap circuit is to provide a drive voltage higher than the input voltage to the internal switching transistor's drive circuit when the chip is operating, ensuring that the switching transistor can reliably turn on and off, thereby improving the chip's operating efficiency.

[0037] The isolated DC-DC power supply circuit also includes a feedback network consisting of resistors R5 and R6, and capacitor C6. The chip's FB pin (pin 4) is connected to pin 5 of transformer BT1 via resistor R5, while resistor R6 and capacitor C6 are connected in parallel between the FB pin and ground (GND). This feedback network detects changes in the output voltage and feeds the voltage signal back to the chip's internal control circuit. By adjusting the operating state of the internal switching transistors, stable control of the output voltage is achieved.

[0038] Transformer Isolation Module: Transformer BT1 is the key component for achieving electrical isolation. Pin 4 of transformer BT1 is connected to the SW pin (pin 2) of the chip, and pin 5 is connected to the node after resistor R5 through the FB pin (pin 4) of the chip. Through the electromagnetic induction principle of the transformer, energy is transferred from the primary side (the side connected to the chip) to the secondary side, while simultaneously achieving electrical isolation between the primary and secondary sides, effectively preventing electrical interference and leakage risks between the two circuits.

[0039] Output Rectifier and Filter Module: Pin 3 of transformer BT1 is connected to the anode of diode VD1. Utilizing the unidirectional conductivity of the diode, the alternating voltage output from the secondary side of the transformer is rectified into a direct current voltage, ensuring current flow in only one direction and providing suitable input for subsequent filter circuits. Capacitors C3 and C4, and resistors R2 and C2 are connected in parallel at the cathode output of diode VD1. Capacitors C3 and C4 in parallel form a primary filter circuit, filtering out high-frequency ripple components in the rectified DC voltage. Resistor R2 and capacitor C2 in parallel further stabilize the output voltage, filtering out low-frequency ripple, ultimately outputting a stable +12V DC power supply. Pin 1 of transformer BT1, the other end of capacitor C3, and the other end of capacitor C4 are simultaneously grounded to GNDP. The other end of resistor R2 and the other end of capacitor C2 are also simultaneously grounded to GNDP.

[0040] In an isolated DC-DC power supply circuit, the output ground is GNDP, which is isolated from the input ground GND to ensure the circuit's isolation performance.

[0041] This isolated DC-DC power supply circuit is designed to convert an input +5V power supply to an output +12V power supply, and uses transformer BT1 to achieve electrical isolation, ensuring the safe and stable operation of the circuit. The circuit outputs a stable 12V power supply, specifically for driving MOSFET VT1, providing reliable power support for the transmission of characteristic current signals and ensuring the stable operation of subsequent circuits.

[0042] See Figure 3 This invention presents a schematic diagram of the characteristic current signal transmission circuit, illustrating PWM wave input, optocoupler control, MOSFET drive, and load capacitor connection to generate and transmit the characteristic current signal. The PWM wave is output by the MCU, and this circuit supports transmitting characteristic current signal frequencies from 100Hz to 1kHz. The characteristic current signal transmitting circuit mainly consists of a signal input section, a power drive section, and a signal transmitting section, and is used to convert control signals into specific current signals and send them to external circuits.

[0043] Signal Input Section: The PWM signal from the MCU is used as input and connected to the anode of the photodiode in optocoupler O1 via resistor R8. The cathode of the photodiode in optocoupler O1 is grounded to GND. Optocoupler O1 provides electrical isolation, connecting the input PWM signal to its input terminal, isolating and converting the input PWM signal to prevent electrical interference between upstream and downstream circuits, while ensuring effective signal transmission. The output of optocoupler O1 is connected to subsequent circuitry.

[0044] Power drive section: The collector of the optotransistor in optocoupler O1 is connected to the gate of the field-effect transistor VT1, and the emitter of the optotransistor in optocoupler O1 is grounded to GNDP. The gate of the field-effect transistor VT1 is connected to a +12V power supply through resistor R4, which is output from an isolated DC-DC power supply circuit. The output signal of optocoupler O1 controls the conduction and cutoff of the field-effect transistor VT1. When the optocoupler output turns on the field-effect transistor VT1, the +12V power supply provides drive current to the field-effect transistor VT1 through resistor R4. Resistor R4 acts as a voltage pull-up resistor, ensuring reliable conduction of the field-effect transistor VT1.

[0045] A Zener diode VP1 is connected in reverse parallel across the MOSFET VT1. The drain of MOSFET VT1 is connected to the cathode of Zener diode VP1, and the anode of Zener diode VP1 and the source of MOSFET VT1 are both grounded to GNDP. Zener diode VP1 is used to suppress the reverse voltage spike generated when MOSFET VT1 is turned off, protecting MOSFET VT1 from breakdown.

[0046] Signal transmission section: Rectifier bridge BR1 is connected between the L and N lines. The L and N lines are connected to the 220V, 50Hz AC power supply from the PT. The characteristic current signal is coupled to the 10KV side through the PT. The positive output terminal of rectifier bridge BR1 is connected to the drain of MOSFET VT1, and the negative output terminal of rectifier bridge BR1 is grounded to GNDP. Capacitor C7 is connected in series between rectifier bridge BR1 and the L line of the PT. Capacitor C7 is a load capacitor with a capacitance range of 2μF~20μF, which can be adjusted according to actual needs to generate a stable characteristic signal frequency.

[0047] When the field-effect transistor VT1 is turned on, the current is rectified by the rectifier bridge BR1. The capacitor C7 is connected in series in the circuit. When VT1 is turned on, the capacitor C7 acts as a capacitive load to generate a specific capacitive current, and finally sends the characteristic current signal to the external circuit to realize the output function of the specific current signal.

[0048] In this characteristic current signal transmission circuit, GNDP is the ground terminal of the power drive section, which is isolated from the input signal ground terminal GND to ensure stable circuit operation.

[0049] See Figure 4 This invention presents a schematic diagram of a PT overvoltage protection circuit within a characteristic current transmitting circuit. This circuit is primarily used to monitor and suppress overvoltages generated by the PT, protecting subsequent circuits from excessive voltage surges. The circuit receives signals from the MCU to control the operation of power devices, and, in conjunction with rectification, filtering, and absorption circuits, achieves overvoltage protection.

[0050] The PT overvoltage protection circuit mainly consists of an optocoupler isolation module, a power control and overvoltage absorption module, and an overvoltage rectification and filtering module.

[0051] Optocoupler isolation module: One end of the TM_BH pin is connected to the MCU to receive its overvoltage detection signal. The other end of the TM_BH pin is connected to the output of optocoupler O2, specifically, the other end of the TM_BH pin is connected to the collector of the optotransistor of optocoupler O2. The emitter of the optotransistor of optocoupler O2 is grounded to GND.

[0052] The +5V power supply is connected to the collector of the optotransistor in optocoupler O2 via resistor R11, providing bias voltage to the output of optocoupler O2. The +12V power supply is connected to the anode of the photodiode in optocoupler O2 via resistor R12, providing bias voltage to the input of optocoupler O2. The cathode of the photodiode in optocoupler O2 is connected to the drain of field-effect transistor VT3.

[0053] Optocoupler O2 provides electrical isolation, preventing electrical interference between the MCU circuit and subsequent power circuits and ensuring reliable signal transmission. The input signal of optocoupler O2 controls the conduction and cutoff of the field-effect transistor VT3.

[0054] Power control and overvoltage absorption module: The gate of MOSFET VT3 is connected to resistors R9 and R14 via resistor R13. Resistor R13 serves as a current limiter and stabilizer. The other end of resistor R14 is grounded to GNDP along with the source of MOSFET VT3. When the circuit detects an overvoltage, a voltage divider circuit composed of resistors R9 and R14 turns on MOSFET VT3, which in turn turns on optocoupler O2, causing the output signal TM_BH to go low. Upon receiving this signal, the MCU stops the characteristic current PWM output.

[0055] The gate of the field-effect transistor VT2 is connected in parallel with a Zener diode VD2, a resistor R10, and then between resistors R13 and R14. The cathode of the Zener diode VD2 is connected to the gate of the field-effect transistor VT2. The anode of the Zener diode VD2, the resistor R10, and the source of the field-effect transistor VT2 are all grounded to GNDP. The drain of the field-effect transistor VT2 is connected to a resistor RL. The Zener diode VD2 is connected in parallel across R10 to clamp the voltage, prevent overvoltage, and protect the circuit components.

[0056] When the voltage across Zener diode VD2 reaches the turn-on voltage of MOSFET VT2, MOSFET VT2 turns on, connecting resistor RL to the circuit. Overvoltage energy is dissipated as heat through resistor RL, preventing overvoltage from being transmitted to subsequent circuits. Resistor R14 is used to adjust the turn-on voltage of MOSFET VT3. When resistor RL is damaged or cannot absorb much energy, the voltage across resistor R14 reaches the turn-on condition for MOSFET VT3. When MOSFET VT3 turns on, optocoupler O2 activates, pulling TM_BH low. Upon detecting the TM_BH signal, the MCU stops the characteristic current PWM output.

[0057] Overvoltage rectification and filtering module: Rectifier bridge BR2 is connected between the L and N lines to convert AC voltage to DC voltage. The L and N lines are the AC input ports of the circuit. Rectifier bridge BR2 ensures that the input voltage is rectified to DC, providing a suitable voltage form for the subsequent overvoltage detection circuit. The positive output terminal of rectifier bridge BR2 is connected in sequence to capacitor C9, resistor R9, and then to resistor RL. The negative output terminal of rectifier bridge BR2 and the other end of capacitor C9 are simultaneously grounded to GNDP. Capacitor C10 is connected in series with resistor R9, and the other end of capacitor C10 is grounded to GNDP.

[0058] The rectified voltage is divided by resistors R9 and R10, and capacitor C10 and resistor R9 form an RC filter circuit to further stabilize the voltage.

[0059] To address the voltage pulse issue caused by the leakage inductance of the PT itself, this circuit absorbs the voltage through resistor RL as described in the circuit diagram. When the characteristic current is transmitted, if an excessively high voltage pulse is generated, resistor RL responds quickly, absorbing the pulse energy. Together with other components (such as MOSFETs VT2 and VT3), it stabilizes the circuit voltage, protecting the entire characteristic current transmission circuit from damage by the voltage pulse and ensuring the smooth progress of the topology identification process. TM_BH is the alarm signal for PT overvoltage. When an excessively high PT voltage is detected, the TM_BH signal notifies the MCU to stop PWM output.

[0060] This invention uses a safety capacitor (2μF-20μF) and a voltage transformer (PT) secondary side co-design to generate a low-frequency characteristic current in the range of 100Hz-1KHZ. It utilizes the physical characteristic that the low-frequency current tends to the point of lowest impedance to achieve accurate verification of the power distribution line, which is different from the existing technology that relies on signal strength analysis or complex algorithms.

[0061] The characteristic current signal transmission circuit of this invention supports the transmission of characteristic current signals at frequencies of 100Hz to 1kHz. It is controlled by the PWM wave output by the MCU, and the load capacitor C7 (adjustable from 2μF to 20μF) ensures the generation of a stable characteristic signal frequency. The L and N terminals are connected to the AC 220V, 50Hz power supply from the PT, and the generated characteristic current signal is coupled to the 10KV side.

[0062] This invention's topology identification circuit for transmitting characteristic currents exhibits high accuracy. It utilizes the natural law that low-frequency currents tend towards the point of lowest impedance, eliminating the need for active feedback control. Furthermore, the low-frequency current exhibits a weak skin effect, resulting in minimal transmission attenuation and a long verification range. The characteristic signal generation module is integrated into each connected FTU device. The implementation relies primarily on relatively simple hardware components such as capacitors, MOSFETs, and control circuits. These components are low-cost, significantly reducing hardware investment costs compared to topology identification methods that require complex measuring instruments and high-end equipment. Due to the simplicity of the equipment, maintenance and repair are relatively easy, requiring no specialized technicians or complex maintenance tools, thus reducing operation and maintenance costs and difficulties. It also minimizes identification failures and grid operation risks caused by equipment malfunctions.

[0063] Topology identification does not require a power outage of the entire distribution area, avoiding inconvenience and economic losses to users caused by power outages, ensuring a continuous power supply, and improving the reliability of power supply and user satisfaction.

[0064] The capacitor is switched in and out on the secondary side of the PT, and the characteristic current generated is relatively small. It has almost no impact on the normal operation of the primary side of the power grid, and will not cause problems such as voltage fluctuations or frequency changes. It will not interfere with the normal operation of other equipment and loads in the power grid.

[0065] By switching in and out of the capacitor, characteristic currents with specific frequencies and amplitudes can be generated. These characteristic currents have unique frequency domain characteristics when transmitted in the power grid, making them easy to distinguish from other current signals in the power grid. They are less affected by other interference signals during the identification process, enabling more accurate extraction and identification of topology information. Even in complex power grid environments and large distribution areas, high identification accuracy can be achieved.

[0066] The capacitor switching operations are performed on the secondary side of the power transformer (PT). The secondary side voltage is relatively low, generally within a safe range, reducing the risk of electric shock for operators during equipment installation, commissioning, and maintenance, thus improving operational safety. Compared to operations on the primary side or other methods that may affect primary side equipment, this approach does not cause additional electrical stress or damage to the high-voltage equipment on the primary side, avoiding primary side equipment failures and safety accidents caused by topology identification, and ensuring the safe and stable operation of the power grid.

[0067] The circuit of this invention can easily adjust capacitor parameters, switching in and out times and frequencies according to the actual power grid conditions and topology identification requirements, thereby generating characteristic currents more suitable for the current power grid environment and further improving the accuracy and reliability of identification. This scheme can be used for topology identification in both small low-voltage distribution areas and large medium- and high-voltage power grids, as long as a PT secondary side exists, demonstrating strong versatility and adaptability. With the development and changes in the power grid, such as the addition of new lines or equipment upgrades, this circuit can be easily expanded and adjusted. Simply adding or adjusting the corresponding capacitors and control strategies can meet new topology identification requirements without requiring large-scale modifications to the entire system.

[0068] It is impossible to describe all possible combinations of components or methods in order to describe the above embodiments; however, those skilled in the art will recognize that further combinations and arrangements of the various embodiments are possible. Therefore, the embodiments described herein are intended to cover all such changes, modifications, and variations that fall within the scope of the appended claims. Furthermore, the term "comprising" as used in the specification or claims is interpreted in a manner similar to the term "including," as interpreted when used as a conjunction in the claims. Additionally, the use of any term "or" in the specification of the claims is intended to mean "non-exclusive or."

Claims

1. A characteristic current transmitting circuit based on a primary and secondary fusion equipment pattern verification system, characterized in that, It includes an isolated DC-DC power supply circuit, a characteristic current signal transmission circuit, and a PT overvoltage protection circuit; the isolated DC-DC power supply circuit includes an input power processing module, a chip enable control module, a transformer isolation module, and an output rectification and filtering module; the characteristic current signal transmission circuit consists of a signal input section, a power drive section, and a signal transmission section; the PT overvoltage protection circuit consists of an optocoupler isolation module, a power control and overvoltage absorption module, and an overvoltage rectification and filtering module. Signal input section: The PWM signal from the MCU is used as the input and is connected to the anode of the photodiode of optocoupler O1 through resistor R8. The cathode of the photodiode of optocoupler O1 is grounded to GND. Power drive section: The collector of the optotransistor of the optocoupler O1 is connected to the gate of the field-effect transistor VT1, the emitter of the optotransistor of the optocoupler O1 is grounded to GNDP, and the gate of the field-effect transistor VT1 is connected to a +12V power supply through a resistor R4; the Zener diode VP1 is connected in reverse parallel across the field-effect transistor VT1, the drain of the field-effect transistor VT1 is connected to the cathode of the Zener diode VP1, and the anode of the Zener diode VP1 and the source of the field-effect transistor VT1 are both grounded to GNDP; Signal transmission section: Rectifier bridge BR1 is connected between L line and N line. The positive output terminal of rectifier bridge BR1 is connected to the drain of field-effect transistor VT1, and the negative output terminal of rectifier bridge BR1 is grounded to GNDP. Capacitor C7 is connected in series between rectifier bridge BR1 and L line of PT.

2. The circuit according to claim 1, characterized in that, In the isolated DC-DC power supply circuit: Input power processing module: It takes +5V power as input, one end is connected to the VIN pin of the chip, and the other end is grounded to GND through capacitor C5; Chip enable control module: The EN pin of the chip is connected to the +5V power supply through resistor R3, and the EN pin of the chip is grounded to GND through resistor R7. A capacitor C8 is connected in parallel across resistor R7. Transformer isolation module: Pin 4 of transformer BT1 is connected to the SW pin of the chip, and pin 5 is connected to the node after resistor R5 of the FB pin of the chip; Output rectifier and filter module: Pin 3 of transformer BT1 is connected to the anode of diode VD1, and the cathode output of diode VD1 is connected in parallel with capacitors C3 and C4, resistor R2, and capacitor C2 in sequence; Pin 1 of transformer BT1 and the other end of capacitor C3 and capacitor C4 are simultaneously grounded to GNDP; the other end of resistor R2 and the other end of capacitor C2 are simultaneously grounded to GNDP.

3. The method according to claim 2, characterized in that, The isolated DC-DC power supply circuit also includes a bootstrap circuit, consisting of capacitor C1 and resistor R1; the BST pin of the chip is connected to the SW pin of the chip through the bootstrap circuit consisting of capacitor C1 and resistor R1.

4. The method according to claim 3, characterized in that, The isolated DC-DC power supply circuit also includes a feedback network, consisting of resistors R5 and R6 and capacitor C6; the FB pin of the chip is connected to pin 5 of the transformer BT1 through resistor R5, and resistor R6 and capacitor C6 are connected in parallel between the FB pin of the chip and ground GND.

5. The method according to claim 1, characterized in that, The optocoupler isolation module includes an optocoupler O2. One end of the TM_BH pin in the optocoupler isolation module is connected to the MCU, and the other end of the TM_BH pin is connected to the collector of the optotransistor of the optocoupler O2. The emitter of the optotransistor of the optocoupler O2 is grounded to GND. The +5V power supply is connected to the collector of the optotransistor of the optocoupler O2 through a resistor R11, and the +12V power supply is connected to the anode of the photodiode of the optocoupler O2 through a resistor R12. The cathode of the photodiode of the optocoupler O2 is connected to the drain of the field-effect transistor VT3.

6. The method according to claim 5, characterized in that, The power control and overvoltage absorption module includes a field-effect transistor VT3, a field-effect transistor VT2, a Zener diode VD2, resistors R9, R10, R13, and R14. The gate of the field-effect transistor VT3 is connected to resistors R9 and R14 through resistor R13. The other end of resistor R14 is grounded to GNDP at the same time as the source of the field-effect transistor VT3. The gate of the field-effect transistor VT2 is connected in parallel with a Zener diode VD2 and a resistor R10, and then connected between resistors R13 and R14. The cathode of the Zener diode VD2 is connected to the gate of the field-effect transistor VT2. The anode of the Zener diode VD2, the resistor R10, and the source of the field-effect transistor VT2 are all grounded to GNDP. The drain of the field-effect transistor VT2 is connected to a resistor RL.

7. The method according to claim 6, characterized in that, The overvoltage rectification and filtering module includes a rectifier bridge BR2, which is connected between the L line and the N line. The positive output terminal of the rectifier bridge BR2 is connected in sequence to a capacitor C9, a resistor R9, and then to a resistor RL. The negative output terminal of the rectifier bridge BR2 and the other end of the capacitor C9 are grounded to GNDP. The capacitor C10 is connected in series with the resistor R9, and the other end of the capacitor C10 is grounded to GNDP.

8. The method according to claim 1, characterized in that, The capacitor C7 is a load capacitor with a capacitance range of 2μF to 20μF.

9. The method according to claim 1, characterized in that, The L and N lines are connected to the AC 220V, 50Hz power supply from the PT, and the characteristic current signal is coupled to the 10KV side through the PT.

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