Apparatus and method for determining target waveform based on FPGA

Abstract

The application discloses a device and method for determining a target waveform based on FPGA, and the method comprises the following steps: obtaining initial parallel data corresponding to a target FPGA; performing trigger processing on the initial parallel data to obtain a first trigger address count value and a first trigger compensation value; determining an initial trigger address according to the first trigger address count value and the first trigger compensation value; processing the initial parallel data according to the initial trigger address to obtain candidate data; performing trigger processing on the candidate data to obtain a second trigger address count value and a second trigger compensation value, and determining a target trigger address according to the second trigger address count value and the second trigger compensation value; determining target parallel data according to the target trigger address and the initial parallel data, and outputting the target parallel data in a waveform form to obtain a target waveform. The application realizes accurate positioning of the target trigger address.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to an apparatus and method for determining a target waveform based on an FPGA. Background Technology

[0002] Triggering is one of the core functions of an oscilloscope, and it is crucial for the stable display of waveforms. Without triggering, the oscilloscope might capture the waveform of the signal being sampled at any time point during the current sampling, resulting in a waveform that is not what we need and an unstable waveform display.

[0003] Trigger signals are typically generated by comparing the measured signal or an external trigger signal with a trigger comparator. After entering the FPGA, trigger identification is performed: the signal is converted to logic "0" or "1". If it is a rising edge trigger and the pre-trigger condition is met, the signal is considered triggered when logic "0" changes to logic "1". When determining the trigger address, the sampled data is stored in memory in sequence. The address where the data is stored when the trigger signal arrives is the trigger address. However, the bit width of the memory is generally much larger than the bit width of a single sampled data. That is, one address in the memory may correspond to multiple sampling points. Software assistance is needed to locate the specific trigger address. Summary of the Invention

[0004] This application provides an apparatus and method for determining the target waveform based on FPGA, which can accurately locate the target trigger address.

[0005] On one hand, this application provides an apparatus for determining a target waveform based on an FPGA, the apparatus comprising: The initial parallel data acquisition module is used to acquire the initial parallel data collected by the analog-to-digital converter corresponding to the target FPGA; The initial trigger address determination module is used to trigger the initial parallel data in a first preset trigger mode to obtain a first trigger address count value and a first trigger compensation value; and to determine the initial trigger address based on the first trigger address count value and the first trigger compensation value. The candidate data acquisition module is used to process the initial parallel data according to the initial trigger address to obtain candidate data; The target trigger address determination module is used to trigger the candidate data in a second preset trigger mode to obtain a second trigger address count value and a second trigger compensation value, and determine the target trigger address based on the second trigger address count value and the second trigger compensation value; The target waveform output module is used to determine the target parallel data based on the target trigger address and the initial parallel data, and output the target parallel data in waveform form to obtain the target waveform.

[0006] In one exemplary embodiment, the candidate data acquisition module includes: A candidate parallel data acquisition unit is used to filter the initial parallel data according to the initial trigger address to obtain candidate parallel data; A candidate serial data acquisition unit is used to perform parallel-to-serial conversion processing on the candidate parallel data to obtain candidate serial data, which is used as the candidate data.

[0007] In one exemplary embodiment, the initial trigger address determination module includes: The first acquisition unit is used to trigger the initial parallel data in the first preset trigger mode to obtain the first trigger address count value and the first trigger compensation value. The third trigger count value determination unit is used to calculate the product value between the first trigger address count value and the preset sampling coefficient to obtain the third trigger count value; The third trigger count compensation value determination unit is used to calculate the product value between the first trigger compensation value and the preset sampling coefficient to obtain the third trigger count compensation value. The initial trigger address determination unit is used to calculate the difference between the third trigger count value and the third trigger count compensation value to obtain the initial trigger address.

[0008] In one exemplary embodiment, the target trigger address determination module includes: The second acquisition unit is used to trigger the candidate data in the second preset trigger mode to obtain the second trigger address count value and the second trigger compensation value. The target trigger address determination unit is used to calculate the difference between the second trigger address count value and the second trigger compensation value, and to perform conversion processing on the calculated target trigger address count value to obtain the target trigger address.

[0009] On the other hand, this application provides a method for determining a target waveform based on an FPGA, the method comprising: Acquire the initial parallel data collected by the analog-to-digital converter corresponding to the target FPGA; The initial parallel data is processed using a first preset trigger mode to obtain a first trigger address count value and a first trigger compensation value; and the initial trigger address is determined based on the first trigger address count value and the first trigger compensation value. The initial parallel data is processed according to the initial trigger address to obtain candidate data; The candidate data is triggered using a second preset trigger mode to obtain a second trigger address count value and a second trigger compensation value. Based on the second trigger address count value and the second trigger compensation value, the target trigger address is determined. Based on the target trigger address and the initial parallel data, the target parallel data is determined, and the target parallel data is output in waveform form to obtain the target waveform.

[0010] In one exemplary embodiment, processing the initial parallel data according to the initial trigger address to obtain candidate data includes: The initial parallel data is filtered based on the initial trigger address to obtain candidate parallel data; The candidate parallel data is subjected to parallel-to-serial conversion to obtain candidate serial data, which is then used as the candidate data.

[0011] In one exemplary embodiment, before filtering the initial parallel data according to the initial trigger address to obtain candidate parallel data, the method further includes: The system receives trigger configuration information corresponding to the target FPGA sent by the host computer; the trigger configuration information carries a preset sampling coefficient, a preset storage area, and a starting address corresponding to the preset storage area. The initial parallel data is sampled using the preset sampling coefficient to obtain sampled parallel data; the sampled parallel data includes at least one sampled data. The at least one sampled data is stored in the preset storage area in a preset storage order, and the sampled count value corresponding to each sampled data is determined. Based on the starting address and the count value after each sampling point, determine the address after each sampling point corresponding to the data after sampling. Based on the data after each sampling point and the address after each sampling point corresponding to the data after each sampling point, determine the address data relationship database; The step of filtering the initial parallel data according to the initial trigger address to obtain candidate parallel data includes: The candidate parallel data is obtained by searching the address data relationship database for parallel data that matches the initial trigger address; the address data relationship database includes a preset mapping relationship between the trigger address and the preset parallel data.

[0012] In one exemplary embodiment, determining the address data relation database based on each sampled data point and the sampled address corresponding to each sampled data point includes: The data after each sampling point is traversed sequentially. For the current data after sampling point that is traversed, the current address after sampling point corresponding to the current data after sampling point is determined. Determine the current data acquisition interval corresponding to the current sampling address; the current data acquisition interval is an interval centered on the current sampling address, with a fluctuation range smaller than a preset address length; Obtain the current parallel data within the current data acquisition interval; Based on the current data acquisition interval corresponding to the current data acquisition interval and the current parallel data within the current data acquisition interval, determine the current parallel data corresponding to the current data acquisition interval; The address data relationship library is constructed based on the mapping relationship between the current extracted address and the current parallel data corresponding to the current extracted address.

[0013] In one exemplary embodiment, the trigger configuration information further carries the first preset trigger mode; the step of triggering the initial parallel data using the first preset trigger mode to obtain a first trigger address count value and a first trigger compensation value; and determining the initial trigger address based on the first trigger address count value and the first trigger compensation value, includes: The initial parallel data is triggered using the first preset trigger mode to obtain the first trigger address count value and the first trigger compensation value. Calculate the product between the first trigger address count value and the preset sampling coefficient to obtain the third trigger count value; Calculate the product between the first trigger compensation value and the preset sampling coefficient to obtain the third trigger count compensation value; The difference between the third trigger count value and the third trigger count compensation value is calculated to obtain the initial trigger address.

[0014] In one exemplary embodiment, the trigger configuration information further carries a preset pre-trigger depth value; the step of storing the at least one sampled data point in the preset storage area according to a preset storage order, and determining the sampled count value corresponding to each sampled data point, includes: The at least one sampled data is stored in the preset storage area according to the preset storage order, and the sampled count value corresponding to each sampled data and the real-time pre-trigger depth value corresponding to the preset storage area are determined. The step of triggering the initial parallel data using the first preset trigger mode to obtain the first trigger address count value and the first trigger compensation value includes: If the real-time pre-trigger depth value is greater than or equal to the preset pre-trigger depth value, the initial parallel data is triggered using the first preset trigger mode to obtain the first trigger address count value and the first trigger compensation value.

[0015] In one exemplary embodiment, calculating the difference between the third trigger count value and the third trigger count compensation value to obtain the initial trigger address includes: The difference between the third trigger count value and the third trigger count compensation value is calculated to obtain the fourth trigger count value; The initial trigger address is determined based on the starting address corresponding to the preset storage area and the fourth trigger count value.

[0016] In one exemplary embodiment, the trigger configuration information further carries the second preset trigger mode; the step of triggering the candidate data using the second preset trigger mode to obtain a second trigger address count value and a second trigger compensation value, and determining the target trigger address based on the second trigger address count value and the second trigger compensation value, includes: The candidate data is triggered using the second preset trigger mode to obtain the second trigger address count value and the second trigger compensation value; Calculate the difference between the second trigger address count value and the second trigger compensation value, and perform conversion processing on the calculated target trigger address count value to obtain the target trigger address.

[0017] In one exemplary embodiment, the step of calculating the difference between the second trigger address count value and the second trigger compensation value, and converting the calculated target trigger address count value to obtain the target trigger address, includes: The difference between the second trigger address count value and the second trigger compensation value is calculated to obtain the target trigger address count value; Obtain the bit width and the preset number of bits of the preset storage area; The number of bytes in the preset storage space is determined based on the bit width and the preset number of bits. The target trigger address is determined based on the target trigger address count value and the number of bytes.

[0018] In one exemplary embodiment, the step of performing parallel-to-serial conversion on the candidate parallel data to obtain candidate serial data, wherein the candidate serial data serves as the candidate data, includes: The candidate parallel data is split into data with a first preset bit width to obtain a first preset number of initial processing parallel data. Each initial parallel data is split into two data segments with a second preset bit width to obtain a second preset number of secondary parallel data segments; the first preset bit width is greater than the second preset bit width; the second preset number is greater than the first preset number. The second preset number of secondary processing parallel data are spliced ​​together to obtain the initial serial data corresponding to each primary processing parallel data. The first preset number of initial serial data is subjected to data splicing processing to obtain the candidate serial data, which is used as the candidate data.

[0019] On the other hand, an electronic device is provided, the device including a processor and a memory, the memory storing at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by the processor as described above for determining the target waveform based on FPGA.

[0020] On the other hand, a computer-readable storage medium is provided, wherein at least one instruction or at least one program is stored therein, the at least one instruction or at least one program being loaded and executed by a processor to implement the FPGA-based method for determining the target waveform as described above.

[0021] On the other hand, a computer program product or computer program is provided, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, executes the computer instructions, and causes the computer device to perform the method for determining a target waveform based on an FPGA as described above.

[0022] The apparatus and method for determining a target waveform based on an FPGA provided in this application have the following technical effects: This application acquires initial parallel data collected by the analog-to-digital converter corresponding to the target FPGA; triggers the initial parallel data using a first preset trigger mode to obtain a first trigger address count value and a first trigger compensation value; determines an initial trigger address based on the first trigger address count value and the first trigger compensation value; processes the initial parallel data according to the initial trigger address to obtain candidate data; triggers the candidate data using a second preset trigger mode to obtain a second trigger address count value and a second trigger compensation value; determines a target trigger address based on the second trigger address count value and the second trigger compensation value; determines target parallel data based on the target trigger address and the initial parallel data; and outputs the target parallel data in waveform form to obtain the target waveform. By performing two-level triggering on the collected initial parallel data, specifically, a first-level triggering is performed on the initial parallel data using a first preset triggering mode to obtain the initial trigger address, thereby processing the initial parallel data to obtain candidate data and narrowing the selection range of the target trigger address; a second-level triggering is performed on the candidate data using a second preset triggering mode to obtain the target trigger address, thereby determining the real sampling point and displaying the sampling waveform required by the user, thus improving the accuracy of the target trigger address determination result. Attached Figure Description

[0023] To more clearly illustrate the technical solutions and advantages in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of an FPGA-based triggering device provided in the embodiments of this specification; Figure 2 This is a schematic diagram of the specific structure of an FPGA-based triggering device provided in the embodiments of this specification; Figure 3 This is a schematic diagram of the structure of a data caching control module provided in the embodiments of this specification; Figure 4 This is a schematic diagram of the structure of the FPGA-based device for determining the target waveform provided in the embodiments of this specification.

[0025] Figure 5 This is a flowchart illustrating a method for determining a target waveform based on an FPGA, as provided in the embodiments of this specification. Figure 6This is a flowchart illustrating a method for determining an initial trigger address provided in an embodiment of this specification; Figure 7 This is a schematic diagram of an edge-triggered level provided in the embodiments of this specification; Figure 8 This is a schematic diagram of a pulse width triggering level provided in the embodiments of this specification; Figure 9 This is a schematic diagram of a slope-triggered level provided in the embodiments of this specification; Figure 10 This is a schematic diagram illustrating the triggering of initial parallel data provided in the embodiments of this specification; Figure 11 This is a flowchart illustrating a method for determining an address data relationship database provided in an embodiment of this specification; Figure 12 This is a flowchart illustrating a method for constructing an address data relational database provided in the embodiments of this specification; Figure 13 This is a flowchart illustrating a method for determining candidate data provided in an embodiment of this specification; Figure 14 This is a schematic diagram of a data splicing method provided in the embodiments of this specification; Figure 15 This is a schematic diagram of a method for determining a target trigger address provided in an embodiment of this specification; Figure 16 This is a flowchart illustrating a method for determining candidate serial data provided in an embodiment of this specification. Detailed Implementation The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0026] In one exemplary implementation, such as Figure 1 As shown, Figure 1 A schematic diagram of an FPGA-based triggering device provided in the embodiments of this specification includes: 101: Host computer; The host computer completes the trigger configuration for the primary data processing module and the secondary data processing module. The primary data processing module is the module that triggers the initial parallel data. The host computer completes the trigger configuration for the primary data processing module, including a first preset trigger mode. The secondary data processing module is the module that triggers the candidate serial data. The host computer completes the trigger configuration for the secondary data processing module, including a second preset trigger mode. At the same time, the host computer interacts with other components, specifically including receiving and sending the initial trigger address of the target FPGA and receiving the target trigger address of the target FPGA. The host computer reads the target parallel data based on the received target trigger address and displays the target waveform.

[0027] 102: Data acquisition module; The data acquisition module sends the acquired multi-channel parallel data to the first-level trigger judgment module.

[0028] 103: Level 1 Data Processing Module; The Level 1 Data Processing Module is used to perform trigger judgment on the initial parallel data, preliminarily determine the initial trigger address, and control the data cache.

[0029] 104: Data storage space; The data storage space is used to store the initial parallel data after sampling.

[0030] 105: Secondary Data Processing Module; The secondary data processing module is used to read the initial parallel data after sampling from the data storage space, process the data to obtain candidate serial data, and perform trigger judgment and target trigger address determination on the candidate serial data.

[0031] In one exemplary implementation, such as Figure 2 As shown, Figure 2 A schematic diagram of a specific structure of an FPGA-based triggering device provided in the embodiments of this specification includes: 201: Data Acquisition Module; The data acquisition module is used to send the acquired multi-channel parallel data, i.e., the initial parallel data, to the data buffer control module and the first-level trigger judgment module.

[0032] 202: Data Cache Control Module; The data cache control module stores the initial parallel data into the data storage space, wherein, Figure 3 This is a schematic diagram of the structure of a data caching control module provided in an embodiment of this specification. Figure 3As can be seen, the data caching control module consists of a sampling module and a first-in-first-out (FIFO) buffer. The sampling module extracts several streams of initial parallel data and reassembles them into new data groups, i.e., parallel data after sampling. This parallel data is then stored in the FIFO buffer and subsequently in the data storage space. The sampling module can perform interval sampling according to settings, i.e., preset sampling coefficients, which helps reduce the sampling rate. Based on the number of sampling points and the time interval between the sampling data being cached in the FIFO, the sampling rate can be switched from 1.5SPS to 256GSPS. The data caching is efficient and convenient, thus enabling quick and accurate determination of the first-level trigger address. The data caching control module adopts an efficient caching mechanism, counting the number of cached data. When the number of cached data reaches a certain amount, i.e., the preset pre-trigger depth value, it sends a start trigger judgment signal to the first-level trigger judgment module. After receiving the trigger signal and the trigger address compensation value, the data caching control module obtains the first trigger address count value based on the trigger signal and, combined with the trigger address compensation value, i.e., the first trigger compensation value, calculates the corresponding first-level trigger address, i.e., the initial trigger address, records it, and transmits it to the host computer.

[0033] 203: Level 1 Trigger Judgment Module; The Level 1 Trigger Judgment Module performs trigger judgment on the initial parallel data according to the trigger configuration, namely the first preset trigger mode, including multiple judgment modes such as edge trigger judgment, pulse width trigger judgment, and slope trigger judgment. After receiving the start trigger judgment signal, it generates a trigger signal and sends it to the data buffer control module, and at the same time sends the first trigger compensation value to the data buffer control module.

[0034] 204: Data storage space; The data storage space is used to store the initial parallel data after sampling, that is, the parallel data after sampling. The data storage space can be the FPGA's internal RAM, HBM and external DDR storage facilities. For example, HBM storage medium can be used. Since multiple ADCs are used for data acquisition, the data acquired by each ADC is stored in a fixed area in HBM, that is, the preset storage area. 205: Host computer; The host computer completes the trigger configuration of the first-level trigger judgment module and the second-level trigger judgment module, and sends the first-level trigger address to the data reading module; The host computer also receives the second-level trigger address, i.e. the target trigger address, and reads data from the data storage space according to the target trigger address for waveform display.

[0035] 206: Data reading module; The data reading module reads a segment of parallel data forward and backward from the data storage space, centered on the first-level trigger address, i.e. the initial trigger address, and sends the read parallel data, i.e. the candidate parallel data, to the data splicing module.

[0036] 207: Data splicing module; converts candidate parallel data into candidate serial data. When multiple acquisition boards are collecting data, the data needs to be spliced ​​and reassembled, and the spliced ​​and reassembled serial data is sent to the secondary trigger address judgment module.

[0037] 208: Secondary trigger address judgment module; The secondary trigger address judgment module counts the received candidate serial data and sends the candidate serial data to the secondary trigger judgment module. After receiving the trigger signal and the trigger address compensation value, i.e. the second trigger compensation value, the secondary trigger address judgment module calculates the secondary trigger address, i.e. the target trigger address, and transmits it to the host computer.

[0038] 209: Secondary trigger judgment module; The secondary trigger judgment module performs trigger judgment on candidate serial data according to the trigger configuration, namely the second preset trigger mode, and sends the trigger signal and the trigger address compensation value, namely the second trigger compensation value, to the secondary trigger address judgment module.

[0039] This manual also provides a device for determining the target waveform based on an FPGA, such as... Figure 4 As shown, the device includes: The initial parallel data acquisition module 401 is used to acquire the initial parallel data collected by the analog-to-digital converter corresponding to the target FPGA; The initial trigger address determination module 402 is used to trigger the initial parallel data in a first preset trigger mode to obtain a first trigger address count value and a first trigger compensation value; and to determine the initial trigger address based on the first trigger address count value and the first trigger compensation value. The candidate data acquisition module 403 is used to process the initial parallel data according to the initial trigger address to obtain candidate data; The target trigger address determination module 404 is used to trigger the candidate data in a second preset trigger mode to obtain a second trigger address count value and a second trigger compensation value, and determine the target trigger address based on the second trigger address count value and the second trigger compensation value; The target waveform output module 405 is used to determine the target parallel data based on the target trigger address and the initial parallel data, and output the target parallel data in waveform form to obtain the target waveform.

[0040] In some embodiments, the candidate data acquisition module includes: A candidate parallel data acquisition unit is used to filter the initial parallel data according to the initial trigger address to obtain candidate parallel data; A candidate serial data acquisition unit is used to perform parallel-to-serial conversion processing on the candidate parallel data to obtain candidate serial data, which is used as the candidate data.

[0041] In some embodiments, the apparatus further includes: A trigger configuration information receiving module is used to receive trigger configuration information corresponding to the target FPGA sent by a host computer; the trigger configuration information carries a preset sampling coefficient, a preset storage area, and a starting address corresponding to the preset storage area. The parallel data acquisition module after sampling is used to perform sampling processing on the initial parallel data with the preset sampling coefficient to obtain parallel data after sampling; the parallel data after sampling includes at least one piece of data after sampling. The sampling count value determination module is used to store the at least one sampling data into the preset storage area in a preset storage order, and determine the sampling count value corresponding to each sampling data. The post-sampling address determination module is used to determine the post-sampling address corresponding to each post-sampling data based on the starting address and the post-sampling count value corresponding to each post-sampling data. The address data relationship database determination module is used to determine the address data relationship database based on each sampled data and the sampled address corresponding to each sampled data. In some embodiments, the candidate parallel data acquisition module further includes: The candidate parallel data determination submodule is used to search for parallel data that matches the initial trigger address in the address data relationship library to obtain the candidate parallel data; the address data relationship library includes a preset mapping relationship between the trigger address and the preset parallel data.

[0042] In some embodiments, the address data relation database determination module further includes: The current sampling address determination submodule is used to sequentially traverse each sampling data and determine the current sampling address corresponding to the current sampling data for the traversed current sampling data. The current data acquisition interval determination submodule is used to determine the current data acquisition interval corresponding to the current sampling address; the current data acquisition interval is an interval centered on the current sampling address with a floating range smaller than a preset address length; The current parallel data acquisition submodule is used to acquire the current parallel data within the current data acquisition interval; The current parallel data determination submodule is used to determine the current parallel data corresponding to the current sampling address based on the current data acquisition interval corresponding to the current sampling address and the current parallel data within the current data acquisition interval; The address data relationship database construction submodule is used to construct the address data relationship database based on the mapping relationship between the current extracted address and the current parallel data corresponding to the current extracted address.

[0043] In some embodiments, the initial trigger address determination module further includes: The first acquisition unit is used to trigger the initial parallel data in the first preset trigger mode to obtain the first trigger address count value and the first trigger compensation value. The third trigger count value determination unit is used to calculate the product value between the first trigger address count value and the preset sampling coefficient to obtain the third trigger count value; The third trigger count compensation value determination unit is used to calculate the product value between the first trigger compensation value and the preset sampling coefficient to obtain the third trigger count compensation value. The initial trigger address determination unit is used to calculate the difference between the third trigger count value and the third trigger count compensation value to obtain the initial trigger address.

[0044] In some embodiments, the post-sampling count value determination module further includes: The real-time pre-trigger depth value acquisition submodule is used to store the at least one sampled data into the preset storage area according to the preset storage order, and determine the sampled count value corresponding to each sampled data and the real-time pre-trigger depth value corresponding to the preset storage area. In some embodiments, the first acquisition unit further includes: The trigger subunit is used to trigger the initial parallel data in the first preset trigger mode if the real-time pre-trigger depth value is greater than or equal to the preset pre-trigger depth value, so as to obtain the first trigger address count value and the first trigger compensation value.

[0045] In some embodiments, the initial trigger address determination unit further includes: The fourth trigger count value acquisition subunit is used to calculate the difference between the third trigger count value and the third trigger count compensation value to obtain the fourth trigger count value; The initial trigger address determination subunit is used to determine the initial trigger address based on the starting address corresponding to the preset storage area and the fourth trigger count value.

[0046] In some embodiments, the target trigger address determination module further includes: The second acquisition unit is used to trigger the candidate data in the second preset trigger mode to obtain the second trigger address count value and the second trigger compensation value. The target trigger address determination unit is used to calculate the difference between the second trigger address count value and the second trigger compensation value, and to perform conversion processing on the calculated target trigger address count value to obtain the target trigger address.

[0047] In some embodiments, the target trigger address determination unit further includes: The target trigger address count value determination subunit is used to calculate the difference between the second trigger address count value and the second trigger compensation value to obtain the target trigger address count value; A sub-unit is used to obtain the bit width and the preset number of bits of the preset storage area; The byte count determination subunit is used to determine the number of bytes in the preset storage space based on the bit width and the preset number of bits. The target trigger address determination subunit is used to determine the target trigger address based on the target trigger address count value and the number of bytes.

[0048] In some embodiments, the candidate serial data acquisition module further includes: The initial processing parallel data acquisition submodule is used to split the candidate parallel data with a first preset bit width to obtain a first preset number of initial processing parallel data. The secondary processing parallel data acquisition submodule is used to split each piece of primary processing parallel data with a second preset bit width to obtain a second preset number of secondary processing parallel data; the first preset bit width is greater than the second preset bit width; the second preset number is greater than the first preset number. The initial serial data acquisition submodule is used to perform data splicing processing on the second preset number of secondary processing parallel data to obtain the initial serial data corresponding to each initial processing parallel data. The candidate serial data acquisition submodule is used to perform data splicing processing on the first preset number of initial serial data to obtain the candidate serial data, and the candidate serial data is used as the candidate data.

[0049] The apparatus and method embodiments described herein are based on the same inventive concept.

[0050] The following describes a method for determining the target waveform based on FPGA, as proposed in this application. Figure 5This is a flowchart illustrating a method for determining a target waveform based on an FPGA, as provided in the embodiments of this specification. Figure 5 As shown, the method can be applied to a controller corresponding to an FPGA, and the method includes: S501: Acquire the initial parallel data collected by the analog-to-digital converter corresponding to the target FPGA.

[0051] In the embodiments of this specification, the target FPGA can be one or more FPGAs. Each FPGA can be equipped with four corresponding analog-to-digital converters (ADCs). Each ADC can acquire 128 channels of analog signals and convert the acquired analog signals into digital signals. Each data channel has a bit width of 8 bits. In actual use, the user can enable the required FPGA, i.e., the target FPGA, and the required ADC corresponding to the required FPGA as needed, and acquire the multiple channels of data acquired by the enabled ADC corresponding to the target FPGA, and combine them into initial parallel data.

[0052] S503: Trigger the initial parallel data using a first preset trigger mode to obtain a first trigger address count value and a first trigger compensation value; and determine the initial trigger address based on the first trigger address count value and the first trigger compensation value.

[0053] In this embodiment, the controller of the target FPGA can receive trigger configuration information sent by the host computer. The trigger configuration information carries a first preset trigger mode and a second preset trigger mode. After acquiring the initial parallel data, the initial parallel data can be stored in a preset storage area. The preset storage area can be a fixed area in the HBM storage medium corresponding to the target FPGA. However, since the initial parallel data has a large capacity, it can be sampled and stored to obtain sampled parallel data, which reduces the number of channels and the sampling rate. The sampled parallel data is then stored in the preset storage area. The sampled data includes at least one sampled data point, which is stored in the preset storage area. During the process, the number of sampled data points stored in the preset storage area is counted. When the number of sampled data points stored reaches the set pre-trigger depth, it indicates that enough data before the trigger point has been cached in the preset storage area. At this time, the initial parallel data is triggered using the first preset trigger mode. When the trigger condition is met in the initial parallel data, a trigger signal is generated. At the same time, the first trigger address count value and the first trigger compensation value corresponding to the trigger signal are obtained. Since the trigger judgment logic itself requires a certain processing time, the existence of the first trigger compensation value is to quantify the delay time, so as to determine the initial trigger address based on the first trigger address count value and the first trigger compensation value.

[0054] In this embodiment of the specification, the trigger configuration information further carries the first preset trigger mode; the initial parallel data is triggered using the first preset trigger mode to obtain a first trigger address count value and a first trigger compensation value; and the initial trigger address is determined based on the first trigger address count value and the first trigger compensation value, such as... Figure 6 As shown, Figure 6 A flowchart illustrating a method for determining an initial trigger address provided in an embodiment of this specification includes: S601: Trigger the initial parallel data using the first preset trigger mode to obtain the first trigger address count value and the first trigger compensation value.

[0055] In the embodiments of this specification, the first preset trigger mode is issued by the host computer, and the first preset trigger mode may include a trigger mode set for the analog-to-digital converter corresponding to the target FPGA and a configuration corresponding to the trigger mode. The trigger mode may include one of edge triggering, pulse width triggering, and slope triggering. Specifically, if the trigger mode is edge triggering, such as... Figure 7 As shown, Figure 7 This is a schematic diagram of an edge-triggered level provided in an embodiment of this specification. Figure 7 As can be seen, Figure 7The sampled data is one channel of the initial parallel data, and the trigger level can be set to dual-level trigger. Specifically, it is... Figure 7 The system uses trigger high and low levels to compare sampled data with each level, obtaining high-level and low-level comparison results. If a sampled value is greater than or equal to the trigger high level, the high-level comparison result for that channel is logic '1'; otherwise, it's logic '0'. Similarly, if a sampled value is greater than or equal to the trigger low level, the low-level comparison result for that channel is logic '1'; otherwise, it's logic '0'. A voltage window is defined using dual-level triggering, with the trigger high level as the upper limit and the trigger low level as the lower limit. After obtaining the high-level and low-level comparison results for each channel, the voltage level between the rising edge of the high-level comparison result and the falling edge of the low-level comparison result is defined as logic '1', yielding the final comparison result for that channel. The window state for each signal is continuously recorded. If the final comparison result is '1', the system continues to record the window state. This indicates that the signal is within the window. If the final comparison result is '0', it means the signal is outside the window. When a data path changes from outside the window (i.e., the previous cycle comparison was '0') to inside the window (i.e., the current cycle comparison is '1'), a rising edge trigger event signal is generated, indicating that the signal has just entered the level window. When a data path changes from inside the window (i.e., the previous cycle comparison was '1') to outside the window (i.e., the current cycle comparison is '0'), a falling edge trigger event signal is generated, indicating that the signal has just left the level window. If set to rising edge trigger, only rising edge events are responded to; if set to falling edge trigger, only falling edge events are responded to; if set to dual edge trigger, all edge events are responded to. When any path detects an edge event that meets the configuration requirements, a global trigger signal is immediately generated. At the instant the trigger signal is generated, the current sampling clock count value, i.e., the first trigger address count value, is latched. This count value represents the time point when the trigger event was detected, and the first trigger compensation value is also acquired. By setting a voltage window instead of a single point, false triggering caused by noise is avoided, which helps to accurately locate the edge. The edge triggering accuracy can reach 62.5ps, and the window width can be adjusted according to the signal characteristics.

[0056] If the triggering mode is pulse width triggering, such as Figure 8 As shown, Figure 8 This is a schematic diagram of a pulse width triggering level provided in an embodiment of this specification. Figure 8 As can be seen, Figure 8 The sampled data is one of the data streams in the initial parallel data set. The trigger level can be set to dual-level trigger, i.e. Figure 8The system uses trigger high and trigger low levels to compare sampled data with each level, obtaining high-level and low-level comparison results. When the high-level comparison result changes from logic '0' to logic '1', the system enters a window and starts a pulse width counter. When the low-level comparison result changes from logic '1' to logic '0', the system exits the window and stops counting, obtaining the positive pulse width value. If the positive pulse width value is greater than or equal to a preset positive pulse width value, a trigger signal is generated. Similarly, when the low-level comparison result changes from logic '1' to logic '0', the system exits the window and starts a pulse width counter. When the high-level comparison result changes from logic '0' to logic '1', the system enters the window and stops counting, obtaining the negative pulse width value. If the negative pulse width value is greater than or equal to a preset negative pulse width value, a trigger signal is generated, resulting in the first trigger address count value and the first trigger compensation value. The pulse width trigger accuracy can reach 125ps.

[0057] If the triggering mode is slope triggering, such as Figure 9 As shown, Figure 9 This is a schematic diagram of a slope-triggered level provided in an embodiment of this specification. Figure 9 As can be seen, Figure 9 The sampled data is one of the initial parallel data streams. Two sets of trigger comparison levels can be set for slope triggering. Specifically, the first set of trigger comparison levels includes trigger high level 1 and trigger low level 1, and the second set includes trigger high level 2 and trigger low level 2. The sampled data is compared with the first and second sets of trigger comparison levels respectively to obtain comparison result 1 and comparison result 2. Then, a logical XOR operation is performed on comparison result 1 and comparison result 2 to obtain the final result. The portion of the XOR result that shares the same falling edge as comparison result 2 is the negative slope. The slope high-level width is counted under clock and compared with the set slope value. If the trigger condition is met, a trigger signal is generated, thereby obtaining the first trigger address count value and the first trigger compensation value. The slope trigger accuracy can reach 125ps.

[0058] S602: Calculate the product between the first trigger address count value and the preset sampling coefficient to obtain the third trigger count value.

[0059] In the embodiments of this specification, since the initial parallel data is the raw data that has not been sampled, and the sampled data is stored in a preset storage area, it is necessary to determine the address of the trigger signal in the preset storage area. Therefore, the product value between the first trigger address count value and the preset sampling coefficient is calculated to obtain the third trigger count value.

[0060] S603: Calculate the product between the first trigger compensation value and the preset sampling coefficient to obtain the third trigger count compensation value.

[0061] In the embodiments of this specification, the product between the first trigger compensation value and the preset sampling coefficient is calculated to obtain the third trigger count compensation value.

[0062] S604: Calculate the difference between the third trigger count value and the third trigger count compensation value to obtain the initial trigger address.

[0063] In the embodiments of this specification, the difference between the third trigger count value and the third trigger count compensation value is calculated to obtain the initial trigger address. For example... Figure 10 As shown, Figure 10 This is a schematic diagram illustrating the triggering of initial parallel data provided in an embodiment of this specification. Figure 10 As can be seen, assuming the fourth data stream is triggered at time T2, due to the fixed delay in the trigger judgment logic, a trigger signal is generated at time T4. The corresponding count value for the trigger signal at time T4 is obtained. Shifting this count value forward by two bits (i.e., subtracting the address compensation value of 2) yields the actual trigger count value. Based on the actual trigger count value and the starting address of the storage space, the actual trigger address can be calculated. By triggering the initial parallel data, the first trigger address count value and the first trigger compensation value are obtained. Combined with a preset sampling coefficient, the initial trigger address is calculated. This means that the fixed delay is eliminated using the first trigger compensation value, and the initial location of the trigger signal is preliminarily determined, improving trigger accuracy.

[0064] In this embodiment of the specification, calculating the difference between the third trigger count value and the third trigger count compensation value to obtain the initial trigger address includes: The difference between the third trigger count value and the third trigger count compensation value is calculated to obtain the fourth trigger count value; In the embodiments of this specification, the difference between the third trigger count value and the third trigger count compensation value is calculated to obtain the fourth trigger count value, which is the count value corresponding to the actual trigger signal.

[0065] The initial trigger address is determined based on the starting address corresponding to the preset storage area and the fourth trigger count value.

[0066] In the embodiments of this specification, the initial trigger address is obtained by calculating the sum of the starting address corresponding to the preset storage area and the fourth trigger count value, thus obtaining the initial judgment result of the actual trigger signal. By combining the starting address of the preset area and the fourth trigger count value corresponding to the trigger signal, the initial trigger address is obtained, providing an accurate candidate address for locating the target trigger address, which helps to relocate the trigger signal in the subsequent process and improves the trigger accuracy.

[0067] S505: Process the initial parallel data according to the initial trigger address to obtain candidate data; In the embodiments of this specification, after the initial trigger address is calculated, the controller of the target FPGA reads a segment of parallel data forward and backward with the initial trigger address as the center and processes it to obtain candidate data.

[0068] In this embodiment of the specification, the step of processing the initial parallel data according to the initial trigger address to obtain candidate data includes: The initial parallel data is filtered based on the initial trigger address to obtain candidate parallel data.

[0069] In the embodiments of this specification, after the initial trigger address is calculated, the initial trigger address can be sent to the host computer, and the host computer can then issue instructions to the controller of the target FPGA so that the controller of the target FPGA reads a segment of parallel data forward and backward with the initial trigger address as the center to obtain candidate parallel data.

[0070] In the embodiments of this specification, before the initial parallel data is filtered according to the initial trigger address to obtain candidate parallel data, as follows: Figure 11 As shown, Figure 11 This is a flowchart illustrating a method for determining an address data relation database provided in an embodiment of this specification. The method further includes: S1101: Receive trigger configuration information corresponding to the target FPGA sent by the host computer; the trigger configuration information carries a preset sampling coefficient, a preset storage area, and a starting address corresponding to the preset storage area.

[0071] In the embodiments of this specification, the trigger configuration information corresponding to the target FPGA sent by the host computer is received, and the trigger configuration information carries a preset sampling coefficient, a preset storage area, and a starting address corresponding to the preset storage area; wherein, the preset storage area can be internal RAM, HBM, and external DDR storage facilities corresponding to the target FPGA, for example, it can be an HBM storage medium, and each ADC is provided with a fixed area in the corresponding HBM storage medium.

[0072] S1102: The initial parallel data is processed by sampling using the preset sampling coefficient to obtain parallel data after sampling; the parallel data after sampling includes at least one piece of data after sampling.

[0073] In the embodiments of this specification, the preset sampling coefficient can be set according to the actual situation during actual use. For example, it can be 1 / 2. For each analog-to-digital converter corresponding to each target FPGA, 128 channels of data are collected. After sampling, it becomes 64 channels. Data from even-numbered channels in the 128 channels can be extracted, thereby reducing the sampling rate. Thus, all initial parallel data are sampled using the preset sampling coefficient to obtain the sampled parallel data. Alternatively, the initial parallel data can be sampled by extracting 1, 2, 4, 8, 32, 64, or 128 channels of data from the 128 channels of 8-bit original data to form a new 1024-bit dataset. Sampling 128 channels from 128 channels is considered as not sampling. The sampling rate is full speed, and the sampled data is consistent with the original data.

[0074] S1103: Store the at least one sampled data in the preset storage area according to a preset storage order, and determine the sampled count value corresponding to each sampled data.

[0075] In the embodiments of this specification, the preset storage order can be based on the time of acquisition. All data after sampling are stored in a preset storage area in a preset storage order. The first data after sampling stored in the preset storage area has a count value of 0, and the count values ​​of the subsequent data after sampling are incremented by 1 in turn, thereby determining the count value corresponding to each data after sampling.

[0076] In this embodiment of the specification, the trigger configuration information further carries a preset pre-trigger depth value; the step of storing the at least one sampled data point in the preset storage area according to a preset storage order, and determining the sampled count value corresponding to each sampled data point, includes: The at least one sampled data is stored in the preset storage area according to the preset storage order, and the sampled count value corresponding to each sampled data and the real-time pre-trigger depth value corresponding to the preset storage area are determined. In the embodiments of this specification, at least one sampled data point is stored in the preset storage area according to the preset storage order, and the sampled count value corresponding to each sampled data point and the real-time pre-trigger depth value corresponding to the preset storage area are determined.

[0077] The step of triggering the initial parallel data using the first preset trigger mode to obtain the first trigger address count value and the first trigger compensation value includes: If the real-time pre-trigger depth value is greater than or equal to the preset pre-trigger depth value, the initial parallel data is triggered using the first preset trigger mode to obtain the first trigger address count value and the first trigger compensation value.

[0078] In the embodiments of this specification, if the real-time pre-trigger depth value is greater than or equal to the preset pre-trigger depth value, it indicates that the pre-trigger data has reached a certain quantity. At this time, the host computer issues a trigger command to trigger the initial parallel data using the first preset trigger mode, obtaining the first trigger address count value and the first trigger compensation value. By setting the preset trigger depth value, it ensures that the complete pre-trigger data before the trigger point is ready, eliminating signal front-end loss caused by storage delay, and realizing that trigger judgment is only opened after the storage depth reaches the standard, thus ensuring data integrity.

[0079] S1104: Determine the post-sampling address corresponding to each post-sampling data based on the starting address and the post-sampling count value corresponding to each post-sampling data.

[0080] In the embodiments of this specification, the sum of the starting address and the count value corresponding to each sampled data point can be used to obtain the sampled address corresponding to each sampled data point.

[0081] S1105: Determine the address data relationship database based on the data after each sampling point and the address after sampling point corresponding to each data after sampling point.

[0082] In the embodiments of this specification, based on the address corresponding to each extracted data point and each extracted data point, the parallel data corresponding to each extracted address can be determined. Combining each extracted address and the parallel data corresponding to each extracted address, the address data relationship database can be determined.

[0083] In the embodiments of this specification, the step of determining the address data relation database based on each sampled data point and the corresponding sampled address is as follows: Figure 12 As shown, Figure 12 A flowchart illustrating a method for constructing an address data relational database provided in this embodiment of the specification includes: S1201: Iterate through each of the extracted data points in sequence, and for the current extracted data point encountered during the iteration, determine the current extracted address corresponding to the current extracted data point.

[0084] In the embodiments of this specification, each data point is sequentially traversed. For the current data point, the sum of the count value corresponding to the current data point and the starting address of the preset storage area is calculated to obtain the current data point address.

[0085] S1202: Determine the current data acquisition interval corresponding to the current sampling address; the current data acquisition interval is an interval centered on the current sampling address with a floating range less than the preset address length.

[0086] In the embodiments of this specification, the current data acquisition interval is an interval centered on the current sampling address, with a fluctuation range less than the preset address length; the current data acquisition interval corresponding to the current sampling address is determined; and the preset address length can be half the capacity of the preset storage area.

[0087] S1203: Obtain the current parallel data within the current data acquisition interval.

[0088] In the embodiments described in this specification, all sampled data within the current data acquisition interval are obtained and combined to obtain the current parallel data.

[0089] S1204: Determine the current parallel data corresponding to the current data acquisition interval corresponding to the current data acquisition interval and the current parallel data within the current data acquisition interval.

[0090] In the embodiments of this specification, the current parallel data corresponding to the current data acquisition interval corresponding to the current data acquisition address after sampling and the current parallel data within the current data acquisition interval can be obtained.

[0091] S1205: Construct the address data relationship library based on the mapping relationship between the current extracted address and the current parallel data corresponding to the current extracted address.

[0092] In the embodiments of this specification, an address data relationship library can be constructed based on the mapping relationship between the current post-sampling address and the current parallel data corresponding to the current post-sampling address. Each post-sampling address can serve as a preset trigger address, and the parallel data corresponding to each post-sampling address can serve as preset parallel data. Furthermore, each preset trigger address corresponds to only one preset set of parallel data. Constructing this address data relationship library facilitates rapid data backtracking after the initial trigger address has been determined, obtaining candidate parallel data while preserving the correlation of key data, preventing edge signal loss, and improving system response speed.

[0093] In this embodiment of the specification, the step of filtering the initial parallel data according to the initial trigger address to obtain candidate parallel data includes: The candidate parallel data is obtained by searching the address data relationship database for parallel data that matches the initial trigger address; the address data relationship database includes a preset mapping relationship between the trigger address and the preset parallel data.

[0094] In the embodiments of this specification, the address data relation library includes a preset mapping relationship between trigger addresses and preset parallel data. The preset trigger address is the address after each sampling point. Searching the address data relation library for parallel data matching the initial trigger address yields candidate parallel data. By constructing the address data relation library, candidate parallel data can be directly determined from the initial trigger address, preserving the complete timing sequence before and after the trigger point, improving trigger accuracy, and facilitating the determination of a precise target trigger address.

[0095] The candidate parallel data is subjected to parallel-to-serial conversion to obtain candidate serial data, which is then used as the candidate data.

[0096] In the embodiments of this specification, the candidate parallel data is converted from parallel to serial based on the sampling time of the candidate parallel data to obtain candidate serial data, and the candidate serial data is used as candidate data; by filtering the initial parallel data based on the initial trigger address to obtain candidate parallel data, the filtering range of the target trigger address is narrowed, and the parallel-to-serial conversion of the candidate parallel data eliminates channel competition between multiple FPGAs and multiple analog-to-digital converters.

[0097] In the embodiments of this specification, the parallel-to-serial conversion process is performed on the candidate parallel data to obtain candidate serial data, and the candidate serial data is used as the candidate data, such as... Figure 13 As shown, Figure 13 A flowchart illustrating a method for determining candidate data provided in an embodiment of this specification includes: S1301: The candidate parallel data is split into data with a first preset bit width to obtain a first preset number of initial processing parallel data.

[0098] In the embodiments of this specification, the target FPGA can be one or at least two FPGAs, depending on how many FPGAs the user enables. Similarly, the analog-to-digital converters corresponding to the target FPGAs are also enabled. For example, assuming the user enables four FPGAs, and each analog-to-digital converter corresponding to each FPGA is enabled, such as... Figure 14 As shown, Figure 14 This is a schematic diagram of data splicing provided in an embodiment of this specification. A preset storage area stores all candidate parallel data from four FPGAs. Taking one FPGA as an example, that is... Figure 14The single FPGA data splicing module in the system has a corresponding storage area for each FPGA, and the bit width is 256. That is, the candidate parallel data corresponding to each FPGA can be stored in a 256-bit width, i.e., a [255:0] first-in-first-out queue FIFO. The first preset bit width can be 64, and the first preset number can be 4, i.e., splitting the candidate parallel data to obtain 4 initial processing parallel data with a bit width of 64, which can be denoted as a [63:0] first-in-first-out queue FIFO.

[0099] S1302: For each initial parallel data, perform data splitting with a second preset bit width to obtain a second preset number of secondary parallel data; the first preset bit width is greater than the second preset bit width; the second preset number is greater than the first preset number.

[0100] In the embodiments of this specification, the second preset bit width can be 8, the second preset number can be 8, and each initial processing parallel data is split into 8 data segments with the second preset bit width of 8 to obtain 8 secondary processing parallel data segments. The secondary processing parallel data segments are also stored in the preset storage area. Each secondary processing parallel data segment can be denoted as a [7:0] first-in-first-out queue (FIFO).

[0101] S1303: Perform data splicing on the second preset number of secondary processing parallel data to obtain initial serial data corresponding to each primary processing parallel data.

[0102] In the embodiments of this specification, for each analog-to-digital converter corresponding to each FPGA, the second preset number of secondary processing parallel data is spliced ​​together, and the splicing is performed according to the acquisition time, so as to obtain the initial serial data corresponding to each initial processing parallel data. The initial serial data is also stored in a preset storage area and is 8 bits wide, which can be denoted as a [7:0] first-in-first-out queue FIFO.

[0103] S1304: Perform data splicing processing on the first preset number of initial serial data to obtain the candidate serial data, and the candidate serial data is used as the candidate data.

[0104] In the embodiments described in this specification, for each FPGA, a first preset number of initial serial data are subjected to data splicing processing, that is, after... Figure 14 Reading data 1 from the database yields candidate serial data for a single FPGA. If multiple FPGAs are enabled simultaneously, the serial data for each FPGA is followed by data concatenation processing based on the acquisition time. Figure 14Reading data 2 from the database yields candidate serial data, which is then stored in a preset storage area (referred to as a [7:0] FIFO). The obtained candidate serial data is then subjected to a second trigger, i.e., triggering processing is performed using a second preset mode. By splitting the candidate parallel data into serial data and finally concatenating them, a four-level cache structure with adaptive bandwidth is achieved, eliminating channel contention between multiple FPGAs and the multi-analog-to-digital converter, and saving storage resources.

[0105] S507: The candidate data is triggered using a second preset trigger mode to obtain a second trigger address count value and a second trigger compensation value, and the target trigger address is determined based on the second trigger address count value and the second trigger compensation value.

[0106] In the embodiments of this specification, the candidate data is triggered using a second preset trigger mode to obtain a second trigger address count value and a second trigger compensation value. Based on the second trigger address count value and the second trigger compensation value, a target trigger address count value corresponding to the actual trigger signal is obtained. Then, the target trigger address count value is converted to obtain the target trigger address.

[0107] In this embodiment of the specification, the trigger configuration information further carries the second preset trigger mode; the step of triggering the candidate data using the second preset trigger mode to obtain a second trigger address count value and a second trigger compensation value, and determining the target trigger address based on the second trigger address count value and the second trigger compensation value, includes: The candidate data is triggered using the second preset trigger mode to obtain the second trigger address count value and the second trigger compensation value; In the embodiments of this specification, the trigger configuration information also carries a second preset trigger mode. Similar to the first preset trigger mode, the second preset trigger mode may include a specific trigger mode for candidate data and a trigger setting corresponding to the specific trigger mode. The specific trigger mode may be one of edge triggering, pulse width triggering, or slope triggering. The candidate data is triggered using the second preset trigger mode. When the candidate data detects a trigger event, a trigger signal is generated, and a second trigger address count value and a second trigger compensation value corresponding to the trigger signal are obtained.

[0108] Calculate the difference between the second trigger address count value and the second trigger compensation value, and perform conversion processing on the calculated target trigger address count value to obtain the target trigger address.

[0109] In the embodiments described in this specification, such as Figure 15 As shown, Figure 15This is a schematic diagram illustrating a method for determining a target trigger address provided in an embodiment of this specification. Figure 15 This is just an example; assuming the candidate data includes data with a count of 563, that is... Figure 15 A trigger occurs at point A, but due to a fixed delay in the trigger judgment logic, it is detected when the count value at the second trigger address is 565. Figure 15 At point B, candidate data triggers the event. Therefore, the second trigger compensation value needs to be subtracted from the detected second trigger address count value to obtain the target trigger address count value, which is 563. This target trigger address count value is then converted to obtain the target trigger address within the preset storage area. By combining the second trigger compensation value with the obtained second trigger address count value to obtain the target trigger address count value corresponding to the actual trigger signal, the target trigger address is determined. This helps to dynamically eliminate fixed circuit delays and reduce trigger positioning errors.

[0110] In this embodiment of the specification, the step of calculating the difference between the second trigger address count value and the second trigger compensation value, and then converting the calculated target trigger address count value to obtain the target trigger address, is as follows: Figure 16 As shown, Figure 16 A flowchart illustrating a method for determining candidate serial data provided in an embodiment of this specification includes: S1601: Calculate the difference between the second trigger address count value and the second trigger compensation value to obtain the target trigger address count value.

[0111] In the embodiments of this specification, the target trigger address count value can be obtained by calculating the difference between the second trigger address count value and the second trigger compensation value.

[0112] S1602: Obtain the bit width and preset number of bits of the preset storage area.

[0113] In the embodiments described in this specification, for example, the preset storage area has a bit width of 256 and a preset number of bits of 8. Since one byte consists of 8 bits, the preset number of bits is a fixed value. S1603: Determine the number of bytes in the preset storage space based on the bit width and the preset number of bits.

[0114] In the embodiments of this specification, the number of bytes of the preset storage space can be calculated based on the bit width and the preset number of bits. For example, it can be 32.

[0115] S1604: Determine the target trigger address based on the target trigger address count value and the number of bytes.

[0116] In the embodiments of this specification, the integer and remainder between the target trigger address count value and the number of bytes are calculated. Based on the starting address of the preset storage area, the calculated integer, remainder, and number of bytes, the target trigger address can be calculated. For example, assuming the target trigger address count value is A, the calculated integer is A / 32, and the calculated remainder is A%32. After determining the number of bytes in the preset storage area, a rounding operation is performed between the calculated target trigger address count value and the number of bytes to quickly locate the storage block. A modulo operation is performed between the calculated target trigger address count value and the number of bytes to accurately locate the bytes within the block, thus achieving precise trigger address location.

[0117] S509: Based on the target trigger address and the initial parallel data, determine the target parallel data and output the target parallel data in waveform form to obtain the target waveform.

[0118] In the embodiments of this specification, after the target trigger address is calculated, the target trigger address is sent to the host computer. The host computer reads the data near the target trigger address in the preset storage area to obtain the target parallel data, and outputs the target parallel data in waveform form to obtain the target waveform.

[0119] This specification provides an electronic device including a processor and a memory. The memory stores at least one instruction or at least one program, which is loaded and executed by the processor to implement the FPGA-based method for determining a target waveform as provided in the above method embodiments.

[0120] The embodiments of this application also provide a computer storage medium, which can be disposed in a terminal to store at least one instruction or at least one program related to implementing a method for determining a target waveform based on an FPGA in the method embodiments. The at least one instruction or at least one program is loaded and executed by the processor to implement the method for determining a target waveform based on an FPGA provided in the above method embodiments.

[0121] Embodiments of this application also provide a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the method for determining a target waveform based on an FPGA provided in the above-described method embodiments.

[0122] The memory described in the embodiments of this specification can be used to store software programs and modules. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory. The memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, application programs required for the functions, etc.; the data storage area may store data created according to the use of the device, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory may also include a memory controller to provide the processor with access to the memory.

[0123] The method embodiments for determining target waveforms based on FPGA provided in this specification can be executed in mobile terminals, computer terminals, servers, or similar computing devices.

[0124] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A device for determining a target waveform based on an FPGA, characterized in that, The device includes: The initial parallel data acquisition module is used to acquire the initial parallel data collected by the analog-to-digital converter corresponding to the target FPGA; The initial trigger address determination module is used to trigger the initial parallel data in a first preset trigger mode to obtain a first trigger address count value and a first trigger compensation value; and to determine the initial trigger address based on the first trigger address count value and the first trigger compensation value. The candidate data acquisition module is used to process the initial parallel data according to the initial trigger address to obtain candidate data; The target trigger address determination module is used to trigger the candidate data in a second preset trigger mode to obtain a second trigger address count value and a second trigger compensation value, and determine the target trigger address based on the second trigger address count value and the second trigger compensation value; The target waveform output module is used to determine the target parallel data based on the target trigger address and the initial parallel data, and output the target parallel data in waveform form to obtain the target waveform.

2. The apparatus according to claim 1, characterized in that, The candidate data acquisition module includes: A candidate parallel data acquisition unit is used to filter the initial parallel data according to the initial trigger address to obtain candidate parallel data; A candidate serial data acquisition unit is used to perform parallel-to-serial conversion processing on the candidate parallel data to obtain candidate serial data, which is used as the candidate data.

3. The apparatus according to claim 1, characterized in that, The initial trigger address determination module includes: The first acquisition unit is used to trigger the initial parallel data in the first preset trigger mode to obtain the first trigger address count value and the first trigger compensation value. The third trigger count value determination unit is used to calculate the product value between the first trigger address count value and the preset sampling coefficient to obtain the third trigger count value; The third trigger count compensation value determination unit is used to calculate the product value between the first trigger compensation value and the preset sampling coefficient to obtain the third trigger count compensation value. The initial trigger address determination unit is used to calculate the difference between the third trigger count value and the third trigger count compensation value to obtain the initial trigger address.

4. The apparatus according to claim 2, characterized in that, The target trigger address determination module includes: The second acquisition unit is used to trigger the candidate data in the second preset trigger mode to obtain the second trigger address count value and the second trigger compensation value. The target trigger address determination unit is used to calculate the difference between the second trigger address count value and the second trigger compensation value, and to perform conversion processing on the calculated target trigger address count value to obtain the target trigger address.

5. A method for determining a target waveform based on an FPGA, the method being based on the apparatus as described in any one of claims 1-4, characterized in that, The method includes: Acquire the initial parallel data collected by the analog-to-digital converter corresponding to the target FPGA; The initial parallel data is processed using a first preset trigger mode to obtain a first trigger address count value and a first trigger compensation value; and the initial trigger address is determined based on the first trigger address count value and the first trigger compensation value. The initial parallel data is processed according to the initial trigger address to obtain candidate data; The candidate data is triggered using a second preset trigger mode to obtain a second trigger address count value and a second trigger compensation value. Based on the second trigger address count value and the second trigger compensation value, the target trigger address is determined. Based on the target trigger address and the initial parallel data, the target parallel data is determined, and the target parallel data is output in waveform form to obtain the target waveform.

6. The method according to claim 5, characterized in that, The step of processing the initial parallel data according to the initial trigger address to obtain candidate data includes: The initial parallel data is filtered based on the initial trigger address to obtain candidate parallel data; The candidate parallel data is subjected to parallel-to-serial conversion to obtain candidate serial data, which is then used as the candidate data.

7. The method according to claim 6, characterized in that, Before filtering the initial parallel data according to the initial trigger address to obtain candidate parallel data, the method further includes: The system receives trigger configuration information corresponding to the target FPGA sent by the host computer; the trigger configuration information carries a preset sampling coefficient, a preset storage area, and a starting address corresponding to the preset storage area. The initial parallel data is processed by sampling using the preset sampling coefficient to obtain sampled parallel data; the sampled parallel data includes at least one sampled data. The at least one sampled data is stored in the preset storage area in a preset storage order, and the sampled count value corresponding to each sampled data is determined. Based on the starting address and the count value after each sampling point, determine the address after each sampling point corresponding to the data after sampling. Based on the data after each sampling point and the address after each sampling point corresponding to the data after each sampling point, determine the address data relationship database; The step of filtering the initial parallel data according to the initial trigger address to obtain candidate parallel data includes: The candidate parallel data is obtained by searching the address data relationship database for parallel data that matches the initial trigger address; the address data relationship database includes a preset mapping relationship between the trigger address and the preset parallel data.

8. The method according to claim 7, characterized in that, The step of determining the address data relationship database based on each sampled data point and the sampled address corresponding to each sampled data point includes: The data after each sampling point is traversed sequentially. For the current data after sampling point that is traversed, the current address after sampling point corresponding to the current data after sampling point is determined. Determine the current data acquisition interval corresponding to the current sampling address; the current data acquisition interval is an interval centered on the current sampling address, with a fluctuation range smaller than a preset address length; Obtain the current parallel data within the current data acquisition interval; Based on the current data acquisition interval corresponding to the current data acquisition interval and the current parallel data within the current data acquisition interval, determine the current parallel data corresponding to the current data acquisition interval; The address data relationship library is constructed based on the mapping relationship between the current extracted address and the current parallel data corresponding to the current extracted address.

9. The method according to claim 7, characterized in that, The trigger configuration information also carries the first preset trigger mode; the initial parallel data is triggered using the first preset trigger mode to obtain a first trigger address count value and a first trigger compensation value; And based on the first trigger address count value and the first trigger compensation value, the initial trigger address is determined, including: The initial parallel data is triggered using the first preset trigger mode to obtain the first trigger address count value and the first trigger compensation value. Calculate the product between the first trigger address count value and the preset sampling coefficient to obtain the third trigger count value; Calculate the product between the first trigger compensation value and the preset sampling coefficient to obtain the third trigger count compensation value; The difference between the third trigger count value and the third trigger count compensation value is calculated to obtain the initial trigger address.

10. The method according to claim 9, characterized in that, The trigger configuration information also carries a preset pre-trigger depth value; the step of storing the at least one sampled data point in the preset storage area according to a preset storage order, and determining the sampled count value corresponding to each sampled data point, includes: The at least one sampled data is stored in the preset storage area according to the preset storage order, and the sampled count value corresponding to each sampled data and the real-time pre-trigger depth value corresponding to the preset storage area are determined. The step of triggering the initial parallel data using the first preset trigger mode to obtain the first trigger address count value and the first trigger compensation value includes: If the real-time pre-trigger depth value is greater than or equal to the preset pre-trigger depth value, the initial parallel data is triggered using the first preset trigger mode to obtain the first trigger address count value and the first trigger compensation value.

11. The method according to claim 9, characterized in that, The step of calculating the difference between the third trigger count value and the third trigger count compensation value to obtain the initial trigger address includes: The difference between the third trigger count value and the third trigger count compensation value is calculated to obtain the fourth trigger count value; The initial trigger address is determined based on the starting address corresponding to the preset storage area and the fourth trigger count value.

12. The method according to claim 7, characterized in that, The trigger configuration information also carries the second preset trigger mode; the step of triggering the candidate data using the second preset trigger mode to obtain a second trigger address count value and a second trigger compensation value, and determining the target trigger address based on the second trigger address count value and the second trigger compensation value, includes: The candidate data is triggered using the second preset trigger mode to obtain the second trigger address count value and the second trigger compensation value; Calculate the difference between the second trigger address count value and the second trigger compensation value, and perform conversion processing on the calculated target trigger address count value to obtain the target trigger address.

13. The method according to claim 12, characterized in that, The step of calculating the difference between the second trigger address count value and the second trigger compensation value, and converting the calculated target trigger address count value to obtain the target trigger address, includes: The difference between the second trigger address count value and the second trigger compensation value is calculated to obtain the target trigger address count value; Obtain the bit width and the preset number of bits of the preset storage area; The number of bytes in the preset storage space is determined based on the bit width and the preset number of bits; The target trigger address is determined based on the target trigger address count value and the number of bytes.

14. The method according to claim 6, characterized in that, The process of converting the candidate parallel data into serial data to obtain candidate serial data, wherein the candidate serial data is used as the candidate data, includes: The candidate parallel data is split into data with a first preset bit width to obtain a first preset number of initial processing parallel data. Each initial parallel data is split into two data segments with a second preset bit width to obtain a second preset number of secondary parallel data segments; the first preset bit width is greater than the second preset bit width; the second preset number is greater than the first preset number. The second preset number of secondary processing parallel data are spliced ​​together to obtain the initial serial data corresponding to each primary processing parallel data. The first preset number of initial serial data is subjected to data splicing processing to obtain the candidate serial data, which is used as the candidate data.

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