A phase-locked method and apparatus

Abstract

The application discloses a phase comparison method and device, converts three-phase voltage signals of a reference end into first square wave signals respectively, converts a target-phase voltage signal of a to-be-measured end into a second square wave signal, determines time differences between rising edges of the first square wave signals of the three phases of the reference end and a rising edge of the second square wave signal respectively, determines phase differences between the target phase and the three phases of the reference end according to the time differences corresponding to the phases of the reference end respectively, and finally determines a phase corresponding to a phase difference within a preset phase difference range among the three phases of the reference end as a same phase of the target phase. The phase difference between the target phase of the to-be-measured end and the three phases of the reference end is directly measured through square wave edge triggering timing, without complex voltage sampling calculation, so that the anti-interference capability is high, real-time performance is high, the same phase of the target phase in the reference end can be quickly and accurately identified, and the safety and reliability of parallel operation of a power system are ensured.

Description

Technical Field

[0001] This invention relates to the field of power system control, and in particular to a phase comparison method and apparatus. Background Technology

[0002] Phase verification, also known as phase checking, is the process of detecting and confirming the phase or phase sequence of two or more electrical devices to be connected in a power system. It is mainly used to verify whether the phase angle difference, phase sequence arrangement, and voltage amplitude between the parts to be connected to the grid or the same power supply system meet the preset parallel operation conditions. In other words, it is to ensure that the phases A, B, and C in a three-phase AC system are strictly corresponding in phase, and to avoid serious accidents such as phase-to-phase short circuits, excessive circulating currents, equipment burnout, or large-scale power outages caused by phase inconsistencies.

[0003] Phase verification is a necessary process to ensure the complexity and safety of power system operation. After the construction, renovation, or maintenance of power lines, or when the system wiring method changes, factors such as line transposition, reversed transformer polarity, incorrect phase sequence calibration, or differences in equipment parameters may lead to inconsistent phase angles or disordered phase sequences between power sources to be connected. If loop-closing or grid connection operations are rashly performed under these conditions, a huge electrical shock will occur. This can cause relay protection devices to malfunction or disconnect power supply, or even directly damage critical power equipment, threatening the stable operation of the power grid and the personal safety of operators. Therefore, phase verification is an indispensable key technical link to ensure safe parallel connection, reliable power supply, and prevent electrical malfunctions in the power system. Summary of the Invention

[0004] The purpose of this invention is to provide a phase comparison method and apparatus that directly measures the phase difference between the target phase at the test end and the three phases at the reference end by triggering timing with a square wave edge. This eliminates the need for complex voltage sampling calculations, provides strong anti-interference capabilities and high real-time performance, and can quickly and accurately identify the in-phase target phase at the reference end, ensuring the safety and reliability of parallel operation of the power system.

[0005] To solve the above-mentioned technical problems, the present invention provides a nucleation method, comprising: The voltage signals of the three phases at the reference terminal are converted into first square wave signals respectively; Convert the voltage signal of the target phase at the end under test into a second square wave signal; Timing begins when the rising edge of the second square wave signal is detected, and the time difference between the rising edges of the first square wave signals corresponding to each phase reaching the reference terminal after timing begins is determined. The phase difference between the target phase and the three phases of the reference end is determined according to the time difference corresponding to each phase of the reference end. The phase whose phase difference is within a preset phase difference range among the three phases of the reference end is determined as the same phase as the target phase.

[0006] Preferably, before starting timing upon detecting the rising edge of the second square wave signal, the method further includes: Determine the period of the first square wave signal in the three phases of the reference terminal; The first voltage values ​​of the first square wave signals of the three phases of the reference terminal are obtained respectively; After half of the cycle, the second voltage values ​​of the first square wave signals of the three phases of the reference terminal are obtained respectively. Determine whether the first voltage value and the corresponding second voltage value of the three phases of the reference terminal are all different; If they are all different, proceed to the step of starting the timing when the rising edge of the second square wave signal is detected; If they are not all different, a phase loss alarm will be triggered.

[0007] Preferably, before triggering the phase loss alarm, the method further includes: Among the three phases of the reference terminal, the phase in which the first voltage value and the corresponding second voltage value are the same is determined as the phase with missing phase; To trigger a phase loss alarm, including: A phase loss alarm is generated based on the phase loss.

[0008] Preferably, determining the phase difference between the target phase and the three phases of the reference end based on the time difference corresponding to each phase of the reference end includes: Determine the periods of the first square wave signal and the second square wave signal; The time difference corresponding to the three phases of the reference end is divided by the period and then multiplied by the angle value corresponding to a complete period to obtain the phase difference between the target phase and the three phases of the reference end.

[0009] Preferably, after determining the phase difference between the target phase and the three phases of the reference end based on the time difference corresponding to each phase of the reference end, the method further includes: Based on the magnitude relationship between the phase differences corresponding to the three phases of the reference end, the phase sequence information of the three phases of the reference end is determined; Phase sequence prompts are provided based on the phase sequence information.

[0010] Preferably, it further includes: If the phase difference corresponding to the three phases of the reference end is not within the preset phase difference range, a phase nucleation failure is indicated.

[0011] Preferably, the three phases of the reference terminal and the target phase of the measured terminal each correspond to a voltage sensor, and the phase comparison method further includes: The first output voltage of the voltage sensor corresponding to the three phases of the reference terminal, and the second output voltage of the voltage sensor corresponding to the target phase of the test terminal are obtained respectively. The voltage signals of the three phases of the reference terminal are determined based on the first output voltage corresponding to the three phases of the reference terminal and the voltage conversion parameters of the corresponding voltage sensor. The voltage signal of the target phase of the terminal under test is determined based on the second output voltage corresponding to the target phase of the terminal under test and the voltage conversion parameters of the corresponding voltage sensor.

[0012] To solve the above-mentioned technical problems, the present invention provides a nucleation device, comprising: Memory, used to store computer programs; A processor, used to implement the steps of the nucleus method as described above when executing a computer program.

[0013] Preferably, it also includes several voltage sensors; Each voltage sensor's input terminal is connected to one of the three phases of the reference terminal and the target phase of the test terminal, respectively. The output terminal of each voltage sensor is connected to the processor to acquire the first output voltage of the three phases of the reference terminal and the second output voltage of the target phase of the test terminal, respectively. This allows the processor to determine the voltage signals of the three phases of the reference terminal based on the first output voltage of the three phases of the reference terminal, and to determine the voltage signal of the target phase of the test terminal based on the second output voltage of the target phase of the test terminal.

[0014] Preferably, the voltage sensor includes a first capacitor and a second capacitor; The first terminal of the first capacitor is the input terminal of the voltage sensor, the second terminal of the first capacitor is the output terminal of the voltage sensor and is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is grounded.

[0015] This application provides a phase comparison method and apparatus. The method converts the voltage signals of the three phases at the reference end into first square wave signals, and converts the voltage signal of the target phase at the test end into a second square wave signal. The time difference between the rising edges of the first and second square wave signals at the three phases of the reference end is determined. Then, based on the time differences corresponding to each phase at the reference end, the phase difference between the target phase and each of the three phases at the reference end is determined. Finally, the phases whose phase differences are within a preset phase difference range are identified as the in-phase phases of the target phase. This method directly measures the phase difference between the target phase at the test end and the three phases at the reference end using square wave edge-triggered timing. It eliminates the need for complex voltage sampling calculations, offers strong anti-interference capabilities and high real-time performance, and can quickly and accurately identify the in-phase phases of the target phase at the reference end, ensuring the safe and reliable operation of the power system in parallel. Attached Figure Description

[0016] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic flowchart of a phase re-examination method provided in this application; Figure 2 A schematic diagram illustrating the principle of a zero-crossing phase difference detection method provided in this application; Figure 3 A schematic diagram of a phase difference detection method using a sinusoidal waveform transformation method provided in this application; Figure 4 This application provides a schematic diagram of a phase sequence recognition process. Figure 5 A schematic diagram of a phase difference determination process provided in this application; Figure 6 This application provides a schematic diagram of the structure of a nucleus phase system. Figure 7 A schematic diagram of a nuclear phase device provided in this application; Figure 8 This is a schematic diagram of the structure of a voltage sensor provided in this application; Figure 9 A schematic diagram of the specific structure of a nuclear phase device provided in this application; Figure 10 A schematic diagram of a waveform conversion circuit provided in this application; Figure 11 This is a schematic diagram of the structure of a computer-readable storage medium provided in this application. Detailed Implementation

[0018] The core of this invention is to provide a phase comparison method and apparatus that directly measures the phase difference between the target phase at the test end and the three phases at the reference end by triggering timing with a square wave edge. This eliminates the need for complex voltage sampling calculations, provides strong anti-interference capabilities and high real-time performance, and can quickly and accurately identify the in-phase target phase at the reference end, ensuring the safety and reliability of parallel operation of the power system.

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Please refer to Figure 1 , Figure 1 This application provides a flowchart illustrating a phase re-examination method, which includes: S11: Convert the voltage signals of the three phases of the reference terminal into first square wave signals respectively; Traditional phase comparison methods typically employ correlation analysis or the Discrete Fourier Transform (DFT) algorithm to calculate phase difference. While the DFT algorithm can eliminate DC components and higher harmonics that affect the measurement results, it requires multiple data acquisitions within each cycle of the voltage signal, resulting in a large amount of statistical and computational work. Furthermore, the software programming based on the DFT algorithm is complex, demanding a high level of programming knowledge from the programmers and requiring high performance from the A / D conversion module (Analog-to-Digital Converter). Additionally, the data acquisition process must occur within the same cycle; otherwise, aliasing, picket fence, and truncation effects can easily occur, affecting the accuracy of the phase comparison results. Correlation analysis can effectively suppress noise interference with voltage signals. In the theoretical derivation, it can be determined that the calculation process is unrelated to the frequency of the voltage signal. Therefore, two sinusoidal signals with similar frequencies do not interfere with the calculation results. Thus, correlation analysis is suitable for measuring the phase difference between high-frequency signals. However, the measurement accuracy of correlation detection is affected by the number of sampling points. The more sampling points, the higher the measurement accuracy. At the same time, the amount of data calculation also increases, the program becomes more complex, lacks real-time performance, and places more stringent requirements on the design of A / D conversion modules and hardware circuits. Based on this, it can be determined that correlation analysis and discrete Fourier transform algorithms have high hardware performance requirements, and the waveform processing circuits and software programming are very complex. Although correlation analysis can effectively eliminate the influence of noise, its calculation process involves various complex algorithms, which requires a large amount of software resources to compensate for for low-power embedded systems. The measurement accuracy of these two methods is closely related to the number of sampling points. If the number of samples does not meet the requirements, the phase comparison results may have a large error with the actual results. In addition, the actual frequency of the power network is not stable and fluctuates within a certain range, which may lead to asynchronous sampling, making it difficult to meet the measurement accuracy requirements.

[0021] In this step, data sampling is not required. Instead, the three-phase voltage signals at the reference terminal, namely the AC voltage waveforms of phases A, B, and C, are first acquired. Since the original voltage signals are in sinusoidal form, they cannot be directly used for edge-triggered timing. Therefore, a zero-crossing comparator or Schmitt trigger is needed to convert the three phases of the sinusoidal voltage signals at the reference terminal into square wave signals of the same frequency, denoted as the first square wave signal. Specifically, when the voltage waveform crosses zero from negative to positive, the comparator output flips to a high level; when it crosses zero from positive to negative, it flips to a low level, thus forming a square wave signal with the same frequency and phase as the voltage signal. Through this conversion, the continuous analog voltage signal is discretized into a digital pulse signal with distinct rising and falling edges, providing a reliable reference for subsequent high-precision timing based on edge triggering. Therefore, the rising edge of the first square wave signal can accurately characterize the moment when the voltage waveform crosses zero, avoiding the delays and errors caused by directly sampling and complex calculations of the sine wave.

[0022] It should be noted that the first square wave signals of the three phases of the reference end are not the same square wave signal, but square wave signals corresponding to the voltage signals of the three phases, with a phase difference of 120° in sequence. They are all marked with the first square wave signal, which will not be elaborated further in this application.

[0023] S12: Convert the voltage signal of the target phase at the end under test into a second square wave signal; This step processes the voltage signal of the target phase at the test end in the same way as the voltage signals of the three phases at the reference end. The target phase at the test end refers to a specific phase conductor in the equipment to be connected to the grid, whose phase affiliation needs to be determined. Its voltage signal is also a sinusoidal AC waveform, and its frequency and wave speed are the same as those of the voltage signal at the reference end, respectively. This application will not elaborate on this further. Similarly, the voltage signal of the target phase at the test end is converted into a square wave signal, denoted as the second square wave signal, using a zero-crossing comparator. The second square wave signal also indicates the zero-crossing time of the voltage waveform of the target phase at the test end with its rising edge. By converting the voltage signal of the target phase at the test end into a square wave signal of the same type and format as the reference end, the zero-crossing times of the reference end and the test end can be compared and measured in a unified signal form, eliminating measurement deviations caused by inconsistent signal types.

[0024] It should be noted that in this application, the reference end and the end under test refer to two or more electrical devices to be connected in a power system. The reference end refers to the power supply side or equipment side in the power system with known phase information, correct wiring, and serving as a reference. The reference end is selected from the busbar, transformer secondary side, or line end with known phase sequence that is already in operation and running stably in the power grid. The three phases (A phase, B phase, C phase) of the reference end have a clear and fixed phase relationship, and its voltage signal phase angle, phase sequence, and frequency serve as the reference quantity for phase verification operation, used for comparison with the end under test. The end under test refers to the target equipment side or line side that needs to be phase verified, and its phase information needs to be confirmed. The end under test may include, but is not limited to, newly built lines, overhauled equipment, generator sets to be connected to the grid, or load ends that need to change their operating mode. The phase and phase sequence of the end under test are unknown or need to be verified relative to the reference end, and there may be phase inconsistencies due to factors such as wiring errors, phase sequence calibration deviations, and line transposition.

[0025] There is a clear reference-measured-quantity relationship between the reference terminal and the terminal under test (DUT). The essence of phase comparison operation is to determine the correspondence between the phase of the DUT and the reference terminal's reference phase by measuring and comparing the voltage signals of corresponding phases of the reference terminal and the DUT, thereby verifying whether they meet the in-phase conditions and phase sequence consistency required for parallel operation or loop operation. In the technical solution of this application, the reference terminal provides a fixed three-phase reference signal, and the DUT provides a single target phase signal. By waveform conversion, time difference measurement, and phase difference calculation of the voltage signals of both, the system ultimately identifies which phase of the three phases of the reference terminal is in phase with the target phase of the DUT.

[0026] It should be noted that the physical locations of the reference end and the end under test can be different bays within the same substation, two ends of the same line, lines to be connected between different substations, or any two electrical nodes that need to be phase-checked. A direct electrical connection between them is not required; they only need to have the same frequency or belong to the same power system to perform phase comparison using the phase-checking method of this invention.

[0027] S13: Start timing when the rising edge of the second square wave signal is detected, and determine the time difference when the rising edge of the first square wave signal of each phase reaches the reference terminal after the timing starts. After the square wave signal conversion is completed, the rising edge of the second square wave signal is used as the starting point for timing. Then, the rising edges of the first square wave signals corresponding to phases A, B, and C of the reference terminal are monitored respectively. When the rising edge of any one of phases A, B, or C arrives, the current timing value is recorded. This timing value is the time difference from the zero-crossing moment of the measured terminal to the zero-crossing moment of that phase on the reference terminal. Specifically, timing begins when the rising edge of the second square wave signal is detected. When the rising edge of the first square wave signal of phase A in the reference terminal is detected, the timing time is determined as the time difference corresponding to A. When the rising edge of the first square wave signal of phase B in the reference terminal is detected, the timing time is determined as the time difference corresponding to B. When the rising edge of the first square wave signal of phase C in the reference terminal is detected, the timing time is determined as the time difference corresponding to C. That is, the starting point of the time difference corresponding to each phase of the reference terminal is the timing starting point corresponding to the rising edge of the second square wave signal, and the timing ending point is the arrival time of the rising edge of the first square wave signal of that phase.

[0028] Through this process, three time differences are obtained between the target phase and the corresponding phases A, B, and C in the reference end.

[0029] It should be noted that the processor 72 has an independent internal crystal oscillator. The output pulses of each crystal oscillator circuit control the timing system. First, the processor 72 is initialized upon power-up. When the processor 72 receives a high level of the second pulse signal from the end under test, it starts the timer and begins counting. At the same time, it starts detecting the zero-crossing point of the three-phase first pulse signal of the reference end. This continues until the positive zero-crossing point (high level) information of the first first pulse signal is received. At this time, the timer is read and recorded as T1, which is the time difference between the first phase of the reference end and the target phase of the end under test. The second high-level information T2 is received again, which is the time difference between the second phase of the reference end and the target phase of the end under test. The last phase is recorded as T3, which is the time difference between the third phase of the reference end and the target phase of the end under test.

[0030] S14: Determine the phase difference between the target phase and the three phases of the reference end based on the time difference corresponding to each phase of the reference end; Since the electrical angles corresponding to the same time difference are not the same when the frequency fluctuates or the rated frequency is different, they cannot be directly used for the determination of phase. Therefore, after obtaining the time difference between the target phase and each phase of the reference end, the time quantity is converted into an angle quantity, that is, the time difference is converted into a phase difference, which facilitates the subsequent phase determination.

[0031] like Figure 2 and Figure 3 As shown, Figure 2 This is a schematic diagram illustrating the principle of a zero-crossing phase difference detection method provided in this application. Figure 3This application provides a schematic diagram of a phase difference detection method using a sinusoidal waveform transformation. Figure 2 As can be seen from this, the period of the two sinusoidal signals is T, and the time difference between the two sinusoidal waveforms is Δt, where Δt = - , and Let these be the zero-crossing times of two sinusoidal signals. After converting the two sinusoidal signals into square wave signals, the difference between the rising edges of the two square wave signals is the time difference between the two sinusoidal signals. The phase difference can then be determined through the time difference.

[0032] S15: Among the three phases of the reference end, the phase whose phase difference is within the preset phase difference range is determined as the same phase as the target phase.

[0033] After obtaining the phase difference between the target phase and the three phases of the reference end, a preset phase difference range is established. This preset phase difference range can be a small angle interval close to 0° (e.g., 0° ± 30°) to determine whether two phases are in phase. For phases A, B, and C of the reference end, it is determined whether their corresponding phase differences fall within this preset phase difference range. If the phase difference of a certain phase falls within the preset phase difference range, it indicates that the phase angle of that phase is basically the same as that of the target phase, and the two are in phase. Through this comparison, it is finally determined which of the three phases (A, B, and C) of the reference end corresponds to the target phase.

[0034] Based on the above embodiments: As a preferred embodiment, before starting timing upon detecting the rising edge of the second square wave signal, the method further includes: Determine the period of the first square wave signal in the three phases of the reference terminal; The first voltage values ​​of the first square wave signals of the three phases of the reference terminal are obtained respectively; After half a cycle, the second voltage values ​​of the first square wave signal of the three phases of the reference terminal are obtained respectively; Determine whether the first voltage value and the corresponding second voltage value of each of the three phases of the reference terminal are different; If they are all different, proceed to the step of starting the timer when the rising edge of the second square wave signal is detected; If they are not all different, a phase loss alarm will be triggered.

[0035] The prerequisite for phase comparison is a complete three-phase signal as a reference, which is then used as a comparison point for the device under test. If the reference signal is incomplete, it will definitely affect the phase comparison result, and may even lead to phase comparison failure, thus defeating the purpose of phase comparison. Therefore, phase loss detection should be performed first. Thus, in this embodiment, to ensure the reliability and safety of the phase comparison operation, phase loss detection is first performed on the three-phase signal at the reference end before the formal timing measurement. Phase loss refers to the absence or poor connection of one or more phases in a three-phase circuit. If phase comparison is performed under these conditions, not only will the correct measurement result not be obtained, but it may also lead to equipment misjudgment or damage.

[0036] First, obtain the period of the first square wave signal of the three phases at the reference end. The period can be obtained by measuring the time interval between two adjacent rising edges, or it can be preset according to the system's rated frequency (e.g., 20ms for 50Hz).

[0037] After determining the period, for phases A, B, and C at the reference terminal, the voltage value of the first square wave signal at the current moment is read and recorded as the first voltage value. Since the square wave signal only has two states, high level and low level, this voltage value is used to characterize the current level state of each phase square wave.

[0038] After acquiring the first voltage value, a half-cycle delay is made, and the voltage values ​​of the first square wave signals of phases A, B, and C are read again and recorded as the second voltage values. The half-cycle delay means that the square wave signal has just completed one level flip, that is, the original high level should become low level, and the original low level should become high level.

[0039] For each of phases A, B, and C, the first voltage value is compared with the second voltage value. Specifically, the first voltage value of phase A is compared with the first voltage value of phase A, the first voltage value of phase B is compared with the first voltage value of phase B, and the first voltage value of phase C is compared with the first voltage value of phase C. Under normal circumstances, the level of the first square wave signal will inevitably reverse after half a cycle; therefore, the first voltage value and the second voltage value should be different. If the first voltage value and the second voltage value of a certain phase are the same, it indicates that the first square wave signal of that phase has not undergone the expected level change, suggesting that the phase may not be connected to a voltage signal or the connection is abnormal, i.e., there is a phase loss fault.

[0040] If the first and second voltage values ​​of the three phases at the reference terminal are different, it is determined that the three-phase connection at the reference terminal is normal and there is no phase loss. At this time, it is allowed to continue to execute the subsequent phase verification process.

[0041] If the first voltage value and the second voltage value of any phase are the same, it is determined that the phase is missing. At this time, a phase missing alarm is triggered, and prompt information is output to the user, such as audible and visual alarm, display of the missing phase location, and the phase comparison process is terminated or the operation is paused until the fault is cleared. This avoids invalid phase comparison measurements in the missing phase state, improving the safety and reliability of the phase comparison operation. In addition, the detection process in this embodiment can be completed using only the level characteristics of the first square wave signal itself and half a cycle delay, without the need to add additional hardware circuits or sensors, resulting in low implementation cost.

[0042] As a preferred embodiment, before triggering the phase loss alarm, the following steps are also included: The phase in which the first voltage value and the corresponding second voltage value are the same among the three phases of the reference terminal is defined as the phase with the missing phase. To trigger a phase loss alarm, including: Phase loss alarm based on the phase loss.

[0043] In this embodiment, the phase loss detection process also includes the location of the phase loss phase. That is, based on the aforementioned phase loss detection, it not only determines whether a phase loss exists, but also identifies the specific phase of the phase loss, and outputs targeted alarm information accordingly, so that on-site operators can quickly locate the fault point and improve the efficiency of fault diagnosis.

[0044] Specifically, after comparing the first and second voltage values ​​of reference phases A, B, and C respectively, for each phase, if the first and second voltage values ​​are the same, it indicates that the expected level flip of the first square wave signal of that phase did not occur after half a cycle, meaning that the voltage signal of that phase is missing or abnormally connected. In this case, that phase is marked as a missing phase. Specifically, if the first and second voltage values ​​of phase A are the same, then phase A is determined to be missing, i.e., phase A is a missing phase; if phase B is the same, then phase B is determined to be missing, i.e., phase B is a missing phase; if phase C is the same, then phase C is determined to be missing, i.e., phase C is a missing phase. If multiple phases simultaneously have the same first and second voltage values, then multiple phases are determined to be missing.

[0045] After identifying the specific phase loss, a targeted alarm operation is executed. For example, if phase A is determined to be missing, the message "Phase A is missing, please check the phase A connection" is output; if phases A and B are determined to be missing simultaneously, the message "Phase A and Phase B are missing, please check the corresponding phase line connection" is output. Alarm methods can include, but are not limited to, text prompts on the display screen, voice broadcasts, and flashing indicator lights (e.g., a flashing red indicator light corresponding to a phase A loss) to intuitively convey fault information to on-site operators. Simultaneously with outputting the phase loss alarm, the phase verification process can be further terminated to ensure that no invalid or dangerous phase verification operations are performed before the fault is resolved.

[0046] As a preferred embodiment, the phase difference between the target phase and the three phases of the reference end is determined according to the time difference corresponding to each phase of the reference end, including: Determine the periods of the first square wave signal and the second square wave signal; The time difference between the three phases of the reference end is divided by the period and then multiplied by the angle value corresponding to a complete period to obtain the phase difference between the target phase and the three phases of the reference end.

[0047] After obtaining the time difference between the target phase and each phase of the reference end, this embodiment further defines the specific implementation method for converting the time difference into a phase difference.

[0048] First, the period of the voltage signal needs to be determined, that is, the period of the first square wave signal and the period of the second square wave signal. The period refers to the time required for the AC voltage waveform to complete one full cycle. For power systems, it is usually the reciprocal of the system frequency; for example, a 50Hz system corresponds to a 20ms period. The period can be obtained, but is not limited to, by directly calculating it by measuring the time interval between two consecutive rising edges of the first or second square wave signal; or, given the system's rated frequency, a preset period value based on the rated frequency. Since the reference terminal and the terminal under test belong to the same power system and have the same frequency, the period value is universal for both.

[0049] After obtaining the time difference and period, for phases A, B, and C at the reference end, the following operations are performed respectively: Divide the corresponding time difference Δt by the period T to obtain the proportion of the time difference to the entire period, i.e., Δt / T. This ratio reflects the relative position of the target phase's zero-crossing moment with respect to the reference end's zero-crossing moment on the time axis; then, multiply this ratio by the angle value corresponding to a complete period to obtain the phase difference Δ between the target phase and the current phase. The angle value corresponding to the complete cycle can be 360 ​​degrees (degrees) or 2π radians (radians), depending on the actual application scenario; this application does not impose any limitation on this. Based on this, the phase difference calculation formula is: Δ =(Δt / T)×360° or Δ =(Δt / T)×2πrad. This calculation yields the three phase differences between the target phase and phases A, B, and C.

[0050] In a preferred embodiment, after determining the phase difference between the target phase and the three phases of the reference end based on the time difference corresponding to each phase of the reference end, the method further includes: Based on the magnitude relationship between the phase differences corresponding to the three phases of the reference end, the phase sequence information of the three phases of the reference end is determined; Phase sequence prompts are provided based on phase sequence information.

[0051] To improve the reliability of data judgment, it is necessary to accurately identify the phase sequence of the three-phase power line at the reference end. There are two types of phase sequence: positive phase sequence and negative phase sequence (reverse phase sequence). The judgment of these two types is determined by the order in which the three-phase lines reach their maximum values. Due to the symmetry of the sinusoidal signal, the phase sequence can also be judged by the order of the zero-crossing points of the three-phase signal. The principle is the same as the maximum value sequence. This application does not limit this.

[0052] After obtaining the phase difference between the target phase and the reference phases A, B, and C, this embodiment further identifies the phase sequence of the three phases at the reference terminal based on the phase difference and outputs a phase sequence prompt to the user. Phase sequence refers to the order in which each phase in a three-phase alternating current reaches its positive maximum value (or zero-crossing point). A correct phase sequence is a fundamental prerequisite for the safe operation of a power system, while an incorrect phase sequence (i.e., reverse sequence) may lead to serious consequences such as motor reversal and malfunction of protection devices. Therefore, synchronously outputting phase sequence information during the phase verification process can help operators promptly detect and correct wiring errors.

[0053] After obtaining the phase difference between the target phase and the reference phases A, B, and C, the phase differences between the target phase and the reference phases A, B, and C are denoted as ΔΦ1, ΔΦ2, and ΔΦ3, respectively. By analyzing the magnitude relationship of these three phase differences, the phase sequence of the three phases at the reference end is determined.

[0054] Specifically, when the reference phase sequence is positive (i.e., phase A leads phase B by 120° and phase B leads phase C by 120°), the phase differences between the target phase and each phase will exhibit a specific ordering pattern. When the reference phase sequence is negative (i.e., reversed), the relationship between the phase differences will exhibit a different ordering pattern. Specifically, by analyzing Δ... 1. Δ 2. Δ 3. Perform pairwise comparisons; the positive and negative phase sequences can be accurately distinguished based on the comparison results. For example, this can be achieved by comparing Δ... 1 and Δ The size of 2, Δ 2 and Δ The size of 3 and Δ 1 and Δ The value of 3 is used to output the phase sequence identification result, that is, to determine the phase sequence information of the three phases of the reference end.

[0055] After determining the phase sequence information of the three phases at the reference terminal, this information is output in a visually intuitive manner. Specific methods for providing the phase sequence indication may include, but are not limited to: directly displaying text information on the screen (e.g., "Phase Sequence: Positive Phase Sequence (ABC)" or "Phase Sequence: Negative Phase Sequence (ACB)"); outputting the phase sequence result via voice announcement; using indicator lights of different colors to indicate the phase sequence status (e.g., green for positive phase sequence, red for negative phase sequence); or uploading the phase sequence information to a smart terminal or backend system via a communication interface. While outputting the phase sequence indication, the device can selectively output subsequent operational suggestions based on whether the phase sequence is correct. For example, if a positive phase sequence is detected, it can prompt "Phase sequence correct, continue phase verification"; if a negative phase sequence is detected, it can prompt "Phase sequence error, please check the reference terminal wiring," to guide the user to correct wiring problems promptly.

[0056] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a phase sequence recognition process provided in this application.

[0057] based on Figure 4 It can be determined that in this application, when determining Δ 1>Δ 2>Δ 3. Δ 3>Δ 1>Δ 2 and Δ 2>Δ 3>Δ When 1 is reached, the output phase sequence is negative, meaning the phase sequence information of the three phases at the reference terminal is negative. This is determined by Δ. 1>Δ 3>Δ 2. Δ 3>Δ 2>Δ 1 and Δ 2>Δ 1>Δ At time 3, the output phase sequence is positive, meaning the three phases at the reference terminal are in positive phase sequence.

[0058] As a preferred embodiment, it also includes: If the phase difference corresponding to the three phases of the reference end is not within the preset phase difference range, the nucleation failure will be indicated.

[0059] In this embodiment, it is determined whether each phase difference falls within the preset phase difference range. If none of the three phase differences fall within the preset phase difference range, it indicates that the target phase does not form a phase relationship with any of the A, B, and C phases of the reference end.

[0060] The reasons for this situation may include, but are not limited to: the reference terminal and the terminal under test not belonging to the same power system, i.e., different frequencies or asynchronous phases; the actual wiring corresponding to the target phase of the terminal under test not matching the expectation; interference during the measurement process causing abnormal time difference measurement; and a fault in the voltage signal of the reference terminal or the terminal under test. In this case, continuing to perform the in-phase determination and forcibly outputting a phase as the result may mislead operators and pose a safety hazard. Therefore, this embodiment triggers a phase verification failure prompt when all three phase differences are detected as not meeting the conditions.

[0061] The methods for indicating a phase comparison failure may include, but are not limited to: displaying the text "Phase comparison failed, please check the wiring or try again" on the screen; issuing a voice prompt indicating a phase comparison error; using an indicator light, such as a flashing yellow light, to indicate an invalid measurement; or uploading the failure information to the backend system via the communication interface. While issuing the prompt, the device can pause the subsequent phase comparison process, waiting for user confirmation or restarting the measurement.

[0062] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a phase difference determination process provided in this application.

[0063] Figure 5 The process involves sequentially determining whether the phase differences corresponding to phases A, B, and C at the reference end are within a preset phase difference range. In this embodiment, the preset phase difference ranges are [0°, 30°] and [330°, 360°]. Considering various possibilities in different test environments and times, there may be no in-phase coincidence signal within the positive 30° range, so a coincidence signal may exist within the -30° range. Since the period of a sinusoidal signal is 360°, phase differences within 330° to 360° still meet the phase comparison standard. These two preset phase difference ranges logically follow an "OR" relationship. This logical judgment can achieve the phase comparison standard. Of course, this application does not limit this; it is also possible to simultaneously determine whether the phase differences corresponding to phases A, B, and C at the reference end are within the preset phase difference range. However, if the phase differences corresponding to phases A, B, and C at the reference end are all outside the preset phase difference range, a phase comparison failure is output, i.e., a phase comparison failure prompt is given.

[0064] In a preferred embodiment, the three phases of the reference terminal and the target phase of the measured terminal each correspond to a voltage sensor. The phase comparison method further includes: Obtain the first output voltage of the voltage sensor corresponding to the three phases of the reference end, and the second output voltage of the voltage sensor corresponding to the target phase of the test end; The voltage signals of the three phases of the reference terminal are determined based on the first output voltage corresponding to the three phases of the reference terminal and the voltage conversion parameters of the corresponding voltage sensors. The voltage signal of the target phase of the test terminal is determined based on the second output voltage corresponding to the target phase of the test terminal and the voltage conversion parameters of the corresponding voltage sensor.

[0065] In the foregoing embodiments, the voltage signals at the reference end and the end under test can be acquired through direct contact, such as using a voltage probe or alligator clips. However, in high-voltage power lines or space-constrained environments, direct contact with live conductors poses safety hazards and is inconvenient to operate. Therefore, this embodiment uses a voltage sensor as the voltage signal acquisition element to obtain the voltage signal. The voltage sensor is characterized by its small size, easy installation, and high safety, making it suitable for high-voltage phase-matching scenarios.

[0066] In this embodiment, phases A, B, and C of the reference end each correspond to a voltage sensor, and the target phase of the test end also corresponds to a voltage sensor. The voltage sensor typically consists of a metal induction plate and an insulating medium. When it is brought close to or fixed near the conductor being measured, a coupling capacitor is formed between the conductor and the induction plate. The alternating voltage on the conductor generates induced charges on the induction plate through this coupling capacitor, thereby forming an induced voltage output with the same frequency and proportionality to the conductor voltage. For the three phases of the reference end, the output voltage of each voltage sensor is read and recorded as the first output voltage; for the target phase of the test end, the output voltage of its voltage sensor is read and recorded as the second output voltage.

[0067] The output voltage of the voltage sensor has a linear relationship with the actual voltage of the conductor being measured, but the specific conversion ratio depends on the voltage conversion parameters of the sensor. Each voltage sensor is calibrated with corresponding voltage conversion parameters before use or at the factory. Using these parameters, the first output voltage is converted into an actual voltage signal. Specifically, for phase A, according to the voltage conversion parameter K_A of its voltage sensor, the first output voltage V_A is converted into an actual voltage signal U_A = K_A × V_A; similarly, for phases B and C, they are converted into U_B and U_C, respectively.

[0068] Similar to the processing at the reference end, for the target phase at the test end, after acquiring the second output voltage V_1 of its voltage sensor, it is converted into an actual voltage signal U_1 = K_1 × V_1 using the voltage conversion parameter K_1 corresponding to the voltage sensor. This conversion process is completely symmetrical with that at the reference end, ensuring that the voltage signals acquired at the reference end and the test end maintain a consistent reference in terms of dimensions, frequency, and phase relationship. The converted voltage signal of the target phase is also a sinusoidal waveform with the same frequency and phase as the actual voltage of the conductor, which can be used for subsequent square wave conversion and phase comparison measurements.

[0069] In summary, this application employs a phase comparison method combining zero-crossing detection and waveform transformation. This method is simple in principle, requires minimal computation, and has a fast response speed. It can measure the phase difference between any two sinusoidal signals of the same frequency, and simultaneously meets the phase comparison requirements of live-line display devices in high-voltage switchgear of different specifications. For example, it is applicable to phase comparison of 6~35KV high-voltage ring main units. Utilizing signal processing technology and the data analysis capabilities of a microcontroller, it performs phase comparison of high and low voltage power lines under operating voltage, determining the phase sequence of the three-phase power lines through comparison. It completes the phase comparison function and phase sequence detection of the measured signal, providing the phase comparison results through LED (Light Emitting Diode) indicators, alarm sounds, and LCD (Liquid Crystal Display) displays. In emergency situations, it can also be used to verify whether a live conductor is energized.

[0070] Please refer to Figure 6 , Figure 6 This application provides a schematic diagram of the structure of a nucleus phase system, which includes: The first conversion unit 61 is used to convert the voltage signals of the three phases of the reference terminal into first square wave signals respectively; The second conversion unit 62 is used to convert the voltage signal of the target phase of the end under test into a second square wave signal; The timing unit 63 is used to start timing when the rising edge of the second square wave signal is detected, and to determine the time difference when the rising edge of the first square wave signal corresponding to each phase reaches the reference end after the timing starts. The first determining unit 64 is used to determine the phase difference between the target phase and the three phases of the reference end according to the time difference corresponding to each phase of the reference end; The second determining unit 65 is used to determine the phase with a phase difference within a preset phase difference range among the three phases of the reference end as the same phase as the target phase.

[0071] For a description of the nucleus system provided by this invention, please refer to the above method embodiments; the invention itself will not be described in detail here.

[0072] Please refer to Figure 7 , Figure 7 This application provides a schematic diagram of the structure of a nucleation device, which includes: Memory 71 is used to store computer program 112; The processor 72 is configured to implement the steps of the core phase method as described above when executing the computer program 112.

[0073] In this embodiment, the processor 72 can be, but is not limited to, a C51 series STC15W4K60S4 microcontroller.

[0074] For a description of the nucleation device provided by the present invention, please refer to the above method embodiments; the present invention will not be described again here.

[0075] In a preferred embodiment, it also includes several voltage sensors; Each voltage sensor's input terminal is connected to one of the three phases of the reference terminal and the target phase of the test terminal, respectively. Each voltage sensor's output terminal is connected to the processor 72 to acquire the first output voltage of the three phases of the reference terminal and the second output voltage of the target phase of the test terminal, respectively. This allows the processor 72 to determine the voltage signals of the three phases of the reference terminal based on the first output voltage of the three phases of the reference terminal and to determine the voltage signal of the target phase of the test terminal based on the second output voltage of the target phase of the test terminal.

[0076] For a description of the nucleation device provided by the present invention, please refer to the above method embodiments; the present invention will not be described again here.

[0077] In a preferred embodiment, the voltage sensor includes a first capacitor and a second capacitor; The first terminal of the first capacitor is the input terminal of the voltage sensor, the second terminal of the first capacitor is the output terminal of the voltage sensor and is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is grounded.

[0078] This embodiment further defines the specific circuit structure of the voltage sensor. By adopting a voltage divider structure with the first capacitor and the second capacitor connected in series, a stable and reliable induced voltage output can be obtained while ensuring safe isolation.

[0079] In this preferred embodiment, the voltage sensor is composed of a first capacitor and a second capacitor connected in series. Please refer to... Figure 8 , Figure 8 This is a schematic diagram of the structure of a voltage sensor provided in this application. Vin is the input terminal of the voltage sensor, Vout is the output terminal of the voltage sensor, the first terminal of the first capacitor serves as the input terminal of the voltage sensor, and is used to be close to or around the wire being measured to form a coupling capacitor with the wire being measured; the second terminal of the first capacitor serves as the output terminal of the voltage sensor and is connected to the first terminal of the second capacitor; the second terminal of the second capacitor is grounded.

[0080] When the input terminal of the voltage sensor is near or around a live conductor, a coupling capacitor is formed between the conductor being measured and the first terminal of the first capacitor. The alternating voltage on the conductor induces a charge on the first capacitor through this coupling capacitor, thereby forming an induced voltage at the first terminal of the first capacitor with the same frequency and proportionality to the conductor voltage. This induced voltage is transmitted to the second terminal of the first capacitor, i.e., the output terminal of the sensor. Since the first and second capacitors are connected in series and the second terminal of the second capacitor is grounded, the first and second capacitors together form a capacitive voltage divider. According to the principle of capacitive voltage division, the ratio of the voltage at the sensor output terminal to the voltage of the conductor being measured is approximately equal to the relationship between the equivalent capacitance of the first and second capacitors connected in series and the coupling capacitor. By reasonably selecting the capacitance values ​​of the first and second capacitors, the sensor output voltage can be made to fall within the appropriate input range of the subsequent signal processing circuit, while achieving high-voltage isolation to ensure measurement safety. Furthermore, the voltage divider formed by the first and second capacitors has high accuracy and stability, and the divided voltage signal has a high degree of linearity and similarity to the measured high-voltage waveform, avoiding distortion and aberration problems during signal acquisition.

[0081] Based on this, for phase A, the specific formula for converting the first output voltage V_A into the actual voltage signal U_A is U_A = ((C1+C2) / C1) × V_A, where C1 is the capacitance value of the first capacitor and C2 is the capacitance value of the second capacitor. Similarly, for phases B and C, as well as the target phase at the end to be measured, the values ​​of the first and second capacitors in their respective voltage sensors are used to convert them into U_B, U_C, and U_1, respectively.

[0082] Figure 8 C1 is the first capacitor, and C2 is the second capacitor.

[0083] In addition, please refer to Figure 9 , Figure 9 This is a schematic diagram of a phase comparison device provided in this application. The reference end in the diagram represents a device in the power system with a known phase. The end to be tested is a device to be connected to the power system, or a device to be connected in parallel with the reference end but with an unknown phase. The end to be tested also includes three phases, each of which can be a target phase. Each phase is connected to a voltage sensor. In this application, phase comparison can be performed on all three target phases simultaneously, or sequentially, without limitation. The output of each voltage sensor is connected to a waveform conversion circuit through a phase comparison aperture. In this embodiment, the processor 72 is not required to perform waveform conversion processing, thus reducing the computational load on the processor 72. When performing phase comparison on each phase of the end to be tested, the processor 72 can control the waveform conversion circuit of the end to be tested to connect to any one of the phase comparison apertures of the end to be tested, as needed. The phase corresponding to the phase comparison aperture connected to the waveform conversion circuit of the end to be tested is the target phase.

[0084] Figure 9 The voltage sensor in the middle is Figure 8 A simplified schematic diagram of a medium voltage sensor.

[0085] Please refer to Figure 10 , Figure 10 This is a schematic diagram of a waveform conversion circuit provided in this application. The P1 terminal is connected to the phase hole and the reference voltage, and the J3 terminal is connected to the processor 72. It can not only perform waveform conversion, but also filter and amplify signals. It avoids the fluctuation of the grid voltage due to load fluctuations, and also avoids the transmission loss and harmonic pollution caused by setting equivalent impedances and distributed capacitances in the impedance path and admittance path in the distributed equivalent circuit of the transmission line. This improves the conversion accuracy of the first square wave signal and the second square wave signal.

[0086] Furthermore, during long-distance power grid transmission, high-frequency signals in the air can interfere with and cause noise to the sinusoidal signal. The effects of these harmonics and noise on the zero-crossing phase can be directly observed through… Figure 10 The filtering effect of the waveform conversion circuit removes it.

[0087] Please refer to Figure 11 , Figure 11 This is a schematic diagram of the structure of a computer-readable storage medium provided in this application. The computer-readable storage medium 111 in this invention stores a computer program 112. When the computer program 112 is executed by the processor 72, it implements the steps of the nucleation method as described above.

[0088] For a description of the computer-readable storage medium 111 provided by the present invention, please refer to the above method embodiments; the present invention will not be described again here.

[0089] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0090] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A nucleus phase method, characterized in that, include: The voltage signals of the three phases at the reference terminal are converted into first square wave signals respectively; Convert the voltage signal of the target phase at the end under test into a second square wave signal; Timing begins when the rising edge of the second square wave signal is detected, and the time difference between the rising edges of the first square wave signals corresponding to each phase reaching the reference terminal after timing begins is determined. The phase difference between the target phase and the three phases of the reference end is determined according to the time difference corresponding to each phase of the reference end. The phase whose phase difference is within a preset phase difference range among the three phases of the reference end is determined as the same phase as the target phase.

2. The nucleus phase method as described in claim 1, characterized in that, Before starting timing upon detecting the rising edge of the second square wave signal, the process also includes: Determine the period of the first square wave signal in the three phases of the reference terminal; The first voltage values ​​of the first square wave signals of the three phases of the reference terminal are obtained respectively; After half of the cycle, the second voltage values ​​of the first square wave signals of the three phases of the reference terminal are obtained respectively. Determine whether the first voltage value and the corresponding second voltage value of the three phases of the reference terminal are all different; If they are all different, proceed to the step of starting the timing when the rising edge of the second square wave signal is detected; If they are not all different, a phase loss alarm will be triggered.

3. The nucleus phase method as described in claim 2, characterized in that, Before triggering a phase loss alarm, the following steps are also required: Among the three phases of the reference terminal, the phase in which the first voltage value and the corresponding second voltage value are the same is determined as the phase with missing phase; To trigger a phase loss alarm, including: A phase loss alarm is generated based on the phase loss.

4. The nucleus phase method as described in claim 1, characterized in that, Determining the phase difference between the target phase and the three phases of the reference end based on the time difference corresponding to each phase of the reference end includes: Determine the periods of the first square wave signal and the second square wave signal; The time difference corresponding to the three phases of the reference end is divided by the period and then multiplied by the angle value corresponding to a complete period to obtain the phase difference between the target phase and the three phases of the reference end.

5. The nucleation method as described in claim 1, characterized in that, After determining the phase difference between the target phase and the three phases of the reference end based on the time difference corresponding to each phase of the reference end, the method further includes: Based on the magnitude relationship between the phase differences corresponding to the three phases of the reference end, the phase sequence information of the three phases of the reference end is determined; Phase sequence prompts are provided based on the phase sequence information.

6. The nucleus phase method as described in claim 1, characterized in that, Also includes: If the phase difference corresponding to the three phases of the reference end is not within the preset phase difference range, a phase nucleation failure is indicated.

7. The nucleation method according to any one of claims 1-6, characterized in that, The three phases of the reference terminal and the target phase of the measured terminal each correspond to a voltage sensor. The phase comparison method further includes: The first output voltage of the voltage sensor corresponding to the three phases of the reference terminal, and the second output voltage of the voltage sensor corresponding to the target phase of the test terminal are obtained respectively. The voltage signals of the three phases of the reference terminal are determined based on the first output voltage corresponding to the three phases of the reference terminal and the voltage conversion parameters of the corresponding voltage sensor. The voltage signal of the target phase of the terminal under test is determined based on the second output voltage corresponding to the target phase of the terminal under test and the voltage conversion parameters of the corresponding voltage sensor.

8. A nucleation device, characterized in that, include: Memory, used to store computer programs; A processor, configured to, when executing a computer program, implement the steps of the nuclear phase method as described in any one of claims 1-7.

9. The nucleation apparatus as described in claim 8, characterized in that, It also includes several voltage sensors; Each voltage sensor's input terminal is connected to one of the three phases of the reference terminal and the target phase of the test terminal, respectively. The output terminal of each voltage sensor is connected to the processor to acquire the first output voltage of the three phases of the reference terminal and the second output voltage of the target phase of the test terminal, respectively. This allows the processor to determine the voltage signals of the three phases of the reference terminal based on the first output voltage of the three phases of the reference terminal, and to determine the voltage signal of the target phase of the test terminal based on the second output voltage of the target phase of the test terminal.

10. The nucleation apparatus as claimed in claim 9, characterized in that, The voltage sensor includes a first capacitor and a second capacitor; The first terminal of the first capacitor is the input terminal of the voltage sensor, the second terminal of the first capacitor is the output terminal of the voltage sensor and is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is grounded.

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