An extremely resource-restricted embedded control device
By using a multi-offset instruction decoding unit and a fixed-timing pipelined execution controller, the problems of code density, startup latency, and memory utilization in embedded systems under extremely resource-constrained scenarios are solved, realizing a high-efficiency, low-power embedded control device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 胡艳红
- Filing Date
- 2026-04-18
- Publication Date
- 2026-06-12
AI Technical Summary
Existing embedded RTOS cannot adapt to extremely resource-constrained scenarios, and suffers from problems such as insufficient code density, high startup latency, large scheduling overhead, and low storage utilization. It cannot solve these core pain points at the same time.
It employs a multi-offset instruction decoding unit and a fixed-timing pipelined execution controller to implement instruction decoding and pipelined execution through hardware circuitry, eliminating task scheduling and synchronization mutual exclusion logic, unifying addressing memory management, enabling in-situ hardware configuration, eliminating the Bootloader and HAL layer, and achieving efficient execution of hardware operations.
It achieves a code density increase of more than 3 times, a startup latency reduction of 20,000 times, a storage resource utilization rate of 100%, a power consumption reduction of more than 70%, and is suitable for scenarios with limited storage of 2KB level.
Smart Images
Figure CN122194812A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of embedded system technology, specifically relating to embedded control devices and execution methods for scenarios with extremely limited resources. Background Technology
[0002] With the large-scale deployment of IoT technology, passive RFID tags, implantable medical chips, micro-nano environmental sensors, and industrial emergency triggering joints are emerging. Extremely resource-constrained scenarios, such as point-to-point operation, place stringent demands on embedded control systems: they typically only have KB-level on-chip storage and microwatt-level power consumption. Due to budget constraints and nanosecond-level startup requirements, existing embedded real-time operating systems (RTOS) are not adequately suited.
[0003] Existing mainstream embedded RTOS, such as FreeRTOS and RT-Thread, have the following core technical shortcomings: 1. Insufficient code density; the minimum trimmed image size is usually ≥6KB, which cannot adapt to extreme storage-constrained scenarios with less than 2KB. 2. Based on a task scheduler, there is inherent scheduling overhead and task switching latency, and it also requires supporting synchronization mechanisms such as semaphores and mutexes. This results in a large amount of redundant code and is prone to race conditions; 3. Relying on the bootloader for hardware initialization and image loading results in a startup latency typically in the millisecond range, which cannot meet the nanosecond-level ultra-fast startup requirements of passive scenarios. Startup requirements; 4. Using a hardware abstraction layer to achieve cross-platform adaptation brings additional execution overhead and code redundancy, and the hardware operation efficiency cannot reach the theoretical limit; 5. The segmented storage design strictly follows the von Neumann architecture, resulting in a large number of storage fill bits and memory fragmentation, leading to low storage resource utilization.
[0004] To address the aforementioned issues, existing technologies can only achieve optimization in a single dimension and cannot simultaneously solve problems related to code density, startup latency, scheduling overhead, etc. The core pain point is storage utilization, and there is no complete hardware engineering solution adapted to extremely resource-constrained scenarios. Summary of the Invention
[0005] 1. Technical problems to be solved The purpose of this invention is to overcome the aforementioned deficiencies of the prior art and provide an embedded control device and execution method with extremely limited resources. Breaking through the architectural limitations of traditional embedded systems, while simultaneously solving problems such as insufficient code density, high startup latency, large scheduling overhead, and storage limitations in existing technologies. The core technical problem is low utilization and inability to adapt to extremely resource-constrained scenarios at the KB level.
[0006] 2. Technical Solution To achieve the above objectives, the present invention adopts the following technical solution: On one hand, this invention provides an extremely resource-constrained embedded control device, including a processor, storage medium, and a multi-offset instruction decoder. Unit, fixed-timing pipelined execution controller; The input terminal of the multi-offset instruction decoding unit is electrically connected to the address output terminal of the storage medium, and the decoding output terminal is electrically connected to the instruction input terminal of the processor. The input pins are pre-set with at least three sets of instruction decoding windows with fixed address offsets, used for decoding binary data within the same continuous linear address space. The data is decoded according to different starting offsets, and at least two sets of independent, valid instruction sequences that can be executed by the processor are output. The timing trigger terminal of the fixed-timing pipelined execution controller is electrically connected to the processor's execution control pin, and the instruction input terminal is electrically connected to the multi-biased... The output of the shift instruction decoding unit is pre-configured with a four-stage fixed-timing hardware execution pipeline, which executes the instruction sequentially according to the pre-configured fixed timing after power-on. It triggers the execution of each level of the pipeline without task scheduling, concurrent switching, or synchronous mutual exclusion arbitration logic.
[0007] On the other hand, the present invention provides an execution method for an extremely resource-constrained embedded system, including a multi-offset instruction encoding step and a fixed-time... Sequential pipeline execution steps.
[0008] 3. Beneficial effects Compared with the prior art, the present invention has the following significant beneficial technical effects: 1. Code density breaks physical limits: Through multi-offset instruction decoding units, multiple independent functional instructions can be encoded within the same storage sequence, reducing code density by one unit. The code density is more than 3 times higher than traditional encoding schemes, and the size of the complete system image can be compressed to 1.8KB, far smaller than the minimum 6KB of existing RTOS. The reduced file size is perfectly suited for scenarios with extremely limited storage, such as those with 2KB or less of storage capacity. 2. Zero-overhead, ultra-fast startup: By starting the hardware configuration unit in place, the bootloader is completely abandoned, and the reset vector directly points to the execution entry point. With zero initialization overhead, on a 32MHz MCU, business code can be executed within 3 clock cycles after power-on, with a startup latency of ≤100ns, compared to current... Embedded systems have seen improvements of over 20,000 times; 3. Zero-scheduling-overhead deterministic execution: By using a fixed-time pipelined execution controller, the traditional task scheduler is completely abandoned, eliminating all scheduling overhead. With minimal overhead and task switching latency, no need for synchronous mutually exclusive components, race conditions are completely eliminated, and execution is 100% deterministic. 4. 100% Storage Resource Utilization: Through a unified addressing storage management unit, code / data boundaries are broken down, resulting in no storage padding and no memory fragmentation. Storage resource utilization reached 100%; 5. Extremely low power consumption: Hardware operations are executed directly at the register level via direct connection to the hardware adapter unit, eliminating abstraction layer overhead and significantly reducing execution cycle time. There are no redundant operations, and the power consumption during sleep mode is reduced to the microwatt level, which is more than 70% lower than that of existing RTOS. Attached Figure Description
[0009] Figure 1 is a block diagram of the overall hardware architecture of the embedded control device of the present invention; Figure 2 is a hardware circuit schematic diagram of the multi-offset instruction decoding unit of the present invention; Figure 3 is a timing triggering logic diagram of the fixed-timing pipeline execution controller of the present invention; Figure 4 is a flowchart of the steps of the embedded system execution method of the present invention. Detailed Implementation
[0010] The present invention will be further described in detail below with reference to specific embodiments and accompanying drawings. Those skilled in the art will be able to understand from the disclosure herein... The contents readily reveal other advantages and benefits of the present invention. The present invention can also be implemented or applied through other different specific embodiments. Furthermore, the details in this specification can be modified or altered in various ways based on different viewpoints and applications without departing from the spirit of this invention. Change. Example
[0011] This embodiment provides an embedded control device with extremely limited resources. The target hardware is a domestically produced CH32V003F4U6 embedded MCU, core- The core configuration is: RISC-V The RV32EC core, with a 48MHz clock speed, 16KB of on-chip Flash, and 2KB of on-chip RAM, perfectly meets the hardware characteristics of extremely resource-constrained scenarios.
[0012] The embedded control device includes a CH32V003 processor, on-chip Flash storage medium, a multi-offset instruction decoding unit, and a fixed timing stream. Waterline execution controller, unified addressing memory management unit, in-situ boot hardware configuration unit, register direct connection hardware adaptation unit, distributed- Redundant fault-tolerant unit.
[0013] 1. Specific implementation of the multi-offset instruction decoding unit. This unit is adapted to RISC-V. The RV32EC architecture features a 16-bit compressed instruction set (C extension). The hardware circuitry consists of three parallel address offset registers, an instruction decoder, and an output... The multiplexer is configured with address offset registers preset to 0 byte address offset, +1 byte address offset, and +2 byte address offset, corresponding to 3 sets of - Command decoding window.
[0014] The same 32-bit contiguous memory address space (addresses 0x00000000-0x00000003) stores binary data as 0x00100113 0x- 00200193, decoded through different decoding windows, yields two completely independent sets of legal instruction sequences: ◦ 0 address offset decoding window output (Function 1: ADC sampling initialization): 0x00000000: 0x00100113 → addi x2, x0, #1 ; Configure ADC sampling channel 1 0x00000004: 0x00200193 → addi x3, x0, #2 ; Configure sampling precision to 12 bits. ◦ +1 byte address offset decoding window output (Function 2: Sleep mode configuration): 0x00000001: 0x10011300 → c.addi x1, #16 ; Configure the sleep clock source 0x00000005: 0x20019300 → c.addi x3, #32 ; Configure deep hibernation mode Meanwhile, the binary value 0x00100113 stored in this segment is directly used as the ADC sampling threshold constant, and 0x00200193 is directly used as the delay value. When function parameters are used, address space reuse is achieved for instructions, data, and configuration parameters.
[0015] 2. Specific implementation of the fixed-time pipelined execution controller This unit is a hardware timing trigger circuit, consisting of four cascaded timing flip-flops. The output of each flip-flop is electrically connected to the processor. The execution control pins and peripheral control pins are triggered sequentially in a fixed order after power-on. There is no task scheduling logic. The specific execution logic is as follows: / / The reset vector points directly to this entry point, with no Bootloader or initialization overhead. void system_entry(void) { while(1) { / / Level 1: Peripheral hijacking level, triggered in the first power-on sequence RCC->APB2PCENR |= RCC_APB2Periph_GPIOA | RCC_APB2Periph_ADC1; GPIOA->CFGLR &= ~0x0F; GPIOA->CFGLR |= 0x00; ADC1->CTLR2 |= ADC_ADON; / / Second level: Operation execution level, second timing trigger ADC1->SAMPTR2 |= 0x07; ADC1->RSQR1 = 0; ADC1->RSQR3 = 0; ADC1->CTLR2 |= ADC_SWSTART; while(!(ADC1->STATR & ADC_EOC)); uint16_t adc_val = ADC1->RDATAR; / / Level 3: Data transmission level, triggered by the third timing sequence while(!(USART1->STATR & USART_FLAG_TC)); USART1->DATAR = adc_val & 0xFF; / / Level 4: Sleep Reset Level, triggered by the fourth timing sequence ADC1->CTLR2 &= ~ADC_ADON; RCC->APB2PCENR &= ~(RCC_APB2Periph_GPIOA | RCC_APB2Periph_ADC1); PWR->CTLR |= PWR_PDDS; __WFI(); } } 3. Specific implementation of other units ◦ Unified Addressing Memory Management Unit: Combines the 16KB Flash memory of CH32V003 with the 2KB... RAM uses unified linear addressing, with an address space of 0x08000000-0x08003FFF (Flash) and 0x20000000-0x200007FF (-). RAM (Random Access Memory) does not have a strict division into code segment, data segment, stack area, and heap area. The address space after instruction execution can be directly used by subsequent data. Overlay reuse; ◦ In-situ startup of the hardware configuration unit: The reset interrupt vector of CH32V003 is directly mapped to the entry point of the system_entry function, without a startup file. No initialization of the .data / .bss segment, no preset stack pointer, and the core code is executed directly after power-on; ◦ Register direct-connect hardware adapter unit: All hardware operations are hard-coded register read / write instructions, with no HAL layer, no driver framework, and no... Indirect calls push hardware operation efficiency to its theoretical limit; ◦ Distributed Redundant Fault-Tolerant Unit: When a single node experiences an exception, the watchdog timer is directly triggered for reset; 10 nodes of the same type form a distributed sampling network. The system outputs the final result through a majority consensus mechanism, achieving high availability at the system level.
[0016] 4. Performance test results of this embodiment Performance indicators Test Results Comparison with FreeRTOS Minimal Version Full image volume 1.8KB 6.2KB, a 71% reduction in size. Power-on startup delay 87ns (3 clock cycles, 32MHz main frequency) 1.8ms, startup speed improved by more than 20,000 times. Runtime RAM usage 184 bytes 1.2KB, RAM usage reduced by 85% Single-cycle execution power consumption 0.8μA / MHz 3.2μA / MHz, power consumption reduced by 75% Code density 3.2 times that of traditional coding 1 times the benchmark value Example
[0017] This embodiment provides an execution method for an extremely resource-constrained embedded system, applied to the embedded control device described in Embodiment 1, including - The following steps: S1 Multi-offset instruction encoding steps: Predefine 3 groups of instruction decoding windows with fixed address offsets, and encode the function code into multi-offset compatible... Instruction sequences enable binary data within the same contiguous linear address space to be decoded into two independent, executable instruction sequences. It can also be used as a computational constant and a hardware configuration parameter; S2 In-situ Rapid Startup Steps: The processor reset interrupt vector is directly mapped to the pipeline execution entry point. Upon power-up, there is no bootloader and no stored... Storage segment initialization, no stack pointer preset, execution starts within 3 clock cycles; S3 Fixed-Timing Pipeline Execution Steps: Following a preset four-level fixed timing sequence, peripheral hijacking, computation execution, data transmission, and... The entire execution cycle of hibernation and reset involves no task scheduling or concurrent switching. S4 memory management steps: Unify on-chip Flash and on-chip RAM with linear addressing, eliminating the addressing of code segments, data segments, stack areas, and heap areas. The boundary is the address space that is dynamically overwritten and reused by subsequent data after the instruction execution is completed; S5 fault tolerance steps: When a single node fails, a hardware reset is directly triggered to restart the execution cycle, through multi-node redundant sampling and result consensus. Achieve system-level high availability.
[0018] The method described in this embodiment can be widely applied to passive RFID sensors, implantable medical chips, industrial emergency trigger sensors, and distributed micro- Extremely resource-constrained scenarios such as large-scale IoT nodes.
[0019] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Any modifications or alterations made within the spirit and principles of the present invention are prohibited. Any modifications, equivalent substitutions, or improvements should be included within the scope of protection of this invention.
Claims
1. An embedded control device with extremely limited resources, characterized in that, Including processor, storage media, multi-offset instruction decoding - Unit, fixed-timing pipelined execution controller; The input terminal of the multi-offset instruction decoding unit is electrically connected to the address output terminal of the storage medium, and the decoding output terminal is electrically connected to the processor's instruction... The input pin, the multi-offset instruction decoding unit, is pre-configured with at least 3 sets of instruction decoding windows with fixed address offsets, the instruction- Let the decoding window be used to decode binary data in the same continuous linear address space in the storage medium, according to different starting address offsets. Decode and output at least two independent, valid instruction sequences that can be executed by the processor; The timing trigger terminal of the fixed-timing pipelined execution controller is electrically connected to the processor's execution control pin, and the instruction input terminal is electrically connected to - The output of the multi-offset instruction decoding unit, the fixed-timing pipeline execution controller has four levels of fixed-timing hardware execution preset. The pipeline, wherein the pipeline execution controller is used to trigger the execution of each stage of the pipeline sequentially according to a preset fixed timing sequence after power-on, without a task. Scheduling logic, non-concurrent switching logic, and non-synchronous mutual exclusion arbitration logic.
2. The embedded control device according to claim 1, characterized in that, The multi-offset instruction decoding unit has three sets of instruction decoding windows. The interface includes: a 0-byte address offset decoding window, a +1-byte address offset decoding window, and a +2-byte address offset decoding window, adapted for 16-bit systems. Compressed instruction set architecture; binary data within the same contiguous linear address space simultaneously serves as executable instructions and arithmetic constants for the processor. It uses quantities and hardware register configuration parameters to achieve address space reuse for instructions, data, and configuration parameters.
3. The embedded control device according to claim 1, characterized in that, The fourth level of the fixed-timing pipelined execution controller - The hardware execution pipeline is electrically connected sequentially according to the trigger order: Peripheral hijacking level circuit: Triggered in the first timing sequence after power-on, it completes minimal hardware initialization through register hard-coding, and exclusively acquires the target. Hardware access permissions for peripherals; power off the clock for non-target peripherals. The execution stage circuitry is triggered by a second timing sequence, controlling the processor to complete preset sensor sampling, data processing, and signal processing logic. Edit; Data transmission stage circuit: Triggered by the third timing sequence, it controls the peripheral interface to complete the wired / wireless transmission of the calculation results; Hibernation reset stage circuit: Fourth timing trigger, controls the processor to enter deep hibernation mode, or triggers the hardware reset circuit to restart the process. Water line.
4. The embedded control device according to claim 1, characterized in that, It also includes a unified addressing storage management unit, the unified addressing storage management unit... The address configuration terminal of the address storage management unit is electrically connected to the address bus of the storage medium, and the read / write control terminal is electrically connected to the address control terminal of the processor. Pins are used to unify the linear addressing of on-chip Flash and on-chip RAM, eliminating the need for separate addressing of code segments, data segments, stack areas, and heap areas. Boundary partitioning allows the address space after instruction execution to be dynamically overwritten and reused by subsequent data.
5. The embedded control device according to claim 1, characterized in that, It also includes an in-situ startup hardware configuration unit. The reset input terminal of the in-situ startup hardware configuration unit is electrically connected to the reset vector pin of the processor, and the execution output terminal is electrically connected to the entry address terminal of the fixed-timing pipeline execution controller. It is used to directly map the processor's reset interrupt vector to the entry address of the pipeline execution controller. After power-on, there is no boot program, no memory segment initialization, and no stack pointer preset, and pipeline execution is directly triggered.
6. The embedded control device according to claim 1, characterized in that, It also includes a register direct-connect hardware adapter unit. The control input terminal of the register direct-connect hardware adapter unit is electrically connected to the general-purpose I / O pin of the processor, and the configuration output terminal is electrically connected to the register configuration pin of the peripheral device. It has a pre-set register address mapping table corresponding to different processor architectures. It matches the register operation instructions of the corresponding architecture through different instruction decoding windows, without a hardware abstraction layer or driver indirect call.
7. The embedded control device according to claim 1, characterized in that, It also includes a distributed redundancy fault-tolerant unit, whose reset output terminal is electrically connected to the processor's hardware reset pin, and whose node communication terminal is electrically connected to the external node communication interface. This unit is used to directly trigger the hardware reset circuit to restart the pipeline when a single node executes an exception. System-level high availability is achieved through multi-node redundant sampling and result consensus.
8. The embedded control device according to claim 1, characterized in that, The processor is a 32-bit RISC-V RV32EC architecture. The embedded microcontroller uses a 16-bit compressed instruction set, which is a RISC-VC extended instruction set.
9. The embedded control device according to claim 1, characterized in that, The complete execution image stored in the storage medium - The product size is ≤2KB, and the startup delay from processor power-on to business code execution is ≤100ns.
10. A method for executing data in an extremely resource-constrained embedded system, characterized in that, Applicable to the embedded system described in any one of claims 1-9 An in-line control device includes the following steps: S1 Multi-offset instruction encoding steps: Predefine at least 3 sets of instruction decoding windows with fixed address offsets, and encode the function code into multi-offset instructions. A transfer-compatible instruction sequence enables binary data within the same contiguous linear address space to be decoded into at least two independent, reproducible sets of instructions. The sequence of instructions executed; S2 Fixed-Timing Pipeline Execution Steps: After power-on, according to the preset four-level fixed timing sequence, peripheral hijacking, computation execution, and... The entire execution cycle of data transmission, hibernation, and reset is completed without task scheduling, concurrent switching, or synchronous mutual exclusion arbitration.
11. The execution method according to claim 10, characterized in that, In step S1, the three sets of instruction decoding windows are respectively located at address 0 offset - Decoding windows with offsets of +1 byte and +2 bytes, adapted to 16-bit compressed instruction sets; same- Binary data in a continuous linear address space, used simultaneously as executable instructions, operational constants, and hardware register configuration parameters.
12. The execution method according to claim 10, characterized in that, The four-level fixed timing in step S2 specifically includes: S21 Peripheral Hijacking Level: Triggered in the first timing sequence after power-on, it completes minimal hardware initialization through register hard-coding, and exclusively acquires the target. Peripheral access permissions, disable the clock of non-target peripherals; S22 Operation Execution Level: Second timing trigger, executes sensor sampling, data processing, and signal processing logic; S23 Data Transmission Level: Triggered by the third timing sequence, the calculation result is transmitted through the peripheral interface; S24 Hibernation Reset Stage: Triggered by the fourth timing sequence, entering deep hibernation mode, or triggering a hardware reset to restart the execution cycle.
13. The execution method according to claim 10, characterized in that, In step S2, the processor reset interrupt vector is directly mapped to - The pipelined execution entry point has no bootloader, no memory segment initialization, and no stack pointer preset after power-on; execution begins within 3 clock cycles. Business logic code.
14. The execution method according to claim 10, characterized in that, In step S1, different instruction decoding windows are used for matching. It can be configured with different processor register addresses without requiring hardware abstraction layer adaptation.
15. The execution method according to claim 10, characterized in that, It also includes memory management steps: unifying on-chip Flash and on-chip RAM. Linear addressing eliminates the address boundaries of code segments, data segments, stack areas, and heap areas. The address space after instruction execution is completed is then used by subsequent instructions. Dynamic data overlay and reuse.
16. The execution method according to claim 10, characterized in that, It also includes fault tolerance steps: when a single node executes an exception, it directly triggers - The hardware reset restart execution cycle is triggered, and system-level high availability is achieved through multi-node redundant sampling and result consensus.
17. The execution method according to claim 10, characterized in that, The method is adapted to RISC-V RV32EC architecture embedded micro- The controller has a full execution image size of ≤2KB and a power-on startup delay of ≤100ns.
18. The execution method according to claim 10, characterized in that, The method is applied to passive RFID sensors and implantable medical devices. Applications include therapeutic chips, industrial emergency trigger sensors, and distributed micro IoT nodes.