A PNT-based remote unified intelligent centralized control system platform

Abstract

The application relates to the technical fields of intelligent control and industrial internet, in particular to a remote unified intelligent centralized control system platform based on PNT, which comprises: a global perception module: collecting time synchronization signals and bottom layer operation telemetry data of a controlled area; a space-time reference construction module: constructing a global network unified space-time reference plane and generating space-time holographic data; a heterogeneous computing power normalization module: shielding bottom layer driving differences and mapping processing capacity into standardized time slice computing power indexes; a time trigger scheduling module: calculating delay according to the computing power indexes and generating time trigger control instructions with future trigger time; and a digital twin verification module: constructing dynamic space-time trajectories and real-time comparing with expected states to generate evaluation results; the application solves the time sequence confusion problem when heterogeneous hardware cooperates and ensures delivery consistency in large-scale concurrent scenarios.

Description

Technical Field

[0001] This invention relates to the field of intelligent control and industrial internet technology, specifically to a remote unified intelligent centralized control system platform based on PNT. Background Technology

[0002] In the application scenario of remote unified intelligent centralized control system, the control center relies on network communication links to issue instructions and monitor the status of all controlled devices. The system usually needs to combine real-time feedback data from the underlying devices to ensure the accurate execution of business logic. For device control in large-scale concurrent scenarios, existing solutions generally adopt a best-effort event-triggered mechanism, in which the cloud directly issues control commands, and the underlying devices respond and execute actions immediately upon receiving the commands, using transmission control protocols to ensure the reachability of the commands. Although this solution is feasible under the condition of homogeneous devices and a stable network environment, it ignores the heterogeneity of the underlying hardware in the context of full localization and substitution. The command response cycle of different architecture chips and the scheduling latency of the operating system are significantly different. When encountering large-scale concurrent control of one person in thousands of rooms, the traditional event-triggered mechanism is prone to inconsistent action of various devices due to jitter and clock drift, causing timing chaos and logic collapse in the macro scenario. Furthermore, existing telemetry data acquisition lacks a unified high-precision spatiotemporal reference. The acquired data only contains physical state values ​​and lacks nanosecond-level absolute timestamps and spatial coordinates, making it difficult for digital twin systems to construct traceable dynamic trajectories based on spatiotemporal holographic data. Moreover, it cannot effectively eliminate transmission delay interference caused by network queuing effects, leading to false alarms or missed alarms in system status assessment. Therefore, how to establish a control mechanism with deterministic latency guarantees, while shielding the differences in underlying heterogeneous computing power, and improving the consistency of network-wide control and the accuracy of operation and maintenance, has become an urgent technical problem to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a remote unified intelligent centralized control system platform based on PNT to solve the problems mentioned in the background art. Specifically, the technical solution of this invention includes: The cloud-based control center has communication connections to a global perception module, a spatiotemporal benchmark construction module, a heterogeneous computing power normalization module, a time-triggered scheduling module, and a digital twin verification module. The global sensing module is used to collect time synchronization signals, spatial location data, and telemetry data of the underlying equipment in the controlled area; The spatiotemporal reference construction module is used to construct a unified spatiotemporal reference plane for the entire network based on time synchronization signals, and to add absolute timestamps and spatial labels to the telemetry data to generate spatiotemporal holographic data. The heterogeneous computing power normalization module is used to shield the driver differences of the underlying devices, calibrate the clock drift of the operating system based on the system clock frequency, and uniformly convert the processing power of heterogeneous chips into the standard task throughput per unit time, thereby mapping it into a standardized time slice computing power index. The time-triggered scheduling module is used to calculate the instruction execution delay based on the time slice computing power index. The instruction execution delay includes the maximum processing time of the target device group identified by the time slice computing power index and the network transmission delay, and generates a time-triggered control instruction with a future trigger time. The digital twin verification module is used to construct a dynamic spatiotemporal trajectory based on spatiotemporal holographic data. It uses a linear interpolation algorithm to reconstruct the actual time of device action from discrete spatiotemporal holographic data and compares the dynamic spatiotemporal trajectory with the expected state of the time-triggered control command in real time to generate system state evaluation results.

[0004] Preferably, the process by which the global sensing module collects time synchronization signals, spatial location data, and telemetry data of the underlying equipment within the controlled area includes: Obtain nanosecond-level time synchronization signals through BeiDou / GPS satellite time sources or network high-precision time protocols; The physical coordinates of the underlying devices are obtained as spatial location data through geographic information systems or indoor positioning tags; Real-time reading of the voltage, current, and I / O port status of the underlying devices is used as operational telemetry data.

[0005] Preferably, the process by which the spatiotemporal reference construction module generates spatiotemporal holographic data includes: By using a field-programmable gate array (FPGA) to analyze the time synchronization signal, a globally unified system clock is established. At the moment when the underlying device collects operational telemetry data, the operational telemetry data is latched using the system clock and associated with the physical coordinates of the device; The combined data, including absolute timestamps, spatial labels, and state values, is encapsulated into spatiotemporal holographic data.

[0006] Preferably, the heterogeneous computing power normalization module calibrates the operating system's clock drift based on the system clock frequency to reflect the processing power of heterogeneous chips, and uniformly converts it into standard task throughput per unit time, thereby mapping it into a standardized time-slice computing power indicator. The process includes: Obtain the task scheduling mechanism and instruction response cycle of different processor architectures in the underlying device; The clock drift of different operating systems is calibrated based on the system clock frequency, and the computing performance of processors with different architectures is uniformly converted into standard task throughput per unit time. Calculate the inherent time required for each underlying device to process standard control commands based on the standard task throughput, and mark this inherent time as a time-slice computing power metric.

[0007] Preferably, the process by which the time-triggered scheduling module generates a time-triggered control instruction with a future trigger time includes: Parse business logic requests to determine the target underlying device group; Retrieve the time-slice computing power metrics of all devices in the target underlying device group and identify the maximum processing time among them; Get the maximum network transmission delay of control commands during network transmission; Set a reserved synchronization buffer time; The current absolute time, maximum processing time, maximum network transmission latency, and synchronization buffer time are added together to obtain the future trigger time; The future trigger time is embedded into the business instruction frame to generate a time-triggered control instruction, so that the target underlying device group can synchronously execute actions when the future trigger time is reached.

[0008] Preferably, the process by which the digital twin verification module generates system status assessment results includes: Create digital twins in the database that correspond one-to-one with the underlying physical devices; Update the expected state trajectory of the digital twin based on time-triggered control commands; Receive spatiotemporal holographic data fed back from the underlying devices and extract the actual state trajectory; Calculate the state deviation and time deviation between the expected state trajectory and the actual state trajectory at the same absolute time point.

[0009] Preferably, the process by which the digital twin verification module generates system state assessment results based on state deviation values ​​and time deviation values ​​is configured as follows: Preset state consistency threshold and time jitter threshold; Execute the hierarchical judgment logic: first judge the state deviation value; if the state deviation value is greater than or equal to the state consistency threshold, then directly generate an alarm signal for physical equipment failure. If the state deviation value is less than the state consistency threshold, the time deviation value is further determined: if the time deviation value is greater than or equal to the time jitter threshold, an early warning signal of network congestion or insufficient computing power is generated; if the time deviation value is less than the time jitter threshold, a result indicating that the system is operating normally is generated.

[0010] Preferably, this system also includes a security authentication module, which is used for: Obtain the spatial location data of the terminal device that initiated the access request; Compare the spatial location data with the preset legal geofence range; In response to the spatial location data being within a legal geofence, terminal devices are allowed to access and distribute time synchronization signals; In response to the fact that the spatial location data is not within the legal geofence area, the access request is rejected and the issuance of control commands is blocked.

[0011] Compared with the prior art, the present invention has the following improvements and advantages: 1. This invention effectively solves the timing disorder problem in large-scale concurrent scenarios by introducing a time-triggered scheduling mechanism and heterogeneous computing power normalization technology. Unlike the traditional best-effort event-triggered mechanism, this solution maps the nonlinear processing capabilities of heterogeneous chips to standardized time-slice computing power indicators and calculates the determined future trigger time by combining network transmission latency. This ensures that under conditions of huge differences in underlying hardware and complex network environment, all controlled devices can strictly execute actions synchronously at the predetermined time, thus ensuring the consistency of macro-level scenario delivery. 2. This invention constructs a spatiotemporal holographic data acquisition system based on FPGA hardware latch, eliminating the uncertainty delay caused by operating system scheduling; by directly parsing the time synchronization signal using parallel logic circuits at the edge, and adding nanosecond-level absolute timestamps and spatial tags to the telemetry data at the instant of physical signal sampling, this method provides a true data source containing accurate physical coordinates and absolute time for digital twin systems, effectively solving the problem of stateful but spatiotemporal data silos in traditional control systems; 3. This invention establishes a network delay compensation model based on end-to-end statistical characteristics, realizing deterministic transmission of control commands in complex network environments. The system no longer relies on a single static estimation, but comprehensively considers the average round-trip time of the link, jitter standard deviation, network hop count, and serialization delay caused by bottleneck bandwidth. By reserving synchronization buffer time and pre-calculating command arrival time, the influence of network queuing effect and one-way jitter on synchronization accuracy is eliminated, ensuring reliable issuance and timely response of control commands. 4. This invention adopts a hierarchical fault determination and dynamic trajectory verification logic based on digital twins, which significantly improves the system's operation and maintenance efficiency and fault diagnosis accuracy. By introducing an interpolation algorithm to reconstruct the actual action time and establishing a dual verification mechanism of steady-state evaluation and dynamic timing deviation, the system can automatically distinguish different types of anomalies such as physical equipment faults, network congestion, or insufficient computing power, avoiding missed detections or false alarms caused by overlapping transient data, and realizing refined intelligent management of large-scale controlled equipment. Attached Figure Description

[0012] The present invention will be further explained below with reference to the accompanying drawings and embodiments: Figure 1 This is a structural diagram of the system of the present invention; Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0014] Example 1:

[0015] Please see Figure 1 A remote unified intelligent centralized control system platform based on PNT includes a cloud-based control center. The cloud-based control center is communicatively connected to a global perception module, a spatiotemporal reference construction module, a heterogeneous computing power normalization module, a time-triggered scheduling module, and a digital twin verification module. The global perception module is used to collect time synchronization signals, spatial location data, and telemetry data of the underlying equipment in the controlled area. The spatiotemporal reference construction module is used to construct a unified spatiotemporal reference plane for the entire network based on the time synchronization signals, and to add absolute timestamps and spatial tags to the telemetry data to generate spatiotemporal holographic data. The heterogeneous computing power normalization module is used to shield the driver differences of underlying devices, calibrate the clock drift of the operating system based on the system clock frequency of the heterogeneous chip processing power, and uniformly convert it into the standard task throughput per unit time, thereby mapping it into a standardized time-slice computing power index. The time-triggered scheduling module is used to calculate the instruction execution latency based on the time-slice computing power index. This instruction execution latency includes the maximum processing time of the target device group identified by the time-slice computing power index and the network transmission latency, and generates a time-triggered control instruction with a future trigger time. The digital twin verification module is used to construct a dynamic spatiotemporal trajectory based on spatiotemporal holographic data, reconstruct the actual occurrence time of device actions from discrete spatiotemporal holographic data using a linear interpolation algorithm, and compare the dynamic spatiotemporal trajectory with the expected state of the time-triggered control instruction in real time to generate a system state evaluation result.

[0016] This embodiment provides a remote unified intelligent centralized control system platform based on PNT (Positioning, Navigation, and Timing). It aims to address the timing chaos and logic collapse issues in large-scale concurrent control scenarios caused by differences in the processing capabilities of heterogeneous underlying chips and different operating system scheduling mechanisms under the background of comprehensive domestic substitution. The core system architecture uses a cloud-based control center as its hub, connecting five core functional modules through a high-bandwidth, low-latency communication network. Furthermore, to ensure the determinism of control command transmission, the cloud-based control center is also equipped with a network monitoring module for real-time monitoring of transmission latency and congestion across the entire network. The global perception module, acting as the system's sensory organ, is responsible for collecting time synchronization signals, spatial location data, and telemetry data from underlying devices within the controlled area. This data acquisition process constitutes the system's raw information input. The spatiotemporal reference construction module, acting as the system's metronome, constructs a unified spatiotemporal reference plane across the entire network based on the collected time synchronization signals. Through hardware-level latching technology, it adds nanosecond-level absolute timestamps and spatial tags to all operational telemetry data, generating spatiotemporal holographic data. This data includes the three-dimensional coordinates, absolute time, and physical state values ​​of physical entities, aiming to provide a traceable and accurate data source for digital twins. Based on this, the heterogeneous computing power normalization module acts as a translator, shielding the differences in the drivers of the underlying devices and mapping the nonlinear processing capabilities of different domestic chips to a unified time-slice computing power index, so that the upper-layer scheduling logic does not need to care about the specific model of the underlying hardware; the time-triggered scheduling module acts as the brain, integrating the network latency data provided by the network monitoring module and the time-slice computing power index to calculate the instruction execution latency. This instruction execution latency includes the maximum processing time of the target device group identified by the time-slice computing power index and the network transmission latency, and generates a time-triggered control instruction with a future trigger time. This instruction requires the device to perform an action at a specific absolute time in the future. The digital twin verification module acts as a quality inspector, constructing a dynamic spatiotemporal trajectory based on spatiotemporal holographic data. It then uses a linear interpolation algorithm to reconstruct the actual timing of device actions from discrete spatiotemporal holographic data and compares the dynamic spatiotemporal trajectory with the expected state of time-triggered control commands in real time to generate a system status assessment result. This embodiment introduces PNT technology to construct a unified spatiotemporal benchmark, transforming the traditional best-effort event-triggered control mechanism into a deterministic time-triggered control mechanism. This mechanism effectively solves the problem of macroscopic scene collapse caused by clock drift and processing jitter when heterogeneous domestic hardware works collaboratively, ensuring consistency in scene delivery and accuracy in operation and maintenance in large-scale concurrent scenarios with one person in thousands of rooms.

[0017] Example 2:

[0018] The process by which the global perception module collects time synchronization signals, spatial location data, and telemetry data of the underlying devices in the controlled area includes: obtaining nanosecond-level time synchronization signals through BeiDou / GPS satellite time sources or network high-precision time protocols; obtaining the physical coordinates of the underlying devices as spatial location data through geographic information systems or indoor positioning tags; and reading the voltage, current, and I / O port status of the underlying devices in real time as operational telemetry data.

[0019] This embodiment further illustrates the specific process of the global perception module collecting data, aiming to establish a high-precision multi-dimensional perception system; the system executes the time synchronization signal acquisition step, which obtains UTC time through the integrated Beidou / GPS dual-mode satellite time receiver, or obtains nanosecond-level time synchronization signal from the network master clock through the IEEE1588PTP precise time protocol. This step aims to ensure that the time reference error of all nodes in the system is controlled within the microsecond level. The system performs the spatial location data acquisition steps. For fixed equipment, its latitude, longitude and altitude information are pre-set through the Geographic Information System (GIS). For mobile equipment or dense indoor equipment, the system reads the UWB ultra-wideband or RFID indoor positioning tags deployed on the equipment to obtain the relative coordinates of the underlying equipment relative to the known anchor point, and combines the latitude and longitude of the anchor point to convert them into absolute geographic coordinates as spatial location data. The system executes the telemetry data acquisition steps, using the ADC analog-to-digital converter and GPIO interface of the underlying hardware to read the voltage, current, and I / O port status of the underlying devices in real time, such as relay on / off status and PWM duty cycle, as operational telemetry data. This embodiment integrates satellite timing, indoor positioning, and underlying electrical telemetry to comprehensively perceive the physical state and spatiotemporal attributes of the devices, providing highly reliable raw data support for the subsequent construction of spatiotemporal holographic data, effectively solving the problem of data silos that exist in traditional control systems but lack spatiotemporal context.

[0020] Example 3:

[0021] The process of generating spatiotemporal holographic data by the spatiotemporal reference construction module includes: using a field-programmable gate array (FPGA) to analyze the time synchronization signal and establish a globally unified system clock; at the moment when the underlying device collects and operates telemetry data, using the system clock to latch the operating telemetry data and associate it with the physical coordinates of the device; and encapsulating the combined data containing absolute timestamps, spatial tags, and state values ​​into spatiotemporal holographic data.

[0022] This embodiment describes in detail the hardware implementation process of the spatiotemporal reference construction module to generate spatiotemporal holographic data, aiming to eliminate the uncertainty and delay caused by the operating system scheduling; the system utilizes the parallel processing capability of the field programmable gate array (FPGA) to directly parse the PPS second pulse and NMEA message output by the Beidou / GPS receiver, or parse the PTP protocol packet, and establish a globally unified system clock in the internal logic circuit of the FPGA, which is strictly synchronized with Coordinated Universal Time (UTC); At the moment when the underlying device acquires telemetry data, such as at the interrupt moment when the ADC sampling ends, the FPGA immediately latches the telemetry data using the aforementioned system clock and simultaneously reads the physical coordinates of the device from the register. The FPGA packages the combined data, which includes absolute timestamps with nanosecond precision, spatial tags (i.e., coordinate data), and status values ​​(i.e., telemetry data), into a spatiotemporal holographic data frame, and transmits it to the local gateway controller via the onboard high-speed bus. The gateway controller then uploads the data to the cloud via the Ethernet interface using the TCP / IP protocol. This embodiment utilizes the hardware parallelism of FPGA for edge-side marking, eliminating the impact of interrupt response delays and task scheduling jitter on timestamp accuracy caused by operating system interrupts such as Linux or RTOS. This ensures that every uploaded data item carries real physical time information, laying a solid truth foundation for subsequent accurate backtracking and digital twin verification.

[0023] Example 4:

[0024] The heterogeneous computing power normalization module calibrates the clock drift of the operating system based on the system clock frequency to normalize the processing power of heterogeneous chips, and uniformly converts it into standard task throughput per unit time, thereby mapping it into a standardized time-slice computing power indicator. The process includes: obtaining the task scheduling mechanism and instruction response cycle of different architecture processors in the underlying devices; calibrating the clock drift of different operating systems based on the system clock frequency, uniformly converting the computing performance of different architecture processors into standard task throughput per unit time; calculating the inherent time required for each underlying device to process standard control instructions based on the standard task throughput, and marking this inherent time as a time-slice computing power indicator.

[0025] This embodiment details the process by which the heterogeneous computing power normalization module standardizes the capabilities of heterogeneous chips, a crucial step in addressing the inconsistent performance of domestically produced chips. The system pre-configures or dynamically acquires task scheduling mechanisms and instruction response cycles for different processor architectures in the underlying devices, such as MIPS or ARM architectures. To quantify the actual computing power of different processors, the system calibrates the clock drift of different operating systems based on the system clock frequency, uniformly converting the computing performance of different processor architectures into standard task throughput per unit time. Regarding clock drift rate Regarding the symbol definition logic, this embodiment modifies the parameter relationships to conform to physical facts, and the calculation formula is as follows: ; in, The processor's system clock frequency, derived from the chip's hardware manual, physically represents the number of clock pulses generated per second by the chip, measured in Hertz (Hz). or ; Clock drift rate, derived from the deviation ratio between the local clock and the standard clock monitored by the spatiotemporal reference construction module, is a dimensionless value; this embodiment explicitly specifies... The sign rule: When the frequency of the underlying crystal oscillator drifts faster due to environmental influences, Take a positive value; otherwise, take a negative value; this correction ensures that when the crystal oscillator speeds up, the (1+) in the formula remains constant. Increasing the term will increase the calculated throughput. As a result, it increases; Architecture efficiency coefficient, derived from benchmark data for this processor architecture, physically represents the number of instructions executed per clock cycle, measured in instructions per cycle (IPC). : Architecture-related standard task conversion factor. This value is retrieved from the system's default architecture-instruction density lookup table. Its physical meaning is the average number of machine instructions required to execute a standard control task under the current processor architecture. The unit is instruction count / task. In this embodiment, the standard control task is uniformly defined as: a complete logical loop that performs a read-invert-write operation on a Boolean variable; different architectures have different levels of instruction set simplification. The values ​​differ significantly; for example, RISC architectures typically have higher values ​​than CISC architectures. This can be achieved by introducing architecture-sensitive... Value, formula used The computational logic is as follows: ; The period in the numerator and denominator cancels out the dimension of the instruction, accurately converting it into... The unit is standard tasks per second, thus clarifying the physical dimension of throughput; Based on this, the system calculates the inherent time required for each underlying device to process standard control commands according to the standard task throughput, and marks it as a time-slice computing power index. The calculation is as follows: ; in, The task equivalent of the target instruction, in this embodiment will be... Defined as the ratio of the computational complexity of the current target control instruction to be processed relative to the standard control task, it is a dimensionless coefficient; its numerical calculation logic is as follows: ; in, The average number of clock cycles required for a target control instruction to execute once under the current processor architecture; Example 4: The number of reference clock cycles required to execute a standard control task once under the current processor architecture, as defined above; and All values ​​were obtained by running the offline instruction set simulator multiple times under standard operating conditions and taking the average value, ensuring the consistency of the benchmark for equivalent conversion; The fixed overhead of operating system context switching and interrupt response is derived from actual system measurements and is expressed in seconds. Time-slice computing power metrics, where the subscript... The term "processing" refers to the inherent processing time of a device for an instruction. This embodiment corrects the physical meaning of the parameter definition through the above normalization process, ensuring the closed loop of dimensional logic; it abstracts the physically different heterogeneous chips into a unified time-slice computing power model; the scheduling module does not need to know whether the underlying layer is a high-performance CPU or a low-cost MCU, it only needs to know how much time it needs to consume to process the task, thereby achieving decoupling between the control logic and the underlying hardware, and greatly reducing the software adaptation cost in the localization substitution.

[0026] Example 5:

[0027] The process by which the time-triggered scheduling module generates time-triggered control commands with future trigger times includes: parsing business logic requests to determine the target underlying device group; retrieving the time-slice computing power metrics of all devices in the target underlying device group to identify the maximum processing time; obtaining the maximum network transmission delay during the network transmission of the control command; setting a reserved synchronization buffer time; accumulating the current absolute time, maximum processing time, maximum network transmission delay, and synchronization buffer time to obtain the future trigger time; embedding the future trigger time into the business command frame to generate time-triggered control commands, so that the target underlying device group synchronously executes actions when the future trigger time is reached.

[0028] This embodiment details the process by which the time-triggered scheduling module generates control instructions with future trigger times, which is the core of achieving deterministic control. The system parses business logic requests, such as activating all multimedia devices in the first teaching building, and determines the target underlying device group. The system retrieves the time-slice computing power indicators of all devices in the target group and identifies the maximum processing time among them. This means that the speed of the entire group's movements depends on the weakest link device; At the same time, obtain the maximum network transmission delay of the control command during network transmission. To eliminate the uncertainty introduced by estimation and to address the fundamental errors in the original formula, this embodiment ignores the serialization latency of non-bottleneck links and underestimates unidirectional jitter, and adopts a calculation formula modified based on end-to-end statistical characteristics and store-and-forward mechanisms: ; in, The network monitoring module utilizes a size of The average round-trip latency of the link within the most recent 100ms, measured by the standard probe packet, in seconds (s); : Standard deviation of latency jitter, in seconds (s); Given the high asymmetry of latency jitter in network congestion scenarios, this embodiment no longer considers... Instead of halving the jitter value, it is directly included in the one-way delay estimation in its entirety; H: Network hop count, which is the number of router / switch nodes traversed on the transmission path from the cloud to the edge device. It is obtained by reverse calculation from the TTL value. The actual size of the business instruction frame, in bytes; : Size of the probe packet, in bytes; End-to-end bottleneck bandwidth: This value is obtained by the network monitoring module through periodic Iperf bandwidth tests, such as once per second or triggered when the bus is idle, and stored in a real-time cache. During calculation, the most recent test value from the cache is retrieved, and the unit is bits per second; in the formula... The operation explicitly converts the byte difference to bits to match the denominator. The dimensions are kept consistent, thus correctly calculating the serialization delay increment; ensuring that control commands arrive reliably earlier than the trigger time; To ensure that all devices operate synchronously, the system incorporates future trigger times. Computational model: ; in, The current absolute time when the instruction was generated is derived from the high-precision UTC system clock calibrated by BeiDou / GPS at the cloud control center, and the unit is timestamp; : The maximum processing time within the group, where the subscript m represents the maximum value Max, determined by the preceding steps, and the unit is seconds; Maximum network transmission delay, calculated using the aforementioned corrected formula, is expressed in seconds. : Reserved synchronization buffer time, where the subscript b represents the buffer, used to accommodate unpredictable small jitters, and is usually taken as the standard deviation of network latency jitter measured in the previous steps. Two to three times that in seconds; The system embeds the calculated future trigger time into the business instruction frame to generate a time-triggered control instruction. After receiving the instruction, the underlying device will not act immediately, but will put the instruction into a waiting queue until the local clock reaches the future trigger time before synchronously executing the action. This embodiment eliminates the asynchronous actions caused by network queuing effects and performance differences of heterogeneous chips by pre-calculating and compensating for all possible delays and using future moments as trigger conditions. Regardless of the device's performance, as long as the instruction is received before the trigger moment, it can act on time at the specified moment, achieving millisecond-level scene synchronization control.

[0029] Example 6:

[0030] The process of generating system status assessment results by the digital twin verification module includes: establishing a digital twin in the database that corresponds one-to-one with the physical underlying device; updating the expected state trajectory of the digital twin according to time-triggered control commands; receiving spatiotemporal holographic data fed back from the underlying device and extracting the actual state trajectory; and calculating the state deviation value and time deviation value between the expected state trajectory and the actual state trajectory at the same absolute time point.

[0031] This embodiment describes the process by which the digital twin verification module generates evaluation results; the system establishes a digital twin in the database that corresponds one-to-one with the underlying physical device; and updates the expected state trajectory of the digital twin according to the issued time-triggered control command. To achieve reproducible trajectory calculations, the system establishes a discretized functional expression based on the physical characteristics of the controlled object, derived from solving differential equations. ; in, This refers to the state at the previous moment. The target value of the instruction. The trigger time set for the command. The step response time constant of the physical device, pre-stored in the digital twin database, reflects the voltage / current settling speed; this function precisely describes the physical state the device should be in at time t; the system receives spatiotemporal holographic data fed back from the underlying device and extracts the actual state trajectory. ; The system performs deviation calculations based on the same absolute time point; addressing the challenges of variable acquisition and logical loop issues mentioned in the specification, this embodiment employs the following improved algorithm: reconstructing the actual action time. To address the issue that precise change times cannot be directly obtained from spatiotemporal holographic data due to its discrete time series nature, the system employs a linear interpolation algorithm. Define action thresholds Definition logic: To ensure the physical meaning of the interpolation points and eliminate background noise interference, this embodiment will... Set as a fixed percentage point for the change from the initial state to the target state, that is: ; in, This is the sensitivity coefficient for motion detection; in this embodiment... Set to 0.15; this value is determined based on the statistical distribution of the signal-to-noise ratio of a large number of sensors, aiming to make the action threshold... It is at least three times higher than the peak value of the background noise, which can both avoid background noise and capture the start of motion in time; this assignment logic ensures the threshold. It dynamically adapts to range changes in control commands and is significantly higher than the sensor's noise floor level; upon detection... When the value falls within the specified interval, interpolation is performed; the state value in the actual state trajectory is retrieved if it crosses the action threshold. two adjacent sampling points These two sampling points were directly extracted from the spatiotemporal holographic data sequence uploaded by the global perception module and tagged in the spatiotemporal reference construction module. All are absolute timestamps at the nanosecond level; expressed by the formula: ; Calculate the actual occurrence time with nanosecond precision. This solves the problem of variable unavailability. Set steady-state evaluation time To solve the problem at the moment of triggering Because the expected state and the initial state are mathematically coincident ( This system no longer uses a single comparison method to address the logical flaw that prevents the detection of equipment malfunctions. Instead of calculating a single moment, the steady-state evaluation moment is calculated for each underlying device individually. ;in The measured step response time constant for this specific device model is derived from the digital twin database; Time, Expected State It is close to the target value. If the equipment is still in this state This will result in significant state deviations; Based on the above definition, the state deviation value is calculated. and time deviation value : ; in, : The expected state value at the steady-state evaluation moment, at which point the expected value is significantly different from the initial value; The state value actually sampled at the steady-state evaluation moment; The actual time when the device's state changed, reconstructed using an interpolation algorithm; The trigger time set by the instruction; This embodiment eliminates the precision loss caused by discrete data and the logical blind spot of transient comparison by introducing interpolation algorithms and steady-state evaluation mechanisms, thus ensuring the closed-loop reliability of remote control.

[0032] Example 7: The digital twin verification module is configured to generate system status assessment results based on state deviation and time deviation values ​​as follows: Preset state consistency threshold and time jitter threshold; execute hierarchical judgment logic: prioritize state deviation value judgment; if the state deviation value is greater than or equal to the state consistency threshold, directly generate an alarm signal for physical equipment failure; if the state deviation value is less than the state consistency threshold, further judge the time deviation value: in response to a time deviation value greater than or equal to the time jitter threshold, generate a warning signal for network congestion or insufficient computing power; in response to a time deviation value less than the time jitter threshold, generate a result indicating normal system operation.

[0033] This embodiment further refines the evaluation logic of the digital twin verification module to distinguish between device failures and network or computing power issues; the system presets a state consistency threshold. and time jitter threshold To ensure the accuracy of the judgment results and address the issue of threshold setting relying on experience, this embodiment clarifies the logical relationship between these two thresholds and the parameters in the aforementioned embodiments: State Consistency Threshold The setting logic is as follows: ; in, The background noise peak value is measured by the bottom sensor through 1000 continuous samplings during non-working periods, and is measured and stored in the device file by the global perception module; For safety reasons, this embodiment is based on The statistical criterion is set to 2.0 to ensure a false alarm rate of less than 5%; this setting ensures that a physical fault is only identified when the state deviation significantly exceeds the measurement noise floor; time jitter threshold. The setting logic is as follows: ; in, The latest latency jitter standard deviation is directly calculated in real time by the network monitoring module in Example 5 and shared with the verification module. The system response time constant defined in Example 6 The allowable fluctuation tolerance is set as a fixed percentage calculation value in this embodiment, namely: ; This setting logic ensures that the threshold dynamically covers normal network fluctuations and inherent device response jitter, thereby accurately distinguishing between normal random fluctuations and network / computing power anomalies; The system executes hierarchical judgment logic: first, it judges the state deviation value, and responds to... This situation corresponds to the equipment malfunction mentioned in Example 6—that is, during the steady-state evaluation time. The expected state has reached the target value. However, the actual state remains unchanged. This causes the difference between the two values ​​to exceed a threshold; at this point, the system determines that the device is not responding at the physical level and directly generates an alarm signal for a physical fault in the device; if This indicates that the device has completed the action and the final state is correct, but the timeliness of the action needs further verification; at this point, the response is... This indicates that although the equipment activated, the activation time was not specified. Significantly lagging behind the instruction trigger time Furthermore, the lag exceeds the normal range of network jitter. This usually means that network congestion is causing late instructions, or that insufficient device computing power is causing processing timeouts, prompting the system to generate a warning signal for network congestion or insufficient computing power; in response to This indicates that the action was accurate and timely, and the system generated a result indicating that the system was operating normally. This embodiment combines steady-state deviation and dynamic timing deviation, and dynamically generates judgment thresholds based on network statistical characteristics. It perfectly repairs the missed detection problem caused by transient overlap and the false alarm problem caused by unclear threshold settings in traditional logic, and realizes automatic fault classification. Maintenance personnel can immediately know whether to go to the site to replace equipment, optimize the network or upgrade computing power, which greatly improves the maintenance efficiency of large-scale systems and realizes refined intelligent management.

[0034] Example 8:

[0035] The system also includes a security authentication module, which is used to: obtain the spatial location data of the terminal device that initiates the access request; compare the spatial location data with the preset legal geofence range; in response to the spatial location data being within the legal geofence range, allow the terminal device to access and distribute time synchronization signals; in response to the spatial location data not being within the legal geofence range, reject the access request and block the issuance of control commands.

[0036] This embodiment adds a security authentication module, leveraging the spatial attributes of PNT to enhance system security. When a terminal device, such as a tablet or debugging handheld device, initiates an access request, the system forces it to upload its spatial location data, including latitude and longitude or indoor positioning coordinates. The system compares this spatial location data with a preset legal geofence range. This geofence range is stored in GeoJSON format, described by a closed polygonal region consisting of no fewer than three latitude and longitude coordinate points, and supports dynamic updates via a cloud management interface. The system executes the following response logic: if the spatial location data is within the legal geofence range, the system considers it a legitimate terminal, allows access, and distributes a time synchronization signal, enabling it to join the PNT network. If the spatial location data is not within the legal geofence range, such as being located off-campus or in an unauthorized area, even if the password is correct, the system rejects the access request and blocks the issuance of control commands. This embodiment introduces spatial authentication based on physical location, adding a physical barrier to traditional identity authentication; this effectively prevents remote hacker attacks or malicious access by unauthorized devices in unauthorized areas, meeting the high security requirements of the information technology innovation environment; It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A remote unified intelligent centralized control system platform based on PNT, characterized in that, This includes a cloud-based control center, which is connected to a global perception module, a spatiotemporal benchmark construction module, a heterogeneous computing power normalization module, a time-triggered scheduling module, and a digital twin verification module. The global sensing module is used to collect time synchronization signals, spatial location data, and telemetry data of the underlying equipment in the controlled area; The spatiotemporal reference construction module is used to construct a unified spatiotemporal reference plane for the entire network based on time synchronization signals, and to add absolute timestamps and spatial labels to the telemetry data to generate spatiotemporal holographic data. The heterogeneous computing power normalization module is used to shield the driver differences of the underlying devices, calibrate the clock drift of the operating system based on the system clock frequency, and uniformly convert the processing power of heterogeneous chips into the standard task throughput per unit time, thereby mapping it into a standardized time slice computing power index. The time-triggered scheduling module is used to calculate the instruction execution delay based on the time slice computing power index. The instruction execution delay includes the maximum processing time of the target device group identified by the time slice computing power index and the network transmission delay, and generates a time-triggered control instruction with a future trigger time. The digital twin verification module is used to construct a dynamic spatiotemporal trajectory based on spatiotemporal holographic data. It uses a linear interpolation algorithm to reconstruct the actual time of device action from discrete spatiotemporal holographic data and compares the dynamic spatiotemporal trajectory with the expected state of the time-triggered control command in real time to generate system state evaluation results.

2. The remote unified intelligent centralized control system platform based on PNT according to claim 1, characterized in that, The process by which the global sensing module collects time synchronization signals, spatial location data, and telemetry data of the underlying equipment within the controlled area includes: Obtain nanosecond-level time synchronization signals through BeiDou / GPS satellite time sources or network high-precision time protocols; The physical coordinates of the underlying devices are obtained as spatial location data through geographic information systems or indoor positioning tags; Real-time reading of the voltage, current, and I / O port status of the underlying devices is used as operational telemetry data.

3. The remote unified intelligent centralized control system platform based on PNT according to claim 1, characterized in that, The process by which the spatiotemporal reference construction module generates spatiotemporal holographic data includes: By using a field-programmable gate array (FPGA) to analyze the time synchronization signal, a globally unified system clock is established. At the moment when the underlying device collects operational telemetry data, the operational telemetry data is latched using the system clock and associated with the physical coordinates of the device; The combined data, including absolute timestamps, spatial labels, and state values, is encapsulated into spatiotemporal holographic data.

4. The remote unified intelligent centralized control system platform based on PNT according to claim 1, characterized in that, The heterogeneous computing power normalization module calibrates the processing power of heterogeneous chips based on the system clock frequency to offset the clock drift of the operating system, and uniformly converts it into standard task throughput per unit time, thereby mapping it into a standardized time-slice computing power indicator. The process includes: Obtain the task scheduling mechanism and instruction response cycle of different processor architectures in the underlying device; The clock drift of different operating systems is calibrated based on the system clock frequency, and the computing performance of processors with different architectures is uniformly converted into standard task throughput per unit time. Calculate the inherent time required for each underlying device to process standard control commands based on the standard task throughput, and mark this inherent time as a time-slice computing power metric.

5. A remote unified intelligent centralized control system platform based on PNT according to claim 1, characterized in that, The process by which the time-triggered scheduling module generates time-triggered control instructions with future trigger times includes: Parse business logic requests to determine the target underlying device group; Retrieve the time-slice computing power metrics of all devices in the target underlying device group and identify the maximum processing time among them; Get the maximum network transmission delay of control commands during network transmission; Set a reserved synchronization buffer time; The current absolute time, maximum processing time, maximum network transmission latency, and synchronization buffer time are added together to obtain the future trigger time; The future trigger time is embedded into the business instruction frame to generate a time-triggered control instruction, so that the target underlying device group can synchronously execute actions when the future trigger time is reached.

6. The remote unified intelligent centralized control system platform based on PNT according to claim 1, characterized in that, The process by which the digital twin verification module generates system status assessment results includes: Create digital twins in the database that correspond one-to-one with the underlying physical devices; Update the expected state trajectory of the digital twin based on time-triggered control commands; Receive spatiotemporal holographic data fed back from the underlying devices and extract the actual state trajectory; Calculate the state deviation and time deviation between the expected state trajectory and the actual state trajectory at the same absolute time point.

7. A remote unified intelligent centralized control system platform based on PNT according to claim 6, characterized in that, The process by which the digital twin verification module generates system status assessment results based on state deviation and time deviation values ​​is configured as follows: Preset state consistency threshold and time jitter threshold; Execute the hierarchical judgment logic: first judge the state deviation value; if the state deviation value is greater than or equal to the state consistency threshold, then directly generate an alarm signal for physical equipment failure. If the state deviation value is less than the state consistency threshold, the time deviation value is further determined: if the time deviation value is greater than or equal to the time jitter threshold, an early warning signal of network congestion or insufficient computing power is generated; if the time deviation value is less than the time jitter threshold, a result indicating that the system is operating normally is generated.

8. A remote unified intelligent centralized control system platform based on PNT according to claim 1, characterized in that, It also includes a security authentication module, which is used for: Obtain the spatial location data of the terminal device that initiated the access request; Compare the spatial location data with the preset legal geofence range; In response to the spatial location data being within a legal geofence, terminal devices are allowed to access and distribute time synchronization signals; In response to the fact that the spatial location data is not within the legal geofence area, the access request is rejected and the issuance of control commands is blocked.

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