Pre-stabilization circuit and chip

Abstract

The application discloses a pre-stabilization circuit and a chip. The pre-stabilization circuit comprises a first Zener diode, a current source module configured to output a bias current to generate a first bias voltage, an isolation module configured to isolate a power supply voltage, a power-on reset module configured to output a power-on reset signal, a compensation module configured to multiplex devices in the power-on reset module to compensate the first bias voltage and output a second bias voltage, and a first stabilization module configured to output a first target voltage based on the second bias voltage and the power supply voltage. The compensation module compensates the first bias voltage to generate the second bias voltage limited in a preset voltage range. Even if a process difference affects a breakdown voltage, the first stabilization module can still output a stable first target voltage based on the second bias voltage, and the stabilization range is not affected. Moreover, the compensation module multiplexes the devices in the power-on reset module, so that the area and power consumption of the pre-stabilization circuit can be reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a pre-regulated circuit and chip. Background Technology

[0002] The pre-regulator circuit is a basic module in integrated circuits. It can perform preliminary voltage regulation on the input high voltage, and generate a lower and more stable voltage before it is supplied to the subsequent circuits.

[0003] Currently, the reverse breakdown characteristic of Zener diodes (also known as Zener diodes) is commonly used to construct pre-regulator circuits. For example, a pre-regulator circuit can be constructed by combining a Zener diode with an NMOS (N-Metal-Oxide-Semiconductor) transistor. The output voltage of a Zener diode-based pre-regulator circuit is primarily determined by the Zener diode's breakdown voltage. However, the breakdown voltage of a Zener diode is easily affected by process variations (such as doping concentration and dielectric thickness fluctuations), resulting in significant variations across different processes. If the breakdown voltage of the Zener diode is too high due to process variations, it will affect the voltage regulation range of the pre-regulator circuit, potentially causing subsequent circuits to withstand voltages exceeding their design withstand voltage. This can lead to device damage or performance degradation in subsequent circuits, impacting their reliability. Summary of the Invention

[0004] This application provides a pre-regulatory circuit and chip to solve the problem that the excessive breakdown voltage of the Zener diode affects the voltage regulation range of the pre-regulatory circuit.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] In a first aspect, this application provides a pre-regulatory circuit, the pre-regulatory circuit comprising:

[0007] The first Zener diode, with its positive terminal grounded;

[0008] The current source module has a first terminal connected to a preset power supply and a second terminal connected to the negative terminal of the first Zener diode, and is used to output bias current to generate a first bias voltage on the first Zener diode.

[0009] An isolation module, with its first end connected to the preset power supply and its second end connected to the negative terminal of the first Zener diode, is used to isolate the power supply voltage of the preset power supply.

[0010] The power-on reset module is used to output a power-on reset signal;

[0011] The compensation module has a first terminal connected to the negative terminal of the first Zener diode, a second terminal grounded, and a third terminal connected to the power-on reset module. It is used to reuse the components in the power-on reset module to compensate for the first bias voltage and output a second bias voltage through the output terminal of the compensation module. The second bias voltage is within a preset voltage range.

[0012] The first voltage regulator module has a first terminal connected to the second bias voltage, a second terminal connected to the isolation module, a third terminal grounded, and an output terminal connected to the power-on reset module. It is used to output a first target voltage based on the second bias voltage and the power supply voltage.

[0013] In one possible implementation, the compensation module includes a first compensation submodule and a second compensation submodule;

[0014] The first terminal of the first compensation submodule is connected to the negative terminal of the first Zener diode, the second terminal is grounded, the third terminal is connected to the power-on reset module through the second compensation submodule, and the output terminal is connected to the first voltage regulator module; the second compensation submodule is connected to the output terminal of the first voltage regulator module.

[0015] The second compensation submodule is used to reuse the devices in the power-on reset module to output a compensation control signal to the first compensation submodule;

[0016] The first compensation submodule is used to compensate the first bias voltage based on the compensation control signal and output the second bias voltage.

[0017] In one possible implementation, the first compensation submodule includes a first resistor, a second resistor, a first capacitor, a first NMOS and a second NMOS; the second compensation submodule includes a first PMOS, a first transistor and a third resistor.

[0018] The first terminal of the first resistor is connected to the negative terminal of the first Zener diode; the first terminal of the first capacitor, the first voltage regulator module, and the drain of the first NMOS are all connected to the second terminal of the first resistor; the source of the first NMOS is grounded through the second NMOS and the second resistor in sequence; the gate of the first NMOS and the second terminal of the first capacitor are both connected to the drain of the first PMOS; the gate of the second NMOS is grounded.

[0019] The source of the first PMOS is connected to the output terminal of the first voltage regulator module, and the drain is grounded through the first transistor and the third resistor in sequence; the gate of the first PMOS and the base of the first transistor are respectively connected to the power-on reset module.

[0020] In one possible implementation, the power-on reset module includes a second PMOS, a third PMOS, a second transistor, a third transistor, and a fourth resistor;

[0021] The source of the second PMOS and the source of the third PMOS are both connected to the output terminal of the first voltage regulator module; the gate of the first PMOS, the gate of the second PMOS, the drain of the second PMOS and the gate of the third PMOS are all connected to the collector of the second transistor.

[0022] The bases of the second transistor and the third transistor are both connected to the base of the first transistor; the emitter of the second transistor is grounded; and the third transistor is grounded through the fourth resistor.

[0023] In one possible implementation, the power-on reset module includes a second PMOS, a third PMOS, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a fourth resistor, and a fifth resistor.

[0024] The source of the second PMOS, the source of the third PMOS, and the collector of the fifth transistor are all connected to the output terminal of the first voltage regulator module; the gate of the first PMOS, the gate of the second PMOS, the drain of the second PMOS, and the gate of the third PMOS are all connected to the first terminal of the fifth resistor; the base of the fourth transistor and the collector of the fourth transistor are both connected to the second terminal of the fifth resistor.

[0025] The emitter of the fourth transistor and the base of the fifth transistor are both connected to the collector of the second transistor; the base of the second transistor, the base of the third transistor, and the emitter of the fifth transistor are all connected to the base of the first transistor; the emitter of the second transistor is grounded; the third transistor is grounded through the fourth resistor.

[0026] In one possible implementation, the isolation module is a third NMOS;

[0027] The gate of the third NMOS is connected to the negative terminal of the first Zener diode, the drain is connected to the preset power supply, and the source is connected to the second terminal of the first voltage regulator module.

[0028] In one possible implementation, the first voltage regulator module includes a fourth NMOS and a second Zener diode;

[0029] The gate of the fourth NMOS is connected to the second bias voltage, and the drain of the fourth NMOS is connected to the source of the third NMOS; the cathode of the second Zener diode and the power-on reset module are both connected to the source of the fourth NMOS; the anode of the second Zener diode is grounded.

[0030] In one possible implementation, the pre-regulator circuit further includes multiple second regulator modules;

[0031] The first terminal of each of the second voltage regulator modules is connected to the second bias voltage; the second terminal of each of the second voltage regulator modules is connected to the isolation module; and the third terminal of each of the second voltage regulator modules is grounded.

[0032] Each of the second voltage regulator modules is used to output a second target voltage through its output terminal based on the second bias voltage and the power supply voltage.

[0033] In one possible implementation, the current source module includes a fifth NMOS and a sixth resistor;

[0034] The drain of the fifth NMOS is connected to the preset power supply, the source is connected to the first end of the sixth resistor, and the gate is connected to the second end of the sixth resistor; the second end of the sixth resistor is connected to the negative terminal of the first Zener diode through a seventh resistor.

[0035] Secondly, this application provides a chip that includes the pre-regulator circuit described in any one of the first aspects above.

[0036] The pre-regulator circuit provided in this application adaptively compensates the first bias voltage through a compensation module to generate a second bias voltage limited within a preset voltage range. This ensures that even if process variations affect the breakdown voltage of the first Zener diode, the first regulator module can still output a stable first target voltage based on the second bias voltage limited within the preset voltage range and the power supply voltage. This does not affect the voltage regulation range of the pre-regulator circuit, preventing component damage or performance degradation in subsequent circuits and guaranteeing their reliability. Furthermore, the compensation module reuses components from the power-on reset module, reducing the area and power consumption of the pre-regulator circuit. Attached Figure Description

[0037] Figure 1 This is a block diagram illustrating a pre-regulator circuit according to an exemplary embodiment;

[0038] Figure 2 It is based on Figure 1 A block diagram of a pre-regulator circuit is shown.

[0039] Figure 3 It is based on Figure 2 A schematic diagram of a pre-regulator circuit is shown.

[0040] Figure 4 It is based on Figure 3 A schematic diagram of a pre-regulator circuit is shown;

[0041] Figure 5 It is based on Figure 3 A schematic diagram of another pre-regulatory circuit is shown;

[0042] Figure 6 It is based on Figure 1 A schematic diagram of a pre-regulator circuit is shown;

[0043] Figure 7 It is based on Figure 1 A schematic diagram of another pre-regulatory circuit is shown;

[0044] Figure 8 It is based on Figure 1 A schematic diagram of another type of pre-regulator circuit is shown;

[0045] Figure 9 It is based on Figure 1 The circuit diagram shown is of a pre-regulator circuit;

[0046] Figure 10 This is a block diagram illustrating a chip according to an exemplary embodiment. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0048] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, the use of "based on" or "according to" implies openness and inclusiveness, because processes, steps, calculations, or other actions "based on" or "according to" one or more of the stated conditions or values ​​may in practice be based on additional conditions or beyond the stated values.

[0049] Figure 1 This is a block diagram illustrating a pre-regulator circuit according to an exemplary embodiment. For example... Figure 1As shown, the pre-regulator circuit 10 includes:

[0050] The positive terminal of the first Zener diode Z1 is grounded.

[0051] The current source module 11 has a first terminal connected to a preset power supply BAT and a second terminal connected to the negative terminal of the first Zener diode Z1, and is used to output bias current to generate a first bias voltage on the first Zener diode Z1.

[0052] The isolation module 12 has its first end connected to the preset power supply BAT and its second end connected to the negative terminal of the first Zener diode Z1, and is used to isolate the power supply voltage of the preset power supply BAT.

[0053] The power-on reset module 13 is used to output a power-on reset signal.

[0054] The compensation module 14 has its first terminal connected to the negative terminal of the first Zener diode Z1, its second terminal grounded, and its third terminal connected to the power-on reset module 13. It reuses the components in the power-on reset module 13 to compensate for the first bias voltage and outputs a second bias voltage through its output terminal. The second bias voltage is within a preset voltage range.

[0055] The first voltage regulator module 15 has a first terminal connected to the second bias voltage, a second terminal connected to the isolation module 12, a third terminal grounded, and an output terminal connected to the power-on reset module 13. It is used to output a first target voltage based on the second bias voltage and the power supply voltage.

[0056] Specifically, after the pre-regulator circuit 10 is powered on, the current source module 11 will output a bias current I. Z This generates a first bias voltage VB1 on the first Zener diode Z1, where the first bias voltage VB1 is actually the breakdown voltage of the first Zener diode Z1.

[0057] The compensation module 14, by cooperating with some components in the power-on reset module 13 (i.e., reusing some components in the power-on reset module 13), can generate a pull-down current I. C The first bias voltage VB1 is adaptively compensated, and a second bias voltage VB2, limited to a preset voltage range, is output to the first voltage regulator module 15. Thus, even if process differences affect the breakdown voltage of the first Zener diode Z1, the second bias voltage VB2 input to the first voltage regulator module 15 is limited to a preset voltage range. This allows the first voltage regulator module 15 to still output a stable first target voltage POWER_OUT1 based on the second bias voltage and the power supply voltage isolated by the isolation module 12, without affecting the voltage regulation range of the pre-regulator circuit.

[0058] Furthermore, by reusing some components in the power-on reset module 13, the compensation module 14 can perform closed-loop feedback control based on the first target voltage POWER_OUT1 to regulate the pull-down current I. C The magnitude of the current is controlled, thereby controlling the magnitude of the second bias voltage VB2, and thus regulating the voltage regulation range of the pre-regulatory circuit 10 to achieve the function of closed-loop voltage regulation.

[0059] In addition, the power-on reset module 13 can output a power-on reset signal to the corresponding downstream circuit (such as a chip) to instruct the downstream circuit to perform a power-on reset operation.

[0060] It should be noted that the pre-regulator circuit 10 in this disclosure is actually based on the existing pre-regulator circuit with the addition of a compensation module 14. At the same time, some components in the power-on reset module 13 are reused to reduce the area and power consumption of the pre-regulator circuit 10 while achieving closed-loop voltage regulation at low cost. This solves the problem that the high breakdown voltage of the Zener diode affects the voltage regulation range of the pre-regulator circuit, and will not affect the normal operation of the subsequent circuit.

[0061] The pre-regulator circuit provided in this application embodiment adaptively compensates the first bias voltage through a compensation module to generate a second bias voltage limited within a preset voltage range. This ensures that even if process differences affect the breakdown voltage of the first Zener diode, the first regulator module can still output a stable first target voltage based on the second bias voltage limited within the preset voltage range and the power supply voltage. This does not affect the voltage regulation range of the pre-regulator circuit, preventing device damage or performance degradation in subsequent circuits and guaranteeing the reliability of those circuits. Furthermore, the compensation module reuses components from the power-on reset module, reducing the area and power consumption of the pre-regulator circuit.

[0062] Optionally, refer to Figure 2 The compensation module 14 includes a first compensation submodule 141 and a second compensation submodule 142.

[0063] The first terminal of the first compensation submodule 141 is connected to the negative terminal of the first Zener diode Z1, the second terminal is grounded, the third terminal is connected to the power-on reset module 13 through the second compensation submodule 142, and the output terminal is connected to the first voltage regulator module 15. The second compensation submodule 142 is connected to the output terminal of the first voltage regulator module 15.

[0064] The second compensation submodule 142 is used to reuse the devices in the power-on reset module 13 to output compensation control signals to the first compensation submodule 141.

[0065] The first compensation submodule 141 is used to compensate the first bias voltage based on the compensation control signal and output the second bias voltage.

[0066] Specifically, the compensation module 14 can be composed of a first compensation submodule 141 and a second compensation submodule 142. The first compensation submodule 141 is used to generate the pull-down current I. C This is used to adaptively compensate for the first bias voltage VB1 and output the second bias voltage VB2.

[0067] The second compensation submodule 142, by reusing some components in the power-on reset module 13, can output a compensation control signal POWER_CT to the first compensation submodule 141 based on the first target voltage POWER_OUT1. This allows the first compensation submodule 141 to regulate the pull-down current I based on the compensation control signal. C The magnitude of the current is adjusted to control the magnitude of the second bias voltage VB2, thereby adaptively compensating for the first bias voltage VB1.

[0068] Optionally, refer to Figure 3 The first compensation submodule 141 includes a first resistor R1, a second resistor R2, a first capacitor C1, a first NMOS transistor NM1, and a second NMOS transistor NM2. The second compensation submodule 142 includes a first PMOS transistor PM1, a first transistor N1, and a third resistor R3.

[0069] The first terminal of the first resistor R1 is connected to the negative terminal of the first Zener diode Z1. The first terminal of the first capacitor C1, the first voltage regulator module 15, and the drain of the first NMOS NM1 are all connected to the second terminal of the first resistor R1. The source of the first NMOS NM1 is grounded sequentially through the second NMOS NM2 and the second resistor R2. The gate of the first NMOS NM1 and the second terminal of the first capacitor C1 are both connected to the drain of the first PMOS PM1. The gate of the second NMOS NM2 is grounded.

[0070] The source of the first PMOS PM1 is connected to the output terminal of the first voltage regulator module 15, and the drain is grounded through the first transistor N1 and the third resistor R3 in sequence. The gate of the first PMOS PM1 and the base of the first transistor N1 are connected to the power-on reset module 13.

[0071] Specifically, the bias current I Z After the first bias voltage VB1 is generated on the first Zener diode Z1, the pull-down current I C The first bias voltage VB1 will be adaptively stepped down through resistor R1 to generate the second bias voltage VB2.

[0072] The first PMOS PM1, the first transistor N1, and the third resistor R3, in conjunction with some components in the power-on reset module 13, can output a compensation control signal POWER_CT to the gate of the first NMOS NM1 based on the first target voltage POWER_OUT1, thereby controlling the gate voltage of the first NMOS NM1 and thus regulating the pull-down current I. C The magnitude of the current is used to control the magnitude of the second bias voltage VB2. Through this closed-loop negative feedback mechanism (POWER_OUT1 as input and POWER_CT as output), the first target voltage POWER_OUT1 can eventually be stabilized at a certain value.

[0073] In one possible implementation, refer to Figure 4 The power-on reset module 13 includes a second PMOS PM2, a third PMOS PM3, a second transistor N2, a third transistor N3, and a fourth resistor R4.

[0074] The source of the second PMOS PM2 and the source of the third PMOS PM3 are both connected to the output terminal of the first voltage regulator module 15. The gate of the first PMOS PM1, the gate of the second PMOS PM2, the drain of the second PMOS PM2, and the gate of the third PMOS PM3 are all connected to the collector of the second transistor N2.

[0075] The bases of the second transistor N2 and the third transistor N3 are both connected to the base of the first transistor N1. The emitter of the second transistor N2 is grounded. The third transistor N3 is grounded through the fourth resistor R4.

[0076] Specifically, the drain of the third PMOS PM3 serves as the output terminal of the power-on reset module 13, used to output a high or low level power-on reset signal POWER_OK.

[0077] The first PMOS PM1, the first transistor N1, and the third resistor R3, in conjunction with the second PMOS PM2 and the second transistor N2 in the power-on reset module 13 (i.e., the compensation module 14 reuses the second PMOS PM2 and the second transistor N2), can output a compensation control signal POWER_CT based on the first target voltage POWER_OUT1. The ratio of the number of the second transistor N2, the first transistor N1, and the third transistor N3 is 1:4:4.

[0078] In order to achieve better temperature characteristics for the pre-regulator circuit 10, in another possible implementation, refer to Figure 5The power-on reset module 13 includes a second PMOS PM2, a third PMOS PM3, a second transistor N2, a third transistor N3, a fourth transistor N4, a fifth transistor N5, a fourth resistor R4, and a fifth resistor R5.

[0079] The source of the second PMOS PM2, the source of the third PMOS PM3, and the collector of the fifth transistor N5 are all connected to the output terminal of the first voltage regulator module 15. The gate of the first PMOS PM1, the gate of the second PMOS PM2, the drain of the second PMOS PM2, and the gate of the third PMOS PM3 are all connected to the first terminal of the fifth resistor R5. The base and collector of the fourth transistor N4 are both connected to the second terminal of the fifth resistor R5.

[0080] The emitter of the fourth transistor N4 and the base of the fifth transistor N5 are both connected to the collector of the second transistor N2. The base of the second transistor N2, the base of the third transistor N3, and the emitter of the fifth transistor N5 are all connected to the base of the first transistor N1. The emitter of the second transistor N2 is grounded. The third transistor N3 is grounded through the fourth resistor R4.

[0081] Specifically, the first transistor N1, the second transistor N2, and resistor R3 will generate a positive temperature coefficient current I1. The voltage drop V1 across resistor R5 caused by I1 is also positive temperature coefficient. Meanwhile, the gate-source voltage VGS of the second PMOS PM2... P2 The base-emitter voltage VBE of the second transistor N2 N2 The base-emitter voltage VBE of the fourth transistor N4 N4 The base-emitter voltage VBE of transistor N5 (the fifth transistor) N5 All of them have negative temperature coefficients. Therefore, by reasonably designing the ratio of the third resistor R3 to the fifth resistor R5, the first voltage regulator module 15 can output the first target voltage POWER_OUT1 with low temperature drift, so that the pre-regulator circuit 10 can achieve better temperature characteristics.

[0082] It should be noted that the fifth transistor N5 is a base current compensation mirror, used to compensate for the deviation of the base current from the final result when using a low-gain NPN transistor.

[0083] In some embodiments, the ratio of the number of the second transistor N2, the fourth transistor N4, the fifth transistor N5, the first transistor N1, and the third transistor N3 is 1:1:1:4:2.

[0084] Optionally, refer to Figure 6 The isolation module 12 is the third NMOS NM3.

[0085] The gate of the third NMOS NM3 is connected to the negative terminal of the first Zener diode Z1, the drain is connected to the preset power supply BAT, and the source is connected to the second terminal of the first voltage regulator module 15.

[0086] Specifically, the third NMOS NM3 is connected between the preset power supply BAT and the first voltage regulator module 15, serving as a high-voltage isolation to prevent the first voltage regulator module 15 from being damaged by high voltage.

[0087] It should be noted that other devices or combinations of devices can also be used to construct the isolation module 12, and this disclosure does not impose any specific restrictions on this.

[0088] Optionally, refer to Figure 6 The first voltage regulator module 15 includes a fourth NMOS NM4 and a second Zener diode Z2.

[0089] The gate of the fourth NMOS NM4 is connected to the second bias voltage, and the drain of the fourth NMOS NM4 is connected to the source of the third NMOS NM3. The cathode of the second Zener diode Z2 and the power-on reset module 13 are both connected to the source of the fourth NMOS NM4. The anode of the second Zener diode Z2 is grounded.

[0090] Specifically, the fourth NMOS NM4 serves as the source follower of the third NMOS NM3, while the second Zener diode Z2 is used to clamp the first target voltage POWER_OUT1 to prevent it from exceeding the withstand voltage of the subsequent circuit, and at the same time to prevent the gate-source voltage of the fourth NMOS NM4 from being too large and breaking down.

[0091] Optionally, refer to Figure 7 The pre-regulator circuit 10 also includes multiple second regulator modules 16.

[0092] The first terminal of each second voltage regulator module 16 is connected to a second bias voltage. The second terminal of each second voltage regulator module 16 is connected to the isolation module 12. The third terminal of each second voltage regulator module 16 is grounded.

[0093] Each second voltage regulator module 16 is used to output a second target voltage through its output terminal based on a second bias voltage and a power supply voltage.

[0094] Specifically, in practical applications, the pre-regulator circuit 10 may need to supply power to multiple downstream circuits simultaneously. In this case, the pre-regulator circuit 10 may also include multiple second regulator modules 16. Each second regulator module 16 can output a second target voltage POWER_OUT2 based on the second bias voltage VB2 and the power supply voltage.

[0095] The second voltage regulator module 16 can adopt the same structure as the first voltage regulator module 15 (in this case, the second voltage regulator module 16 is actually the first voltage regulator module 15, i.e., there are multiple first voltage regulator modules 15). For example, the second voltage regulator module 16 can be composed of an NMOS transistor and a Zener diode connected in series. When the second voltage regulator module 16 and the first voltage regulator module 15 adopt the same structure, the second target voltage POWER_OUT2 output by the second voltage regulator module 16 is the same as the first target voltage POWER_OUT1 output by the first voltage regulator module.

[0096] Optionally, refer to Figure 8 The current source module 11 includes a fifth NMOS NM5 and a sixth resistor R6.

[0097] The drain of the fifth NMOS NM5 is connected to the preset power supply BAT, the source is connected to the first terminal of the sixth resistor R6, and the gate is connected to the second terminal of the sixth resistor R6. The second terminal of the sixth resistor R6 is connected to the cathode of the first Zener diode Z1 through the seventh resistor R7.

[0098] Specifically, the fifth NMOS NM5 is a depletion-type NMOS. At this time, the first bias voltage VB1 is actually the voltage across the first Zener diode Z1 and the seventh resistor R7.

[0099] It should be noted that other devices or combinations of devices can also be used to construct the current source module 11, and this disclosure does not impose any specific restrictions on this.

[0100] The following is Figure 9 The working principle of the pre-regulator circuit 10 will be explained in detail using an example:

[0101] After the pre-regulator circuit 10 is powered on, the fifth NMOS NM5 and the sixth resistor R6 will output the bias current I of the first Zener diode Z1. Z This generates a first bias voltage VB1 across the first Zener diode Z1 and the seventh resistor R7. The first bias voltage VB1 is applied to the pull-down current I... C The second bias voltage VB2 is generated under the action of the first resistor R1. The second bias voltage VB2 is input to the gate of the fourth NMOS NM4, the fourth NMOS NM4 is turned on, and the source of the fourth NMOS NM4 outputs the first target voltage POWER_OUT1.

[0102] The first PMOS PM1, the first transistor N1, and the third resistor R3, in conjunction with the second PMOS PM2 and the second transistor N2, can output a compensation control signal POWER_CT to the gate of the first NMOS NM1 based on the first target voltage POWER_OUT1, thereby regulating the pull-down current I. CThe magnitude of the current is used to control the magnitude of the second bias voltage VB2. The entire circuit forms a closed loop, with POWER_OUT1 as the input and POWER_CT as the output. Its balance formula can be derived from the following formula:

[0103] The current flowing through the second transistor N2 is Among them, I S VT is the saturation current of the transistor and the thermal voltage.

[0104] When the number of N1 items is 4 times that of N2, ;

[0105] I2 = I1; where, This is the drain-source current of the second PMOS PM2. It is the product of carrier mobility and gate oxide capacitance. The aspect ratio is 4.5. Threshold voltage;

[0106] POWER_OUT1=VBE N2 +VBE N5 +VBE N4 +I1R5+VGS PM2 =VB1-I C ·R1-VGS N4 ;

[0107] By applying the above formulas, we can see that the final output voltage POWER_OUT1 is no longer a voltage determined by the breakdown voltage of the first Zener diode Z1, but a voltage calculated by the compensation module 14.

[0108] This application also provides a chip 20, such as Figure 10 As shown, the chip 20 may include Figures 1-9 Any one of the pre-regulator circuits 10.

[0109] The aforementioned chip 20 can be a motor drive chip, a power management chip, or other chips involving pre-voltage regulation.

[0110] Regarding the chip 20 in the above embodiments, the specific manner in which the pre-regulator circuit 10 performs its operation has been described in detail in the embodiments relating to the circuit, and will not be elaborated upon here.

[0111] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A pre-regulator circuit, characterized in that, The pre-regulator circuit includes: The first Zener diode, with its positive terminal grounded; The current source module has a first terminal connected to a preset power supply and a second terminal connected to the negative terminal of the first Zener diode, and is used to output bias current to generate a first bias voltage on the first Zener diode. An isolation module, with its first end connected to the preset power supply and its second end connected to the negative terminal of the first Zener diode, is used to isolate the power supply voltage of the preset power supply. The power-on reset module is used to output a power-on reset signal; The compensation module has a first terminal connected to the negative terminal of the first Zener diode, a second terminal grounded, and a third terminal connected to the power-on reset module. It is used to reuse the components in the power-on reset module to compensate for the first bias voltage and output a second bias voltage through the output terminal of the compensation module. The second bias voltage is within a preset voltage range. The first voltage regulator module has a first terminal connected to the second bias voltage, a second terminal connected to the isolation module, a third terminal grounded, and an output terminal connected to the power-on reset module. It is used to output a first target voltage based on the second bias voltage and the power supply voltage.

2. The pre-regulator circuit according to claim 1, characterized in that, The compensation module includes a first compensation submodule and a second compensation submodule; The first terminal of the first compensation submodule is connected to the negative terminal of the first Zener diode, the second terminal is grounded, the third terminal is connected to the power-on reset module through the second compensation submodule, and the output terminal is connected to the first voltage regulator module; the second compensation submodule is connected to the output terminal of the first voltage regulator module. The second compensation submodule is used to reuse the devices in the power-on reset module to output a compensation control signal to the first compensation submodule; The first compensation submodule is used to compensate the first bias voltage based on the compensation control signal and output the second bias voltage.

3. The pre-regulator circuit according to claim 2, characterized in that, The first compensation submodule includes a first resistor, a second resistor, a first capacitor, a first NMOS and a second NMOS; the second compensation submodule includes a first PMOS, a first transistor and a third resistor. The first terminal of the first resistor is connected to the negative terminal of the first Zener diode; the first terminal of the first capacitor, the first voltage regulator module, and the drain of the first NMOS are all connected to the second terminal of the first resistor; the source of the first NMOS is grounded through the second NMOS and the second resistor in sequence; the gate of the first NMOS and the second terminal of the first capacitor are both connected to the drain of the first PMOS; the gate of the second NMOS is grounded. The source of the first PMOS is connected to the output terminal of the first voltage regulator module, and the drain is grounded through the first transistor and the third resistor in sequence; the gate of the first PMOS and the base of the first transistor are respectively connected to the power-on reset module.

4. The pre-regulator circuit according to claim 3, characterized in that, The power-on reset module includes a second PMOS, a third PMOS, a second transistor, a third transistor, and a fourth resistor; The source of the second PMOS and the source of the third PMOS are both connected to the output terminal of the first voltage regulator module; the gate of the first PMOS, the gate of the second PMOS, the drain of the second PMOS and the gate of the third PMOS are all connected to the collector of the second transistor. The bases of the second transistor and the third transistor are both connected to the base of the first transistor; the emitter of the second transistor is grounded; and the third transistor is grounded through the fourth resistor.

5. The pre-regulator circuit according to claim 3, characterized in that, The power-on reset module includes a second PMOS, a third PMOS, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a fourth resistor, and a fifth resistor; The source of the second PMOS, the source of the third PMOS, and the collector of the fifth transistor are all connected to the output terminal of the first voltage regulator module; the gate of the first PMOS, the gate of the second PMOS, the drain of the second PMOS, and the gate of the third PMOS are all connected to the first terminal of the fifth resistor; the base of the fourth transistor and the collector of the fourth transistor are both connected to the second terminal of the fifth resistor. The emitter of the fourth transistor and the base of the fifth transistor are both connected to the collector of the second transistor; the base of the second transistor, the base of the third transistor, and the emitter of the fifth transistor are all connected to the base of the first transistor; the emitter of the second transistor is grounded; the third transistor is grounded through the fourth resistor.

6. The pre-regulator circuit according to claim 1, characterized in that, The isolation module is a third NMOS; The gate of the third NMOS is connected to the negative terminal of the first Zener diode, the drain is connected to the preset power supply, and the source is connected to the second terminal of the first voltage regulator module.

7. The pre-regulator circuit according to claim 6, characterized in that, The first voltage regulator module includes a fourth NMOS and a second Zener diode; The gate of the fourth NMOS is connected to the second bias voltage, and the drain of the fourth NMOS is connected to the source of the third NMOS; the cathode of the second Zener diode and the power-on reset module are both connected to the source of the fourth NMOS; the anode of the second Zener diode is grounded.

8. The pre-regulator circuit according to claim 1, characterized in that, The pre-regulator circuit also includes multiple second regulator modules; The first terminal of each of the second voltage regulator modules is connected to the second bias voltage; the second terminal of each of the second voltage regulator modules is connected to the isolation module; and the third terminal of each of the second voltage regulator modules is grounded. Each of the second voltage regulator modules is used to output a second target voltage through its output terminal based on the second bias voltage and the power supply voltage.

9. The pre-regulator circuit according to claim 1, characterized in that, The current source module includes a fifth NMOS and a sixth resistor; The drain of the fifth NMOS is connected to the preset power supply, the source is connected to the first end of the sixth resistor, and the gate is connected to the second end of the sixth resistor; the second end of the sixth resistor is connected to the negative terminal of the first Zener diode through a seventh resistor.

10. A chip, characterized in that, Includes the pre-regulator circuit as described in any one of claims 1-9.

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