A register-based chip frequency fine-tuning method, device and storage medium

Abstract

The application discloses a register-based chip main frequency fine adjustment method and device and a storage medium, relates to the single-chip microcomputer technical field, and comprises the following steps: acquiring an ideal frequency reference value stored in a chip memory according to a work target, testing a chip actual main frequency, and obtaining a frequency deviation value; collecting a current work voltage and a work temperature of the chip in real time, and respectively calculating a voltage compensation factor and a temperature compensation factor; adding the frequency deviation value, the voltage compensation factor and the temperature compensation factor to obtain a total target frequency deviation value; and mapping the total target frequency deviation value to a frequency fine adjustment register of the chip, adjusting electrical parameters of an internal oscillator through the frequency fine adjustment register, and compensating for main frequency deviation. The application solves the dynamic drift of low-end microcontroller main frequency with environmental fluctuations, and takes into account the problems of high-precision adjustment and low hardware overhead.

Description

Technical Field

[0001] This invention relates to the field of microcontroller integrated circuit technology, specifically to a register-based chip clock frequency fine-tuning method, device, and storage medium. Background Technology

[0002] In the field of microcontroller (MCU) integrated circuit design, internal high-frequency RC oscillators (IHRCs) have become the preferred clock source for applications such as consumer electronics, small appliance control, and industrial sensing due to their advantages, including eliminating the need for external quartz crystal components, fast start-up speed, low material cost, and significant saving of pin resources. However, due to the physical characteristics of semiconductor manufacturing processes, IHRCs naturally exhibit frequency distribution deviations during production. Even different chips on the same wafer often cannot directly achieve the nominal oscillation frequency, making frequency calibration a necessary step to ensure the correctness of timing logic.

[0003] To correct for process deviations, existing technologies typically employ static calibration at the factory. This involves measuring the frequency using precision instruments in a controlled laboratory environment (e.g., room temperature 25°C, nominal voltage 5V) and then permanently storing the calibration values ​​in the chip's non-volatile memory (e.g., MTP or OTP). However, this static approach suffers from significant time-sensitivity: after the chip is actually put into use, drastic changes in ambient temperature and fluctuations in power supply voltage can cause secondary shifts in the internal electrical parameters of the IHRC. This dynamic drift can lead to malfunctions in timing-sensitive functional modules (such as UART serial communication, infrared decoding, and high-frequency PWM output), and in severe cases, even system crashes or control failures.

[0004] To address the dynamic frequency drift problem, traditional capacitor array adjustment methods suffer from low accuracy and large chip area requirements. High-performance computing chips (such as AI processors or high-end SoCs) have developed Dynamic Frequency Scaling (DVFS) solutions based on complex algorithms and power prediction models. However, these solutions often require built-in high-precision current / power monitoring sensors and consume significant computing resources for closed-loop iterative calculations. For 8-bit MCUs with extremely limited computing resources, small storage space, and stringent standby power consumption requirements, directly porting these solutions is not feasible due to both hardware cost and software overhead.

[0005] Therefore, it is essential to design a register-based chip frequency fine-tuning method, device, and storage medium that can achieve high-precision frequency adjustment while also taking into account multi-factor fluctuations, under extremely simple hardware resource configuration. Summary of the Invention

[0006] The purpose of this invention is to provide a register-based chip clock frequency fine-tuning method, device, and storage medium to solve the problems mentioned in the background art.

[0007] To address the aforementioned technical problems, this invention provides the following technical solution: a register-based chip clock frequency fine-tuning method, comprising the following steps: Step S100: Obtain the ideal frequency reference value stored in the chip memory according to the working target. Test the actual clock frequency of the chip The frequency deviation value was obtained. ; Step S200: Real-time acquisition of the chip's current operating voltage and temperature, and calculation of the voltage compensation factor. and temperature compensation factor ; Step S300: The frequency deviation value The voltage compensation factor and the temperature compensation factor The total target frequency deviation value is obtained by summing the values. ; Step S400: Calculate the total target frequency deviation value. A frequency fine-tuning register mapped to the chip is used to adjust the electrical parameters of the internal oscillator to compensate for the main frequency offset.

[0008] According to the above technical solution, step S100 further includes: Step S110: Use an external clock source as a time window, the period of which is... Obtain the number of internal chip pulses corresponding to an external clock source within N cycles, denoted as The original frequency value of the chip was calculated. ; Step S120: By continuously acquiring the original frequency values ​​of M groups of chips, a recursive average filtering algorithm is used to obtain a stable actual main frequency value of the chip. ; Step S130: Obtain the frequency deviation value The calculation formula is: ; Furthermore, it also includes step S140, which includes: The actual clock frequency of the chip is compared with the ideal frequency reference value to calculate the initial frequency deviation ratio. The calculation formula is as follows: .

[0009] According to the above technical solution, step S200 further includes: Step S210: Measure the current operating voltage using the chip's voltage detection circuit. The voltage change was obtained. ,in This is the chip's nominal power supply voltage; Step S220: Calculate the voltage compensation factor The corresponding calculation formula is: ,in This is the voltage compensation coefficient. The voltage compensation intercept was obtained through chip voltage experiments. Step S230: Measure the current operating temperature using a temperature sensor. The change in temperature was obtained. ,in This is the chip's nominal temperature; Step S240: Divide the temperature into , , Three intervals, the three intervals respectively corresponding to the interval The value of i ranges from 1, 2, to 3; Step S250: Determine the current operating temperature corresponding interval Calculate the temperature compensation factor The corresponding calculation formula is: in , , This is the temperature compensation coefficient. , The temperature compensation intercept was obtained through chip temperature experiments.

[0010] According to the above technical solution, step S200 further includes step S260: calculating the voltage-temperature cross-compensation factor, wherein the cross-compensation factor... The cross-compensation coefficient The deviation ratio from the initial frequency was obtained through chip temperature and voltage experiments. Positive correlation.

[0011] The step S300 further includes step S300': converting the frequency deviation value... The voltage compensation factor The temperature compensation factor and the cross-compensation factor The total target frequency deviation value is obtained by summing the values. .

[0012] According to the above technical solution, the following step S500 is further included: synchronously correcting the timer reload value or baud rate generator parameter of the peripheral module according to the change ratio of the main frequency.

[0013] The present invention also provides a register-based chip frequency fine-tuning device, including an environment sensing module, a central control and storage module, a frequency control module, and an oscillation generation module: The environmental sensing module is configured to collect physical parameters of the chip's operating environment in real time and convert analog signals into digital signals, providing a basis for parameter adjustment for chip frequency fine-tuning; The central control and storage module includes a processor module and a memory module, and is communicatively connected to the environmental perception module. The memory module is configured to store the frequency calibration reference, and the processor module is configured to execute a compensation algorithm according to the working objective to calculate the calibration parameters required for frequency fine-tuning. The frequency control module is communicatively connected to the central control module and the storage module, and is configured to convert the calibration parameters required for frequency fine-tuning into bias current. The oscillation generation module is communicatively connected to the frequency control module and is configured to control the oscillator to generate a stable system clock based on the bias current, thereby achieving fine-tuning of the main frequency.

[0014] According to the above technical solution, the environmental sensing module includes a temperature sensing module, a voltage monitoring module, and an analog-to-digital conversion module; The temperature sensing module is communicatively connected to the analog-to-digital conversion module and is configured to detect the current temperature of the chip and output an analog voltage signal that is proportional to the temperature. The voltage monitoring module is communicatively connected to the analog-to-digital conversion module and is configured to acquire the power supply voltage of the chip in real time and output an analog voltage signal proportional to the power supply voltage. The analog-to-digital conversion module is configured to convert the analog voltage signals output by the temperature sensing module and the voltage monitoring module into digital quantities and transmit them to the central control and storage module.

[0015] According to the above technical solution, the frequency control module includes a register module and a current-mode digital-to-analog converter module; The register module is configured to write the calibration parameters required for receiving frequency fine-tuning into the register as an 8-bit calibration code. The current-mode digital-to-analog converter module is connected in communication with the register module and is configured to input an 8-bit calibration code and output an analog bias current increment.

[0016] The present invention also provides a register-based chip clock frequency fine-tuning device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of any of the methods described above.

[0017] The present invention also provides a storage medium, which is a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements a register-based chip clock frequency fine-tuning method as described above.

[0018] Compared with the prior art, the beneficial effects achieved by the present invention are: (1) By setting up an 8-bit high-resolution current-type digital-to-analog converter and a corresponding frequency fine-tuning register, the precision of the main frequency calibration is significantly improved without increasing the chip area, and the frequency deviation can be converged from the traditional ±(2-5)% level to a level far better than ±1%.

[0019] (2) By setting up an environmental sensing module that includes temperature sensing and voltage monitoring, the function of real-time and automatic correction of the main frequency offset according to environmental fluctuations is realized. The modular design reduces the complexity of the system and the difficulty of calibration, ensuring that the chip can maintain a stable clock reference under extreme conditions such as battery voltage drop or motor heating.

[0020] (3) By introducing an initial frequency deviation ratio identification mechanism and a cross-compensation factor correlation model, adaptive calibration for individual chip physical characteristics is realized, which solves the problem of chip environmental sensitivity differences caused by production process fluctuations. Furthermore, by deeply canceling the triple coupling interference of process, temperature and voltage, insufficient or excessive compensation under extreme conditions is avoided, which significantly improves the reliability and control accuracy of the system in complex dynamic environments. Attached Figure Description

[0021] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of a method flow according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a module composition according to an embodiment of the present invention; Figure 3 This is a graph showing the experimental results of voltage and temperature in an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Example 1 See Figure 1 The present invention provides a technical solution: a register-based chip clock frequency fine-tuning method, comprising the following steps: Step S100: Obtain the ideal frequency reference value stored in the chip memory according to the working target. Test chip actual clock frequency The frequency deviation value was obtained. ; Specifically, the actual clock frequency of the test chip The testing steps are as follows: Step S110: Use an external clock source as a time window, the period of which is... Obtain the number of internal chip pulses corresponding to an external clock source within N cycles, denoted as The original frequency data was obtained through calculation. The internal clock pulses are counted within a precise time window using a high-precision external reference clock to calculate the single frequency value.

[0024] Step S120: By continuously collecting M sets of raw frequency data, a stable actual main frequency is obtained using a recursive averaging filtering algorithm. By recursively averaging multiple single measurements, random interference is suppressed, thereby obtaining a stable actual frequency value.

[0025] Step S130: Compare the actual clock frequency with the preset ideal frequency reference value in the memory, and calculate the initial frequency deviation ratio. .

[0026] Step S100 obtains the ideal frequency deviation value of the chip. However, during operation, changes in environmental conditions can cause the oscillator frequency to drift. For example, start-up, shutdown, or sudden load changes can cause a drop in power supply voltage or an increase in ripple, leading to a significant deviation in the internal oscillator frequency. Similarly, prolonged operation or drastic changes in ambient temperature can also cause a significant frequency deviation in the internal oscillator. These two factors have the greatest impact, therefore compensation should be prioritized through real-time monitoring of voltage and temperature.

[0027] Step S200: Real-time acquisition of the chip's current operating voltage and operating temperature, and calculation of the voltage compensation factor. and temperature compensation factor ; Specifically, step S210: The current operating voltage is measured by the chip's voltage detection circuit. The voltage change was obtained. ,in This is the chip's nominal power supply voltage; Step S220: Calculate the voltage compensation factor The corresponding calculation formula is: ,in This is the voltage compensation coefficient. The voltage compensation intercept was obtained through chip voltage experiments. For example, the chip is placed in a temperature chamber powered by a programmable precision power supply, and its clock output pin is connected to a high-precision frequency meter. The temperature chamber is set to the nominal temperature of 25°C, and the temperature is allowed to stabilize completely. The power supply voltage is set to the nominal voltage. Measure and record the frequency at this time as the reference frequency. .

[0028] Select multiple test points within the chip's operating voltage range (e.g., 3.0V to 6.0V). For each voltage point, wait for the chip circuit to stabilize, then measure and record the frequency. Record the voltage deviation for each data point. and frequency deviation The calculation formulas are as follows: Voltage deviation ; Relative frequency deviation is ; by The x-axis is... Using the ordinate as the vertical axis, plot all data points on a scatter plot and fit the data using the least squares method to obtain the equation of the fitted line, as shown below. Figure 3 As shown in a: Where 1.54% is the voltage compensation coefficient. This indicates that for every 1V decrease in power supply voltage, the chip's main frequency decreases by 1.54%. 0.02% is the voltage compensation intercept. This indicates that at the nominal voltage point, the fitted curve almost passes through the reference point, and the linear model is very ideal. The goodness of fit is... This indicates a high degree of fit, conforming to a linear model.

[0029] Step S230: Measure the current operating temperature using a temperature sensor. The change in temperature was obtained. ,in This is the chip's nominal temperature; Step S240: Divide the temperature into , , Three intervals, the three intervals respectively corresponding to the interval The value of i ranges from 1, 2, to 3; Step S250: Determine the current operating temperature corresponding interval Calculate the temperature compensation factor The corresponding calculation formula is: in , , This is the temperature compensation coefficient. , The temperature compensation intercept was obtained through chip temperature experiments.

[0030] For example, the oven temperature is set in small increments across the chip's entire operating temperature range (e.g., -20°C to 80°C). At each temperature point, after the chip reaches thermal equilibrium, its actual output frequency is measured, resulting in a complete set of data points. The temperature deviation is recorded for each data point. and frequency deviation The calculation formulas are as follows: Temperature deviation ; Relative frequency deviation is ; Temperature deviation is plotted on the x-axis, and relative frequency deviation on the y-axis. A scatter plot is created using all data points to observe the curve's shape and find the optimal segmentation points. This allows for a high-precision fit using the simplest possible function within each sub-interval. Iterative fitting is employed, trying different temperature points as candidate segmentation points. For each segmentation scheme, a function is fitted to the data within each interval. The sum of squared residuals of the overall error between the fitted curve and all data points is evaluated for each segmentation scheme. The temperature segmentation scheme and function combination with the smallest overall error are selected, such as... Figure 3 As shown in b.

[0031] Low temperature range of Within the interval, the correlation coefficient exhibits a quadratic curve characteristic: A = -0.003%, B = -0.029%, C = -0.14%, and the correlation coefficient is... .

[0032] Normal temperature of Within the interval, a linear relationship exists: K is 0.02%, b is 0.04%, and the correlation coefficient is... .

[0033] High temperature range of Within the interval, it exhibits a quadratic curve characteristic: A is 0.002%, B is -0.07%, C is 1.02%, and the correlation coefficient is... .

[0034] Step S300: The frequency deviation value The voltage compensation factor and the temperature compensation factor The total target frequency deviation value is obtained by summing the values. The voltage and temperature compensation calculations are separated, and the modular design reduces the system complexity and calibration difficulty. The linear model effectively offsets the linear effect of power supply voltage fluctuations. Furthermore, a zoned temperature compensation strategy is adopted to match the most suitable mathematical model for different temperature zones, thereby significantly improving the accuracy of frequency compensation across the entire temperature range. This provides a stable timing basis for chip control and significantly improves the reliability of the system in complex working environments.

[0035] Further, step S200 also includes step S260: calculating the voltage-temperature cross-compensation factor, wherein the cross-compensation factor... The cross-compensation coefficient The deviation ratio from the initial frequency was obtained through chip temperature and voltage experiments. Positive correlation. The initial frequency deviation ratio is an inherent frequency error of the chip, mainly caused by process deviations during wafer manufacturing. By setting up a mechanism for recognizing and correcting the initial frequency deviation ratio, an adaptive calibration function is achieved, effectively solving the problem of inconsistent environmental sensitivity among different chips due to fluctuations in semiconductor manufacturing processes.

[0036] Step S300': The frequency deviation value The voltage compensation factor The temperature compensation factor and the cross-compensation factor The total target frequency deviation value is obtained by summing the values. By setting a functional correlation model between the initial deviation ratio and the temperature / voltage compensation factor, i.e., cross-compensation logic, a deep cancellation function for the triple coupling interference of process, temperature, and voltage is achieved. This avoids the over-compensation or under-compensation that occurs under extreme conditions in traditional single-dimensional compensation, and minimizes the dynamic deviation of the main frequency in the full temperature and full voltage range.

[0037] Step S400: Calculate the total target frequency deviation value. A frequency fine-tuning register mapped to the chip is used to adjust the electrical parameters of the internal oscillator to compensate for the main frequency offset.

[0038] Further, in step S500: based on the change ratio of the main frequency, synchronously correct the timer reload value or baud rate generator parameters of the peripheral module to maintain the constant physical timing of the peripherals. By setting up linkage synchronization logic between main frequency fine-tuning and peripheral module reload parameters, the function of keeping the physical output timing of peripherals (such as PWM pulse width and serial port baud rate) constant during dynamic frequency switching is realized. This effectively eliminates the data transmission garbled characters that may be caused by instantaneous clock adjustment, and greatly enhances the continuity and reliability of system operation. Example 2 See Figure 2 The present invention also provides a register-based chip main frequency fine-tuning device, including an environment sensing module, a central control and storage module, a frequency control module, and an oscillation generation module: The environmental sensing module is configured to collect physical parameters of the chip's operating environment in real time and convert analog signals into digital signals, providing a basis for parameter adjustment for chip frequency fine-tuning; Specifically, the environmental sensing module includes a temperature sensing module, a voltage monitoring module, and an analog-to-digital conversion module; The temperature sensing module is communicatively connected to the analog-to-digital conversion module and is configured to detect the current temperature of the chip and output an analog voltage signal that is proportional to the temperature. The voltage monitoring module is communicatively connected to the analog-to-digital conversion module and is configured to acquire the power supply voltage of the chip in real time and output an analog voltage signal proportional to the power supply voltage. The analog-to-digital conversion module is configured to convert the analog voltage signals output by the temperature sensing module and the voltage monitoring module into digital quantities and transmit them to the central control and storage module.

[0039] The central control and storage module includes a processor module and a memory module, and is communicatively connected to the environmental perception module. The memory module is configured to store the frequency calibration reference, and the processor module is configured to execute a compensation algorithm according to the working objective to calculate the calibration parameters required for frequency fine-tuning. The frequency control module is communicatively connected to the central control module and the storage module, and is configured to convert the calibration parameters required for frequency fine-tuning into bias current. Specifically, the frequency control module includes a register module and a current-mode digital-to-analog converter module; The register module is configured to write the calibration parameters required for receiving frequency fine-tuning into the register as an 8-bit calibration code. The current-mode digital-to-analog converter (I-DAC) module is communicatively connected to the register module and is configured to input an 8-bit calibration code and output an analog bias current increment. The internal current-mode DAC is controlled via an 8-bit digital interface, with each register increment corresponding to a small frequency change. High-precision frequency adjustment is achieved by altering the bias current of the oscillation circuit.

[0040] The oscillation generation module is communicatively connected to the frequency control module and is configured to control the oscillator to generate a stable system clock based on the bias current, thereby achieving fine-tuning of the main frequency.

[0041] The following description uses a preferred embodiment. In this embodiment, the main frequency of the robot servo angle control chip is finely adjusted. The servo angle is precisely determined by the duty cycle of the pulse width modulation (PWM) signal. Typically, in a 50Hz PWM signal, a pulse width of 0.5ms to 2.5ms corresponds to a servo angle of 0° to 180°. If the chip's main frequency drifts by 1%, it will result in a 20μs error in the pulse width, which in turn will cause an angle deviation of approximately 1.8° or severe jitter in the servo.

[0042] The core modules of this embodiment include: Environmental perception module: Temperature sensing module: monitors the impact of heat generated by the servo motor during long-term operation on the chip junction temperature.

[0043] Voltage monitoring module: Monitors the impact of battery voltage drop on the bias current of the oscillation circuit during high torque operation of the servo motor.

[0044] Analog-to-digital converter (ADC): Converts the above analog parameters into 8-bit or 12-bit digital signals, with a sampling frequency set to 10Hz-100Hz to balance response speed and power consumption.

[0045] Central control and storage module: Memory module: Pre-stores the frequency calibration reference code for the 16MHz nominal frequency at the factory, as well as the initial frequency deviation ratio for the current individual chip. .

[0046] Processor module: Executes the adaptive compensation algorithm unique to this invention.

[0047] Frequency control module: Register module: Built-in 8-bit IHRCCAL register, supporting numerical adjustment in the range of 0-255 levels.

[0048] The current-mode digital-to-analog converter (I-DAC) module: Each change in the least significant bit (LSB) alters the bias current of the internal oscillator (ICO), resulting in a step in the output frequency. In this embodiment, as shown in the tuning table below, taking a 7-bit valid calibration code (128 levels) as an example, the typical frequency step for each LSB is approximately 60kHz, with a relative change rate of approximately 0.36%. Because the system possesses high-resolution digital tuning capabilities across the entire frequency modulation range (-21.87% to +41.48%), the closed-loop control algorithm can precisely converge and stabilize the final frequency deviation within the change corresponding to one LSB, thereby achieving a high-precision clock that is far superior to the ±2%-5% initial error level of traditional RC oscillators.

[0049] In the next instruction cycle after the main frequency fine-tuning is completed, the processor synchronously corrects the reload register value of the servo motor's PWM generator. For example, if the main frequency is increased by 0.7%, the PWM cycle count value increases by 0.7% accordingly, thereby compensating for the impact of physical frequency changes on pulse width and achieving seamless compensation of the servo motor angle.

[0050] This technical solution constructs a closed-loop link encompassing environmental perception, digital prediction, and current fine-tuning. Through a digitally programmable current adjustment mechanism, it elevates the static frequency accuracy of a traditional RC oscillator to the dynamic accuracy level of a closed-loop adaptive system. The solution utilizes an 8-bit high-resolution DAC to precisely control the core bias current of the oscillator, enabling the main frequency to be accurately set in steps of approximately 60kHz (based on a nominal value of 16MHz). Combined with voltage and temperature sensing and compensation algorithms, the system not only converges the frequency deviation from the traditional ±(2-5)% level to a level far exceeding ±1%, but also responds to environmental changes in real time, significantly improving long-term stability and reliability under complex working conditions. Furthermore, it greatly enhances the chip's accuracy performance in timing-sensitive scenarios such as robot servo control, achieving a deep integration of low cost, small size, and high-performance control.

[0051] The present invention also provides a register-based chip clock frequency fine-tuning device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of any of the methods described above.

[0052] The present invention also provides a storage medium, which is a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements a register-based chip clock frequency fine-tuning method as described above.

[0053] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0054] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0055] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0056] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A register-based chip clock frequency fine-tuning method, characterized in that, Includes the following steps: Step S100: Obtain the ideal frequency reference value stored in the chip memory according to the working target. Test the actual clock frequency of the chip The frequency deviation value was obtained. ; Step S200: Real-time acquisition of the chip's current operating voltage and temperature, and calculation of the voltage compensation factor. and temperature compensation factor ; Step S300: The frequency deviation value The voltage compensation factor and the temperature compensation factor The total target frequency deviation value is obtained by summing the values. ; Step S400: Calculate the total target frequency deviation value. A frequency fine-tuning register mapped to the chip is used to adjust the electrical parameters of the internal oscillator to compensate for the main frequency offset.

2. The chip clock frequency fine-tuning method based on registers according to claim 1, characterized in that, Step S100 further includes: Step S110: Use an external clock source as a time window, the period of which is... Obtain the number of internal chip pulses corresponding to an external clock source within N cycles, denoted as The original frequency value of the chip was calculated. ; Step S120: By continuously acquiring the original frequency values ​​of M groups of chips, a recursive average filtering algorithm is used to obtain a stable actual main frequency value of the chip. ; Step S130: Obtain the frequency deviation value The calculation formula is: ; Furthermore, it also includes step S140, which includes: The actual clock frequency of the chip is compared with the ideal frequency reference value to calculate the initial frequency deviation ratio. The calculation formula is as follows: .

3. The chip clock frequency fine-tuning method based on registers according to claim 1, characterized in that, Step S200 further includes: Step S210: Measure the current operating voltage using the chip's voltage detection circuit. The voltage change was obtained. ,in This is the chip's nominal power supply voltage; Step S220: Calculate the voltage compensation factor The corresponding calculation formula is: ,in This is the voltage compensation coefficient. The voltage compensation intercept was obtained through chip voltage experiments. Step S230: Measure the current operating temperature using a temperature sensor. The change in temperature was obtained. ,in This is the chip's nominal temperature; Step S240: Divide the temperature into , , Three intervals, the three intervals respectively corresponding to the interval The value of i ranges from 1, 2, to 3; Step S250: Determine the current operating temperature corresponding interval Calculate the temperature compensation factor The corresponding calculation formula is: in , , This is the temperature compensation coefficient. , The temperature compensation intercept was obtained through chip temperature experiments.

4. The chip clock frequency fine-tuning method based on registers according to claim 2, characterized in that: Step S200 further includes step S260: calculating the voltage-temperature cross-compensation factor, wherein the cross-compensation factor... The cross-compensation coefficient The deviation ratio from the initial frequency was obtained through chip temperature and voltage experiments. Positive correlation; The step S300 further includes step S300': converting the frequency deviation value... The voltage compensation factor The temperature compensation factor and the cross-compensation factor The total target frequency deviation value is obtained by summing the values. .

5. The chip clock frequency fine-tuning method based on registers according to claim 4, characterized in that, Further includes: Step S500: Based on the change ratio of the main frequency, synchronously correct the timer reload value or baud rate generator parameter of the peripheral module.

6. A register-based chip main frequency fine-tuning system, comprising an environment sensing module, a central control and storage module, a frequency control module, and an oscillation generation module, characterized in that: The environmental sensing module is configured to collect physical parameters of the chip's operating environment in real time and convert analog signals into digital signals, providing a basis for parameter adjustment for chip frequency fine-tuning; The central control and storage module includes a processor module and a memory module, and is communicatively connected to the environmental perception module. The memory module is configured to store the frequency calibration reference, and the processor module is configured to execute a compensation algorithm according to the working objective to calculate the calibration parameters required for frequency fine-tuning. The frequency control module is communicatively connected to the central control module and the storage module, and is configured to convert the calibration parameters required for frequency fine-tuning into bias current. The oscillation generation module is communicatively connected to the frequency control module and is configured to control the oscillator to generate a stable system clock based on the bias current, thereby achieving fine-tuning of the main frequency.

7. The register-based chip clock frequency fine-tuning system according to claim 6, characterized in that: The environmental sensing module includes a temperature sensing module, a voltage monitoring module, and an analog-to-digital conversion module; The temperature sensing module is communicatively connected to the analog-to-digital conversion module and is configured to detect the current temperature of the chip and output an analog voltage signal that is proportional to the temperature. The voltage monitoring module is communicatively connected to the analog-to-digital conversion module and is configured to acquire the power supply voltage of the chip in real time and output an analog voltage signal proportional to the power supply voltage. The analog-to-digital conversion module is configured to convert the analog voltage signals output by the temperature sensing module and the voltage monitoring module into digital quantities and transmit them to the central control and storage module.

8. The chip clock frequency fine-tuning system based on registers according to claim 6, characterized in that: The frequency control module includes a register module and a current-mode digital-to-analog converter module; The register module is configured to write the calibration parameters required for receiving frequency fine-tuning into the register as an 8-bit calibration code. The current-mode digital-to-analog converter module is connected in communication with the register module and is configured to input an 8-bit calibration code and output an analog bias current increment.

9. A register-based chip clock frequency fine-tuning device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 5.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements a register-based chip clock frequency fine-tuning method as described in any one of claims 1 to 5.

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