A real-time clock power switching anti-jitter control method

Abstract

The application provides a real-time clock power switching anti-jitter control method, which adopts a real-time clock power switching anti-jitter circuit, and the real-time clock power switching anti-jitter circuit comprises a main power supply, a backup power supply, a first voltage detector, a second voltage detector, a detection output module, a power switching module and a real-time clock module; the main power supply is connected with the first voltage detector, the second voltage detector, the detection output module and the power switching module respectively; the detection output module is connected with the first voltage detector, the second voltage detector and the power switching module respectively; the power switching module is connected with the real-time clock module; and the backup power supply is connected with the real-time clock module. The real-time clock power switching anti-jitter control method provided by the application improves the working stability of the real-time clock and the continuous working time after power failure.

Description

Technical Field

[0001] This invention relates to a power switching control method, and more particularly to a real-time clock power switching anti-jitter control method. Background Technology

[0002] A real-time clock, as a timekeeping device, provides real-time time information to the system. A real-time clock needs to provide an accurate clock reference continuously over a long period. To ensure continuous operation, in addition to the main power supply, a backup power supply is typically provided for the real-time clock. When the main power supply fails, the system must promptly and reliably switch to the backup power supply.

[0003] Current technology for real-time clock power switching typically involves monitoring the main power supply voltage. When the main power supply voltage falls below a switching threshold, the system switches to backup power. However, when the main power supply experiences a voltage drop due to depletion, poor contact, or changes in line impedance, the supply voltage often doesn't decrease monotonically but oscillates repeatedly within a certain range. When the voltage oscillates near the switching threshold, it leads to frequent switching between the main and backup power supplies. This jitter from frequent power switching can cause instability in the internal oscillation circuit of the real-time clock, resulting in crystal oscillation delays or frequency shifts, affecting timing accuracy. Furthermore, each power switch changes the operating mode of the real-time clock, causing changes in circuit impedance load and generating transient currents. This significantly consumes the backup power supply (such as a coin cell battery), shortening its operating time. In addition, in real-time clock systems that need to record main power failure events, this jitter will repeatedly trigger the timestamp recording of the power failure event, making it difficult or incorrect to identify the true power failure event. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a real-time clock power switching anti-jitter control method to address the shortcomings of the prior art. When the main power supply voltage fluctuates, the real-time clock power supply is prevented from frequently switching between the main power supply and the backup power supply, thereby eliminating the switching jitter caused by the switching jitter. After eliminating the switching jitter, the method ensures that the recorded power failure event is real and valid.

[0005] This invention provides a real-time clock power switching anti-jitter control method, employing a real-time clock power switching anti-jitter circuit. The real-time clock power switching anti-jitter circuit includes: a main power supply, a backup power supply, a first voltage detector, a second voltage detector, a detection output module, a power switching module, and a real-time clock module. The main power supply is connected to the first voltage detector, the second voltage detector, the detection output module, and the power switching module. The detection output module is connected to the first voltage detector, the second voltage detector, and the power switching module. The power switching module is connected to the real-time clock module. The backup power supply is connected to the real-time clock module. The method includes the following steps: Step S1: Set a first voltage detection threshold for the first voltage detector. The first voltage detection threshold is lower than the standard voltage of the main power supply and higher than the main / backup power supply switching threshold voltage inside the real-time clock module. Set a second voltage detection threshold for the second voltage detector. The second voltage detection threshold is lower than the main / backup power supply switching threshold voltage inside the real-time clock module and not lower than the minimum operating voltage of the real-time clock module. Step S2: Real-time detection of the main power supply's operating voltage. When the main power supply's operating voltage is higher than the first voltage detection threshold, both the first voltage detector and the second voltage detector output a high-level signal to the detection output module. When the main power supply's operating voltage is lower than the first voltage detection threshold but higher than the second voltage detection threshold, the first voltage detector outputs a low-level signal to the detection output module, and the second voltage detector outputs a high-level signal to the detection output module. When the main power supply's operating voltage is lower than the second voltage detection threshold, both the first voltage detector and the second voltage detector output a low-level signal to the detection output module. Step S3: The detection output module performs logical AND processing and delay processing on the signals received from the first voltage detector and the second voltage detector, and then outputs the processed signals to the power switching module. In step S4, the power switching module controls the main power supply to power the real-time clock module according to the signal received from the detection output module: when the detection output module outputs a high-level signal to the power switching module, the power switching module controls the main power supply to power the real-time clock module; when the detection output module outputs a low-level signal to the power switching module, the power switching module controls the main power supply to shut down and power the real-time clock module, and the real-time clock module switches to backup power supply.

[0006] A further improvement of the present invention is that the detection output module is connected to the real-time clock module; in step S3, the detection output module performs logical AND processing and delay processing on the signals received from the first voltage detector and the second voltage detector, and then outputs the processed signals to the power switching module and the real-time clock module.

[0007] A further improvement of the present invention is that the detection output module includes a logic AND circuit and a delay circuit, the logic AND circuit being connected to the first voltage detector, the second voltage detector and the delay circuit respectively, and the delay circuit being connected to the power switching module and the real-time clock module respectively.

[0008] A further improvement of the present invention is that the detection output module is connected to the external event input pin of the real-time clock chip in the real-time clock module; in step S3, the detection output module processes the signals output by the first voltage detector and the second voltage detector through a logic AND circuit, then delays them through a delay circuit, and finally outputs the delayed signal to the power switching module and the real-time clock module. When the delayed signal changes from high level to low level, the external power failure event is triggered by the external event input pin of the real-time clock chip.

[0009] A further improvement of the present invention is that the power switching module includes an inverting drive circuit and a high-side switching circuit, the inverting drive circuit being connected to the detection output module and the high-side switching circuit respectively, and the high-side switching circuit being connected to the main power supply and the real-time clock module respectively.

[0010] A further improvement of the present invention is that, in step S4, the power switching module switches between the main power supply and the backup power supply to the real-time clock module according to the signal received from the detection output module: when the detection output module outputs a high-level signal to the power switching module, the power switching module passes the high-level signal through the inverting drive circuit and controls the high-side switch circuit to turn on the main power supply to the real-time clock module; when the detection output module outputs a low-level signal to the power switching module, the power switching module passes the low-level signal through the inverting drive circuit and controls the high-side switch circuit to turn off the main power supply to the real-time clock module, and the real-time clock module switches to the backup power supply.

[0011] A further improvement of the present invention is that the logic circuit includes a pull-up resistor R1; the outputs of the first voltage detector and the second voltage detector are both open-drain outputs; one end of the pull-up resistor R1 is connected to the output terminals of the first voltage detector and the second voltage detector, and the other end of the pull-up resistor R1 is connected to the main power supply.

[0012] A further improvement of the present invention is that the delay circuit includes a capacitor C1, one end of which is connected to one end of the pull-up resistor R1, and the other end of which is grounded.

[0013] A further improvement of the present invention is that both the first voltage detector and the second voltage detector are delayed output type voltage detectors.

[0014] A further improvement of the present invention is that it further includes diodes D1, D2, and D3; the anode of diode D1 is connected to the backup power supply, and the cathode of diode D1 is connected to the real-time clock module; the cathode of diode D2 is connected to the first voltage detector, and the anode is connected to one end of the pull-up resistor R1; the cathode of diode D3 is connected to the second voltage detector, and the anode is connected to one end of the pull-up resistor R1.

[0015] Compared with existing technologies, the advantages of this invention are as follows: Unlike existing technologies that only set one voltage detection threshold point for real-time clock power switching, this invention sets two voltage detection threshold points using a first voltage detector and a second voltage detector, forming a voltage detection window to control the switching between the main power supply and the backup power supply. Furthermore, by using a time delay output, it eliminates real-time clock power switching jitter within a certain voltage and time range, and after eliminating the switching jitter, ensures that the real-time clock records true and valid power failure events. The real-time clock power switching anti-jitter control method proposed in this invention improves the working stability of the real-time clock and its continuous working time after a power failure. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of one embodiment of the present invention.

[0017] Figure 2 This is a circuit schematic diagram of one embodiment of the present invention.

[0018] Figure labels: 1-Detection output module; 101-Logic AND circuit; 102-Delay circuit; 2-Power switching module; 201-Inverting drive circuit; 202-High-side switch circuit; 3-Real-time clock module. Detailed Implementation

[0019] In the description of this invention, if directional descriptions are involved, such as "up," "down," "front," "back," "left," "right," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, it is only for the convenience of describing the invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. If a technical feature is referred to as "set," "fixed," "connected," or "installed" on another technical feature, it can be directly set, fixed, or connected to the other technical feature, or it can be indirectly set, fixed, connected, or installed on the other technical feature.

[0020] In the description of this invention, the term "several" means one or more; the term "multiple" means two or more; the terms "greater than," "less than," "exceeding," "higher than," and "lower than" are all understood to exclude the stated number; the terms "above," "below," "within," "not higher than," and "not lower than" are all understood to include the stated number. The terms "first," "second," etc., are understood to be used only to distinguish identical or similar technical feature names, and should not be construed as implying / indicating the relative importance of the technical features, the number of technical features, or the sequential relationship between the technical features.

[0021] The preferred embodiments of the present invention will now be described in further detail with reference to the accompanying drawings.

[0022] like Figure 1 As shown, this embodiment provides a real-time clock power switching anti-jitter control method, which employs a real-time clock power switching anti-jitter circuit. The real-time clock power switching anti-jitter circuit includes: a main power supply VCC, a backup power supply BT1, a first voltage detector U1, a second voltage detector U2, a detection output module 1, a power switching module 2, and a real-time clock module 3. The main power supply VCC is connected to the first voltage detector U1, the second voltage detector U2, the detection output module 1, and the power switching module 2, respectively. The detection output module 1 is connected to the first voltage detector U1, the second voltage detector U2, and the power switching module 2, respectively. The power switching module 2 is connected to the real-time clock module 3. The backup power supply BT1 is connected to the real-time clock module 3. The method includes the following steps: Step S1: Set the first voltage detection threshold of the first voltage detector U1. The first voltage detection threshold is lower than the standard voltage of the main power supply VCC and higher than the internal main / backup power supply switching threshold voltage of the real-time clock module 3. Set the second voltage detection threshold of the second voltage detector U2. The second voltage detection threshold is lower than the internal main / backup power supply switching threshold voltage of the real-time clock module 3 and not lower than the minimum operating voltage of the real-time clock module 3. Step S2: Real-time detection of the operating voltage of the main power supply VCC. When the operating voltage of the main power supply VCC is higher than the first voltage detection threshold, both the first voltage detector U1 and the second voltage detector output a high-level signal to the detection output module 1. When the operating voltage of the main power supply VCC is lower than the first voltage detection threshold but higher than the second voltage detection threshold, the first voltage detector U1 outputs a low-level signal to the detection output module, and the second voltage detector U2 outputs a high-level signal to the detection output module 1. When the operating voltage of the main power supply VCC is lower than the second voltage detection threshold, both the first voltage detector U1 and the second voltage detector U2 output a low-level signal to the detection output module 1. Step S3: The detection output module 1 performs logical AND processing and delay processing on the signals received from the first voltage detector U1 and the second voltage detector U2, and then outputs the processed signals to the power switching module 2. In step S4, the power switching module 2 controls the main power supply VCC to supply power to the real-time clock module 3 according to the signal received from the detection output module 1: when the detection output module 1 outputs a high-level signal to the power switching module 2, the power switching module 2 controls the main power supply VCC to be turned on to supply power to the real-time clock module 3; when the detection output module 1 outputs a low-level signal to the power switching module 2, the power switching module 2 controls the main power supply VCC to be turned off to supply power to the real-time clock module 3, and the real-time clock module 3 switches to the backup power supply BT1.

[0023] It needs to be explained, such as Figure 2 As shown, the standard voltage of the main power supply VCC is 3.3V, and the backup power supply BT1 is a coin cell battery with a standard voltage of 3.0V. The real-time clock chip U3 in real-time clock module 3 is model RX8111CE, with a minimum operating voltage of 1.1V. The real-time clock chip RX8111CE provides a main power supply interface VDD and a backup power supply interface VBAT. It integrates a 1.3V voltage detector to detect the voltage of the main power supply interface VDD and switch between main and backup power supplies. Therefore, the internal main and backup power supply switching threshold voltage of real-time clock module 3 is 1.3V: when the voltage of the main power supply interface VDD is lower than 1.3V, U3 is powered through the backup power supply interface VBAT; when the voltage of the main power supply interface VDD is higher than 1.3V, U3 is powered through the main power supply interface VDD. It should be noted that although the RX8111CE provides voltage detection for the main power supply VDD, it only performs single-point voltage detection. When the VDD voltage of U3 fluctuates around 1.3V, the RX8111CE will frequently switch between the VDD and VBAT power supply circuits. This frequent switching may cause unstable power supply to the internal oscillation circuit of the RX8111CE, affecting the timing accuracy. On the other hand, each power switch will change the operating mode of the real-time clock, causing changes in the circuit impedance load and resulting in transient current, which will significantly consume the power of the backup power supply BT1 and shorten the backup power supply's operating time.

[0024] In this embodiment, as Figure 2As shown, the first voltage detector U1 and the second voltage detector U2 are both low-voltage detection chips, both model BL8506. The low-voltage detection chip BL8506 can select a detection voltage range of 0.9V to 6.0V (in 0.1V steps). The first voltage detector U1 selects a detection voltage of 2.5V as the first voltage detection threshold. When the operating voltage of the main power supply VCC monitored by the input terminal VDD of the first voltage detector U1 is lower than 2.5V, the output terminal VOUT of U1 will output a low level. The second voltage detector U2 selects a detection voltage of 1.1V as the second voltage detection threshold. When the operating voltage of the main power supply VCC monitored by the input terminal VDD of the second voltage detector U2 is lower than 1.1V, the output terminal VOUT of U2 will output a low level. The detection output module 1 performs logical AND and delay processing on the signals of the output terminals VOUT of the first voltage detector U1 and VOUT of the second voltage detector U2, and then outputs the signal to the power switching module 2.

[0025] When the main power supply VCC operating voltage is lower than 1.1V, the output terminals VOUT of both U1 and U2 are at a low level. After the VOUT signals at the output terminals of U1 and U2 are processed by the logic AND of the detection output module 1 to a low level, and after a delay, the detection output module 1 outputs a control to the power switching module 2 to shut down the main power supply VCC and supply power to the real-time clock module 3. That is, the main power supply interface VDD of the real-time clock chip U3 is turned off. At this time, the real-time clock module 3 switches to the backup power supply BT1, that is, the real-time clock module 3 switches to the backup power supply BT1 connected to the backup power supply interface VBAT through the real-time clock chip U3 to be powered.

[0026] When the main power supply VCC operates at a voltage higher than 1.1V but lower than 2.5V, the output VOUT of U1 is low, and the output VOUT of U2 is high. After the VOUT signals from U1 and U2 are processed by the detection output module 1 using a logical AND operation, they remain low. After a delay, the detection output module 1 outputs a control to the power switching module 2 to shut down the main power supply VCC and supply power to the real-time clock module 3. Specifically, the main power supply interface VDD of the real-time clock chip U3 is turned off. At this time, the real-time clock module 3 switches to the backup power supply BT1, meaning it is powered by the backup power supply BT1 connected to the backup power supply interface VBAT via the real-time clock chip U3.

[0027] When the operating voltage of the main power supply VCC is higher than 2.5V, the output terminals VOUT of U1 and U2 are both high. After the VOUT signals of U1 and U2 are processed by the logic AND of the detection output module 1, they are high. After a delay, the detection output module 1 outputs a control to the power switching module 2 to turn on the main power supply VCC to supply power to the real-time clock module 3. That is, the main power supply VCC supplies power to the real-time clock module 3 through the main power supply interface VDD of the real-time clock chip U3.

[0028] More specifically, the setting of the first and second voltage detection thresholds is mainly based on the following: the voltage window formed by the first and second voltage detection thresholds is wide enough to cover the range of main power supply VCC jitter and to cover the internal main / backup power supply switching threshold voltage point of the real-time clock module 3. In this embodiment, the first voltage detection threshold is set to 2.5V, which is lower than the standard voltage of the main power supply VCC (3.3V) and higher than the internal main / backup power supply switching threshold of the real-time clock module 3 (1.3V); the second voltage detection threshold is set to 1.1V, which is lower than the internal main / backup power supply switching threshold of the real-time clock module 3 (1.3V) and not lower than the minimum operating voltage of the real-time clock module 3 (1.1V). By setting a first voltage detection threshold and a second voltage detection threshold, a voltage window of 1.1V to 2.5V is formed for detection. This voltage window covers the internal main and backup power switching threshold voltage of the real-time clock module 3. On the one hand, it avoids the competition risk of internal and external switching between the main power supply and the backup power supply. On the other hand, when the voltage of the main power supply VCC fluctuates within the range of 1.1V to 2.5V, it will not frequently switch between the main power supply and the backup power supply.

[0029] In addition, the detection output module 1 performs logical AND processing and delay processing on the signals received from the first voltage detector U1 and the second voltage detector U2 before outputting them to the power switching module 2. Therefore, within the time range of the delay / delay processing, there will be no switching action between the main power supply VCC and the backup power supply BT1, thereby eliminating the frequent switching between the main power supply and the backup power supply within the time range of the delay / delay processing.

[0030] like Figure 1 As shown, the detection output module 1 is connected to the real-time clock module 3; in step S3, the detection output module 1 performs logical AND processing and delay processing on the signals received from the first voltage detector U1 and the second voltage detector U2, and then outputs the processed signals to the power switching module 2 and the real-time clock module 3.

[0031] like Figure 1 and Figure 2As shown, the detection output module 1 includes a logic AND circuit 101 and a delay circuit 102. The logic AND circuit 101 is connected to the first voltage detector U1, the second voltage detector U2 and the delay circuit 102 respectively. The delay circuit 102 is connected to the power switching module 2 and the real-time clock module 3 respectively.

[0032] It should be noted that in the detection output module 1, after the output signals of the first voltage detector U1 and the second voltage detector U2 are processed by the logic AND circuit 101 and the delay circuit 102, they are output to the power switching module 2 and the real-time clock module 3, thus eliminating the switching jitter of the main and backup power supplies of the real-time clock module within a certain voltage range and time range.

[0033] like Figure 2 As shown, the detection output module 1 is connected to the external event input pin EVIN of the real-time clock chip U3 in the real-time clock module 3. In step S3, the detection output module 1 processes the signals received from the first voltage detector U1 and the second voltage detector U2 through the logic AND circuit 101, then delays them through the delay circuit 102, and finally outputs the delayed signal to the power switching module 2 and the real-time clock module 3. When the delayed signal changes from high level to low level, the external power failure event is triggered by the external event input pin EVIN of the real-time clock chip U3.

[0034] More specifically, the EVIN pin of the RX8111CE is the external event input pin. The RX8111CE can record a maximum of 8 sets of externally triggered timestamped events. Externally triggered event records exceeding 8 sets will be overwritten cyclically. In this example, the detection output module 1 is connected to the EVIN pin of U3 to record power-down events. When the detection output module 1 outputs a signal to the power switching module 2, it also outputs a signal to the real-time clock module 3. When this signal changes from high to low, that is, when the real-time clock module 3 switches from main power supply VCC to backup power supply BT1, the EVIN pin triggers the recording of external power-down events. Because the signal received by the EVIN pin is a control signal after filtering out jitter, it will not be overwritten due to repeated recordings of power-down events caused by main power supply VCC voltage jitter, thus ensuring that the recorded power-down events are authentic and valid.

[0035] like Figure 1 As shown, the power switching module 2 includes an inverting drive circuit 201 and a high-side switching circuit 202. The inverting drive circuit 201 is connected to the detection output module 1 and the high-side switching circuit 202, respectively. The high-side switching circuit 202 is connected to the main power supply VCC and the real-time clock module 3, respectively.

[0036] like Figure 1 and Figure 2 As shown, in step S4, the power switching module 2 switches between the main power supply VCC or the backup power supply BT1 to power the real-time clock module 3 according to the signal received from the detection output module 1: when the detection output module 1 outputs a high-level signal to the power switching module 2, the power switching module 2 passes the high-level signal through the inverting drive circuit 201 and controls the high-side switch circuit 202 to turn on the main power supply VCC to power the real-time clock module 3; when the detection output module 1 outputs a low-level signal to the power switching module 2, the power switching module 2 passes the low-level signal through the inverting drive circuit 202 and controls the high-side switch circuit 202 to turn off the main power supply VCC to power the real-time clock module 3, and at the same time, the real-time clock module 3 switches to the backup power supply BT1, that is, the real-time clock module 3 switches to the backup power supply BT1 connected to the backup power supply interface VBAT through the real-time clock chip U3 to be powered.

[0037] It should be noted that the real-time clock module 3 is powered by either the main power supply VCC or the backup power supply BT1, and the power supply control needs to be switched on the positive (high side) of the power supply. Furthermore, since the control signal logic output by the detection output module 1 is opposite to the switching control logic of the high-side switching circuit 202, in this embodiment, the power switching module 2 uses the inverting drive circuit 201 to invert the control signal output by the detection output module 1, and then uses the high-side switching circuit 202 to control the main power supply VCC to power the real-time clock module 3.

[0038] More specifically, such as Figure 2 As shown, when the signal output from the detection output module 1 to the reverse drive circuit 201 is high, the base (B) of the PNP transistor Q1 is high, Q1 is cut off, and the collector (C) of Q1 is pulled down to a low level through resistor R2. The gate (G) of the PMOS transistor Q2 in the high-side switching circuit 202 is low, Q2 is turned on, and the main power supply VCC supplies power to the main power supply interface VDD of the real-time clock chip U3 of the real-time clock module 3. When the signal output from the detection output module 1 to the reverse drive circuit 201 is low, the base (B) of the PNP transistor Q1 is low, Q1 is turned on, and the gate (G) of the PMOS transistor Q2 is pulled high by the main power supply VCC through Q1, Q2 is cut off, and the main power supply VCC supplies power to the real-time clock chip U3 of the real-time clock module 3. Simultaneously, the real-time clock module 3 switches to the backup power supply BT1, meaning the real-time clock module 3 switches to the backup power supply BT1 connected to the backup power supply interface VBAT through the real-time clock chip U3.

[0039] like Figure 2As shown, the logic circuit 101 includes a pull-up resistor R1; the outputs of the first voltage detector U1 and the second voltage detector U2 are both open-drain outputs; one end of the pull-up resistor R1 is connected to the outputs of the first voltage detector U1 and the second voltage detector U2, and the other end of the pull-up resistor R1 is connected to the main power supply VCC.

[0040] More specifically, the low-voltage detection chip BL8506 can be configured with either CMOS output or open-drain output. In this embodiment, both the first voltage detector U1 and the second voltage detector U2 are selected as open-drain outputs. The output terminals VOUT of the first voltage detector U1 and the second voltage detector U2 are interconnected and pulled up to VCC via pull-up resistor R1, forming a wired-AND logic. The detection output module 1 implements the logic-AND function. In this embodiment, the logic-AND function implemented by the wired-AND structure composed of open-drain output and pull-up resistor has a simple circuit structure and low cost.

[0041] like Figure 2 As shown, the delay circuit 102 includes a capacitor C1, one end of which is connected to one end of the pull-up resistor R1, and the other end of which is grounded.

[0042] More specifically, in this embodiment, the pull-up resistor R1 has a resistance of 1MΩ, and the capacitor C1 has a capacitance of 0.1uF. The pull-up resistor R1 and capacitor C1 in the detection output module 1 form an RC delay filter circuit. The filtering time of the delay filter circuit for the output level is approximately 0.1 seconds. That is to say, within a time range of 0.1 seconds, the output jitter of the detection output module 1 to the power switching module 2 will be filtered out. In specific circuit applications, the filtering time constant can be changed by changing the resistance of the pull-up resistor R1 and the capacitance of the capacitor C1, thereby adjusting the jitter time that needs to be filtered out.

[0043] Alternatively, both the first voltage detector U1 and the second voltage detector U2 can be delayed output type voltage detectors, preferably replaced by BL8518. BL8518 can internally delay the voltage detection signal by 200ms before outputting the signal through the output terminal VOUT. Therefore, within the 200ms time range, the output jitter of the detection output module 1 to the power switching module 2 will be eliminated.

[0044] like Figure 2As shown, it also includes diodes D1, D2, and D3; the anode of diode D1 is connected to the backup power supply BT1, and the cathode of diode D1 is connected to the real-time clock module 3; the cathode of diode D2 is connected to the first voltage detector U1, and the anode is connected to one end of the pull-up resistor R1; the cathode of diode D3 is connected to the second voltage detector U2, and the anode is connected to one end of the pull-up resistor R1.

[0045] More specifically, such as Figure 2 As shown, the function of diode D1 is to prevent the backup battery BT1 from being damaged by reverse charging, since the backup battery BT1 uses a non-rechargeable button cell. The functions of diodes D2 and D3 are to isolate the output VOUT of the first voltage detector U1 and the output VOUT of the second voltage detector U2. A low output level from either U1's output VOUT or U2's output VOUT will maintain a low output level.

[0046] In summary, the real-time clock power switching anti-jitter control method provided in this embodiment differs from existing technologies that only set a single voltage detection threshold point for real-time clock power switching. This invention uses two voltage detection threshold points to form a voltage detection window to control the switching between the main power supply and the backup power supply. Furthermore, by using a time delay output, it eliminates the jitter of real-time clock power switching within a certain voltage and time range. After eliminating the switching jitter, it ensures that the real-time clock records accurate and valid power failure events. The real-time clock power switching anti-jitter control method proposed in this invention improves the operational stability of the real-time clock and its continuous operating time after a power failure.

[0047] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A real-time clock power switching anti-jitter control method, characterized in that, A real-time clock power switching anti-jitter circuit is adopted, which includes: a main power supply, a backup power supply, a first voltage detector, a second voltage detector, a detection output module, a power switching module, and a real-time clock module. The main power supply is connected to the first voltage detector, the second voltage detector, the detection output module, and the power switching module. The detection output module is connected to the first voltage detector, the second voltage detector, and the power switching module. The power switching module is connected to the real-time clock module. The backup power supply is connected to the real-time clock module. The circuit includes the following steps: Step S1: Set a first voltage detection threshold for the first voltage detector. The first voltage detection threshold is lower than the standard voltage of the main power supply and higher than the main / backup power supply switching threshold voltage inside the real-time clock module. Set a second voltage detection threshold for the second voltage detector. The second voltage detection threshold is lower than the main / backup power supply switching threshold voltage inside the real-time clock module and not lower than the minimum operating voltage of the real-time clock module. Step S2: Real-time detection of the main power supply's operating voltage. When the main power supply's operating voltage is higher than the first voltage detection threshold, both the first voltage detector and the second voltage detector output a high-level signal to the detection output module. When the main power supply's operating voltage is lower than the first voltage detection threshold but higher than the second voltage detection threshold, the first voltage detector outputs a low-level signal to the detection output module, and the second voltage detector outputs a high-level signal to the detection output module. When the main power supply's operating voltage is lower than the second voltage detection threshold, both the first voltage detector and the second voltage detector output a low-level signal to the detection output module. Step S3: The detection output module performs logical AND processing and delay processing on the signals received from the first voltage detector and the second voltage detector, and then outputs the processed signals to the power switching module. In step S4, the power switching module controls the main power supply to power the real-time clock module according to the signal received from the detection output module: when the detection output module outputs a high-level signal to the power switching module, the power switching module controls the main power supply to power the real-time clock module; when the detection output module outputs a low-level signal to the power switching module, the power switching module controls the main power supply to shut down and power the real-time clock module, and the real-time clock module switches to backup power supply.

2. The real-time clock power switching anti-jitter control method according to claim 1, characterized in that, The detection output module is connected to the real-time clock module; in step S3, the detection output module performs logical AND processing and delay processing on the signals received from the first voltage detector and the second voltage detector, and then outputs the processed signals to the power switching module and the real-time clock module.

3. The real-time clock power switching anti-jitter control method according to claim 2, characterized in that, The detection output module includes a logic AND circuit and a delay circuit. The logic AND circuit is connected to the first voltage detector, the second voltage detector, and the delay circuit, respectively. The delay circuit is connected to the power switching module and the real-time clock module, respectively.

4. The real-time clock power switching anti-jitter control method according to claim 3, characterized in that, The detection output module is connected to the external event input pin of the real-time clock chip in the real-time clock module. In step S3, the detection output module processes the signals received from the first voltage detector and the second voltage detector through a logic AND circuit, then delays them through a delay circuit, and finally outputs the delayed signal to the power switching module and the real-time clock module. When the delayed signal changes from high level to low level, the external power failure event is triggered by the external event input pin of the real-time clock chip.

5. The real-time clock power switching anti-jitter control method according to claim 2, characterized in that, The power switching module includes an inverting drive circuit and a high-side switching circuit. The inverting drive circuit is connected to the detection output module and the high-side switching circuit, respectively. The high-side switching circuit is connected to the main power supply and the real-time clock module, respectively.

6. The real-time clock power switching anti-jitter control method according to claim 5, characterized in that, In step S4, the power switching module switches between main power and backup power to supply power to the real-time clock module based on the signal received from the detection output module: when the detection output module outputs a high-level signal to the power switching module, the power switching module passes the high-level signal through the inverting drive circuit and controls the high-side switching circuit to turn on the main power to supply power to the real-time clock module; when the detection output module outputs a low-level signal to the power switching module, the power switching module passes the low-level signal through the inverting drive circuit and controls the high-side switching circuit to turn off the main power to supply power to the real-time clock module, and the real-time clock module switches to backup power supply.

7. The real-time clock power switching anti-jitter control method according to claim 4 or 6, characterized in that, The logic circuit includes a pull-up resistor R1; the outputs of the first voltage detector and the second voltage detector are both open-drain outputs; one end of the pull-up resistor R1 is connected to the output terminals of the first voltage detector and the second voltage detector, and the other end of the pull-up resistor R1 is connected to the main power supply.

8. The real-time clock power switching anti-jitter control method according to claim 7, characterized in that, The delay circuit includes a capacitor C1, one end of which is connected to one end of the pull-up resistor R1, and the other end of the capacitor C1 is grounded.

9. The real-time clock power switching anti-jitter control method according to claim 7, characterized in that, Both the first voltage detector and the second voltage detector are delayed output type voltage detectors.

10. The real-time clock power switching anti-jitter control method according to claim 7, characterized in that, It also includes diodes D1, D2, and D3; the anode of diode D1 is connected to the backup power supply, and the cathode of diode D1 is connected to the real-time clock module; the cathode of diode D2 is connected to the first voltage detector, and the anode is connected to one end of the pull-up resistor R1; the cathode of diode D3 is connected to the second voltage detector, and the anode is connected to one end of the pull-up resistor R1.

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