An intelligent jamming identification network FPGA acceleration architecture for software radar

Abstract

This invention implements an intelligent interference identification network for software-defined radar on a resource-constrained FPGA platform, simultaneously meeting the requirements of accuracy, speed, and low power consumption. A co-processing architecture between the host computer and the FPGA is designed, leveraging the parallel capabilities of the FPGA to accelerate the algorithm. At the PL end, a main structure is designed with double buffering at both ends of the network, serial inter-level processing, and partially parallel processing within each level. Three substructures and one optimization method are provided: a data packet buffering substructure, a substructure for merging and pipelining within each level, and a substructure for parallel data flow within each level to improve processing speed; a bit-width truncation method is used to ensure identification accuracy and reduce hardware resource consumption. The interference recognition network implemented on the KCU1500 platform has a time complexity of 0.6872 GOPs, 316.1602KB of parameters, and 29.7070KB of output feature maps. At a 200MHz clock speed, it achieves a computation speed of 57.8696 GOPS, consumes 5.806W of power, utilizes 67.01% of BRAM resources, and 3.79% of DSP resources. Processing 100 416×416 sub-images takes 1.16773s. It outperforms CPUs, consumes less power than GPUs, and possesses better computational capabilities and higher DSP efficiency.

Description

Technical Field

[0001] This invention relates to the field of software-defined radar signal processing and neural network hardware acceleration technology, specifically to an FPGA-accelerated architecture for an intelligent interference identification network for software-defined radar. It is applicable to scenarios such as software-defined radar interference type identification and interference feature extraction in complex electromagnetic environments in civilian applications. It can be used in conjunction with software-defined radar sensing and detection equipment such as low-altitude security monitoring, UAV detection, civilian spectrum monitoring, and terrain mapping, providing real-time computing power support for intelligent radar anti-interference decision-making. Background Technology

[0002] As the civilian electromagnetic environment becomes increasingly complex, software-defined radar (SDR) places higher demands on the real-time performance, accuracy, and hardware adaptability of intelligent interference identification. Interference identification algorithms based on the Tiny-YOLO series of convolutional neural networks have become one of the core algorithms for intelligent interference processing in SDR due to their combination of computational efficiency and recognition accuracy. However, in the process of engineering implementation, these algorithms face many challenges in hardware platform adaptation: CPU platforms have slow computing speeds, failing to meet the real-time response requirements of SDR for interference identification; GPU platforms have high computing power but high power consumption, making them difficult to adapt to the demanding deployment environments of civilian SDR in outdoor and industrial scenarios; traditional FPGA implementations suffer from low resource utilization, time-consuming data interaction between layers, significant accuracy loss, and difficulties in adapting specialized designs to the modular requirements of SDR.

[0003] Existing FPGA acceleration solutions either only complete functional simulation without board-level verification, employ high-level synthesis methods leading to poor code portability and optimizability, or suffer from time waste and error accumulation due to frequent data migration between layers to external storage. None of these solutions meet the comprehensive requirements of software-defined radar for low power consumption, high real-time performance, high accuracy, and high resource utilization in intelligent interference identification, nor are they compatible with the standardized and modular signal processing systems of software-defined radar. Therefore, there is an urgent need to design an FPGA-accelerated architecture for intelligent interference identification networks adapted to the needs of software-defined radar, enabling efficient hardware deployment of interference identification neural networks while meeting multi-dimensional performance requirements and possessing high adaptability and scalability to software-defined radar systems. Summary of the Invention

[0004] The purpose of this invention is to provide an FPGA-accelerated architecture for intelligent interference identification networks in software-defined radar. This architecture addresses the problems of high power consumption, poor real-time performance, low resource utilization, significant accuracy loss, and poor system adaptability inherent in existing neural network hardware acceleration solutions for intelligent interference identification in software-defined radar scenarios. It enables efficient engineering implementation of the Tiny-YOLO convolutional neural network on an FPGA platform, providing low-power, high-real-time, and high-precision hardware computing power support for intelligent interference identification in software-defined radar. Furthermore, it adapts to the modular and standardized design requirements of software-defined radar, exhibiting good scalability and system interoperability.

[0005] This architecture adopts a heterogeneous collaborative design between a host computer and an FPGA. The core parallel accelerated computing of the intelligent interference identification network is realized on the PL terminal of the FPGA. Through the design of main structure innovation, substructure optimization and accuracy guarantee methods, the computing speed is greatly improved and the hardware resource consumption and power consumption are reduced while ensuring the accuracy of interference identification. The overall architecture design fits the signal processing flow and engineering requirements of software-defined radar. It can be directly integrated into the intelligent decision module of software-defined radar and seamlessly interface with the radar's signal acquisition, preprocessing and main control scheduling modules, providing real-time and reliable computing power support for interference type classification and interference feature extraction.

[0006] The specific design of this architecture includes three parts: the overall collaborative processing architecture, the FPGA-side core acceleration structure, and the accuracy guarantee and resource optimization methods. The design of each part is as follows:

[0007] I. Overall Collaborative Processing Architecture

[0008] The overall architecture adopts a heterogeneous collaborative processing architecture of host computer + FPGA. The host computer is responsible for radar interference feature data management, identification result analysis and visualization, while the FPGA is responsible for the parallel acceleration calculation of the entire intelligent interference identification network. The two achieve high-speed data interaction through the PCIe interface, which is fully adapted to the data flow transmission and processing requirements of software-defined radar. The overall structure diagram is as follows. Figure 1 As shown.

[0009] 1. Host Computer Function Module: This module comprises four core functions: data reading, data interaction, calculation and analysis, and display output. It is responsible for encapsulating the electromagnetic interference characteristic data acquired by the software-based radar in a quantized format and sending it to the FPGA via the PCIe interface in groups of four sub-images. It also receives the neural network calculation results from the FPGA and uses a non-maximum suppression algorithm to calculate the interference feature coordinates and type labels. Ultimately, it achieves real-time display of radar interference perception data and interference identification results, while simultaneously feeding back the identification results to the upper-level software-based radar intelligent decision-making system, providing core data support for the generation of radar anti-interference strategies. The structural diagram of this function is shown below. Figure 2 As shown.

[0010] 2. FPGA Core Functions: As the core unit for accelerating computation in the intelligent interference identification network, it is based on the Xilinx KU115 FPGA chip to build a dedicated processing architecture on the PL side. It receives radar interference feature data and network parameters sent by the host computer, completes the entire parallel computation of the Tiny-YOLO convolutional neural network, and sends the computation results back to the host computer in real time. At the same time, it supports timing synchronization with the software-defined radar system and can provide real-time feedback on hardware resource utilization, computation completion status, fault information, etc., to ensure collaborative work with various modules of the software-defined radar.

[0011] II. FPGA-side core acceleration structure

[0012] A dedicated main acceleration structure with double buffers at the beginning and end of the network, serial communication between layers and partial parallel communication within layers is designed at the PL end of the FPGA. At the same time, three substructures are designed to achieve dual optimization of computing speed and hardware resource utilization. The main structure and substructures work together to achieve efficient parallel processing of software-based radar interference feature data. Up to 8 sub-images can be processed at the same time, which greatly improves the real-time performance of software-based intelligent radar interference identification.

[0013] 1. Main acceleration structure:

[0014] Composed of an input double-buffered module, a Tiny-YOLO interference identification network calculation module, and an output double-buffered module, this system achieves ping-pong caching of interference feature data and pipelined network computation. The FPGA ping-pong stores the received radar interference feature data packets into the input double-buffered area. Assuming consistent processing time across network layers, the interference feature sub-graphs flow sequentially into the network calculation module. The calculated data is then ping-pong cached in the output double-buffered area, and once full, it is transmitted back to the host computer in real time. This structure avoids frequent data transfer between layers, improves the continuity of data processing, and adapts to the continuous acquisition and real-time processing requirements of software-based radar interference feature data. The main structural block diagram is shown below. Figure 3 As shown.

[0015] 2. Data grouping cache substructure:

[0016] To address the convolution calculation requirements of software-defined radar interference feature data, an integrated design of zero-padding and grouped caching is implemented. Multi-channel interference feature data is extracted by a factor of 3 and stored in three groups of RAM. Each RAM group stores eight columns of data at the same depth. A counter is used for cyclic counting to achieve precise control of the read address logic, ensuring that 3×3 convolutional data can be read in each clock cycle, with continuous output between clock cycles. This optimizes the computation time for convolution calculations, meeting the high-speed computation requirements of software-defined radar interference identification. The data grouped caching substructure diagram is shown below. Figure 4 As shown.

[0017] 3. Intra-hierarchical unit merging and pipelined computation substructure:

[0018] Convolutional layers, Batch Normalization (BN) layers, Leaky ReLU activation layers, and max pooling layers are grouped into a single computational unit, employing a parallel pipelined architecture for integrated computation. Each clock cycle completes the convolution, multiplication, and addition operations on 3×3 interference feature data; multi-channel convolution results are accumulated over several clock cycles per channel. The multiplication and addition terms of the BN layer are pre-calculated by the host computer, with the FPGA performing only efficient multiplication and addition operations. The Leaky ReLU layer achieves low-complexity computation through multiplication optimization, and the max pooling layer extracts the maximum value of a 2×2 matrix using a comparator. The overall computational unit's time consumption is negligible, significantly improving computational efficiency within the layer. The computation merging and pipelined structure are as follows: Figure 5 As shown.

[0019] 4. Parallel substructures of data flow within the hierarchy:

[0020] To address the computational differences across different network layers during software-based radar jamming feature data processing, a differentiated parallelism setting was implemented for multi-channel data: the parallelism of layers 4 and 7 was set to 2, and the parallelism of layers 5 and 8 was set to 4. This ensured consistent processing time across all network layers except the first and last layers, guaranteeing a streamlined processing effect between subgraphs and avoiding processing bottlenecks caused by differences in computational load between layers. This significantly improved the overall processing speed of radar jamming feature data. Table 1 shows the computation time statistics for each layer before parallel optimization.

[0021] Table 1 Time statistics before parallel optimization

[0022] Number of levels Write the number of ram / clk entries Read the number of ram / clk entries Calculation unit / clk count Max pool / clk number L1 7524 346112 12 0 L2 0 1384448 18 4 L3 0 1384448 18 0 L4 0 5537792 18 0 L5 0 11075584 18 4 L6 0 2768896 18 0 L7 0 5537792 18 0 L8 0 11075584 18 4 Out1 0 389376 14 0 Out2 0 1557504 14 0

[0023] After adding this substructure to the main structure, up to 8 subgraphs can be processed simultaneously, greatly reducing the processing speed of multiple subgraphs.

[0024] III. Accuracy Assurance and Resource Optimization Methods

[0025] This design employs a bit-width truncation method to optimize FPGA timing and reduce hardware storage resource consumption, while ensuring the accuracy of software-based intelligent radar interference identification. This fundamentally solves the problems of resource waste, timing degradation, and accuracy loss caused by excessive bit width in traditional solutions.

[0026] 1. Real-time bit width calculation:

[0027] After receiving radar interference characteristic data and network parameters, the FPGA calculates the minimum number of sign bits for each level of data written to RAM in real time and records the sharing index. At the same time, it calculates the bit width occupied by each level of coefficients and accurately calculates the maximum bit width of the output data of each level of computing unit (maximum bit width of input data + bit width of coefficients).

[0028] 2. Precise bit width truncation:

[0029] After each layer of the neural network is computed, 18 bits are truncated from the maximum bit width of the data as the output of this level and sent to the next level of RAM for storage. By passing the shared exponent across layers, invalid truncation in scenarios with large bit width and small data is avoided, effectively reducing the accumulation of errors in step-by-step computation.

[0030] 3. Optimization Results:

[0031] This method effectively reduces FPGA storage resource consumption and optimizes timing performance, while ensuring the accuracy of software-based radar in identifying interference. Board-level verification shows that it can accurately identify the characteristics and types of various civilian electromagnetic interferences without significant loss of accuracy.

[0032] IV. Hardware Implementation Parameters and Performance Indicators of the Architecture

[0033] This architecture is implemented based on the Xilinx KCU1500 development board (equipped with the XCKU115-2EFLVB2104 chip), with a main clock frequency of 200MHz. To meet the requirements of software-based intelligent radar interference identification, the Tiny-YOLO convolutional neural network model was engineered and optimized: the model input was changed to 416×416×1 to adapt to the single-channel radar interference feature data processing requirements and reduce data caching. The main body of the model has an 8-layer core structure, each layer containing zero-padding, convolution, batch normalization, and LeakyReLU layers. 2×2 max-pooling layers are added to layers 2, 5, and 8. The network time complexity is 0.6872 GOPs, the space complexity parameter size is 316.1602KB, and the output feature map data size is 29.7070KB. The network structure diagram is shown below. Figure 6 As shown.

[0034] Based on actual board-level verification, the hardware implementation parameters and performance indicators of this architecture are as follows:

[0035] 1. Resource consumption:

[0036] BRAM36K resource usage is 67.01%, DSP48E resource usage is 4.29%, LUT resource usage is 7.05%, and FF resource usage is 8.07%. The resource usage of each hardware component does not exceed the resource limit of the FPGA chip, the resource utilization is low, and it fully meets the engineering implementation requirements. The resource usage table is shown in Table 2.

[0037] Table 2 Resource Usage List

[0038] resource Already used Available Percentage / % LUT 46797 663360 7.05 LUTRAM 965 293760 0.33 FF 107078 1326720 8.07 BRAM36K 1447.5 2160 67.01 DSP48E 237 5520 4.29

[0039] 2. Computational performance:

[0040] The computation delay for a single jamming feature sub-image is 93.419ms, and the processing time for 100 416×416 radar jamming feature sub-images is only 1.16773s, with a computation speed of 57.8696 GOPS.

[0041] 3. Power consumption specifications:

[0042] The FPGA has a total power consumption of 5.806W and a computing energy efficiency of 9.9672GOP / s / W, which is far lower than that of the GPU platform, making it suitable for the low-power deployment requirements of software-based radar in outdoor and industrial scenarios.

[0043] 4. System adaptability:

[0044] It can be directly integrated into the intelligent decision-making module of software-defined radar, and seamlessly connect with the radar's signal acquisition, preprocessing, and main control scheduling modules. It supports continuous acquisition, real-time processing, and result feedback of radar interference characteristic data, providing stable and efficient computing power support for interference type classification and anti-interference strategy generation of software-defined radar.

[0045] Beneficial effects

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] 1. Low power consumption and high real-time performance, adaptable to the deployment requirements of software-based radar: This architecture is based on FPGA to accelerate the computation of intelligent interference identification network. The total power consumption is only 5.806W, and the computing speed reaches 57.8696GOPS, which is far superior to the computing performance of CPU and the power consumption of GPU. It can be adapted to the harsh deployment environment of software-based radar in outdoor, industrial and remote area surveying and mapping, and meet the real-time requirements of radar intelligent interference identification.

[0048] 2. High resource utilization and high precision ensure reliable interference identification: The three substructures achieve dual optimization of computing speed and hardware resource utilization. DSP resource usage is only 4.29%, and BRAM resource usage is 67.01%, resulting in low resource utilization and no resource waste. A dedicated bit width truncation method is designed to achieve real-time calculation and accurate truncation of data bit width, effectively reducing error accumulation and ensuring the identification accuracy of software-based radar for civilian electromagnetic interference without significant accuracy loss.

[0049] 3. Modular design, highly compatible with software-defined radar systems: The overall design of this architecture is aligned with the signal processing flow and engineering requirements of software-defined radar. It can be directly integrated into the intelligent decision-making module of software-defined radar, seamlessly connecting with the radar's acquisition, preprocessing, and main control scheduling modules, supporting timing synchronization and real-time status feedback. It also supports online updates of network parameters, flexibly adapting to the intelligent interference identification needs of software-defined radar in multiple scenarios and tasks.

[0050] 4. Strong engineering feasibility and good scalability and portability: This architecture has completed full-process board-level verification. All designs are based on engineering implementation and mass production application requirements. Hardware resource usage meets engineering standards and can be directly applied to the development of software-defined radar products. The architecture adopts a standardized and modular design, which can flexibly adjust the interference identification network model and FPGA calculation parameters according to different needs of software-defined radar, adapting to different types of civilian electromagnetic interference identification tasks, and has good scalability and hardware portability. Attached Figure Description

[0052] To more clearly illustrate the technical solution of the present invention, the following is a brief description of the accompanying drawings:

[0053] Appendix Figure 1 This is the overall structural diagram;

[0054] Appendix Figure 2 This is a block diagram of the host computer's functional structure;

[0055] Appendix Figure 3 This is the main structural diagram;

[0056] Appendix Figure 4 This is a diagram of the data grouping cache substructure;

[0057] Appendix Figure 5 This is a block diagram of the computational merging and pipeline structure;

[0058] Appendix Figure 6 This is a structural diagram of the Tiny-Yolo network;

[0059] Appendix Figure 7 This is a real-time display of the software-based radar interference identification results. Detailed Implementation

[0060] The technical solution of the present invention will be described in detail below with reference to specific embodiments. It should be noted that these embodiments are only used to explain the present invention and do not constitute a limitation on the scope of protection of the present invention. The FPGA acceleration architecture of the present invention can be directly integrated into the intelligent decision-making module of civilian software-defined radar, providing real-time computing power support for civilian electromagnetic interference type identification and interference feature extraction of software-defined radar. The specific implementation process is as follows:

[0061] I. Hardware Platform Setup:

[0062] 1. The Xilinx KCU1500 development board is selected as the FPGA acceleration core, equipped with the XCKU115-2EFLVB2104 chip. This chip has 1451K logic resources, 5520 DSP48E resources, and 75.9Mb BRAM resources, which fully meet the hardware implementation requirements of this architecture.

[0063] 2. Establish a high-speed communication link between the host computer and the FPGA. The two interact with each other through the PCIe interface, and the communication rate is precisely adapted to the transmission requirements of software-based radar interference characteristic data.

[0064] 3. This FPGA acceleration architecture is integrated into the civilian software-based radar signal processing system. It is connected to the radar's signal acquisition board and main control interface board through timing synchronization signals to ensure the timing consistency between the FPGA and each module of the software-based radar signal processing system. The FPGA receives interference characteristic data from the radar acquisition board through a high-speed interface and feeds back the calculation status and interference identification results to the main control interface board in real time.

[0065] II. Adaptation of Intelligent Interference Recognition Network Model

[0066] To address the practical needs of software-based intelligent radar interference identification, the Tiny-YOLO model was engineered to fully adapt to the hardware computing capabilities of FPGAs and the requirements for processing radar interference feature data.

[0067] 1. The model input data volume was changed from 416×416×3 to 416×416×1 to adapt to the processing requirements of software-based radar single-channel interference characteristic data and significantly reduce the data cache size;

[0068] 2. The model hierarchy is simplified, retaining an 8-layer core structure. Each layer includes zero-padding, convolution, BN, and LeakyReLU layers. 2×2 max pooling layers are added to layers 2, 5, and 8 to minimize the amount of FPGA computation while ensuring the accuracy of interference recognition.

[0069] 3. The model parameters are quantized, and the host computer performs pre-calculation of the parameters (such as multiplication and addition terms in the BN layer). The quantized parameters and radar interference feature data are packaged in a unified format for use in FPGA calculations.

[0070] III. FPGA Programming and Configuration

[0071] 1. Based on the VIVADO development platform, write Verilog hardware description language code for the FPGA side to implement the main acceleration structure of double buffering at the beginning and end + serial inter-level and partial parallel inter-level, as well as the hardware logic of three substructures: data grouping and buffering, intra-level cell merging and pipelined computation, and intra-level partial data flow parallelism.

[0072] 2. Write dedicated logic code for bit width truncation to achieve real-time calculation and accurate truncation of interference feature data bit width, while ensuring the accuracy of interference identification and optimizing hardware resource consumption and timing performance;

[0073] 3. Write the completed program to the FPGA chip, configure the clock frequency to 200MHz, complete the initialization configuration of each functional module, set the data cache address, PCIE communication parameters, timing synchronization signals, etc., to ensure efficient collaborative work between the FPGA, the host computer, and the software-based radar signal processing system.

[0074] IV. Actual Operation Process of Software-Based Intelligent Radar Interference Identification

[0075] 1. Data Acquisition and Distribution: The software-defined radar signal acquisition board completes the acquisition and preprocessing of interference signals in complex civilian electromagnetic environments, extracts 416×416 interference feature data, and uploads it to the host computer; the host computer distributes the interference feature data and pre-calculated network parameters into groups of four sub-graphs and distributes them to the FPGA at high speed via the PCIe interface.

[0076] 2. FPGA-based accelerated computation: The FPGA ping-pong stores the received interference feature data packets into the input double-buffer module. Zero padding and grouping of the data are completed through the data grouping buffer substructure. Pipeline computation is performed according to the main structure of serial inter-level and partial parallel intra-level. Intra-level computation efficiency is improved through cell merging and pipelined computation, and partial data stream parallel substructure. After the computation of each level is completed, the bit width truncation method is used to ensure accuracy and optimize resources. Finally, the computation results are ping-pong stored into the output double-buffer module.

[0077] 3. Result Feedback and Analysis: After the output double buffer module is full, the interference identification network calculation results are fed back to the host computer in real time through the PCIE interface. The host computer calculates the interference feature coordinates and type labels through the non-maximum suppression algorithm, realizes the real-time display of radar interference perception data and identification results, and feeds back the identification results to the intelligent decision-making module of the software-based radar, providing core data support for the dynamic adjustment of radar working mode and parameters and the generation of anti-interference strategies.

[0078] 4. Status Feedback and System Collaboration: During the calculation process, the FPGA provides real-time feedback to the software-defined radar main control interface board on status data such as hardware resource utilization, calculation completion flags, and fault information, ensuring timing coordination with various modules of the radar signal processing system. If it is necessary to adjust the interference identification strategy, the network parameters can be updated online through the host computer to achieve flexible adaptation of the algorithm parameters on the FPGA side, meeting the interference identification needs of the software-defined radar in multiple scenarios.

[0079] V. Verification of Implementation Results

[0080] Using electromagnetic interference identification of software-based radar for civilian low-altitude security monitoring as a verification scenario, 100 interference feature sub-images (416×416) actually collected by the radar were selected as the test dataset to comprehensively verify the implementation effect of this architecture. The verification results are as follows: Figure 7 As shown:

[0081] The following table 3 compares the FPGA structure with the RTX2060 and Raspberry Pi platforms in terms of power consumption, computing performance, and chip structure:

[0082] Table 3 Performance Comparison of Different Platforms

[0083] platform Power consumption / W Delay / ms Architecture TX2i 110 20 Tegra X2 (GPU) ZCU104 PS 5.3 13100 Cortex-A53 (CPU) KCU1500 5.806 93.419 KCU1500 (FPGA)

[0084] As shown in the table, FPGAs consume significantly less power than GPUs, with power consumption only 5.2% of that of GPUs; compared to CPUs, FPGAs are also much faster, with speeds only 7% faster. Therefore, implementing convolutional neural networks on FPGAs offers certain advantages, exhibiting low power consumption and high performance compared to the other two platforms.

[0085] Regarding the performance comparison of similar platforms, we found some papers on implementing neural networks on FPGAs, and listed them in Table 4 below.

[0086] Table 4 Comparison of acceleration performance on the same platform

[0087] article algorithm hardware platform clock speed / MHz DSP usage Power consumption / W Computing power / GOPS <![CDATA[Energy efficiency / (GOPS * W -1 )]]> <![CDATA[Dsp efficiency / (GOPS * W -1 )]]> Reference [1] YoLov4-tiny XC7Z020 180 216 / 200 2.860 9.24 3.23 0.0428 Reference [2] YoLov5s XC7Z020 100 197 / 200 2.508 5.83 2.32 0.0296 Reference [3] YoLov1 XC7Z045 200 800 / 900 1.167 18.82 16.13 0.0235 Reference [4] YoLov2-tiny XC7Z045 100 784 / 900 7.500 41.99 5.60 0.0536 Reference [5] YoLov5s KCU116 / 1200 / 1824 12.100 44.90 3.71 0.0374 This article YoLo-tiny KU115 200 237 / 5520 5.806 57.86 9.96 0.2441

[0088] The clock frequency of this architecture is 200MHz, which is relatively high for such a complex FPGA system; the power consumption is 5.806W, which is moderate among all items; the computing power reaches 57.8696 GOPS, which is relatively high. This is mainly due to the fact that the architecture can ensure that the data to be convolved is read out one time for each CLK and that the CLKs are continuous. At the same time, the design time between each layer tends to be consistent, and a maximum of 8 subgraphs can be processed at the same time; the energy efficiency reaches 9.96 GOPS / W, which is relatively high; the DSP resource efficiency can reach 6 times that of other articles. This is because this FPGA architecture only uses 9 times the parallelism of DSP resources per layer. The DSP IP core is in continuous use from the start of the system, thus increasing the energy efficiency of DSP usage.

[0089] The FPGA acceleration architecture of this invention provides an efficient and reliable technical solution for the engineering application of convolutional neural networks in the field of software-based radar intelligent interference identification. It effectively solves the pain points of existing hardware acceleration solutions, significantly improves the intelligent interference identification capability and anti-interference decision-making efficiency of software-based radar, and can be widely used in civilian software-based radar perception and detection scenarios such as low-altitude security monitoring, UAV detection, civilian spectrum monitoring, topographic mapping, and meteorological detection. It has extremely high engineering application value.

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Claims

1. An FPGA-accelerated architecture for intelligent interference identification networks in software-defined radar, characterized in that, Adopting an overall design of heterogeneous collaborative processing between the host computer and FPGA, it consists of three parts: the overall collaborative processing architecture, the core acceleration structure on the FPGA side, and the precision guarantee and resource optimization method. The FPGA builds a dedicated processing architecture for the PL side based on the Xilinx KU115 chip to complete the full-process parallel computing of the Tiny-YOLO convolutional neural network for adapting to the software-defined radar, providing low-power, high-real-time, and high-precision hardware computing power support for the intelligent interference recognition of the software-defined radar.

2. The FPGA-accelerated architecture for intelligent interference identification networks for software-defined radar according to claim 1, characterized in that, The overall collaborative processing architecture realizes the high-speed data interaction between the host computer and FPGA through the PCIE interface, and the specific implementation is as follows: S1: The host computer sets four major functional modules: data reading, data interaction, calculation parsing, and display output, which are responsible for the management of interference feature data of the software-defined radar, the visualization of the parsing of recognition results, and the feedback of anti-interference core data to the radar intelligent decision-making system. S2: The FPGA supports the timing synchronization with the software-defined radar system, and real-time feedbacks the hardware resource occupancy rate, calculation completion status, and fault information to ensure the collaborative work with each module of the radar.

3. The FPGA-accelerated architecture for intelligent interference identification networks for software-defined radar according to claim 1, characterized in that, The core acceleration structure on the FPGA side is a combined design of three sub-structures supporting the main acceleration structure, and the specific details are as follows: S1: The main acceleration structure is a network with double buffers at both ends, serial between levels and partial parallel within levels, consisting of an input double buffer module, a Tiny-YOLO interference recognition network calculation module, and an output double buffer module. Through the ping-pong buffer mechanism, it realizes the continuous input of interference feature data and the real-time output of calculation results, avoiding frequent data transfer between levels. S2: Supporting three sub-structures of data grouping cache, unit merging and pipelined calculation within levels, and partial data stream parallelism within levels, the main structure and sub-structures cooperate to achieve efficient parallel processing of interference feature data, and can process up to 8 sub-graphs simultaneously.

4. The FPGA-accelerated architecture for intelligent interference identification networks for software-defined radar according to claim 3, characterized in that, The specific implementation of the three sub-structures is as follows: S1: The data grouping cache sub-structure realizes an integrated design of zero-padding and grouping cache. The multi-channel interference feature data is decimated by 3 times by rows and stored in 3 groups of RAM. Each group of RAM stores 8 columns of data at the same depth. The read address logic is controlled by a counter loop to ensure that 3×3 data to be convolved is read out every clock cycle and continuously output between clocks. S2: The unit merging and pipelined calculation sub-structure within levels divides the convolutional layer, BN layer, LeakyReLU activation layer, and max pooling layer into the same calculation unit and adopts a parallel pipelined structure to achieve integrated calculation. S3: The partial data stream parallelism sub-structure within levels sets different parallel degrees according to the calculation amount differences of different network levels. The parallel degrees of the 4th and 7th layers are set to 2, and the parallel degrees of the 5th and 8th layers are set to 4, so that the processing times of all network levels except the first and last levels are kept consistent.

5. The FPGA-accelerated architecture for intelligent interference identification networks for software-defined radar according to claim 4, characterized in that, The integrated calculation of the unit merging and pipelined calculation sub-structure within levels is realized as follows: S1: The multiplication term and addition term of the BN layer are pre-calculated by the host computer, and the FPGA only performs the multiplication and addition operations. S2: The LeakyReLU layer realizes low-complexity calculation through multiplication optimization, and the max pooling layer completes the extraction of the maximum value of the 2×2 matrix through a comparator. S3: Each clock cycle completes the convolution multiplication and addition operation of 3×3 interference feature data, and the multi-channel convolution results are accumulated over several clock cycles of each channel.

6. The FPGA-accelerated architecture for intelligent interference identification networks for software-defined radar according to claim 1, characterized in that, The accuracy guarantee and resource optimization method is a bit-width truncation method, and the specific implementation steps are as follows: S1: After receiving interference characteristic data and network parameters, the FPGA calculates the minimum number of sign bits for each level of RAM data and records the sharing exponent in real time. At the same time, it calculates the bit width occupied by each level of coefficients and accurately calculates the maximum bit width of the output data of each level of computing unit. S2: After the computation of each layer of the neural network is completed, 18 bits are truncated from the maximum bit width of the data as the output of this layer and sent to the next level of RAM for storage. S3: By passing the shared exponent across levels, invalid truncation in scenarios with large bit width and small data is avoided, and the accumulation of errors in step-by-step calculations is reduced.

7. The FPGA-accelerated architecture for intelligent interference identification networks for software-defined radar according to any one of claims 1-6, characterized in that, The model adaptation and engineering implementation requirements for the architecture are as follows: S1: The Tiny-YOLO convolutional neural network adapted for software-defined radar has an 8-layer core structure. The input is a single-channel interference feature data of 416×416×1. Each layer includes zero-padding, convolution, BN, and LeakyReLU layers. The 2nd, 5th, and 8th layers have an additional 2×2 max pooling layer. S2: The architecture is based on the Xilinx KCU1500 development board with a clock frequency of 200MHz. It can be directly integrated into the intelligent decision-making module of the software-defined radar and seamlessly connected with the radar's signal acquisition board, preprocessing module, and main control scheduling module. S3: Supports online updates of network parameters, adapting to civilian software-based radar application scenarios such as low-altitude security monitoring, drone detection, civilian spectrum monitoring, and terrain mapping.

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