Timeout fault-tolerant method, system and medium for phase-based series configuration of PCIe based on FPGA

Abstract

This invention provides a timeout-tolerant fault-tolerance method for phased serial configuration of PCIe based on FPGA. First, after acquiring the system power-on completion signal, a timeout counter is started and the status monitoring of the PCIe LTSSM is initiated. Then, the link timeout flag signal and the latched LTSSM status value are received, and user-pre-configured hardware parameters are loaded. Based on the above information, a configuration control command is generated through preset decision logic analysis. Subsequently, according to the configuration control command, rollback retry, degraded bitstream switching, or termination of configuration operations are executed, ultimately achieving automatic fault-tolerance processing when PCIe link establishment fails. This invention effectively avoids blind loading of the second-stage bitstream when PCIe link establishment fails through closed-loop control of the timeout counter and LTSSM status awareness, as well as multi-mode decision-making and adaptive degradation mechanisms, thereby improving system reliability and self-healing capabilities.

Description

Technical Field

[0001] This invention relates to the field of FPGA configuration and PCIe interface technology, and in particular to a timeout fault-tolerant method, system and medium for FPGA-based phased serial configuration of PCIe. Background Technology

[0002] The PCIe (Peripheral Component Interconnect Express) specification requires devices to complete link training and host enumeration within 120ms after the power signal stabilizes. As FPGA chip capacity continues to increase, the full bitstream loading time often exceeds the time window required by the PCIe specification. Therefore, a staged serial configuration scheme for PCIe using FPGAs has become the mainstream solution. This scheme divides the FPGA bitstream into a first-stage minimum PCIe bitstream and a second-stage user logic bitstream, loading them sequentially to ensure that the PCIe link can be established within the specified time.

[0003] However, in existing technologies, the link retraining mechanism of the PCIe specification can only solve the parameter renegotiation problem after the link is successfully established. It is only applicable to parameter renegotiation after the link has successfully entered the L0 working state. It cannot cover the problems of premature assertion of the PCIe reset signal and start-up jitter of 100MHz differential reference clock in the FPGA staged serial configuration PCIe scenario, which leads to the failure of the first link establishment after the first stage loading is completed. Traditional FPGA staged serial configuration PCIe solutions do not have configuration-level automatic backoff retry and adaptive degradation mechanisms. After the link establishment fails, they cannot heal themselves and can only rely on the whole machine reset, resulting in poor startup reliability. This approach fails to meet the requirements of high-reliability scenarios. Traditional FPGA-based phased serial PCIe configuration schemes employ a continuous streaming read mechanism, where the first and second stage bit streams are packaged back-to-back and stored in Flash without physical separation or state awareness. Even if the first stage connection fails, Flash will still automatically read and load the second stage user logic, resulting in continuous writing to the FPGA configuration RAM, generating invalid dynamic power consumption and wasting hardware resources. At the same time, PCIe hard cores that fail to establish a connection cannot implement the second stage user logic, which may lead to problems such as internal state machine anomalies, cross-clock domain metastability, and bus access chaos.

[0004] Therefore, there is an urgent need for a timeout fault-tolerant method that can automatically detect, roll back and retry, and adaptively degrade when link establishment failure occurs during the phased serial configuration of PCIe on an FPGA. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a timeout fault-tolerant method for FPGA-based phased serial configuration of PCIe, which can automatically interrupt subsequent bit stream loading when PCIe link establishment fails through closed-loop control with timeout counter and LTSSM state awareness, and realize rollback retry and adaptive degradation according to multi-mode decision logic, thereby improving system reliability and self-healing capability.

[0006] The first aspect of this invention provides a timeout fault-tolerant method for FPGA-based staged serial configuration of PCIe, comprising: Obtain the system power-on completion signal; In response to the signal, a timeout counter is started, and status monitoring of the PCIe LTSSM is enabled; Receive the link timeout flag signal and the latched LTSSM status value generated during the monitoring process; Load user-configured hardware parameters; Based on the link timeout flag signal, the latched LTSSM status value, and the hardware parameters, a configuration control instruction is generated through analysis using a preset decision logic. The configuration control instruction is one of a rollback retry instruction, a degraded bitstream switching instruction, or a termination configuration instruction. According to the configuration control instructions, perform the corresponding operation in the configuration, such as rollback retry, downgrade bitstream switching, or termination.

[0007] In this solution, the steps of starting the timeout counter and initiating status monitoring of the LTSSM include: After the system power is stable and the reference clock is locked, the FPGA configuration controller loads the first-stage configuration bitstream from the standard initial address of the non-volatile memory. The first-stage configuration bitstream contains a minimal configuration of the PCIe hard core, core clock, and reset logic. The timeout counter is started while loading the first-stage configuration bitstream; After detecting the signal that the first stage configuration bitstream loading is complete, monitoring of the PCIe LTSSM status register begins; When the count value of the timeout counter reaches its preset threshold, the current value of the LTSSM status register is obtained; If the current value indicates that the PCIe link is in L0 working state, the link is determined to be successfully established, and the subsequent configuration process continues. The link timeout flag is cleared and the timeout counter is turned off. If the current value indicates that the PCIe link is not in L0 working state, the link establishment is determined to have failed, the link timeout flag is set, the current value is latched, and the subsequent bit stream loading operation is interrupted by disabling the interface of the non-volatile memory.

[0008] In this scheme, the step of generating configuration control commands by analyzing the link timeout flag signal, the latched LTSSM status value, and the hardware parameters through preset decision logic includes: Load user-preconfigured hardware parameters, including basic retry threshold, degradation enable signal, maximum degradation level, and priority mode encoding; Based on the priority mode encoding, the currently effective working mode is determined, including performance priority mode, availability priority mode, or adaptive mode; In performance-priority mode, the effective retry threshold is set to twice the base retry threshold; it is determined whether the current cumulative number of retries is less than the effective retry threshold; if so, the rollback retry instruction is generated; if not, it is further determined whether the degradation enable signal is valid and whether the current degradation level is less than the maximum degradation level; if so, the degradation bitstream switching instruction is generated, otherwise the termination configuration instruction is generated. In availability-first mode, the effective retry threshold is set to 1; it is determined whether the current cumulative number of retries is less than the effective retry threshold; if yes, the fallback retry instruction is generated; if no, it is further determined whether the degradation enable signal is valid and whether the current degradation level is less than the maximum degradation level; if yes, the degradation bitstream switching instruction is generated, otherwise the termination configuration instruction is generated. In adaptive mode, the effective retry threshold is dynamically determined based on the latched LTSSM status value. If the status value is in the detection or polling state, the basic retry threshold is used as the effective retry threshold. If the status value is in the configuration or recovery state, the effective retry threshold is set to 1. Subsequently, a corresponding configuration control instruction is generated based on the comparison result between the effective retry threshold and the current cumulative number of retries.

[0009] In this solution, the steps of performing rollback retry, downgrade bitstream switching, or termination of the corresponding operation in the configuration according to the configuration control command include: When the configuration control instruction is a rollback retry instruction, the retry counter is incremented and a configuration reset signal is triggered to reset the configuration logic of the FPGA. After the reset is completed, the FPGA configuration controller is controlled to reload the first-stage configuration bit stream from the initial address of the non-volatile memory. When the configuration control instruction is a downgrade bitstream switching instruction, the downgrade level counter is incremented and the retry counter is cleared. According to the updated downgrade level, the corresponding backup bitstream storage address is queried from the preset address mapping table, and the FPGA is triggered to reload the configuration bitstream from the backup bitstream storage address through the internal configuration access port. When the configuration control instruction is a terminate configuration instruction, the chip select signal of the non-volatile memory is controlled to invalidate it, thereby stopping the reading of configuration data and placing the FPGA in a state of waiting for external intervention.

[0010] In this scheme, under adaptive mode, the dynamic determination of the effective retry threshold includes: Acquire multiple sets of link quality characteristic data recorded during the historical configuration process. The link quality characteristic data includes the dwell time distribution under each LTSSM state and the link recovery success rate after the corresponding state. The currently latched LTSSM state value and the link quality feature data are used as inputs and processed by a preset threshold calculation function to obtain the effective retry threshold in the current scenario. The threshold calculation function is configured to output an increased effective retry threshold when the input data indicates that the link recovery probability is higher than a preset probability threshold, and to output a decreased effective retry threshold when the input data indicates that the link recovery probability is lower than the preset probability threshold.

[0011] In this solution, when applied to a system containing multiple FPGAs, a cross-device configuration collaboration step is also included: Each FPGA periodically broadcasts its own configuration status information via a predefined communication bus. The configuration status information includes at least the current LTSSM status value, the number of retries, and the degradation level. Each FPGA receives the configuration status information from the other FPGAs; Each FPGA extracts state path features related to the successful establishment of links with other FPGAs from the received configuration state information, as prior knowledge. When any FPGA enters the decision analysis state, it calculates the matching degree between its latched LTSSM state value and the successful state path in the prior knowledge. If the calculated matching degree is higher than the preset matching threshold, then any FPGA adopts the same working mode and decision parameters as the FPGA that provides the prior knowledge to generate local configuration control instructions. If the calculated matching degree is lower than the preset matching threshold, then any FPGA will independently generate configuration control instructions in an adaptive mode.

[0012] This solution also includes power consumption optimization steps: Record the characteristic information of each configuration failure event, including the LTSSM state value latched at the time of failure and the time of failure, to form a configuration failure feature library; Analyzing the configuration failure feature library, when multiple consecutive configuration failure events correspond to the same LTSSM state value, the state value is marked as a high-probability failure state. During the monitoring phase of the subsequent configuration process, when the LTSSM is detected to enter the high-probability fault state and the dwell time in the state exceeds a preset time threshold, the operation of turning off the configuration RAM write enable signal is actively triggered.

[0013] A second aspect of the present invention provides a timeout fault-tolerant method system based on FPGA-based staged serial configuration of PCIe, comprising a memory and a processor. The memory includes a timeout fault-tolerant method program based on FPGA-based staged serial configuration of PCIe. When the processor executes the timeout fault-tolerant method program based on FPGA-based staged serial configuration of PCIe, it performs the following steps: Obtain the system power-on completion signal; In response to the signal, a timeout counter is started, and status monitoring of the PCIe LTSSM is enabled; Receive the link timeout flag signal and the latched LTSSM status value generated during the monitoring process; Load user-configured hardware parameters; Based on the link timeout flag signal, the latched LTSSM status value, and the hardware parameters, a configuration control instruction is generated through analysis using a preset decision logic. The configuration control instruction is one of a rollback retry instruction, a degraded bitstream switching instruction, or a termination configuration instruction. According to the configuration control instructions, perform the corresponding operation in the configuration, such as rollback retry, downgrade bitstream switching, or termination.

[0014] In this solution, the steps of starting the timeout counter and initiating status monitoring of the LTSSM specifically include: After the system power is stable and the reference clock is locked, the FPGA configuration controller loads the first-stage configuration bitstream from the standard initial address of the non-volatile memory. The first-stage configuration bitstream contains a minimal configuration of the PCIe hard core, core clock, and reset logic. The timeout counter is started while loading the first-stage configuration bitstream; After detecting the signal that the first stage configuration bitstream loading is complete, monitoring of the PCIe LTSSM status register begins; When the count value of the timeout counter reaches its preset threshold, the current value of the LTSSM status register is obtained; If the current value indicates that the PCIe link is in L0 working state, the link is determined to be successfully established, and the subsequent configuration process continues. The link timeout flag is cleared and the timeout counter is turned off. If the current value indicates that the PCIe link is not in L0 working state, the link establishment is determined to have failed, the link timeout flag is set, the current value is latched, and the subsequent bit stream loading operation is interrupted by disabling the interface of the non-volatile memory.

[0015] In this solution, the step of generating configuration control commands by analyzing the link timeout flag signal, the latched LTSSM status value, and the hardware parameters through preset decision logic specifically includes: Load user-preconfigured hardware parameters, including basic retry threshold, degradation enable signal, maximum degradation level, and priority mode encoding; Based on the priority mode encoding, the currently effective working mode is determined, including performance priority mode, availability priority mode, or adaptive mode; In performance-priority mode, the effective retry threshold is set to twice the base retry threshold; it is determined whether the current cumulative number of retries is less than the effective retry threshold; if so, the rollback retry instruction is generated; if not, it is further determined whether the degradation enable signal is valid and whether the current degradation level is less than the maximum degradation level; if so, the degradation bitstream switching instruction is generated, otherwise the termination configuration instruction is generated. In availability-first mode, the effective retry threshold is set to 1; it is determined whether the current cumulative number of retries is less than the effective retry threshold; if yes, the fallback retry instruction is generated; if no, it is further determined whether the degradation enable signal is valid and whether the current degradation level is less than the maximum degradation level; if yes, the degradation bitstream switching instruction is generated, otherwise the termination configuration instruction is generated. In adaptive mode, the effective retry threshold is dynamically determined based on the latched LTSSM status value. If the status value is in the detection or polling state, the basic retry threshold is used as the effective retry threshold. If the status value is in the configuration or recovery state, the effective retry threshold is set to 1. Subsequently, a corresponding configuration control instruction is generated based on the comparison result between the effective retry threshold and the current cumulative number of retries.

[0016] A third aspect of the present invention provides a computer-readable storage medium comprising a timeout fault-tolerant method program for FPGA-based phased serial configuration of PCIe, wherein when the FPGA-based phased serial configuration of PCIe timeout fault-tolerant method program is executed by a processor, it implements the steps of the timeout fault-tolerant method for FPGA-based phased serial configuration of PCIe as described in any of the preceding claims.

[0017] This invention discloses a timeout-tolerant fault-tolerance method for phased serial configuration of PCIe based on FPGA. First, after acquiring the system power-on completion signal, a timeout counter is started and the status monitoring of the PCIe LTSSM is initiated. Then, the link timeout flag signal and the latched LTSSM status value are received, and user-pre-configured hardware parameters are loaded. Based on the above information, a configuration control command is generated through preset decision logic analysis. Subsequently, according to the configuration control command, rollback retry, degraded bitstream switching, or termination of configuration operations are executed, ultimately achieving automatic fault-tolerance processing when PCIe link establishment fails. This invention, through closed-loop control of the timeout counter and LTSSM status awareness, as well as multi-mode decision-making and adaptive degradation mechanisms, effectively avoids blind loading of the second-stage bitstream when PCIe link establishment fails, improving system reliability and self-healing capabilities. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope.

[0019] Figure 1 The flowchart of the timeout fault-tolerant method for FPGA-based phased serial configuration of PCIe is shown. Figure 2 The flowchart of the timeout fault-tolerant method for FPGA-based phased serial configuration of PCIe is shown. Figure 3 This diagram illustrates the state transition of the timeout fault-tolerant method based on FPGA-based phased serial configuration of PCIe in this invention. Figure 4 The diagram shows a block diagram of the timeout fault-tolerant method system based on FPGA-based phased serial configuration of PCIe according to the present invention; Figure 5 The diagram illustrates the state transitions of the timeout-tolerant fault-tolerant method for FPGA-based phased serial configuration of PCIe. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used in embodiments of this invention shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in a common dictionary shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as being interpreted in an idealized or highly formalized sense, unless expressly defined in this embodiment of the invention.

[0022] The terms "first," "second," and similar words used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "a," "one," or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Likewise, the terms "including" or "comprising" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The terms "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The steps preceding or following the steps in the method of the embodiments of this invention are not necessarily performed precisely in sequence. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0023] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0024] Figure 1 The flowchart of the timeout fault-tolerant method for FPGA-based phased serial configuration of PCIe is shown.

[0025] like Figure 1 As shown, the first aspect of this invention discloses a timeout fault-tolerant method based on FPGA-based phased serial configuration of PCIe, the method comprising: S102, Obtain the system power-on completion signal; S104, in response to the signal, start the timeout counter and enable status monitoring of the PCIe LTSSM; S106, Receive the link timeout flag signal generated during the monitoring process and the latched LTSSM status value; S108, loads user-preconfigured hardware parameters; S110, based on the link timeout flag signal, the latched LTSSM status value and the hardware parameters, analyze through preset decision logic to generate a configuration control instruction, wherein the configuration control instruction is one of a rollback retry instruction, a degraded bitstream switching instruction or a termination configuration instruction. S112, according to the configuration control command, execute the corresponding operation in the configuration, such as rollback retry, downgrade bitstream switching, or termination.

[0026] like Figure 2 and 5As shown, it should be noted that the timeout fault-tolerant method for FPGA-based phased serial PCIe configuration described in this invention is applied to an FPGA-based phased serial PCIe configuration architecture. The FPGA-based phased serial PCIe configuration scheme refers to a configuration architecture where the FPGA bitstream is divided into a first-stage minimum PCIe bitstream and a second-stage user logic bitstream, which are loaded sequentially. In traditional schemes, after the first-stage bitstream is loaded, the PCIe link status is not detected. When the PCIe bitstream connection fails to establish itself, the Flash still blindly and continuously loads the second-stage user logic, resulting in additional power consumption and loading time. Furthermore, the user logic is loaded under conditions of no valid clock, reset, or link status, causing anomalies that cannot be self-healed and require a complete system reset. Specifically, the existing PCIe link retraining mechanism can only solve the parameter renegotiation problem after successful link establishment. It is only applicable to parameter renegotiation after the link has successfully entered the L0 working state. It cannot cover problems such as premature assertion of PCIe reset signal and start-up jitter of 100MHz differential reference clock in FPGA staged serial configuration PCIe scenarios, which leads to the failure of the first link establishment after the first stage loading is completed. Traditional solutions lack configuration-level automatic back-off retry and adaptive degradation mechanisms. After the link establishment fails, it cannot heal itself and can only rely on whole-machine reset, resulting in poor startup reliability and failing to meet the requirements of high reliability scenarios. Traditional solutions adopt a continuous stream reading mechanism, with the first and second stage bit streams packaged back-to-back and stored in Flash without physical separation or state awareness. Even if the first stage link establishment fails, Flash will still automatically read and load the second stage user logic, resulting in continuous writing to FPGA configuration RAM, generating invalid dynamic power consumption and wasting hardware resources. At the same time, the PCIe hard core that failed to establish a link cannot implement the second stage user logic, which may cause problems such as internal state machine abnormalities, cross-clock domain metastability, and bus access chaos. This invention introduces a closed-loop control mechanism combining a timeout counter and LTSSM status monitoring after the first-stage bitstream loading is completed. This enables real-time sensing of the PCIe link establishment status and automatically interrupts subsequent loading processes when connection establishment fails. Fault-tolerant operations such as rollback retry, downgraded bitstream switching, or termination configuration are selected through decision logic, effectively addressing the aforementioned shortcomings of traditional solutions. This solution achieves automatic sensing and fault-tolerant handling of PCIe link establishment failures, avoiding unnecessary dynamic power consumption and abnormal loading, improving system startup reliability and self-healing capabilities, and meeting the requirements of high-reliability scenarios.

[0027] According to an embodiment of the present invention, the step of starting the timeout counter and initiating status monitoring of the LTSSM specifically includes: After the system power is stable and the reference clock is locked, the FPGA configuration controller loads the first-stage configuration bitstream from the standard initial address of the non-volatile memory. The first-stage configuration bitstream contains a minimal configuration of the PCIe hard core, core clock, and reset logic. The timeout counter is started while loading the first-stage configuration bitstream; After detecting the signal that the first stage configuration bitstream loading is complete, monitoring of the PCIe LTSSM status register begins; When the count value of the timeout counter reaches its preset threshold, the current value of the LTSSM status register is obtained; If the current value indicates that the PCIe link is in L0 working state, the link is determined to be successfully established, and the subsequent configuration process continues. The link timeout flag is cleared and the timeout counter is turned off. If the current value indicates that the PCIe link is not in L0 working state, the link establishment is determined to have failed, the link timeout flag is set, the current value is latched, and the subsequent bit stream loading operation is interrupted by disabling the interface of the non-volatile memory.

[0028] It should be noted that in this embodiment, the first-stage configuration bitstream in the FPGA-based phased serial PCIe configuration scheme is a minimal configuration containing only the PCIe hard core, core clock, and reset logic. Its purpose is to complete the PCIe link initialization as quickly as possible, meeting the PCIe specification's requirement to complete link training and host enumeration within 120ms. After the system powers on, once the power supply is stable and the reference clock is locked, the FPGA configuration controller loads the first-stage configuration bitstream from the standard initial address of the Flash (non-volatile memory) and simultaneously starts a timeout counter. The default threshold can be set to 100ms (with a 20ms redundancy). It should be pointed out that in practical applications, the initial link establishment failure after the first stage loading is often not due to defects in the bitstream itself, but rather to physical layer timing issues such as premature assertion of the PCIe reset signal or jitter at the start of the 100MHz differential reference clock. These issues often resolve successfully after retries. However, the existing PCIe link retraining mechanism only applies to parameter renegotiation after the link has successfully entered the L0 working state, and cannot cover scenarios where the initial link establishment fails. After the first-stage configuration is confirmed by the DONE signal going high, the LTSSM status register is monitored. When the timeout counter reaches a threshold, a two-branch logic is executed: if the LTSSM is stably in the L0 state, the PCIe link establishment is successful, and the subsequent second-stage user logic loading can continue; if the LTSSM has not entered the L0 state, the link establishment has failed. In this case, the link timeout flag is set, the current LTSSM status value is latched, and FCS_B (Flash chip select signal, active low) is pulled high to disable Flash reading, forcibly interrupting the second-stage loading and disabling configuration RAM writing, thus avoiding blindly loading user logic in an invalid link state. This scheme enables real-time perception and rapid response to the PCIe link status, timely interruption of subsequent loading in case of link establishment failure, effectively avoiding resource waste and abnormal loading, and providing triggering conditions for subsequent rollback retries and adaptive degradation.

[0029] According to an embodiment of the present invention, the step of generating configuration control instructions by analyzing the link timeout flag signal, the latched LTSSM status value, and the hardware parameters through a preset decision logic specifically includes: Load user-preconfigured hardware parameters, including basic retry threshold, degradation enable signal, maximum degradation level, and priority mode encoding; Based on the priority mode encoding, the currently effective working mode is determined, including performance priority mode, availability priority mode, or adaptive mode; In performance-priority mode, the effective retry threshold is set to twice the base retry threshold; it is determined whether the current cumulative number of retries is less than the effective retry threshold; if so, the rollback retry instruction is generated; if not, it is further determined whether the degradation enable signal is valid and whether the current degradation level is less than the maximum degradation level; if so, the degradation bitstream switching instruction is generated, otherwise the termination configuration instruction is generated. In availability-first mode, the effective retry threshold is set to 1; it is determined whether the current cumulative number of retries is less than the effective retry threshold; if yes, the fallback retry instruction is generated; if no, it is further determined whether the degradation enable signal is valid and whether the current degradation level is less than the maximum degradation level; if yes, the degradation bitstream switching instruction is generated, otherwise the termination configuration instruction is generated. In adaptive mode, the effective retry threshold is dynamically determined based on the latched LTSSM status value. If the status value is in the detection or polling state, the basic retry threshold is used as the effective retry threshold. If the status value is in the configuration or recovery state, the effective retry threshold is set to 1. Subsequently, a corresponding configuration control instruction is generated based on the comparison result between the effective retry threshold and the current cumulative number of retries.

[0030] like Figure 3As shown, it should be noted that in this embodiment, after receiving the link timeout flag, the state machine enters the ANALYZE state, loads hardware parameters, and selects the working mode according to the priority mode. The hardware parameters include user-preconfigured parameters such as the basic retry threshold, degradation enable signal, maximum degradation level, and priority mode encoding. The decision logic for the three working modes is as follows: Performance-first mode (code 00) sets the effective retry threshold to twice the basic retry threshold, maximizing retry opportunities and suitable for scenarios with high link performance requirements; Availability-first mode (code 01) sets the effective retry threshold to 1, considering degradation after only one retry, suitable for scenarios with high system availability requirements; Adaptive mode (code 10) intelligently matches the retry strategy based on the latched LTSSM state value—when the LTSSM is in the Detect or Polling state, it indicates that the link has not yet entered the advanced training stage, and the possibility of recovery is relatively high, so the basic retry threshold is used; when the LTSSM is in the Configuration or Recovery state, it indicates that the link has failed in the advanced stage, and recovery is more difficult, so degradation is considered after only one retry. In each mode, when the cumulative number of retries reaches the effective threshold, it is further determined whether the degradation enable signal is valid and whether the current degradation level is less than the maximum degradation level, in order to decide whether to perform a degradation bitstream switch or terminate the configuration. The above solution allows for flexible adjustment of fault tolerance strategies based on different application scenarios and link states, achieving an optimal balance between performance and availability.

[0031] According to an embodiment of the present invention, the step of performing the corresponding operation in the configuration control instruction, such as rollback retry, downgrade bitstream switching, or termination, specifically includes: When the configuration control instruction is a rollback retry instruction, the retry counter is incremented and a configuration reset signal is triggered to reset the configuration logic of the FPGA. After the reset is completed, the FPGA configuration controller is controlled to reload the first-stage configuration bit stream from the initial address of the non-volatile memory. When the configuration control instruction is a downgrade bitstream switching instruction, the downgrade level counter is incremented and the retry counter is cleared. According to the updated downgrade level, the corresponding backup bitstream storage address is queried from the preset address mapping table, and the FPGA is triggered to reload the configuration bitstream from the backup bitstream storage address through the internal configuration access port. When the configuration control instruction is a terminate configuration instruction, the chip select signal of the non-volatile memory is controlled to invalidate it, thereby stopping the reading of configuration data and placing the FPGA in a state of waiting for external intervention.

[0032] It should be noted that in this embodiment, the state machine enters different execution states according to the control instructions output by the decision logic. During rollback retry, the state machine enters the RETRY state, increments the retry counter, triggers the CFG_RESET (configuration reset) signal to reset the FPGA's configuration logic, and after the reset is complete, controls the FPGA configuration controller to reload the first-stage configuration bitstream from the initial Flash address, then enters the WAITDONE state to wait for loading to complete. During degradation bitstream switching, the state machine enters the DOWNGRADE state, increments the degradation level counter and clears the retry counter, selects the corresponding backup bitstream address from the Flash's preset address mapping table, and sends the IPROOG (Internal Reconfiguration Start) instruction through the ICAP (Internal Configuration Access Port) to trigger the FPGA to load the degradation bitstream from the new Flash address. An example of the correspondence between degradation levels and bitstream specifications is: Level 0 corresponds to Gen3x8, Level 1 corresponds to Gen3x4, Level 2 corresponds to Gen2x4, and Level 3 corresponds to Gen1x1. The success rate of link establishment is improved by gradually reducing the PCIe link width and speed. Upon termination of configuration, the state machine enters the ABORT state, pulls FCS_B high to interrupt Flash read, outputs a connection failure signal, latches the error state, and waits for an external reset. It is important to note that in traditional solutions, the first and second stage bit streams are packaged back-to-back and stored in Flash, using a continuous streaming read mechanism without physical separation or state awareness. Even if the first stage connection fails, Flash will still automatically read and load the second stage user logic, leading to continuous writing to the FPGA configuration RAM, resulting in invalid dynamic power consumption and wasted hardware resources. Simultaneously, the PCIe hard core that failed to establish a connection cannot provide a valid clock and reset signal for the second stage user logic, potentially causing serious problems such as internal state machine abnormalities, cross-clock domain metastability, and bus access chaos. This invention, by pulling FCS_B high after a timeout to disable Flash read and prohibit configuration RAM writing, physically cuts off the loading channel of the second stage bit stream, effectively avoiding the aforementioned invalid dynamic power consumption and abnormal loading problems. The above solution enables the selection of the optimal fault tolerance strategy based on different chain establishment failure scenarios, achieving flexible configuration control that allows for interruption, retry, and degradation, thus meeting the requirements of high reliability scenarios.

[0033] According to an embodiment of the present invention, in adaptive mode, the dynamic determination of the effective retry threshold specifically includes: Acquire multiple sets of link quality characteristic data recorded during the historical configuration process. The link quality characteristic data includes the dwell time distribution under each LTSSM state and the link recovery success rate after the corresponding state. The currently latched LTSSM state value and the link quality feature data are used as inputs and processed by a preset threshold calculation function to obtain the effective retry threshold in the current scenario. The threshold calculation function is configured to output an increased effective retry threshold when the input data indicates that the link recovery probability is higher than a preset probability threshold, and to output a decreased effective retry threshold when the input data indicates that the link recovery probability is lower than the preset probability threshold.

[0034] It should be noted that in this embodiment, the dynamic effective retry threshold determination mechanism in adaptive mode further incorporates the analysis of historical configuration data. The system records multiple sets of link quality characteristic data during historical configuration, including the dwell time distribution under each LTSSM state and the link recovery success rate after the corresponding state. When entering decision analysis, the currently latched LTSSM state value and historical link quality characteristic data are used as input and processed through a preset threshold calculation function. This threshold calculation function is configured as follows: when the input data indicates that the link recovery probability corresponding to the current LTSSM state is higher than a preset probability threshold, an increased effective retry threshold is output to encourage more retries to fully utilize the possibility of natural link recovery; when the input data indicates that the link recovery probability is lower than the preset probability threshold, a decreased effective retry threshold is output to avoid wasting time and power in low recovery probability scenarios. Through the above scheme, the decision accuracy in adaptive mode can be further optimized based on historical experience data, making the fault tolerance strategy more intelligent and efficient.

[0035] According to an embodiment of the present invention, when applied to a system containing multiple FPGAs, the cross-device configuration coordination step specifically includes: Each FPGA periodically broadcasts its own configuration status information via a predefined communication bus. The configuration status information includes at least the current LTSSM status value, the number of retries, and the degradation level. Each FPGA receives the configuration status information from the other FPGAs; Each FPGA extracts state path features related to the successful establishment of links with other FPGAs from the received configuration state information, as prior knowledge. When any FPGA enters the decision analysis state, it calculates the matching degree between its latched LTSSM state value and the successful state path in the prior knowledge. If the calculated matching degree is higher than the preset matching threshold, then any FPGA adopts the same working mode and decision parameters as the FPGA that provides the prior knowledge to generate local configuration control instructions. If the calculated matching degree is lower than the preset matching threshold, then any FPGA will independently generate configuration control instructions in an adaptive mode.

[0036] It should be noted that in this embodiment, in a system containing multiple FPGAs, each FPGA periodically broadcasts its own configuration status information, including the current LTSSM status value, retry count, and degradation level, through a predefined communication bus (such as I2C, SPI, or a custom bus). After receiving the configuration status information from other FPGAs, any FPGA extracts the state path features related to successfully establishing a link as prior knowledge. When the FPGA enters the decision analysis state, it calculates the matching degree between its latched LTSSM status value and the successful state path in the prior knowledge. If the matching degree is higher than a preset threshold, it indicates that the current state is similar to the historical path of an FPGA that has successfully established a link, and the same working mode and decision parameters are used for local decision-making to improve the accuracy of the decision. If the matching degree is lower than the preset threshold, it indicates that the current situation is relatively unique, and an adaptive mode is used to independently generate configuration control instructions. Through the above scheme, the collective experience of the multi-FPGA system can be used to accelerate the decision-making process and improve the overall system's link establishment success rate.

[0037] According to an embodiment of the present invention, the power consumption optimization step specifically includes: Record the characteristic information of each configuration failure event, including the LTSSM state value latched at the time of failure and the time of failure, to form a configuration failure feature library; Analyzing the configuration failure feature library, when multiple consecutive configuration failure events correspond to the same LTSSM state value, the state value is marked as a high-probability failure state. During the monitoring phase of the subsequent configuration process, when the LTSSM is detected to enter the high-probability fault state and the dwell time in the state exceeds a preset time threshold, the operation of turning off the configuration RAM write enable signal is actively triggered.

[0038] It should be noted that in this embodiment, the power optimization step achieves intelligent power management by recording and analyzing the characteristic information of configuration failure events. The system records the characteristic information of each configuration failure event, including the LTSSM state value latched at the time of failure and the time of failure, forming a configuration failure feature library. By analyzing the configuration failure feature library, when multiple consecutive configuration failure events correspond to the same LTSSM state value, this state value is marked as a high-probability failure state. In the monitoring phase of the subsequent configuration process, when it is detected that the LTSSM has entered this high-probability failure state and the time spent in this state exceeds a preset time threshold, the operation of turning off the configuration RAM write enable signal is actively triggered, thereby avoiding the continued invalid writing of configuration data in a known high-probability failure state and reducing unnecessary power consumption. Through the above scheme, preventive power optimization can be achieved based on historical failure modes, further improving the system's energy efficiency performance in abnormal scenarios.

[0039] Please see Figure 4 The present invention also provides a timeout fault-tolerant system 4 based on FPGA-based phased serial configuration of PCIe, the system including a memory 401 and a processor 402, the memory including a timeout fault-tolerant method program based on FPGA-based phased serial configuration of PCIe, the timeout fault-tolerant method program based on FPGA-based phased serial configuration of PCIe, when executed by the processor, implements the following steps: Obtain the system power-on completion signal; In response to the signal, a timeout counter is started, and status monitoring of the PCIe LTSSM is enabled; Receive the link timeout flag signal and the latched LTSSM status value generated during the monitoring process; Load user-configured hardware parameters; Based on the link timeout flag signal, the latched LTSSM status value, and the hardware parameters, a configuration control instruction is generated through analysis using a preset decision logic. The configuration control instruction is one of a rollback retry instruction, a degraded bitstream switching instruction, or a termination configuration instruction. According to the configuration control instructions, perform the corresponding operation in the configuration, such as rollback retry, downgrade bitstream switching, or termination.

[0040] It should be noted that, in this embodiment, the timeout fault-tolerant method system based on FPGA-based phased serial PCIe configuration uses a method program stored in memory, which is executed by the processor to achieve automatic detection and fault-tolerant processing of link establishment failure during the FPGA-based phased serial PCIe configuration process. After power-on, the system automatically starts a timeout counter and link monitoring. When a link timeout is detected, it analyzes the current state and pre-configured parameters through preset decision logic and automatically selects fault-tolerant strategies such as rollback retry, degraded bitstream switching, or termination of configuration. This effectively avoids the problem of blindly loading the second-stage bitstream when link establishment fails in traditional solutions, improving the system's reliability and self-healing capability.

[0041] According to an embodiment of the present invention, the step of starting the timeout counter and initiating status monitoring of the LTSSM specifically includes: After the system power is stable and the reference clock is locked, the FPGA configuration controller loads the first-stage configuration bitstream from the standard initial address of the non-volatile memory. The first-stage configuration bitstream contains a minimal configuration of the PCIe hard core, core clock, and reset logic. The timeout counter is started while loading the first-stage configuration bitstream; After detecting the signal that the first stage configuration bitstream loading is complete, monitoring of the PCIe LTSSM status register begins; When the count value of the timeout counter reaches its preset threshold, the current value of the LTSSM status register is obtained; If the current value indicates that the PCIe link is in L0 working state, the link is determined to be successfully established, and the subsequent configuration process continues. The link timeout flag is cleared and the timeout counter is turned off. If the current value indicates that the PCIe link is not in L0 working state, the link establishment is determined to have failed, the link timeout flag is set, the current value is latched, and the subsequent bit stream loading operation is interrupted by disabling the interface of the non-volatile memory.

[0042] It should be noted that, in this embodiment, when the processor in the system executes the steps of starting the timeout counter and monitoring the LTSSM status, it loads the first-stage configuration bitstream from non-volatile memory through the FPGA configuration controller, starts the timeout counter, and monitors the LTSSM status register in real time after configuration is completed. When the timeout counter reaches a preset threshold, it determines whether the link establishment was successful based on the LTSSM status. If it fails, it sets the timeout flag, latches the status value, and interrupts subsequent loading operations. Through the above scheme, the system can achieve real-time monitoring and rapid response to the PCIe link status at the hardware level.

[0043] According to an embodiment of the present invention, the step of generating configuration control instructions by analyzing the link timeout flag signal, the latched LTSSM status value, and the hardware parameters through preset decision logic specifically includes: Load user-preconfigured hardware parameters, including basic retry threshold, degradation enable signal, maximum degradation level, and priority mode encoding; Based on the priority mode encoding, the currently effective working mode is determined, including performance priority mode, availability priority mode, or adaptive mode; In performance-priority mode, the effective retry threshold is set to twice the base retry threshold; it is determined whether the current cumulative number of retries is less than the effective retry threshold; if so, the rollback retry instruction is generated; if not, it is further determined whether the degradation enable signal is valid and whether the current degradation level is less than the maximum degradation level; if so, the degradation bitstream switching instruction is generated, otherwise the termination configuration instruction is generated. In availability-first mode, the effective retry threshold is set to 1; it is determined whether the current cumulative number of retries is less than the effective retry threshold; if yes, the fallback retry instruction is generated; if no, it is further determined whether the degradation enable signal is valid and whether the current degradation level is less than the maximum degradation level; if yes, the degradation bitstream switching instruction is generated, otherwise the termination configuration instruction is generated. In adaptive mode, the effective retry threshold is dynamically determined based on the latched LTSSM status value. If the status value is in the detection or polling state, the basic retry threshold is used as the effective retry threshold. If the status value is in the configuration or recovery state, the effective retry threshold is set to 1. Subsequently, a corresponding configuration control instruction is generated based on the comparison result between the effective retry threshold and the current cumulative number of retries.

[0044] It should be noted that, in this embodiment, when the processor in the system executes the decision logic analysis step, it selects the corresponding working mode according to the user-preconfigured priority mode encoding, and determines the effective retry threshold in performance-first, availability-first, or adaptive modes respectively. It then generates configuration control instructions by combining parameters such as the degradation enable signal and the maximum degradation level. Through the above scheme, the system can flexibly adjust the fault tolerance strategy according to different application scenarios and link states, achieving intelligent configuration control.

[0045] The present invention also provides a computer-readable storage medium storing a computer program thereon, the computer-readable storage medium including a timeout fault-tolerant method program for FPGA-based phased serial configuration of PCIe, the timeout fault-tolerant method program for FPGA-based phased serial configuration of PCIe being executed by a processor to implement the steps of the timeout fault-tolerant method for FPGA-based phased serial configuration of PCIe as described above.

[0046] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A timeout fault-tolerant method based on FPGA-based staged serial configuration of PCIe, characterized in that, Includes the following steps: Obtain the system power-on completion signal; In response to the signal, a timeout counter is started, and status monitoring of the PCIe LTSSM is enabled; Receive the link timeout flag signal and the latched LTSSM status value generated during the monitoring process; Load user-configured hardware parameters; Based on the link timeout flag signal, the latched LTSSM status value, and the hardware parameters, a configuration control instruction is generated through analysis using a preset decision logic. The configuration control instruction is one of a rollback retry instruction, a degraded bitstream switching instruction, or a termination configuration instruction. According to the configuration control instructions, perform the corresponding operation in the configuration, such as rollback retry, downgrade bitstream switching, or termination.

2. The method according to claim 1, characterized in that, The steps of starting the timeout counter and enabling status monitoring of the LTSSM include: After the system power is stable and the reference clock is locked, the FPGA configuration controller loads the first-stage configuration bitstream from the standard initial address of the non-volatile memory. The first-stage configuration bitstream contains a minimal configuration of the PCIe hard core, core clock, and reset logic. The timeout counter is started while loading the first-stage configuration bitstream; After detecting the signal that the first stage configuration bitstream loading is complete, monitoring of the PCIe LTSSM status register begins; When the count value of the timeout counter reaches its preset threshold, the current value of the LTSSM status register is obtained; If the current value indicates that the PCIe link is in L0 working state, the link is determined to be successfully established, and the subsequent configuration process continues. The link timeout flag is cleared and the timeout counter is turned off. If the current value indicates that the PCIe link is not in L0 working state, the link establishment is determined to have failed, the link timeout flag is set, the current value is latched, and the subsequent bit stream loading operation is interrupted by disabling the interface of the non-volatile memory.

3. The method according to claim 1, characterized in that, The step of generating configuration control commands by analyzing the link timeout flag signal, the latched LTSSM status value, and the hardware parameters through preset decision logic includes: Load user-preconfigured hardware parameters, including basic retry threshold, degradation enable signal, maximum degradation level, and priority mode encoding; Based on the priority mode encoding, the currently effective working mode is determined, including performance priority mode, availability priority mode, or adaptive mode; In performance-priority mode, the effective retry threshold is set to twice the base retry threshold; it is determined whether the current cumulative number of retries is less than the effective retry threshold; if so, the rollback retry instruction is generated; if not, it is further determined whether the degradation enable signal is valid and whether the current degradation level is less than the maximum degradation level; if so, the degradation bitstream switching instruction is generated, otherwise the termination configuration instruction is generated. In availability-first mode, the effective retry threshold is set to 1; it is determined whether the current cumulative number of retries is less than the effective retry threshold; if yes, the fallback retry instruction is generated; if no, it is further determined whether the degradation enable signal is valid and whether the current degradation level is less than the maximum degradation level; if yes, the degradation bitstream switching instruction is generated, otherwise the termination configuration instruction is generated. In adaptive mode, the effective retry threshold is dynamically determined based on the latched LTSSM status value. If the status value is in the detection or polling state, the basic retry threshold is used as the effective retry threshold. If the status value is in the configuration or recovery state, the effective retry threshold is set to 1. Subsequently, a corresponding configuration control instruction is generated based on the comparison result between the effective retry threshold and the current cumulative number of retries.

4. The method according to claim 1, characterized in that, The steps of executing the corresponding operation in the configuration according to the configuration control command, such as rollback retry, downgrade bitstream switching, or termination, include: When the configuration control instruction is a rollback retry instruction, the retry counter is incremented and a configuration reset signal is triggered to reset the configuration logic of the FPGA. After the reset is completed, the FPGA configuration controller is controlled to reload the first-stage configuration bit stream from the initial address of the non-volatile memory. When the configuration control instruction is a downgrade bitstream switching instruction, the downgrade level counter is incremented and the retry counter is cleared. According to the updated downgrade level, the corresponding backup bitstream storage address is queried from the preset address mapping table, and the FPGA is triggered to reload the configuration bitstream from the backup bitstream storage address through the internal configuration access port. When the configuration control instruction is a terminate configuration instruction, the chip select signal of the non-volatile memory is controlled to invalidate it, thereby stopping the reading of configuration data and placing the FPGA in a state of waiting for external intervention.

5. The method according to claim 3, characterized in that, In adaptive mode, the dynamic determination of the effective retry threshold includes: Acquire multiple sets of link quality characteristic data recorded during the historical configuration process. The link quality characteristic data includes the dwell time distribution under each LTSSM state and the link recovery success rate after the corresponding state. The currently latched LTSSM state value and the link quality feature data are used as inputs and processed by a preset threshold calculation function to obtain the effective retry threshold in the current scenario. The threshold calculation function is configured to output an increased effective retry threshold when the input data indicates that the link recovery probability is higher than a preset probability threshold, and to output a decreased effective retry threshold when the input data indicates that the link recovery probability is lower than the preset probability threshold.

6. The method according to claim 1, characterized in that, When applied to systems containing multiple FPGAs, it also includes cross-device configuration coordination steps: Each FPGA periodically broadcasts its own configuration status information via a predefined communication bus. The configuration status information includes at least the current LTSSM status value, the number of retries, and the degradation level. Each FPGA receives the configuration status information from the other FPGAs; Each FPGA extracts state path features related to the successful establishment of links with other FPGAs from the received configuration state information, as prior knowledge. When any FPGA enters the decision analysis state, it calculates the matching degree between its latched LTSSM state value and the successful state path in the prior knowledge. If the calculated matching degree is higher than the preset matching threshold, then any FPGA adopts the same working mode and decision parameters as the FPGA that provides the prior knowledge to generate local configuration control instructions. If the calculated matching degree is lower than the preset matching threshold, then any FPGA will independently generate configuration control instructions in an adaptive mode.

7. The method according to claim 1, characterized in that, It also includes power consumption optimization steps: Record the characteristic information of each configuration failure event, including the LTSSM state value latched at the time of failure and the time of failure, to form a configuration failure feature library; Analyzing the configuration failure feature library, when multiple consecutive configuration failure events correspond to the same LTSSM state value, the state value is marked as a high-probability failure state. During the monitoring phase of the subsequent configuration process, when the LTSSM is detected to enter the high-probability fault state and the dwell time in the state exceeds a preset time threshold, the operation of turning off the configuration RAM write enable signal is actively triggered.

8. A timeout-tolerant fault-tolerant system based on FPGA-based staged serial configuration of PCIe, characterized in that, The system includes a memory and a processor. The memory includes a timeout fault-tolerant method program based on FPGA-based phased serial configuration of PCIe. When the processor executes the timeout fault-tolerant method program based on FPGA-based phased serial configuration of PCIe, it performs the following steps: Obtain the system power-on completion signal; In response to the signal, a timeout counter is started, and status monitoring of the PCIe LTSSM is enabled; Receive the link timeout flag signal and the latched LTSSM status value generated during the monitoring process; Load user-configured hardware parameters; Based on the link timeout flag signal, the latched LTSSM status value, and the hardware parameters, a configuration control instruction is generated through analysis using a preset decision logic. The configuration control instruction is one of a rollback retry instruction, a degraded bitstream switching instruction, or a termination configuration instruction. According to the configuration control instructions, perform the corresponding operation in the configuration, such as rollback retry, downgrade bitstream switching, or termination.

9. A timeout-tolerant fault-tolerant system based on FPGA-based phased serial configuration of PCIe as described in claim 8, characterized in that, The steps of starting the timeout counter and enabling status monitoring of the LTSSM specifically include: After the system power is stable and the reference clock is locked, the FPGA configuration controller loads the first-stage configuration bitstream from the standard initial address of the non-volatile memory. The first-stage configuration bitstream contains a minimal configuration of the PCIe hard core, core clock, and reset logic. The timeout counter is started while loading the first-stage configuration bitstream; After detecting the signal that the first stage configuration bitstream loading is complete, monitoring of the PCIe LTSSM status register begins; When the count value of the timeout counter reaches its preset threshold, the current value of the LTSSM status register is obtained; If the current value indicates that the PCIe link is in L0 working state, the link is determined to be successfully established, and the subsequent configuration process continues. The link timeout flag is cleared and the timeout counter is turned off. If the current value indicates that the PCIe link is not in L0 working state, the link establishment is determined to have failed, the link timeout flag is set, the current value is latched, and the subsequent bit stream loading operation is interrupted by disabling the interface of the non-volatile memory.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer-readable storage medium includes a timeout fault-tolerant method program based on FPGA-based phased serial configuration of PCIe. When the timeout fault-tolerant method program based on FPGA-based phased serial configuration of PCIe is executed by a processor, it implements the steps of the timeout fault-tolerant method based on FPGA-based phased serial configuration of PCIe as described in any one of claims 1 to 7.

Images