Chip, method for monitoring chip startup abnormalities, storage medium, and electronic device

Abstract

This document discloses a chip, a method for monitoring chip startup abnormalities, a storage medium, and electronic equipment. [Solution] The chip includes a power management circuit, a processor, and a monitoring circuit, wherein the power management circuit is used to trigger the monitoring circuit to perform a timing operation in response to the power management circuit entering an operational state, the processor is used to trigger the monitoring circuit to stop the execution of the timing operation in response to the processor entering an operational state, and the monitoring circuit is used to determine the numerical relationship between the current timing time length of the timing operation and the preset startup time length, and to determine the startup abnormality monitoring result of the chip based on the numerical relationship. Embodiments of this disclosure make it possible to effectively perform startup abnormality monitoring of the chip.

Description

[Technical Field]

[0001] This disclosure relates to functional safety technologies, particularly chips, methods for monitoring chip startup abnormalities, storage media, and electronic devices. [Background technology]

[0002] Currently, the applications of chips are very broad. For example, in the field of intelligent drives, the applications of intelligent drive chips are extremely wide-ranging.

[0003] Furthermore, the normal startup of a chip is a prerequisite for the chip to function properly. Conversely, if a startup abnormality occurs in the chip, there is a high probability that the chip will not be able to function properly, therefore, startup abnormality monitoring of the chip is necessary. How to implement startup abnormality monitoring of the chip is a matter of interest to those skilled in the art. [Overview of the project] [Problems that the invention aims to solve]

[0004] To solve the above technical problems, this disclosure provides a chip, a method for monitoring chip startup abnormalities, a storage medium, and electronic equipment. [Means for solving the problem]

[0005] A chip according to one embodiment of the present disclosure includes a power management circuit, a processor, and a monitoring circuit. The power management circuit is used to trigger the monitoring circuit and perform timing operations in response to the power management circuit entering an operating state. The processor is used to trigger the monitoring circuit and stop the execution of the timing operation in response to the processor entering an operating state. The monitoring circuit is used to determine the numerical relationship between the current timing time length of the timing operation and the preset startup time length, and to determine the startup abnormality monitoring result of the chip based on the numerical relationship.

[0006] A chip startup abnormality monitoring method according to another embodiment of the embodiments of this disclosure is: The steps include: performing a timing operation in response to the power management circuit within the chip entering an operational state; The steps include stopping the execution of the timing operation in response to the processor in the chip entering an operating state, The steps include determining the numerical relationship between the current timing time length of the aforementioned timing operation and the preset start time length, The process includes the step of determining the startup abnormality monitoring result of the chip based on the numerical relationship.

[0007] A computer-readable storage medium according to a further embodiment of the embodiments of this disclosure stores a computer program, when executed by a processor, for performing the above-described chip startup abnormality monitoring method.

[0008] Electronic devices relating to other embodiments of the present disclosure are Processor and The processor includes a memory for storing executable instructions, The processor is used to read and execute the executable instructions from the memory in order to implement the above-described chip startup abnormality monitoring method.

[0009] According to another embodiment of the present disclosure, a computer program product is provided, and when instructions in the computer program product are executed by a processor, the above-described chip startup abnormality monitoring method is executed. [Effects of the Invention]

[0010] According to the chip, chip startup abnormality monitoring method, storage medium, electronic device, and program product provided in the above embodiments of this disclosure, in the chip provided in the embodiments of this disclosure, the power management circuit can trigger the monitoring circuit to perform a timing operation in response to entering an operating state, and the processor can trigger the monitoring circuit to stop the execution of the timing operation in response to entering an operating state. In the flow of a normal chip startup, when power is supplied to the chip, the power management circuit can start operating immediately, and after the power management circuit has been operating for a certain period of time, the processor can start operating, and the processor triggers the monitoring circuit to stop the execution of the timing operation. Therefore, the monitoring circuit stops timing before the current timing time length of the timing operation reaches the preset startup time length, and accordingly, the current timing time length does not exceed the preset startup time length. Conversely, if a startup anomaly exists in the chip, it is highly likely that the processor will not be able to start operating. Naturally, the processor will also be unable to trigger the monitoring circuit to stop the execution of the timing operation, and the timing state of the monitoring circuit will be maintained for a long time. Consequently, it is highly likely that the current timing time will exceed the preset startup time. Therefore, by referring to the numerical relationship between the current timing time and the preset startup time, it is possible to effectively infer whether the processor can successfully trigger the monitoring circuit to stop the execution of the timing operation, thereby determining the result of the chip startup anomaly monitoring. For example, if the processor can successfully trigger the monitoring circuit to stop the execution of the timing operation, the result of the chip startup anomaly monitoring can be used to characterize that there is no startup anomaly in the chip. If the processor cannot successfully trigger the monitoring circuit to stop the execution of the timing operation, the result of the chip startup anomaly monitoring can be used to characterize that there is a startup anomaly in the chip.

[0011] As will be understood hereinafter, in the embodiments of the present disclosure, through the collaborative operation of the power management circuit, the processor, and the monitoring circuit, it is possible to effectively implement startup anomaly monitoring for the chip. It should be emphasized that the power management circuit, the processor, and the monitoring circuit all belong to the components of the chip. In this way, in the embodiments of the present disclosure, the chip does not need to rely on external circuits to perform startup anomaly monitoring on itself, has high reliability, and also has higher monitoring efficiency.

Brief Description of the Drawings

[0012] [Figure 1] It is a schematic diagram of the structure of a chip provided in some exemplary embodiments of the present disclosure. [Figure 2] It is a schematic diagram of the structure of a chip provided in some other exemplary embodiments of the present disclosure. [Figure 3-1] It is a schematic diagram of the structure of a monitoring circuit in some exemplary embodiments of the present disclosure. [Figure 3-2] It is a schematic diagram of the structure of a monitoring circuit in some other exemplary embodiments of the present disclosure. [Figure 4] It is a schematic diagram of the structure of a monitoring circuit in some further exemplary embodiments of the present disclosure. [Figure 5] It is a schematic diagram of the structure of a chip provided in some further exemplary embodiments of the present disclosure. [Figure 6] It is a schematic diagram of the structure of a monitoring circuit in some other exemplary embodiments of the present disclosure. [Figure 7] It is a flowchart of a method for monitoring startup anomalies of a chip provided in some embodiments of the present disclosure. [Figure 8-1] It is a flowchart of a method for determining the startup anomaly monitoring result of a chip based on numerical relationships in some embodiments of the present disclosure. [Figure 8-2] It is a flowchart of a method for determining the startup anomaly monitoring result of a chip based on numerical relationships and utilizing the startup anomaly monitoring result in some embodiments of the present disclosure. [Figure 8-3]A flowchart of a method for determining a chip startup anomaly monitoring result based on a numerical relationship and using the startup anomaly monitoring result in some other embodiments of the present disclosure. [Figure 9] A flowchart of a method for stopping the execution of a timing operation in some embodiments of the present disclosure. [Figure 10] A flowchart of a chip startup anomaly monitoring method provided in some other embodiments of the present disclosure. [Figure 11] A schematic diagram of the structure of an electronic device provided in some exemplary embodiments of the present disclosure.

Embodiments for Carrying Out the Invention

[0013] To interpret the present disclosure, exemplary embodiments of the present disclosure will be described in detail below with reference to the drawings. Clearly, the described embodiments are only some embodiments of the present disclosure, not all embodiments, and the present disclosure is not limited to the exemplary embodiments.

[0014] Unless otherwise specifically described, the scope of the present disclosure is not limited to the relative arrangements of the members and steps, mathematical formulas, and numerical values described in these embodiments.

[0015] Summary of the Application The startup of a chip can be understood as a series of hardware-level initialization processes from power-on to the chip or reset of the chip until the operating system or application program starts to operate. It involves a very complex flow, such as power-on or reset, clock initialization, memory detection and initialization, hardware self-test, and loading of system settings.

[0016] If a startup anomaly occurs in a chip, it is highly likely that the chip will not be able to function properly. If the chip is used in intelligent drive systems, the vehicle system is also highly likely to malfunction, potentially impacting vehicle safety. Therefore, startup anomaly monitoring is necessary for the chip.

[0017] Exemplary structure Figure 1 is a schematic diagram of the structure of a chip provided in some exemplary embodiments of the present disclosure. As shown in Figure 1, the chip may include a power management circuit 10, a processor 20, and a monitoring circuit 30.

[0018] The power management circuit 10 is used to trigger the monitoring circuit 30 to perform timing operations in response to the power management circuit 10 entering an operating state.

[0019] The processor 20 is used to trigger the monitoring circuit 30 in response to the processor 20 entering an operational state, thereby stopping the execution of the timing operation.

[0020] The monitoring circuit 30 is used to determine the numerical relationship between the current timing time length of the timing operation and the preset startup time length, and to determine the startup abnormality monitoring result of the chip based on the numerical relationship.

[0021] Optionally, the power management circuit 10 may be a component within the chip for managing the power supply. The power management circuit 10 can control and monitor the power supply to maintain a stable and efficient power supply under various workload conditions. The power management circuit 10 may also be called a Power Management Unit (PMU).

[0022] Optionally, the processor 20 may be a component within the chip for executing program instructions and processing data. The processor 20 may include, but is not limited to, a Central Processing Unit (CPU), a Micro Controller Unit (MCU), etc.

[0023] Selectively, the monitoring circuit 30 may be a core component within the chip for monitoring startup abnormalities. The monitoring circuit 30 may be electrically connected to the power management circuit 10 and the processor 20, respectively. The monitoring circuit 30 may have a timing function. The timing function may be either a count-up function or a count-down function. The monitoring circuit 30 may have a preset startup time length set. For example, preliminary experiments can be used to statistically determine the average time required from when power is applied to the chip until the processor 20 starts operating when the chip starts up normally. A new time length can be obtained by increasing a certain margin time based on this average time length, and this new time length can be set as the preset startup time length in the monitoring circuit 30.

[0024] When the power management circuit 10 enters an operating state, the power management circuit 10 can send a trigger signal to the monitoring circuit 30 to trigger the monitoring circuit 30 and have it perform a timing operation, via the electrical connection between the power management circuit 10 and the monitoring circuit 30. When the processor 20 enters an operating state, the processor 20 can send a trigger signal to the monitoring circuit 30 to trigger the monitoring circuit 30 and have it stop performing the timing operation, via the electrical connection between the processor 20 and the monitoring circuit 30. The monitoring circuit 30 can maintain a timing state from the time the monitoring circuit 30 is triggered by the power management circuit 10 to perform a timing operation until the monitoring circuit 30 is triggered by the processor 20 to stop performing the timing operation. In the timing state of the monitoring circuit 30, the monitoring circuit 30 can determine the current timing time length of the timing operation and determine the numerical relationship between the current timing time length and the preset start time length.

[0025] Selectively, the numerical relationship between the current timing time and the preset startup time may be a relative relationship between the current timing time and the preset startup time, or a ratio relationship between the current timing time and the preset startup time. If the numerical relationship between the current timing time and the preset startup time is a relative relationship between the current timing time and the preset startup time, and this relationship specifically means that the current timing time is greater than or equal to the preset startup time (corresponding to the current timing time reaching the preset startup time), the chip startup anomaly monitoring result can be used to characterize the presence of a startup anomaly in the chip. If the numerical relationship between the current timing time and the preset startup time is a ratio between the current timing time and the preset startup time, for example, the ratio of the current timing time to the preset startup time, and the value of this ratio is greater than or equal to a preset ratio such as 1, 1.1, or 1.2 (corresponding to the current timing time reaching the preset startup time), then the chip startup anomaly monitoring result can be used to characterize the presence of a startup anomaly in the chip.

[0026] In the chip provided in the embodiment of this disclosure, the power management circuit 10 can trigger the monitoring circuit 30 to execute a timing operation in response to entering an operating state, and the processor 20 can trigger the monitoring circuit 30 to stop the execution of the timing operation in response to entering an operating state. In the flow of the chip to start up normally, when power is supplied to the chip, the power management circuit 10 can start operating immediately, and after the power management circuit 10 has been operating for a certain period of time, the processor 20 can start operating, and the processor 20 triggers the monitoring circuit 30 to stop the execution of the timing operation. As a result, the monitoring circuit 30 stops timing before the current timing time of the timing operation reaches the preset startup time, and accordingly, the current timing time does not exceed the preset startup time. Conversely, if a startup anomaly exists in the chip, it is highly likely that the processor 20 will not be able to start operating. Consequently, the processor 20 will not be able to trigger the monitoring circuit 30 to stop the execution of the timing operation, and the timing state of the monitoring circuit 30 will be maintained for a long time. Accordingly, it is highly likely that the current timing time will exceed the preset startup time. Therefore, by referring to the numerical relationship between the current timing time and the preset startup time, it is possible to effectively infer whether the processor 20 can successfully trigger the monitoring circuit 30 to stop the execution of the timing operation, and thereby determine the startup anomaly monitoring result for the chip. For example, if the processor 20 can successfully trigger the monitoring circuit 30 to stop the execution of the timing operation, the startup anomaly monitoring result for the chip can be used to characterize that there is no startup anomaly in the chip. If the processor 20 cannot successfully trigger the monitoring circuit 30 to stop the execution of the timing operation, the startup anomaly monitoring result for the chip can be used to characterize that there is a startup anomaly in the chip.

[0027] As will be seen, in the embodiments of this disclosure, the collaborative operation of the power management circuit 10, the processor 20, and the monitoring circuit 30 makes it possible to effectively perform startup abnormality monitoring on the chip. It should be emphasized that the power management circuit 10, the processor 20, and the monitoring circuit 30 are all components of the chip. As a result, in the embodiments of this disclosure, the chip does not need to rely on external circuits to perform startup abnormality monitoring on itself, resulting in high reliability and higher monitoring efficiency.

[0028] In some selectable examples, as shown in Figure 2, the monitoring circuit 30 may include a timer 302 and a monitoring sub-circuit 304.

[0029] The power management circuit 10 is used to trigger the monitoring circuit 30 and perform timing operations in response to the power management circuit 10 entering an operating state. The power management circuit 10 is used to trigger a timer 302 and perform a timing operation in response to the power management circuit 10 entering an operating state.

[0030] The monitoring circuit 30 is used to determine the numerical relationship between the current timing time length of the timing operation and the preset startup time length, and to determine the startup abnormality monitoring result of the chip based on this numerical relationship. Timer 302 is used to determine a numerical relationship between the current timing time and a preset start time of a timing operation, and to send a timeout signal to monitoring subcircuit 304 in response to the numerical relationship characterizing that the current timing time has reached the preset start time.

[0031] The monitoring subcircuit 304 is used to determine the reception status of the timeout signal and to determine the chip startup abnormality monitoring result based on the reception status.

[0032] Selectively, the timer 302 may be a device having a timing function and a timeout notification function. The timer 302 may have a preset start-up time length set. The timer 302 may also be called a start-up alert timer. The power management circuit 10 may be electrically connected to the timer 302.

[0033] Optionally, the monitoring subcircuit 304 may be a core component within the monitoring circuit 30 for obtaining startup abnormality monitoring results. The monitoring subcircuit 304 may be electrically connected to the timer 302.

[0034] When the power management circuit 10 enters an operating state, the power management circuit 10 can send a trigger signal to the timer 302 to trigger the timer 302 and perform a timing operation, due to the electrical connection between the power management circuit 10 and the timer 302. In the timing state of the timer 302, the timer 302 compares the current timing duration of the timing operation with a preset start time duration to determine the numerical relationship between the current timing duration and the preset start time duration. If the numerical relationship is characterized in that the current timing duration has not reached the preset start time duration, the timer 302 can continue to maintain the timing state. If the numerical relationship is characterized in that the current timing duration has reached the preset start time duration, the timer 302 can send a timeout signal to the monitoring sub-circuit 304, and the timer 302 can also exit the timing state (i.e., stop timing).

[0035] In one example, as shown in Figure 2, the timer 302 may be connected to the monitoring subcircuit 304 via the timeout signal transmission line 40 (specifically, it may be an electrical connection). If the numerical relationship is characterized in that the current timing time has not reached the preset start time, the level signal transmitted on the timeout signal transmission line 40 may be a low-level signal. If the numerical relationship is characterized in that the current timing time has reached the preset start time, the level signal transmitted on the timeout signal transmission line 40 may be a high-level signal, and this high-level signal may be the timeout signal that the timer 302 sends to the monitoring circuit 304.

[0036] The monitoring subcircuit 304 can determine the reception status of the timeout signal. The reception status can be used to characterize whether or not the monitoring subcircuit 304 has acquired the timeout signal. The monitoring subcircuit 304 can further determine the startup anomaly monitoring result of the chip based on the reception status. For example, if the reception status is used to characterize that the monitoring subcircuit 304 has acquired the timeout signal, the startup anomaly monitoring result of the chip can be used to characterize that a startup anomaly exists in the chip. If the reception status is used to characterize that the monitoring subcircuit 304 has not acquired the timeout signal, the startup anomaly monitoring result of the chip can be used to characterize that there is no startup anomaly in the chip.

[0037] In the embodiments of this disclosure, the power management circuit 10 can trigger the timer 302 to perform a timing operation in response to entering an operating state, and the timer 302 can send a timeout signal to the monitoring subcircuit 304 in response to the current timing duration of the timing operation reaching a preset startup time duration. If the monitoring subcircuit 304 receives a timeout signal from the timer 302, it indicates that the timing operation of the timer 302 was not triggered on the processor 20 and could not be stopped within the preset startup time duration, that is, the processor 20 could not enter an operating state within a predetermined time window, and there is a high possibility that the processor 20 cannot operate normally, and that there is a high possibility that there is a startup abnormality in the chip. If the monitoring subcircuit 304 does not receive a timeout signal from the timer 302 for a long time, it indicates that the timing operation of the timer 302 was triggered on the processor 20 and could be stopped within the preset startup time duration, that is, the processor 20 entered an operating state within a predetermined time window, and the processor 20 can operate normally, in which case the chip startup is also normal. Therefore, it is possible to effectively determine the startup abnormality monitoring result of the chip based on the reception status of the timeout signal by the monitoring subcircuit 304, which is advantageous in ensuring the accuracy and reliability of the startup abnormality monitoring result.

[0038] In some selectable examples, as shown in Figure 3-1, the monitoring circuit 30 may include at least two timers 302, and the preset start time lengths corresponding to each timer 302 may be the same.

[0039] The monitoring subcircuit 304 is used to determine the startup abnormality monitoring result of the chip based on the reception status. The monitoring subcircuit 304 is used to determine that a startup anomaly exists in response to a reception status characterized by the monitoring subcircuit 304 receiving a timeout signal from one or more timers 302.

[0040] The number of timers 302 included in the monitoring circuit 30 may be N, where N is 2, 3, or an integer greater than 3, and these will not be listed here. The N timers 302 may all be set to the same preset startup time length. For example, the preset startup time length set for the N timers 302 may all be 1 second or 2 seconds. The N timers 302 may be electrically connected to the monitoring subcircuit 304 via N timeout signal transmission lines 40. The N timeout signal transmission lines 40 may correspond one-to-one with the N timers 302.

[0041] Selectively, the monitoring subcircuit 304 can determine the reception status of the timeout signal. If the level signal from one or more of the N timeout signal transmission lines 40 is a high-level signal, it indicates that the monitoring subcircuit 304 has received a timeout signal from one or more timers 302, in which case the chip startup abnormality monitoring result may indicate that a startup abnormality exists.

[0042] Furthermore, there is a possibility that a high-level signal may be generated on the timeout signal transmission line 40 due to electromagnetic interference or the like, and the timer 302 may not have sent a timeout signal to the monitoring circuit 30 by increasing the level of the signal. In view of this, in the embodiment of the present disclosure, the monitoring circuit 30 may include at least two timers 302 corresponding to the same preset startup time length, and only when the monitoring subcircuit 304 receives a timeout signal from one or more timers 302 does the monitoring subcircuit 304 determine that a startup abnormality exists in the chip startup abnormality monitoring result. This is equivalent to introducing a majority rule policy to determine the startup abnormality monitoring result of the chip, which is advantageous in avoiding adverse effects on the determination of the startup abnormality monitoring result due to electromagnetic interference or the like, and thereby is advantageous in guaranteeing the accuracy and reliability of the startup abnormality monitoring result.

[0043] In some selectable examples, as shown in Figure 3-2, the timer 302 can be connected to each monitoring subcircuit 304 via at least two timeout signal transmission lines 40.

[0044] The monitoring subcircuit 304 is used to determine the startup abnormality monitoring result of the chip based on the reception status. The monitoring subcircuit 304 is used to determine that a startup anomaly exists in response to a reception status characterized in that the monitoring subcircuit 304 has acquired a corresponding timeout signal via one or more timeout signal transmission lines 40.

[0045] Selectively, the number of timeout signal transmission lines 40 between timer 302 and monitoring subcircuit 304 may be M. M may be 2, 3, or an integer greater than 3, and these will not be listed here.

[0046] Selectively, the monitoring subcircuit 304 can determine the reception status of the timeout signal. If the level signals from one or more of the M timeout signal transmission lines 40 are high-level signals, the monitoring subcircuit 304 indicates that the timer 302 has received the timeout signals transmitted by one or more of the timeout signal transmission lines 40, and in this case, the chip startup abnormality monitoring result may indicate that a startup abnormality exists.

[0047] Furthermore, there is a possibility that a high-level signal may be generated on the timeout signal transmission line 40 due to electromagnetic interference or the like, and the timer 302 may not have sent a timeout signal to the monitoring circuit 30 by increasing the level of the signal. In view of this, in the embodiment of the present disclosure, M timeout signal transmission lines 40 can be provided between the same timer 302 and the monitoring sub-circuit 304, and only when the monitoring sub-circuit 304 obtains the corresponding timeout signal via one or more timeout signal transmission lines 40 will the monitoring sub-circuit 304 determine that a startup abnormality exists as the result of monitoring the chip's startup abnormality. This is equivalent to introducing a majority-rule policy to determine the result of monitoring the chip's startup abnormality, which is advantageous in avoiding adverse effects on the determination of the startup abnormality monitoring result due to electromagnetic interference or the like, and thereby is advantageous in guaranteeing the accuracy and reliability of the startup abnormality monitoring result.

[0048] In some selectable examples, as shown in Figure 3-1, the monitoring circuit 30 may include at least two timers 302, each timer 302 having a different preset startup time.

[0049] The monitoring subcircuit 304 is used to determine the startup abnormality monitoring result of the chip based on the reception status. The monitoring subcircuit 304 is used to determine that a startup anomaly exists in the chip when the reception status is characterized by the monitoring subcircuit 304 having received a timeout signal from each timer 302, and the duration of the timeout signal corresponding to each timer 302 reaches a preset duration.

[0050] Selectively, the number of timers 302 included in the monitoring circuit 30 may be R. R may be 2, 3, or an integer greater than 3, and these will not be listed here. Each of the R timers 302 may have a preset activation time length set, and the preset activation time lengths set for different timers 302 may be different. For example, the R timers 302 may consist of three timers 302, one of which may have a preset activation time length of 1 second, another may have a preset activation time length of 2 seconds, and yet another may have a preset activation time length of 3 seconds. The R timers 302 may be electrically connected to the monitoring subcircuit 304 via R timeout signal transmission lines 40. The R timeout signal transmission lines 40 may correspond one-to-one with the R timers 302.

[0051] Selectively, the monitoring subcircuit 304 can determine the reception status of the timeout signal. If all level signals from the R timeout signal transmission lines 40 are high-level signals, and the duration of each high-level signal reaches the preset duration, the monitoring subcircuit 304 will indicate that it has acquired the timeout signals from each timer 302, and that the duration of the timeout signal corresponding to each timer 302 has reached the preset duration. In this case, the startup abnormality monitoring result for the chip may indicate the presence of a startup abnormality. Here, the preset duration may be 5 milliseconds, 8 milliseconds, 10 milliseconds, etc., and will not be listed here.

[0052] Furthermore, there is a possibility that a high-level signal may be generated on the timeout signal transmission line 40 due to electromagnetic interference, etc., and the timer 302 may not have sent a timeout signal to the monitoring circuit 30 by increasing the level signal. In addition, high-level signals generated due to electromagnetic interference, etc., often appear instantaneously and do not last for a certain period of time. In view of this, in the embodiments of the present disclosure, the monitoring circuit 30 may include at least two timers 302 corresponding to different preset startup time lengths, and the monitoring subcircuit 304 acquires timeout signals from each timer 302, and only when the duration of the timeout signals corresponding to each timer 302 reaches the preset duration length does the monitoring subcircuit 304 determine that a startup abnormality exists in the chip. This is equivalent to determining the startup abnormality monitoring result of the chip by introducing a majority rule policy and a time length verification mechanism (i.e., verifying whether or not the preset duration length has been reached), and it is possible to avoid adverse effects of instantaneously generated high-level signals due to electromagnetic interference, etc., on the determination of the startup abnormality monitoring result, which is advantageous in ensuring the accuracy and reliability of the startup abnormality monitoring result.

[0053] In some selectable examples, as shown in Figure 4, the monitoring circuit 30 may include a timer 302 and a monitoring sub-circuit 304, as well as a setting sub-circuit 306.

[0054] The setting subcircuit 306 is used to set abnormality reporting setting information in the monitoring subcircuit 304.

[0055] The monitoring subcircuit 304 is used to generate a startup anomaly notification in response to the chip startup anomaly monitoring result indicating the presence of a startup anomaly and the anomaly report setting information instructing the execution of an anomaly report, or the monitoring subcircuit 304 is used to record the chip startup anomaly information in response to the chip startup anomaly monitoring result indicating the presence of a startup anomaly and the anomaly report setting information instructing the avoidance of an anomaly report.

[0056] Selectively, the anomaly reporting setting information can be used to indicate whether or not to perform an anomaly report. For example, the anomaly reporting setting information can be 1, which can be used to instruct the system to perform an anomaly report. Alternatively, the anomaly reporting setting information can be 0, which can be used to instruct the system to avoid performing an anomaly report.

[0057] Selectively, the setting subcircuit 306 may be a circuit capable of configuring other components within the chip. For example, the setting subcircuit 306 can set a preset start time length to timer 302. The setting subcircuit 306 may be electrically connected to monitoring subcircuit 304. The electrical connection between the setting subcircuit 306 and monitoring subcircuit 304 allows the setting subcircuit 306 to set abnormality reporting setting information to monitoring subcircuit 304.

[0058] If the startup abnormality monitoring result for the chip indicates the presence of a startup abnormality, and abnormality reporting setting information is used to instruct the execution of an abnormality report, the monitoring subcircuit 304 can generate a startup abnormality notification. The monitoring subcircuit 304 can also output a startup abnormality notification. For example, if the chip is an intelligent drive chip applied to the intelligent drive field, the vehicle system may include a System Micro Controller Unit 50 as shown in Figure 1, and the monitoring subcircuit 304 can report the startup abnormality notification to the System Micro Controller 50, and the System Micro Controller 50 can take several processing measures on the chip, including, but not limited to, controlling the chip to reset or cutting the power and restarting it.

[0059] If the chip startup anomaly monitoring result indicates the presence of a startup anomaly, and the anomaly report setting information is used to instruct the system to avoid executing the anomaly report, the monitoring subcircuit 304 may not generate a startup anomaly notification, and the monitoring subcircuit 304 may also record the chip startup anomaly information. For example, the monitoring subcircuit 304 may record the chip startup anomaly information using a log format, and the startup anomaly information may include at least the time information of the monitored startup anomaly.

[0060] In the embodiments of this disclosure, the setting subcircuit 306 can set abnormality reporting setting information in the monitoring subcircuit 304. This allows the monitoring subcircuit 304 to determine, based on the abnormality reporting setting information, whether to generate and output an abnormality notification or simply record the abnormality information, if an abnormality occurs in the chip. The generation and output of the abnormality notification provides timely notification to the vehicle system of the abnormality in the chip, enabling the vehicle system to detect the abnormality and take appropriate action. This reduces the likelihood of the vehicle system crashing and improves the stability and reliability of the vehicle system. Recording the abnormality information allows for subsequent review of the abnormality information if necessary.

[0061] In some selectable examples, in response to the power management circuit 10 entering an operational state, the power management circuit 10 is used to trigger the monitoring circuit 30 to generate first random data according to a preset generation policy.

[0062] The processor 20 is used to trigger the monitoring circuit 30 in response to the processor 20 entering an operational state, in order to stop the execution of the timing operation. The processor 20 is used to generate second random data according to a preset generation policy in response to the processor 20 entering an operational state, The monitoring circuit 30 includes stopping the execution of the timing operation in response to the second random data being the same as the first random data.

[0063] Optionally, the preset generation policy may be a policy for generating random data that is pre-set. The preset generation policy can be represented, for example, in polynomial form. In one example, the polynomial can be ax 4 +bx 3 +cx 2 +dx, where a, b, c, and d are pre-set coefficients. The preset generation policy may be pre-set in either the monitoring circuit 10 or the processor 20. Also, the preset numerical value may be pre-set in either the monitoring circuit 10 or the processor 20. The preset numerical value may be set according to the actual situation, and the present disclosure is not limited thereto.

[0064] When the power management circuit 10 enters the operating state, through the electrical connection between the power management circuit 10 and the monitoring circuit 30, the power management circuit 10 can send a trigger signal to the monitoring circuit 30 to trigger the monitoring circuit 30 to generate first random data according to the preset generation policy. For example, triggered by the power management circuit 10, the monitoring circuit 30 can substitute the preset numerical value as the value of x into the polynomial of ax 4 +bx 3 +cx 2 +dx for calculation, and the obtained calculation result value can be used as the first random data.

[0065] Similarly, when the processor 20 enters the operating state, the processor 20 can substitute the preset numerical value as the value of x into the polynomial of ax 4 +bx 3 +cx 2 +dx for calculation, and the obtained calculation result value can be used as the second random data.

[0066] The monitoring circuit 30 can determine whether the second random data is the same as the first random data. If the second random data is the same as the first random data, the monitoring circuit 30 can stop the timing operation. If the second random data is different from the first random data, the monitoring circuit 30 can maintain the timing state.

[0067] In embodiments of this disclosure, the power management circuit 10 can trigger the monitoring circuit 30 to generate first random data according to a preset generation policy in response to the power management circuit 10 entering an operating state, and the processor 20 can generate second random data according to a preset generation policy in response to the processor 20 entering an operating state. Since both the power management circuit 10 and the processor 20 generate data according to a preset generation policy, if the chip starts up normally, the processor 20 can operate normally, and the first random data generated by the power management circuit 10 is theoretically the same as the second random data generated by the processor 20. In view of this, it is possible to determine whether the processor 20 has actually generated second random data, and if second random data has been generated, it is possible to determine whether the second random data is actually the same as the first random data, thereby determining whether the actual situation matches the theoretical situation. If the actual situation matches the theoretical situation, it can be determined that the processor 20 can operate normally, and in this case, the monitoring circuit 30 can stop executing the timing operation in order to avoid the current timing time length reaching the preset startup time length. If the actual situation and the theoretical situation do not match, it can be determined that the processor 20 cannot operate normally, in which case the monitoring circuit 30 can maintain the timing state, and accordingly the current timing length can later reach the preset startup length. Clearly, in the embodiments of this disclosure, the numerical relationship between the current timing length and the preset startup length is closely related to whether or not a startup anomaly exists in the chip, and therefore, it is possible to effectively determine the startup anomaly monitoring result of the chip based on the numerical relationship between the current timing length and the preset startup length.

[0068] In some selectable examples, as shown in Figure 5, the monitoring circuit 30 may include a timer 302 and a linear feedback shift register (LFSR) 308.

[0069] The power management circuit 10 is used to trigger the monitoring circuit 30 to generate first random data according to a preset generation policy in response to the power management circuit 10 entering an operating state. The power management circuit 10 includes being used to trigger a linear feedback shift register 308 so that it generates first random data according to a preset generation policy, in response to the power management circuit 10 entering an operating state.

[0070] The power management circuit 10 is used to trigger the monitoring circuit 30 and perform timing operations in response to the power management circuit 10 entering an operating state. The power management circuit 10 is used to trigger a timer 302 and perform a timing operation in response to the power management circuit 10 entering an operating state.

[0071] The monitoring circuit 30 stops executing the timing operation in response to the second random data being the same as the first random data. The linear feedback shift register 308 is used to trigger a timer 302 to stop the execution of the timing operation in response to the second random data being the same as the first random data.

[0072] Selectively, the linear feedback shift register 308 may be a special type of shift register. The linear feedback shift register 308 may have a pseudo-random number generation function; for example, the linear feedback shift register 308 may generate random data according to a preset generation policy. The linear feedback shift register 308 may have preset numerical values ​​stored in it beforehand. The linear feedback shift register 308 may be electrically connected to the power management circuit 10. The linear feedback shift register 308 may also be electrically connected to the timer 302.

[0073] When the power management circuit 10 enters an operating state, the power management circuit 10 can, through its electrical connection with the linear feedback shift register 308, trigger the linear feedback shift register 308 to send a trigger signal, causing the linear feedback shift register 308 to generate first random data according to a preset generation policy. For example, the linear feedback shift register 308 might use a preset numerical value x as the value of ax. 4 +bx 3 +cx 2 By substituting this into the polynomial +dx and performing the calculation, the first random data can be obtained. The linear feedback shift register 308 can store the first random data.

[0074] When the power management circuit 10 enters an operating state, the power management circuit 10 can also trigger the timer 302 to perform timing operations through an electrical connection between the power management circuit 10 and the timer 302.

[0075] When processor 20 enters an operational state, processor 20 sets a preset value for x and ax 4 +bx 3 +cx 2 By substituting this into the polynomial of +dx and performing the calculation, we can obtain the second random data point.

[0076] The linear feedback shift register 308 can acquire the second random data generated by the processor 20 and determine whether the second random data generated by the processor 20 is the same as the first random data stored in the linear feedback shift register 308. If the second random data is the same as the first random data, the linear feedback shift register 308 can send a trigger signal to the timer 302 via the electrical connection between the linear feedback shift register 308 and the timer 302, thereby triggering the timer 302 and stopping the execution of the timing operation. If the second random data is different from the first random data, the linear feedback shift register 308 does not send a trigger signal to the timer 302, and the timer 302 can maintain the timing state.

[0077] In the embodiments of this disclosure, the pseudo-random number generation function of the linear feedback shift register 308 can be used to efficiently and reliably generate first random data. If the first random data is the same as the second random data generated by the processor 20, the linear feedback shift register 308 can timely trigger the timer 302 to stop executing the timing operation. In this way, through the cooperative operation of the timer 302, the linear feedback shift register 308, and the processor 20, the numerical relationship between the current timing time length and the preset startup time length can be closely related to whether or not a startup anomaly exists in the chip. Therefore, it is possible to effectively determine the startup anomaly monitoring result of the chip based on the numerical relationship between the current timing time length and the preset startup time length.

[0078] In several selectable examples, as shown in Figure 6, the monitoring circuit 30 may include a timer 302, a monitoring sub-circuit 304, a setting sub-circuit 306, and a linear feedback shift register 308. The setting sub-circuit 306 can configure the timer 302, the monitoring sub-circuit 304, the linear feedback shift register 308, etc. For example, the setting sub-circuit 306 can set a preset startup time length in the timer 302. Furthermore, for example, the setting sub-circuit 306 can set abnormality reporting setting information in the monitoring sub-circuit 304. The timer 302 is triggered by the power management circuit 10 to perform a timing operation, and can send a timeout signal to the monitoring sub-circuit 304 when the current timing time length of the timing operation reaches the preset startup time length. The linear feedback shift register 308 can trigger the timer 302 to stop the execution of the timing operation if the first random data is the same as the second random data. The monitoring sub-circuit 304 can determine the startup abnormality monitoring result of the chip based on the reception status of the timeout signal. For example, if both timers 304 in Figure 6 send a timeout signal to the monitoring subcircuit 304, and the duration of the timeout signals corresponding to each of the two timers 304 exceeds the preset duration, the chip startup anomaly monitoring result can be used to characterize the presence of a startup anomaly in the chip.

[0079] Exemplary Method Figure 7 is a flowchart of a chip startup abnormality monitoring method provided in some embodiments of this disclosure. The method shown in Figure 7 is Step 710, which performs a timing operation in response to the power management circuit within the chip entering an operational state, Step 720, in response to the processor in the chip entering an operational state, stops the execution of the timing operation, Step 730 determines the numerical relationship between the current timing time length of the timing operation and the preset start time length, This may include step 740, which determines the result of monitoring for chip startup abnormalities based on numerical relationships.

[0080] In some selectable examples, step 710 may include triggering a timer in the chip to perform a timing operation in response to the power management circuit in the chip entering an operational state.

[0081] As shown in Figure 8-1, step 740 is, Step 810, in response to the numerical relationship characterizing that the current timing length has reached a preset start-up length, sends a timeout signal to a monitoring subcircuit in the chip via the timer. The procedure may include step 820, which determines the startup abnormality monitoring result of the chip based on the reception status of the timeout signal by the monitoring subcircuit.

[0082] In some of the selectable examples, there are at least two timers, and the preset activation time for each timer is the same.

[0083] Step 820 may include determining that a startup anomaly monitoring result for the chip is present, in response to the reception status being characterized by the monitoring subcircuit receiving a timeout signal from one or more timers.

[0084] In some of the selectable examples, the timer is connected to each monitoring subcircuit via at least two timeout signal transmission lines.

[0085] Step 820 may include determining that a startup anomaly is present in response to the reception status being characterized by the monitoring subcircuit having acquired a corresponding timeout signal via one or more timeout signal transmission lines.

[0086] In some of the selectable examples, there are at least two timers, and the preset activation time for each timer is different.

[0087] Step 820 may include determining that a startup anomaly exists in response to the reception status being characterized by the monitoring subcircuit receiving timeout signals from each timer and the duration of the timeout signals corresponding to each timer reaching a preset duration.

[0088] In some of the selectable examples, as shown in Figure 8-2, the methods provided in the embodiments of this disclosure further... The procedure may include step 830, which generates a startup anomaly notification in response to the chip startup anomaly monitoring result indicating the presence of a startup anomaly and the anomaly report setting information instructing the execution of an anomaly report.

[0089] In some of the selectable examples, as shown in Figure 8-3, the methods provided in the embodiments of this disclosure further... The procedure may include step 840, which records the chip startup anomaly information in response to the chip startup anomaly monitoring result indicating the presence of a startup anomaly and the anomaly reporting setting information instructing the avoidance of an anomaly report.

[0090] In some of the selectable examples, as shown in Figure 9, the methods provided in the embodiments of this disclosure further... Step 910 triggers the on-chip monitoring circuit to generate first random data according to a preset generation policy in response to the power management circuit entering an operational state, Step 920, in response to the processor entering an operational state, generates second random data through the processor according to a preset generation policy, Step 930 may include stopping the execution of the timing operation in response that the second random data is the same as the first random data, Here, the combination of step 920 and step 930 can be an optional embodiment of step 720 of the present disclosure.

[0091] In some selectable examples, step 910 may include triggering a linear feedback shift register in the monitoring circuit to generate first random data according to a preset generation policy in response to the power management circuit entering an operational state.

[0092] Step 710 may include triggering a timer in the monitoring circuit to perform a timing operation in response to the power management circuit entering an operational state.

[0093] Step 930 may include triggering a timer via a linear feedback shift register to stop the execution of the timing operation in response to the second random data being the same as the first random data.

[0094] In several selectable examples, as shown in Figure 10, after the chip has started to boot up, when the power management circuit enters an operational state, a timer can be triggered to perform a timing operation. The timer can determine whether the timing operation has timed out (i.e., whether the current timing duration has reached the preset boot duration). Assuming the chip has three timers, if the timing operation times out, the monitoring subcircuit within the chip can determine whether it has received timeout signals from at least two timers. If the monitoring subcircuit has received timeout signals from at least two timers, it can determine, based on the anomaly reporting configuration information, whether it is necessary to report a chip boot anomaly. If it is necessary to report a chip boot anomaly, a boot anomaly notification can be generated and sent to the system microcontroller outside the chip. If it is not necessary to report a chip boot anomaly, the startup anomaly notification can not be generated or sent.

[0095] In summary, by adopting the embodiments of this disclosure, startup anomaly monitoring for the chip can be effectively implemented, and if a startup anomaly exists in the chip, it can be detected and dealt with in a timely manner, thereby minimizing the potential impact of the startup anomaly on the vehicle system and ensuring the stability and reliability of the vehicle system.

[0096] In the methods disclosed herein, the various selectable embodiments, selectable forms, and selectable examples disclosed above can all be flexibly selected and combined as needed to achieve the corresponding functions and effects, and are not listed individually in this disclosure.

[0097] Exemplary electronic device Figure 11 shows a block diagram of an electronic device according to an embodiment of the present disclosure, the electronic device 1100 including one or more processors 1110 and memory 1120.

[0098] The processor 1110 may be a central processing unit (CPU), or it may be another form of processing unit having data processing capability and / or instruction execution capability, and it can control other components in the electronic device 1100 to perform a desired function.

[0099] The memory 1120 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or high-speed cache memory (cache). Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions can be stored in the computer-readable storage media, and the processor 1110 can execute one or more computer program instructions to perform the methods of each embodiment of the present disclosure described above and / or other desired functions.

[0100] In one example, the electronic device 1100 may further include an input device 1130 and an output device 1140, which are connected to each other via a bus system and / or other forms of connection mechanisms (not shown).

[0101] The input device 1130 may further include, for example, a keyboard, a mouse, etc.

[0102] The output device 1140 can output various types of information to the outside, including, for example, a display, a speaker, a printer, and a communication network and remote output devices connected thereto.

[0103] Naturally, for the sake of simplification, Figure 11 shows only some of the components of the electronic device 1100 relevant to this disclosure, omitting components such as buses and input / output interfaces. In addition to these, the electronic device 1100 may further include any other appropriate components depending on the specific application.

[0104] Exemplary computer program products and computer-readable storage media In addition to the methods and apparatus described above, embodiments of the present disclosure may further be computer program products including computer program instructions, which, when executed by a processor, perform steps in the methods of various embodiments of the present disclosure as described in the “Exemplary Methods” portion of this specification.

[0105] Computer program products can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and common procedural programming languages ​​such as the C language or similar programming languages, to create program code for performing the operations of the embodiments of this disclosure. The program code may run entirely on a user computing device, partially on a user computing device, as a standalone software package, partially on a user computing device, partially on a remote computing device, or entirely on a remote computing device or server.

[0106] Furthermore, embodiments of the present disclosure may also be computer-readable storage media in which computer program instructions are stored, and when the computer program instructions are executed by a processor, the processor performs the steps in the methods of various embodiments of the present disclosure as described in the “Exemplary Methods” section of this specification.

[0107] Any combination of one or more readable media can be used as the computer-readable storage medium. The readable media may be a readable signal medium or a readable storage medium. The readable storage medium may include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any combination thereof. More specific examples of readable storage media (a non-exclusive list) include electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.

[0108] The above has described the basic principles of this disclosure with reference to specific examples, but the advantages, superiority, and effects mentioned in this disclosure are merely illustrative and not intended to be limiting, and should not be considered as something that each example of this disclosure must possess. The specific details disclosed above are for illustrative purposes and to facilitate understanding, and are not intended to be limiting, and the above details do not limit this disclosure to being realized using the above specific details.

[0109] A person skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present application. In this way, the present disclosure is intended to encompass such modifications and variations to the extent that they fall within the scope of the claims of the present disclosure and their technical equivalents.

Claims

1. A chip including a power management circuit, a processor, and a monitoring circuit, The power management circuit is used to trigger the monitoring circuit and perform timing operations in response to the power management circuit entering an operating state. The processor is used to trigger the monitoring circuit and stop the execution of the timing operation in response to the processor entering an operating state. The monitoring circuit is used to determine the numerical relationship between the current timing time length of the timing operation and the preset startup time length, and to determine the startup abnormality monitoring result of the chip based on the numerical relationship.

2. The aforementioned monitoring circuit includes a timer and a monitoring sub-circuit. The power management circuit is used to trigger the monitoring circuit and perform timing operations in response to the power management circuit entering an operating state. The power management circuit is used to trigger the timer and perform a timing operation in response to the power management circuit entering an operating state. The monitoring circuit is used to determine the numerical relationship between the current timing time length of the timing operation and the preset startup time length, and to determine the startup abnormality monitoring result of the chip based on the numerical relationship. The timer is used to determine a numerical relationship between the current timing duration of the timing operation and a preset start-up duration, and to transmit a timeout signal to the monitoring subcircuit in response to the numerical relationship characterizing that the current timing duration has reached the preset start-up duration. The chip according to claim 1, wherein the monitoring subcircuit is used to determine the reception state of the timeout signal and to determine the startup abnormality monitoring result of the chip based on the reception state.

3. The monitoring circuit includes at least two timers, and the preset startup time lengths corresponding to each timer are the same. The monitoring subcircuit is used to determine the startup abnormality monitoring result of the chip based on the reception status. The chip according to claim 2, wherein the monitoring subcircuit is used to determine that a startup anomaly monitoring result for the chip is present, in response to the reception state being characterized in that the monitoring subcircuit has received the timeout signal from one or more of the timers.

4. The timers are connected to the monitoring subcircuits via at least two timeout signal transmission lines, The monitoring subcircuit is used to determine the startup abnormality monitoring result of the chip based on the reception status. The chip according to claim 2, wherein the monitoring subcircuit is used to determine that a startup abnormality exists in the startup abnormality monitoring result of the chip, in response to the reception state being characterized by the monitoring subcircuit acquiring the corresponding timeout signal via one or more timeout signal transmission lines.

5. The monitoring circuit includes at least two timers, and the preset startup time lengths corresponding to each timer are different. The monitoring subcircuit is used to determine the startup abnormality monitoring result of the chip based on the reception status. The chip according to claim 2, wherein the monitoring subcircuit is used to determine that a startup abnormality exists in response to the reception state being characterized in that the monitoring subcircuit has acquired the timeout signal from each of the timers and the duration of the timeout signal corresponding to each of the timers has reached a preset duration.

6. The monitoring circuit further includes a setting subcircuit, The aforementioned setting subcircuit is used to set abnormality reporting setting information in the monitoring subcircuit. The chip according to claim 2, wherein the monitoring subcircuit generates a startup abnormality notification in response to the startup abnormality monitoring result of the chip indicating the presence of a startup abnormality and the abnormality report setting information instructing the execution of an abnormality report, or the monitoring subcircuit records startup abnormality information of the chip in response to the startup abnormality monitoring result of the chip indicating the presence of a startup abnormality and the abnormality report setting information instructing the avoidance of an abnormality report.

7. The power management circuit is used to trigger the monitoring circuit to generate first random data according to a preset generation policy in response to the power management circuit entering an operating state. The processor is used to trigger the monitoring circuit and stop the execution of the timing operation in response to the processor entering an operating state. The processor is used to generate second random data in accordance with the preset generation policy in response to the processor entering an operating state, The chip according to claim 1, wherein the monitoring circuit includes stopping the execution of the timing operation in response to the second random data being the same as the first random data.

8. The monitoring circuit includes a timer and a linear feedback shift register. The power management circuit is used to trigger the monitoring circuit to generate first random data according to a preset generation policy in response to the power management circuit entering an operating state. The power management circuit is used to trigger the linear feedback shift register so that it generates first random data according to a preset generation policy in response to the power management circuit entering an operating state. The power management circuit is used to trigger the monitoring circuit and perform timing operations in response to the power management circuit entering an operating state. The power management circuit is used to trigger the timer and perform a timing operation in response to the power management circuit entering an operating state. The monitoring circuit stops the execution of the timing operation in response to the second random data being the same as the first random data. The chip according to claim 7, wherein the linear feedback shift register is used to trigger the timer and stop the execution of the timing operation in response to the second random data being the same as the first random data.

9. The steps include: performing a timing operation in response to the power management circuit within the chip entering an operational state; The steps include stopping the execution of the timing operation in response to the processor in the chip entering an operating state, The steps include determining the numerical relationship between the current timing time length of the aforementioned timing operation and the preset start time length, The step includes determining the startup abnormality monitoring result of the chip based on the numerical relationship, A method for monitoring chip startup abnormalities, which is performed by the chip itself.

10. A computer-readable storage medium storing a computer program for performing the chip startup abnormality monitoring method described in claim 9 when executed by a processor.

11. Processor and The processor includes a memory for storing executable instructions, The processor reads and executes the executable instructions from the memory and is used to realize the chip startup abnormality monitoring method described in claim 9. electronic equipment.

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