Control chip, control system and method

Abstract

A control chip, a control system and a method are disclosed. The control chip is coupled with an external chip and includes an interface control circuit, a first memory, a second memory and a processing circuit. The interface control circuit outputs data to the external chip according to a transmission setting value. The first memory is used to store a performance state and an interface setting value. The second memory is used to store a preset data. The processing circuit dynamically adjusts the transmission setting value according to the performance state, the interface setting value and the preset data, so as to change the transmission efficiency of the interface control circuit.

Description

Technical Field

[0001] This invention relates to a control chip, and more particularly to a control chip for dynamically adjusting the transmission performance of an interface control circuit. Background Technology

[0002] With the advancement of technology, electronic devices are becoming increasingly diverse in type and function. Most electronic devices contain at least one control chip. Due to the limited computing power of the control chip, the performance of its transmission interface is fixed. However, when the transmission interface is in a highly interfering environment, the error rate of the transmitted data will increase. Summary of the Invention

[0003] One embodiment of the present invention provides a control chip coupled to an external chip, and includes an interface control circuit, a first memory, a second memory, and a processing circuit. The interface control circuit outputs data to the external chip according to a transmission setting value. The first memory stores a performance state and an interface setting value. The second memory stores preset data. The processing circuit dynamically adjusts the transmission setting value according to the performance state, the interface setting value, and the preset data to change the transmission efficiency of the interface control circuit.

[0004] The present invention also provides a control system, including a first chip and a second chip. The second chip includes an interface control circuit, a memory, a central processing unit (CPU), and a neural processing circuit. The interface control circuit outputs data to the first chip according to a transmission setting value. The memory stores a performance state and an interface setting value. The CPU enables a trigger signal. When the trigger signal is enabled, the neural processing circuit inputs the performance state and the interface setting value to a neural network model to generate an inference result. The memory stores the inference result. The CPU accesses the inference result in the memory and adjusts the transmission setting value according to the inference result.

[0005] The present invention further provides a control method for dynamically adjusting the transmission efficiency between an interface control circuit and an external chip. The control method of the present invention includes: monitoring a performance state of the interface control circuit; storing the performance state and an interface setting value; processing the performance state and the interface setting value using a neural network model to generate an inferred setting value; and adjusting the transmission efficiency between the interface control circuit and the external chip based on the inferred setting value.

[0006] The control method of the present invention can be implemented via the control chip and control system of the present invention, which are hardware or firmware capable of performing specific functions, or can be implemented by recording program code in a recording medium and combined with specific hardware. When the program code is loaded and executed by an electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes the control chip and control system for implementing the present invention. Attached Figure Description

[0007] Figure 1A This is a schematic diagram of the control system of the present invention.

[0008] Figure 1B This is another schematic diagram of the control system of the present invention.

[0009] Figure 2 This is a schematic diagram of the adjustment circuit of the present invention.

[0010] Figure 3 This is a flowchart illustrating the control method of the present invention.

[0011] Symbol Explanation

[0012] 100A, 100B: Control System

[0013] 110, 120, 130, 140, 150, 200: Chips

[0014] 111, 131, 205: Adjustment circuit

[0015] 112, 132, 133, 260, 270: Interface control circuit

[0016] TS, TS_1, TS_2: Transmission settings

[0017] 210: Processing circuit

[0018] 211: Central Processing Unit

[0019] 212: Neural Processing Circuit

[0020] 220: Monitoring circuit

[0021] 230: Internal connection circuit

[0022] 240, 250: Memory

[0023] 241, 243: Performance Status

[0024] 242, 244: Interface settings

[0025] 251: Preset Data

[0026] IOC_1, IOC_2: Inferred setting values Detailed Implementation

[0027] To make the objectives, features, and advantages of this invention more apparent and understandable, embodiments are provided below in conjunction with the accompanying drawings for detailed description. This specification provides different embodiments to illustrate the technical features of different implementations of the invention. The configuration of the elements in the embodiments is for illustrative purposes only and is not intended to limit the invention. Furthermore, the repetition of some reference numerals in the embodiments is for simplification and does not imply any correlation between different embodiments.

[0028] Figure 1A This is a schematic diagram of the control system of the present invention. As shown, the control system 100A includes chips 110 and 120. The present invention does not limit the types of chips 110 and 120. In one possible embodiment, at least one of chips 110 and 120 is a microcontroller (MCU) or a microprocessor (MPU). In this embodiment, chips 110 and 120 are independent of each other. For chip 110, chip 120 is an external chip. In one possible embodiment, chip 110 is referred to as a control chip.

[0029] In this embodiment, chip 110 includes an adjustment circuit 111 and an interface control circuit 112. The adjustment circuit 111 determines the application field of the interface control circuit 112 based on the current performance status of the interface control circuit 112, and adjusts the transmission setting value TS of the interface control circuit 112 appropriately based on the determination result, so that the interface control circuit 112 provides the best transmission performance.

[0030] For example, when the number of data retransmissions in the interface control circuit 112 exceeds a threshold, it indicates that the interface control circuit 112 is in an application environment with high environmental interference. At this time, the error rate of the data output by the interface control circuit 112 may increase significantly. Therefore, the adjustment circuit 111 may reduce the data transmission rate of the interface control circuit 112. For example, suppose the operating frequency of the interface control circuit 112 is 100MHz, and the preset value of the data transmission rate is 100MHz. In this example, when the number of data retransmissions in the interface control circuit 112 does not exceed a threshold, the data transmission rate of the interface control circuit 112 is 100MHz. However, when the number of data retransmissions in the interface control circuit 112 exceeds a threshold, the adjustment circuit 111 reduces the data transmission rate of the interface control circuit 112 from 100MHz to 50MHz. At this time, although the data transmission rate of the interface control circuit 112 is reduced to 50MHz, the operating frequency of the interface control circuit 112 remains at 100MHz. In another possible embodiment, when the number of data retransmissions by the interface control circuit 112 exceeds a threshold, the adjustment circuit 111 may require the interface control circuit 112 to use a parity check to verify the correctness of the output data. In other embodiments, the adjustment circuit 111 may require the interface control circuit 112 to increase the number of error correction codes (ECCs) to reduce the data error rate.

[0031] However, when the number of data retransmissions in the interface control circuit 112 falls below a critical value, it indicates that the interface control circuit 112 is operating in an application environment with low environmental interference. In this case, the adjustment circuit 111 improves the transmission performance of the interface control circuit 112. For example, the adjustment circuit 111 increases the data transmission rate of the interface control circuit 112 from 50MHz to 100MHz. In other embodiments, the adjustment circuit 111 requires the interface control circuit 112 to reduce the amount of redundant data (e.g., reduce the number of ECCs) or increase the clock frequency of the interface control circuit 112.

[0032] This invention does not limit how the adjustment circuit 111 detects the application field of the interface control circuit 112. In one possible embodiment, the adjustment circuit 111 uses a lookup table (LUT) or a neural network model to determine the application field of the interface control circuit 112. Based on the application field of the interface control circuit 112, the adjustment circuit 111 adjusts the transmission setting value TS of the interface control circuit 112 so that the interface control circuit 112 provides optimal transmission efficiency.

[0033] The interface control circuit 112 outputs data to the chip 120 or receives data from the chip 120 according to the transmission setting value TS. In some embodiments, the chip 110 further includes a control circuit (not shown). In this example, the interface control circuit 112 outputs data from the control circuit to the chip 120 or provides data from the chip 120 to the control circuit. The present invention does not limit the architecture of the interface control circuit 112. In one possible embodiment, the interface control circuit 112 includes at least one of a Universal Asynchronous Transceiver (UART), a Serial Peripheral Interface (SPI), an Internal Integrated Circuit (I2C), an Improved Internal Integrated Circuit (I3C), and a Controller Area Network (CAN).

[0034] In this embodiment, the interface control circuit 112 has an interface 113. Interface 113 is coupled to interface 121 of chip 120. The type of interface 113 is the same as that of interface 121. For example, both interfaces 113 and 121 are serial peripheral interfaces. In other embodiments, the interface control circuit 112 further includes an interface 114. Interfaces 114 and 113 may be coupled to different chips, or to different interfaces of the same chip. In one possible embodiment, interface 114 is coupled to interface 122 of chip 120. In this example, the type of interface 114 may be different from that of interface 113. For example, interface 113 is a serial peripheral interface, and interface 114 is a UART interface.

[0035] Figure 1B This is another schematic diagram of the control system of the present invention. As shown, the control system 100B includes chips 130, 140, and 150. In one possible embodiment, at least one of chips 130, 140, and 150 is a microcontroller or a microprocessor. In this embodiment, chip 130 includes an adjustment circuit 131, interface control circuits 132 and 133. The adjustment circuit 131 determines the application field of the interface control circuits 132 and 133 based on their performance status, and appropriately adjusts the transmission setting values ​​TS_1 and TS_2 of the interface control circuits 132 and 133 according to the determination result. Since the characteristics of the adjustment circuit 131 are similar to those of the adjustment circuit 111, they will not be described in detail.

[0036] Interface control circuit 132 outputs data to chip 140 or receives data from chip 140 according to the transmission setting value TS_1. Interface control circuit 133 outputs data to chip 150 or receives data from chip 150 according to the transmission setting value TS_2. Since the characteristics of interface control circuits 132 and 133 are similar to those of interface control circuit 112, they will not be described in detail.

[0037] Figure 2This is a schematic diagram of the control chip of the present invention. As shown, the control chip 200 includes an adjustment circuit 205 and an interface control circuit 260. The interface control circuit 260 outputs data to an external chip (not shown) according to the transmission setting value TS_1. Since the characteristics of the interface control circuit 260 are similar to... Figure 1A The characteristics of the interface control circuit 112 are not described in detail here.

[0038] The adjustment circuit 205 includes a processing circuit 210, a monitoring circuit 220, and a memory 240. The monitoring circuit 220 monitors the performance status of the interface control circuit 260 to generate a performance status 241. In one possible implementation, the monitoring circuit 220 monitors the interface control circuit 260 for at least one of the following during the current transmission process: throughput (MB / s), number of data retransmissions (times / transaction), number of error bits (bits / transaction), signal strength attenuation (e.g., peak voltage at the receiver), propagation delay, turnaround time, and signal-to-noise ratio.

[0039] This invention does not limit the architecture of the monitoring circuit 220. In one possible embodiment, the monitoring circuit 220 is a processor (such as a CPU). The monitoring circuit 220 executes a monitoring software program to monitor the performance status of the interface control circuit 260. For example, while the interface control circuit 260 is sending data to an external device, the monitoring circuit 220 starts a counter (not shown). When the interface control circuit 260 receives an ACK signal, the monitoring circuit 220 stops the counter. The monitoring circuit 220 calculates a transmission delay time based on the counter's count value. In this example, the monitoring circuit 220 uses the transmission delay time as performance status 241.

[0040] In another possible embodiment, when the interface control circuit 260 sends a request to an external device, the monitoring circuit 220 starts a counter (not shown). After the external device completes a specific action according to the request, the external device generates a response signal to the interface control circuit 260. When the interface control circuit 260 receives the response signal from the external device, the monitoring circuit 220 stops the counter. The monitoring circuit 220 calculates the turnaround time based on the counter's count value. In this example, the monitoring circuit 220 uses the turnaround time as performance status 241.

[0041] In some embodiments, monitoring circuit 220 executes monitoring software to determine the degree of signal strength attenuation between interface control circuit 260 and an external chip. For example, suppose interface control circuit 260 outputs data to an external chip via at least one transmission line. In this example, monitoring circuit 220 executes monitoring software to issue a command requiring interface control circuit 260 to restore the actual voltage level of the transmission line (e.g., 0.8V). Monitoring circuit 220 determines the degree of signal strength attenuation between interface control circuit 260 and the external chip, such as 0.2V, based on the difference between the actual voltage level of the transmission line (e.g., 0.8V) and a preset voltage level (e.g., 1V). In this example, monitoring circuit 220 uses the degree of signal strength attenuation between interface control circuit 260 and the external chip as performance state 241.

[0042] In another embodiment, when the interface control circuit 260 outputs data to an external chip through at least one transmission line, the interface control circuit 260 actively informs the signal-to-noise ratio (SNR) on the transmission line. In some embodiments, the monitoring circuit 220 executes a monitoring software program to issue a command requiring the interface control circuit 260 to inform the SNR on the transmission line. In this example, the monitoring circuit 220 uses the SNR on the transmission line between the interface control circuit 260 and the external chip as performance state 241.

[0043] Memory 240 stores performance state 241. In some embodiments, memory 240 further stores an interface setting value 242. During an initial period, processing circuitry 210 accesses memory 240 to obtain interface setting value 242. Processing circuitry 210 uses interface setting value 242 as transmission setting value TS_1 and provides transmission setting value TS_1 to interface control circuitry 260.

[0044] In one possible embodiment, the interface setting 242 (i.e., the transmission setting TS_1) is related to at least one of the following: the number of error correction codes output by the interface control circuit 260, the error detection method used by the interface control circuit 260, the clock frequency of the interface control circuit 260, the size of the output packet of the interface control circuit 260, the drive voltage of the interface control circuit 260, the capacitance of a decoupling capacitor coupled to the interface control circuit 260, and the termination resistance coupled to the interface control circuit 260.

[0045] The processing circuit 210 dynamically adjusts the transmission setting value TS_1 based on the performance state 241, the interface setting value 242, and a preset data 251 to change the transmission efficiency of the interface control circuit 260. In one possible embodiment, the preset data 251 is a table. The table records multiple preset states and multiple preset setting values. Each preset state corresponds to a preset setting value. The processing circuit 210 determines whether the performance state 241 is the same as a specified state among the multiple preset states. When the performance state 241 is the same as a specified state of the preset data 251, the processing circuit 210 updates the transmission setting value TS_1 according to a specific preset setting value corresponding to the specified state.

[0046] In other embodiments, the adjustment circuit 205 further includes an internal connection circuit 230. The internal connection circuit 230 is coupled to the processing circuit 210, the monitoring circuit 220, the memory 240, and the interface control circuit 260, and is responsible for communication between the processing circuit 210, the monitoring circuit 220, the memory 240, and the interface control circuit 260.

[0047] For example, processing circuitry 210 accesses memory 240 or adjusts the transmission setting TS_1 of interface control circuitry 260 via internal connection circuitry 230. The present invention does not limit the architecture of internal connection circuitry 230. In one possible embodiment, internal connection circuitry 230 includes at least one of an Advanced eXtensible Interface (AXI), an Advanced High-performance Bus (AHB), and an Advanced Peripheral Bus (APB).

[0048] In some embodiments, the adjustment circuit 205 further includes a memory 250. The memory 250 stores preset data 251. The present invention does not limit the types of memories 240 and 250. In one possible embodiment, the memory 240 is a volatile memory, such as RAM. In another possible embodiment, the memory 250 is a non-volatile memory, such as Flash. In some embodiments, the processing circuit 210 may load the preset data 251 from the memory 250 into the memory 240.

[0049] This invention does not limit the architecture of the processing circuit 210. In one possible embodiment, the processing circuit 210 includes a central processing unit (CPU) 211 and a neural processing circuit (NPU) 212. The CPU 211 generates a trigger signal. The NPU 212 receives the trigger signal through an internal connection circuit 230. When the CPU 211 enables the trigger signal, the NPU 212 performs an inference operation. In one possible embodiment, the NPU 212 accesses a memory 250 through the internal connection circuit 230 to read preset data 251. In this example, the preset data 251 is a neural network model. During the inference operation, the NPU 212 accesses a memory 240 through the internal connection circuit 230 to read a performance state 241 and an interface setting value 242. After completing the inference operation, the NPU 212 generates an inference setting value IOC_1.

[0050] In one possible embodiment, the preset data 251 may include a pre-trained model architecture, such as a neural network model. In one possible embodiment, the neural network model includes at least one fully-connected layer. In some embodiments, the preset data 251 further includes multiple model parameters (weights / biases).

[0051] The neural processing circuit 212 inputs the performance state 241 and the interface setting value 242 into preset data 251. The preset data 251 calculates the performance state 241 and the interface setting value 242 to generate an inference setting value IOC_1. In one possible embodiment, the neural processing circuit 212 provides the inference setting value IOC_1 to the interface control circuit 260 through the internal connection circuit 230. In this example, the interface control circuit 260 updates the transmission setting value TS_1 according to the inference setting value IOC_1, and outputs data to an external chip according to the updated transmission setting value TS_1. In another possible embodiment, the neural processing circuit 212 writes the inference setting value IOC_1 into the memory 240 through the internal connection circuit 230. In this example, the central processing unit 211 reads the inference setting value IOC_1 from the memory 240 through the internal connection circuit 230, and then adjusts the transmission setting value TS_1 according to the inference setting value IOC_1.

[0052] In some embodiments, the control chip 200 further includes an interface control circuit 270. The adjustment circuit 205 adjusts the transmission setting value TS_2 of the interface control circuit 270 to adjust the transmission efficiency of the interface control circuit 270. In this example, the monitoring circuit 220 monitors the performance status of the interface control circuit 270 to generate a performance status 243. The performance status 243 may be stored in the memory 240. In this example, the memory 240 further stores an interface setting value 244. During an initial period, the processing circuit 210 accesses the memory 240 to obtain the interface setting value 244. The processing circuit 210 uses the interface setting value 244 as the transmission setting value TS_2 and provides the transmission setting value TS_2 to the interface control circuit 270. The interface control circuit 270 outputs data to an external chip according to the transmission setting value TS_2.

[0053] In one possible embodiment, the processing circuit 210 determines whether the performance state 243 is the same as a specified state among a plurality of preset states recorded in the preset data 251. When the performance state 243 is the same as a specified state in the preset data 251, the processing circuit 210 updates the transmission setting value TS_2 according to a specific preset setting value corresponding to the specified state. In another possible embodiment, when the central processing unit 211 triggers the neural processing circuit 212, the neural processing circuit 212 reads the memories 240 and 250. The neural processing circuit 212 inputs the performance state 243 and the interface setting value 244 into a neural network model (i.e., the preset data 251) to generate an inference setting value IOC_2.

[0054] The neural processing circuit 212 updates the transmission setting value TS_2 of the interface control circuit 270 based on the inference setting value IOC_2. In another possible embodiment, the neural processing circuit 212 writes the inference setting value IOC_2 to the memory 240. In this example, the central processing unit 211 updates the transmission setting value TS_2 based on the inference setting value IOC_2 in the memory 240.

[0055] This invention does not limit the architecture of the neural processing circuit 212. In one possible embodiment, the neural processing circuit 212 includes at least one multiply-add (MAC) operation unit and a nonlinear operation unit. In some embodiments, the nonlinear operation unit includes an activation function, such as a sigmoid function.

[0056] In some embodiments, when a preset event occurs, the central processing unit 211 triggers the neural processing circuit 212. The present invention does not limit the type of preset event. In one possible embodiment, the preset event refers to the count value of a counter (not shown) reaching a target value. In another possible embodiment, the preset event is that performance state 241 or 243 reaches a trigger criterion. Taking performance state 241 as an example, assume that performance state 241 is related to the number of error bits. When the number of error bits between the interface control circuit 260 and the external chip reaches a critical value, it indicates that a preset event has occurred. Therefore, the central processing unit 211 triggers the neural processing circuit 212. The neural processing circuit 212 performs an inference operation based on performance state 241, interface setting value 242, and preset data 251 to generate an inferred setting value IOC_1. The central processing unit 211 or the neural processing circuit 212 updates the transmission setting value TS_1 based on the inferred setting value IOC_1 to adjust the performance state of the interface control circuit 260. In one possible embodiment, the interface control circuit 260 increases the number of error correction codes according to the updated transmission setting value TS_1.

[0057] In other embodiments, the central processing unit 211 executes a monitoring software program to monitor the performance status of the interface control circuit 260. The central processing unit 211 stores the monitoring results as a performance status 241 in memory 240. In this example, the monitoring circuit 220 may be omitted. In some embodiments, the monitoring software program may be stored in memory 240 or 250. In another possible embodiment, the monitoring software program is stored in a preset memory (not shown). This preset memory is independent of memory 240 and 250.

[0058] Figure 3 This is a flowchart illustrating the control method of the present invention. The control method of the present invention dynamically adjusts the transmission efficiency between an interface control circuit and an external chip, and this adjustment can exist through program code. When the program code is loaded and executed by the machine, the machine becomes a device for implementing the adjustment circuit and chip of the present invention.

[0059] First, a neural processing circuit is triggered (step S311). In one possible embodiment, a central processing unit triggers the neural processing circuit when a preset event occurs. The preset event may refer to a counter reaching a target value, or the performance state of an interface control circuit reaching a trigger criterion. In some embodiments, the performance state of the interface control circuit is related to at least one of the following: transmission throughput, number of retransmissions, number of error bits, signal strength attenuation, transmission delay time, turnaround time, and signal-to-noise ratio.

[0060] Next, the neural processing circuit performs an inference operation (step S312). In one possible embodiment, a monitoring circuit monitors the current performance state of an interface control circuit and stores the monitoring results in a first memory. Additionally, the interface settings of the interface control circuit are also stored in the first memory. In some embodiments, the interface settings are related to at least one of the following: the number of error correction codes output by the interface control circuit, the error detection method used by the interface control circuit, the clock frequency of the interface control circuit, the size of the output packet of the interface control circuit, the drive voltage of the interface control circuit, the capacitance of a decoupling capacitor coupled to the interface control circuit, and the value of a terminating resistor coupled to the interface control circuit.

[0061] This invention does not limit the type of the first memory. The first memory may be a volatile memory. In some embodiments, the first memory further stores a neural network model, but this is not intended to limit the invention. In other embodiments, the neural network model is stored in a second memory. The second memory may be a non-volatile memory. In some embodiments, the neural network model in the second memory is loaded into the first memory.

[0062] In this embodiment, when a preset event occurs, the neural processing circuit reads the first and second memories to obtain the performance status of the interface control circuit, the interface settings, and the neural network model. The neural network model processes the performance status and interface settings of the interface control circuit to generate an inference setting. In one possible embodiment, the inference setting may be stored in the first memory.

[0063] Based on the inferred setting value, the transmission efficiency between the interface control circuit and the external chip is adjusted (step S313). In one possible embodiment, the central processing unit or neural processing circuit provides the inferred setting value to the interface control circuit to update an interface setting value of the interface control circuit. The interface control circuit communicates with the external chip based on the updated interface setting value.

[0064] The control method, or a specific form or part thereof, of the present invention may exist in the form of program code. The program code may be stored on physical media, such as floppy disks, optical disks, hard disks, or any other machine-readable (e.g., computer-readable) storage media, or may be a computer program product, not limited to an external form. When the program code is loaded and executed by a machine, such as a computer, that machine becomes a participant in the adjustment circuitry and control chip of the present invention. The program code may also be transmitted via transmission media, such as wires or cables, optical fibers, or any transmission method. When the program code is received, loaded, and executed by a machine, such as a computer, that machine becomes a participant in the adjustment circuitry and control chip of the present invention. When implemented in a general-purpose processing unit, the program code, in conjunction with the processing unit, provides a unique device that operates similarly to an application-specific logic circuit.

[0065] Unless otherwise defined, all terms herein (including technical and scientific terms) are as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, unless expressly stated otherwise, definitions of terms in general dictionaries should be interpreted as consistent with their meaning in the context of their respective technical fields, and not as idealized or overly formal expressions. While terms such as “first” and “second” may be used to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. In the claims, terms such as “first” and “second” are used as designations and are not intended to impose numerical requirements on their contents.

[0066] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods described in the embodiments of the present invention can be implemented in physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A control chip, characterized in that, Coupled to an external chip, and includes: An interface control circuit outputs data to the external chip according to a transmission setting value; A first memory for storing a performance state and an interface setting value; A second memory for storing preset data; and A processing circuit dynamically adjusts the transmission setting value based on the performance status, the interface setting value, and the preset data, in order to change the transmission efficiency of the interface control circuit.

2. The control chip as described in claim 1, characterized in that: The preset data is in the form of a table, which records multiple preset states and multiple preset settings. Each preset state corresponds to one preset setting. When the performance state is equal to a specified state among the plurality of preset states, the processing circuit updates the transmission setting value according to a specific preset setting value corresponding to the specified state.

3. The control chip as described in claim 1, characterized in that: The preset data is a neural network model. The neural network model calculates the performance state and the interface settings to generate an inferred setting. The processing circuit updates the transmission setting value based on the inferred setting value.

4. The control chip as described in claim 3, characterized in that, The processing circuit includes: A neural processing circuit reads the second memory to load the neural network model and reads the first memory to input the performance status and the interface settings into the neural network model.

5. The control chip as described in claim 4, characterized in that, The processing circuit further includes: A central processing unit triggers the neural processing circuit when a preset event occurs. The central processing unit updates the transmission setting value based on the inferred setting value.

6. The control chip as described in claim 5, characterized in that, Including: An internal connection circuit is coupled to the central processing unit, the neural processing circuit, the interface control circuit, and the first and second memories. The first memory is a volatile memory, and the second memory is a non-volatile memory.

7. The control chip as described in claim 6, characterized in that, Including: A monitoring circuit monitors the interface control circuit to generate the performance status.

8. A control method, characterized in that, The control method is used to dynamically adjust the transmission efficiency between an interface control circuit and an external chip, and includes: Monitor the performance status of the interface control circuit; Store the performance status and an interface setting value; A neural network model is used to process the performance state and the interface settings to generate an inferred setting; and Based on this inference, the transmission efficiency between the interface control circuit and the external chip is adjusted.

9. A control system, characterized in that, include: The first chip; as well as A second chip, comprising: A first interface control circuit outputs data to the first chip according to a first transmission setting value; A memory for storing a first performance state and a first interface setting value; A central processing unit, enabling a trigger signal; and A neural processing circuit, when enabled by the trigger signal, inputs the first performance state and the first interface setting value to a neural network model to generate a first inference result. in: The memory stores the first inference result, the central processing unit accesses the first inference result in the memory, and adjusts the first transmission setting value according to the first inference result.

10. The control system as described in claim 9, characterized in that, Including: A second interface control circuit outputs data to a third chip based on a second transmission setting value. in: The neural processing circuit calculates a second performance state and a second interface setting value based on the neural network model to generate a second inference result. The memory stores the second inference result, the central processing unit accesses the second inference result in the memory, and adjusts the second transmission setting value according to the second inference result.

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