Memory access method and device of multi-core particle system, electronic equipment and storage medium
By adding a chip interconnect protocol interface and address allocation algorithm for SOC chip cascading in a multi-chip system, the problem of low data processing capacity caused by dedicated memory controllers is solved, and the scalability of data processing capacity and memory bandwidth is improved.
CN122195893APending Publication Date: 2026-06-12CIX TECH (SHANGHAI) CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CIX TECH (SHANGHAI) CO LTD
- Filing Date
- 2026-05-15
- Publication Date
- 2026-06-12
AI Technical Summary
Technical Problem
The dedicated memory controller in existing multi-core systems results in low data processing capacity, which cannot meet the data processing requirements of the edge CPU and cannot expand the content capacity and bandwidth.
Method used
By adding a first-chip interconnect protocol interface to the SOC chip cascade, when the system bus receives a memory access request, the memory access request is evenly distributed to each memory controller according to the system integrated configuration topology and address allocation algorithm, avoiding dedicated memory controllers.
Benefits of technology
It improves the data processing capacity and memory bandwidth expansion capability of the multi-core data system, and achieves more efficient memory access.
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Smart Images
Figure CN122195893A_ABST
Abstract
The application provides a memory access method and device of a multi-core particle system, an electronic device and a storage medium. When a system bus receives a first memory access request, the controller position of each memory controller is determined according to a system integration configuration topology. Based on an address allocation algorithm, the first memory access request is allocated to at least one memory controller connected with a SOC core particle and / or at least one memory controller connected with an NPU core particle based on the controller position of each memory controller and a first chip interconnection protocol interface, so as to perform memory access through the memory controller. In this way, the condition of low data processing amount caused by memory controller specialization can be avoided, and the data processing amount of the multi-core particle data system, the expansion capability of the system memory bandwidth and capacity are improved.
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