A multi-path interface distribution system and method based on MPSoC

Abstract

The application provides a multi-path interface distribution system and a distribution method based on an MPSoC. The multi-path interface distribution system comprises an interface logic circuit module, an interface distribution module and an interface application module. The interface logic circuit module extends a multi-path interface on an FPGA side. The interface application module sends a request to the interface distribution module according to actual task requirements, and realizes the allocation of the multi-path interface to the belonging relationship of different ARM processor cores. The allocation of the multi-path interface can be changed through software configuration. The ARM core to which different interfaces belong is adjusted according to actual task requirements. The FPGA logic or hardware does not need to be modified or redesigned. The overall flexibility of the heterogeneous MPSoC can be improved. The method is simple, efficient, high in resource utilization and fast in processing speed.

Description

Technical Field

[0001] This invention belongs to the field of embedded system technology, specifically relating to a multi-channel interface allocation system and allocation method based on MPSoC. Background Technology

[0002] As the complexity of embedded systems continues to increase, MPSoC, with its integration of heterogeneous computing resources such as high-performance application processors (A cores), real-time processors (R cores), and programmable logic (FPGAs), has become an ideal platform for realizing high-performance and flexible system designs. These processors often require the expansion of various communication interfaces, such as UART and CAN bus, through programmable logic on the FPGA side to meet diverse external device connectivity needs.

[0003] Currently, in MPSoC-based system design, both A-cores and R-cores can be instantiated for the multi-channel communication interfaces extended on the FPGA side. However, A-cores are suitable for handling highly complex parallel tasks, while R-cores are suitable for handling real-time tasks. If the relationship between the interface and the processor core cannot be correctly bound, the interface resources cannot be adjusted according to the actual task requirements, resulting in high system complexity and difficult maintenance.

[0004] Therefore, a flexible configuration solution with multiple interfaces is needed to fundamentally solve the problem of fixed allocation of FPGA-side expansion interfaces in MPSoC, and realize flexible allocation and management of interface resources between A cores and R cores, thereby fully releasing the potential of the MPSoC computing platform. Summary of the Invention

[0005] (a) Technical problems to be solved This invention proposes a multi-channel interface allocation system and method based on MPSoC to solve the technical problem of fixed resource allocation for extended communication interfaces (such as UART, CAN, etc.) on the FPGA side, and realize flexible allocation and instantiation of interface resources, thereby improving the overall flexibility and processing efficiency of MPSoC.

[0006] (II) Technical Solution To address the aforementioned technical problems, this invention proposes a multi-interface allocation system based on MPSoC, which includes an interface logic circuit module, an interface allocation module, and an interface application module; wherein... The interface logic circuit module is integrated on the PL side of the MPSoC chip, including multiple extended interface IP cores, which are interconnected with the processor system of the MPSoC chip through the AXI standard bus. Each interface IP core is configured to have a unified control and status register mapping space. The interface allocation module runs on the PS processing system of the MPSoC chip and consists of two parts: a device tree and an interface management driver. The device tree is used to instantiate each interface IP core in the interface logic circuit module and define the hardware attributes of each interface IP core. The interface management driver is used to implement the allocation of the ownership relationship between the multiple interfaces and the A core and R core processors, and provides the A core and R core user space configuration interface, allowing the user space to specify the owner processor of each interface IP core according to task requirements. The interface application module consists of the A and R cores of the ARM processor within the MPSoC chip. By sending access requests for the target interface IP core to the interface allocation module, it enables flexible access to multiple interfaces and executes corresponding communication tasks.

[0007] Furthermore, the MPSoC chip is a heterogeneous MPSoC chip composed of an FPGA, an application processing unit Cortex-A core, and a real-time processing unit Cortex-R core.

[0008] Furthermore, the hardware attributes of each interface IP core include physical base address, interrupt number, and clock frequency.

[0009] Furthermore, the interface management driver provides user space configuration interfaces for A cores and R cores, and interface allocation requests are issued through the user space configuration interfaces.

[0010] Furthermore, for the interface IP cores assigned to their respective processors, the interface management driver ensures that the interface IP cores can access devices within the operating system of the processor they belong to, and prevents the interface IP cores from being accessed in operating systems of other processors.

[0011] Furthermore, the interface management driver prevents access from being made in non-local processor operating systems by unloading and hiding the corresponding device node in non-local processor operating systems.

[0012] Furthermore, this invention also proposes a multi-interface allocation method based on MPSoC, which employs the aforementioned multi-interface allocation system and includes the following steps: S1. Build IP cores on the PL side of the MPSoC chip, allocate independent address space and interrupt number to each interface IP core, and realize multi-channel expansion of serial port and CAN bus interfaces; The device tree in the S2 interface allocation module creates a device tree node for each serial port and CAN bus interface on the PL side. Each device tree node includes the hardware attributes of the target physical interface IP core. Different serial port and CAN bus nodes are distinguished by specifying different addresses and interrupt resources for each interface. S3. The interface application module sends an interface allocation request to the interface management driver of the interface allocation module according to the task requirements; S4. The interface management driver receives the interface allocation request from the interface application module, and binds the access of the target processor core and the interface to the interface requested by the A core and R core respectively. This includes mapping the physical interface address of the interface IP core to the virtual address accessed by the processor core, routing the interrupt signal generated by the interface IP core to the interrupt controller of the processor core, and writing the configuration parameters of the processor core to the interface into the corresponding register of the interface IP core. S5. The interface management driver initializes after the interface driver is matched, registers the tty device node in the processor core system to which the interface belongs, and the applications on the A core and R core access the corresponding interface IP core through the tty device node to complete data communication.

[0013] Furthermore, in step S1, the IP core is built on the PL side of the MPSoC chip using the Verilog language.

[0014] Furthermore, in step S1, the IP core includes AXI-UART and AXI-CanFd.

[0015] (III) Beneficial Effects This invention proposes a multi-interface allocation system and method based on MPSoC. The multi-interface allocation system includes an interface logic circuit module, an interface allocation module, and an interface application module. The interface logic circuit module extends multiple interfaces on the FPGA side. The interface application module sends requests to the interface allocation module according to actual task requirements, realizing the allocation of multiple interfaces to different ARM processor cores. The allocation of multiple interfaces can be changed through software configuration, adjusting the ARM core to which different interfaces belong according to actual task requirements, without modifying the FPGA logic or redesigning the hardware. This improves the overall flexibility of heterogeneous MPSoC, is simple and efficient, has high resource utilization, and fast processing speed. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the principle of the MPSoC-based multi-interface allocation system of the present invention. Detailed Implementation

[0017] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0018] This embodiment proposes a multi-interface allocation system based on MPSoC. The MPSoC chip is a heterogeneous MPSoC chip composed of an FPGA, an application processing unit Cortex-A core, and a real-time processing unit Cortex-R core. The composition principle of this multi-interface allocation system is as follows: Figure 1 As shown, it mainly includes an interface logic circuit module, an interface allocation module, and an interface application module.

[0019] The interface logic circuit module is integrated on the PL side of the MPSoC chip, i.e., the FPGA programmable logic circuit, and includes multiple extended interface IP cores. It is interconnected with the processor system of the MPSoC chip through the AXI standard bus. Each interface IP core is configured to have a unified control and status register mapping space.

[0020] The interface allocation module runs on the PS processing system of the MPSoC chip and mainly consists of two parts: a device tree and an interface management driver. The device tree instantiates each interface IP core in the interface logic circuit module, defining hardware attributes such as the physical base address, interrupt number, and clock frequency of each interface IP core. The interface management driver implements the allocation of multiple interfaces to the A-core and R-core processors, providing user-space configuration interfaces for the A-core and R-core. Interface allocation requests are sent through the user-space configuration interface, allowing user space to specify the processor to which each interface IP core belongs based on task requirements.

[0021] For the interface IP core assigned to the processor, ensure that the interface IP core can access the device in the processor's operating system, and prevent it from being accessed in non-processor operating systems by unloading and hiding the corresponding device node.

[0022] The interface application module mainly consists of the A core and R core of the ARM processor within the MPSoC chip. The A core is used to handle interfaces with high task complexity, while the R core is used to handle interfaces with high real-time requirements. By sending access requests for the target interface IP core to the interface allocation module, flexible access to multiple interfaces is achieved, and corresponding communication tasks are executed.

[0023] The multi-interface allocation method of the MPSoC-based multi-interface allocation system specifically includes the following steps: S1. Use Verilog language to build IP cores such as AXI-UART and AXI-CanFd on the PL side of the MPSoC chip, allocate independent address space and interrupt number for each interface IP core, and realize multi-channel expansion of interfaces such as serial port and CAN bus; The device tree in the S2 interface allocation module creates a device tree node for each serial port and CAN bus interface on the PL side. Each device tree node includes the register base address, interrupt number, clock frequency, etc. of the target physical interface IP core. Different serial port and CAN bus nodes are distinguished by specifying different addresses and interrupt resources for each interface. S3. The interface application module sends an interface allocation request to the interface management driver of the interface allocation module according to the task requirements; S4. The interface management driver receives the interface allocation request from the interface application module, and binds the access of the target processor core and the interface to the interface requested by the A core and R core respectively. This includes mapping the physical interface address of the interface IP core to the virtual address accessed by the processor core, routing the interrupt signal generated by the interface IP core to the interrupt controller of the processor core, and writing the configuration parameters of the processor core to the interface into the corresponding register of the interface IP core. S5. The interface management driver initializes after the interface driver is matched, registers the tty device node in the processor core system to which the interface belongs, and the applications on the A core and R core access the corresponding interface IP core through the tty device node to complete data communication.

[0024] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A multi-interface allocation system based on MPSoC, characterized in that, The MPSoC-based multi-interface allocation system includes an interface logic circuit module, an interface allocation module, and an interface application module; wherein... The interface logic circuit module is integrated on the PL side of the MPSoC chip, including multiple extended interface IP cores, which are interconnected with the processor system of the MPSoC chip through the AXI standard bus. Each interface IP core is configured to have a unified control and status register mapping space. The interface allocation module runs on the PS processing system of the MPSoC chip and consists of two parts: a device tree and an interface management driver. The device tree is used to instantiate each interface IP core in the interface logic circuit module and define the hardware attributes of each interface IP core. The interface management driver is used to implement the allocation of the ownership relationship between the multiple interfaces and the A core and R core processors, and provides the A core and R core user space configuration interface, allowing the user space to specify the owner processor of each interface IP core according to task requirements. The interface application module consists of the A and R cores of the ARM processor within the MPSoC chip. By sending access requests for the target interface IP core to the interface allocation module, it enables flexible access to multiple interfaces and executes corresponding communication tasks.

2. The MPSoC-based multi-interface allocation system as described in claim 1, characterized in that, The MPSoC chip is a heterogeneous MPSoC chip composed of an FPGA, an application processing unit Cortex-A core, and a real-time processing unit Cortex-R core.

3. The MPSoC-based multi-interface allocation system as described in claim 1, characterized in that, The hardware attributes of each interface IP core include physical base address, interrupt number, and clock frequency.

4. The MPSoC-based multi-interface allocation system as described in claim 1, characterized in that, The interface management driver provides user space configuration interfaces for A cores and R cores, and interface allocation requests are issued through the user space configuration interfaces.

5. The MPSoC-based multi-interface allocation system as described in claim 1, characterized in that, For an interface IP core assigned to its own processor, the interface management driver ensures that the interface IP core can access the device in the operating system of the processor it belongs to, and prevents the interface IP core from being accessed in an operating system other than the processor it belongs to.

6. The MPSoC-based multi-interface allocation system as described in claim 5, characterized in that, The interface management driver prevents access from non-local processor operating systems by unloading and hiding the corresponding device node.

7. A method for allocating multiple interfaces based on MPSoC, characterized in that, The multi-interface allocation method employs the multi-interface allocation system according to any one of claims 1 to 6, and includes the following steps: S1. Build IP cores on the PL side of the MPSoC chip, allocate independent address space and interrupt number to each interface IP core, and realize multi-channel expansion of serial port and CAN bus interfaces; The device tree in the S2 interface allocation module creates a device tree node for each serial port and CAN bus interface on the PL side. Each device tree node includes the hardware attributes of the target physical interface IP core. Different serial port and CAN bus nodes are distinguished by specifying different addresses and interrupt resources for each interface. S3. The interface application module sends an interface allocation request to the interface management driver of the interface allocation module according to the task requirements; S4. The interface management driver receives the interface allocation request from the interface application module, and binds the access of the target processor core and the interface to the interface requested by the A core and R core respectively. This includes mapping the physical interface address of the interface IP core to the virtual address accessed by the processor core, routing the interrupt signal generated by the interface IP core to the interrupt controller of the processor core, and writing the configuration parameters of the processor core to the interface into the corresponding register of the interface IP core. S5. The interface management driver initializes after the interface driver is matched, registers the tty device node in the processor core system to which the interface belongs, and the applications on the A core and R core access the corresponding interface IP core through the tty device node to complete data communication.

8. The MPSoC-based multi-interface allocation method as described in claim 7, characterized in that, In step S1, the IP core is built on the PL side of the MPSoC chip using the Verilog language.

9. The MPSoC-based multi-interface allocation method as described in claim 7, characterized in that, In step S1, the IP core includes AXI-UART and AXI-CanFd.

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