A majority logic replacement optimization method based on two-step screening and back derivation
The optimization of majority logic replacement by a two-step screening and reverse derivation method solves the problems of large search space and low efficiency in majority logic networks, and improves the speed and quality of circuit optimization, especially in complex circuits, effectively reducing the number of nodes and logic depth.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU JIUZHIXING SOFTWARE CO LTD
- Filing Date
- 2026-05-18
- Publication Date
- 2026-06-12
AI Technical Summary
Most existing logic replacement methods are inefficient when dealing with a large number of gate nodes, especially in large-scale circuit optimization where the search space is large and there is a lack of efficient candidate selection mechanisms, resulting in wasted computational resources and low optimization efficiency.
A majority logic replacement optimization method based on two-step screening and reverse derivation is adopted. By introducing pairwise constraint properties, constant-time screening is carried out. Multi-level replacement candidate structures are constructed by combining recursive screening and synthesis. Counterexamples are fed back in the SAT verification closed loop to ensure functional equivalence.
It significantly reduces the search space of most logic networks, improves optimization speed and quality, reduces computational complexity, increases the success rate of optimization in complex circuits, and avoids algorithm dead loops.
Smart Images
Figure CN122197754A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the fields of Electronic Design Automation (EDA) and logic synthesis, and relates to a replacement optimization method for majority logic networks, particularly a majority logic replacement optimization method based on two-step screening and reverse derivation. Background Technology
[0002] In the logic synthesis and optimization of modern digital circuits, Boolean resubstitution is a key structural optimization technique. Its core idea is to use existing digits in the circuit network to re-express the function of the target node. If the re-expressed local structure is smaller than the original structure, the original target node is replaced with the new structure, and redundant nodes in the original node's maximum fanout-free cone (MFFC) are removed, thereby reducing the circuit area or logic depth.
[0003] With the emergence of new computational paradigms, logic representation methods based on majority gates (MAJs), such as Majority-Inverter Graph (MIG) and XOR-Majority Graph (XMG), have been widely applied. However, existing replacement methods face severe efficiency bottlenecks when processing MAJ nodes. To find a single-node MAJ replacement structure, traditional methods need to exhaustively search for combinations and polarities of the three divisors in the divisor set, resulting in a search complexity of up to [insert time complexity here]. While existing technologies have proposed effective screening metrics such as Distinguishing Bit Power (DBP) for operators like XOR, there is still a lack of efficient candidate screening mechanisms for the MAJ operator, resulting in a large amount of computational resources being wasted on enumerating combinations of invalid candidates.
[0004] Furthermore, to achieve better optimization quality, it is often necessary to explore two-node resubstitution (i.e., substitution using two new nodes). If a forward exhaustive strategy is continued in 2-resub, the search space will expand dramatically. This is completely unacceptable when dealing with large-scale industrial circuits. Therefore, there is an urgent need for a logic optimization method that can significantly reduce the MAJ candidate search space while maintaining verification correctness and supporting two-node re-replacement extension. Summary of the Invention
[0005] To address the shortcomings of existing majority logic replacement techniques, such as large search space and low efficiency, this invention provides a majority logic replacement optimization method based on two-step screening and back-reasoning. This method introduces pairwise constraints for constant-time screening, combines back-reasoning and recursive screening with synthesis to construct a multi-level candidate replacement structure, and implements counterexample (CEX) feedback in the SAT verification loop, significantly improving search efficiency while ensuring functional equivalence. This method can be seamlessly integrated into mainstream logic synthesis toolchains, effectively improving the optimization speed and quality of large-scale majority logic networks.
[0006] The technical solution adopted by this invention to solve the above-mentioned technical problems is: a majority logic re-replacement optimization method based on two-step screening and reverse derivation, comprising the following steps: S1. Convert the netlist of the circuit to be optimized into a logic network containing a majority of gate operators, and obtain the truth signature of each node in the logic network by random simulation. S2. Select the target node and its truth signature in the logical network to obtain the set of candidate divisors; S3. Select two divisors from the candidate divisor set to form a candidate pair. Use the pairwise constraint property of majority functions to filter the candidates. Select the candidate pairs that pass the filter. Enumerate the third divisor from the remaining candidate divisors in the candidate divisor set. Perform a matching process; if a match is found, generate a single-node replacement candidate structure. Then jump to S5; otherwise proceed to S4. S4. When no match is found in S3 and the search space needs to be expanded, the replacement structure of the fixed target node is used. and candidate pairs Derive the third divisor in reverse The irrelevant item mask and truth signature, and the third divisor among the remaining candidate divisors in the candidate divisor set. Recursive screening and synthesis are performed to obtain Candidate structures for level-replacement; S5. Perform functional equivalence verification on the candidate replacement structure. If the verification passes, replace the target node with the candidate replacement structure and remove redundant nodes. If the verification fails, extract counterexamples for simulation and update the truth signatures of nodes in the logic network. Return to S3 until the verification passes or the maximum number of iterations is exceeded. S6. Traverse all nodes in the logical network in topological order, and repeat S2 to S5.
[0007] The method of this invention utilizes the pairwise constraint property of majority functions for screening. By selecting only two divisors, it can eliminate the vast majority of invalid combinations, thus replacing the traditional single-node re-replacement method. In engineering practice, the complexity of exhaustive search is reduced to near When a single node match fails, the internal signals are deduced in reverse through the replacement structure of the target node. The irrelevant item mask and truth signature transform the blind exhaustive search of multi-level replacements into a target-driven recursive logic synthesis, avoiding the need for dual-node replacements. The search overhead is significantly reduced, greatly improving the success rate of finding optimal structures in complex arithmetic circuits. By combining simulation signature and SAT verification loop, when verification fails, counterexamples are extracted, signatures are updated, and re-entry filtering is performed, ensuring functional equivalence while avoiding algorithmic dead loops.
[0008] Preferably, in S1, the logic network containing majority gate operators is an XOR-majority graph network or a majority-inverse graph network, which stores and retrieves the truth signature data based on bit vectors. XOR-majority graph networks and majority-inverse graph networks are currently the mainstream representations of majority logic synthesis, possessing excellent expressive power. Storing and retrieving truth signatures based on bit vectors allows all Boolean operations in the random simulation mode to be performed in parallel through bit operations, significantly improving simulation and caching efficiency and providing fast data access for subsequent filtering steps. As a further preferred embodiment, the number of random simulation test modes is set to 1024 groups.
[0009] Preferably, in step S2, the maximum fanless cone of the target node is extracted, and the available signals within a local window are used as a candidate divisor set. In step S5, if the verification passes, the target node is replaced using a replacement candidate structure, and redundant nodes in the maximum fanless cone are removed. By extracting the maximum fanless cone of the target node and using the available signals within a local window as a candidate divisor set, the search range is effectively limited, avoiding global enumeration. After verification, replacing the target node with a replacement candidate structure and removing redundant nodes in the maximum fanless cone directly reduces the number of gates in the network, achieving circuit area reduction and significantly reducing the number of nodes.
[0010] Preferably, in S3, the filtering is implemented based on bitwise operations, and the filtering process is as follows: Construct the mask region: (1) (2) If and only if When determining candidate pairs Through screening; In this context, any three candidate divisors in the candidate divisor set are referred to as the first candidate divisor, the second candidate divisor, and the third candidate divisor, respectively. , These represent the truth signatures of the first and second candidate divisors, respectively. The truth signature representing the target node. represent The bitwise inverse result; The bitmask representing that the first and second candidate divisors are both 1. A bitmask representing a first and second candidate divisor that are both zero; the symbol " "Represents the logical operator AND, symbol" " represents the logical operator OR.
[0011] The above-mentioned filtering method based on bitwise operations is used to construct... and After the two masked regions, only execution is required. and Two bitwise operations and a zero-checking operation can determine whether a candidate pair is likely to form the target majority gate in constant time; this pairwise constraint property eliminates a large number of invalid candidates, making it possible to reduce the time required to exhaustively search for the third divisor. The complexity is reduced to By combining the screening and enumeration of the scale, a comparison of the screening time between the traditional method and the method of this invention shows that the time in the cavlc.aig test was reduced from 27.49 seconds to 3.53 seconds, a speedup of about 7.8 times.
[0012] As a preferred option, in S3, when enumerating the third divisor... During the matching process, a bitmask for the difference regions is constructed: (3) Calculate the candidate structure for single-node replacement Output truth signature The calculation formula is as follows: (4) like and If they are equal or opposite, the match is successful; otherwise, the match is unsuccessful. in, The bitmask representing the difference region between the first and second candidate divisors; The truth signature representing the third candidate divisor; the symbol " " represents the logical operator XOR.
[0013] After the candidate pairs pass the screening, a bitmask of the difference regions is constructed. And using the formula The truth signature is calculated and output. This calculation only requires one AND operation and one OR operation to quickly verify the third divisor. Does it match? If so... and A match is successful if the elements are equal or opposite. This matching process avoids truth table expansion or SAT calculation, greatly improving the generation speed of single-node replacement.
[0014] As a preferred option, in S4, the third divisor is derived in reverse. The formulas for calculating the irrelevant item mask and the truth signature are as follows: (5) (6) in, The third divisor irrelevant item mask, The third divisor Truth signature; According to formula (6), the truth signature Equivalent to the truth signature of the target node In irrelevant item mask The value under the cover; The recursive filtering and synthesis process involves: calculating the truth signature... As the new target signature, an internal majority gate structure or an internal XOR gate structure is constructed from the remaining candidate divisors in the candidate divisor set, and its output signature is determined in the irrelevant term mask. Is it covered by Consistency is achieved to form a candidate structure for dual-node replacement, and this is used to deduce... Candidate structures for level-replacement.
[0015] The internal signal can be accurately calculated using the above reverse derivation method. The truth signature and irrelevant term mask, where the irrelevant term mask indicates that the output is completely determined when a≠b. Those bits that are determined are covered by this mask. Only in the position of concern Consistent. The above recursive screening and synthesis method can transform the two-node replacement problem into a local replacement subproblem with irrelevant terms, which greatly relaxes the matching conditions. This can effectively reduce the number of nodes in complex arithmetic circuits that are originally difficult to exhaustively enumerate, while maintaining the correctness of the logical function.
[0016] As a preferred option, in S5, the method for verifying the functional equivalence of the replacement candidate structure is as follows: construct the miter circuit between the replacement candidate structure and the target node, and call the SAT verifier to perform functional equivalence verification.
[0017] As a preferred option, in S6, all nodes in the logic network are traversed in the topological order from the main input to the main output to ensure that the new replaced nodes participate in subsequent replacements and expand the solution space.
[0018] Compared with the prior art, the present invention has the following advantages: (1) This invention significantly reduces the computational complexity of MAJ candidate search. Traditional methods require exhaustively searching all three divisors to verify the majority gate output, while this invention utilizes the pairwise constraint property of majority functions (the output is determined when two inputs are the same) for screening. By selecting only two divisors, the vast majority of invalid combinations can be eliminated. In practical circuit optimization, this significantly reduces the computational complexity of traditional single-node re-replacement. In engineering practice, the complexity of exhaustive search is reduced to near The method of this invention can be seamlessly integrated into mainstream logic synthesis toolchains, effectively improving the optimization speed and quality of large-scale majority logic networks.
[0019] (2) Transform multi-level exhaustive search into goal-driven recursive logic composition. This is useful when dealing with multi-level resubstitution (such as 2-resub) and... When resubmitting, this invention abandons the extremely high-overhead strategy of simultaneously enumerating both inner and outer layers. By fixing the replacement structure of the target node (i.e., the outer structure), the internal signal is accurately calculated. The irrelevant term mask and truth signature transform the blind exhaustive search of multi-level re-substitution into a goal-driven recursive logic synthesis, thereby transforming the problem into a local re-substitution subproblem with irrelevant term constraints, which greatly improves the success rate of finding optimal structures in complex arithmetic circuits.
[0020] (3) An efficient and robust engineering closed loop is constructed. This invention seamlessly combines global pre-simulation, topology traversal, fast filtering, and SAT counterexamples. By combining simulation signature and SAT verification closed loop, when the verification fails, counterexamples are extracted, signatures are updated, and filtering is re-entered, ensuring functional equivalence while avoiding algorithm dead loops, and has extremely high engineering practical value. Attached Figure Description
[0021] Figure 1 This is a flowchart of the optimization method in the embodiment; Figure 2 For target node-based XMG networks n An example of a small local window that is constructed. Detailed Implementation
[0022] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0023] Example: Taking arithmetic circuits (such as multipliers and dividers) from the open-source EPFL benchmark circuit set as an example, the method of this invention is used to optimize the area and depth of their XOR-majority graph (XMG), such as... Figure 1 As shown, the specific steps are as follows: S1. Using an open-source logic synthesis tool (such as Yosys / mockturtle), the Verilog netlist file of the arithmetic circuit to be optimized is parsed and transformed into an XMG network. This XMG network consists of three-input majority gates (MAJ), three-input XOR gates (XOR3), and inverting edges. 1024 sets of random simulation test modes are assigned to the global main input of the circuit. A full graph Boolean simulation is performed on the entire network, recording the response of each node under the 1024 sets of inputs. This result is the node's simulation signature, represented as a bit vector of length 1024. All node signatures are cached to avoid the overhead of subsequent repeated simulations.
[0024] S2. Construct a replacement local window for the target node. The construction of the replacement local window starts from the target node, performing a depth search towards the input until the window input reaches its limit, and then a depth search towards the output until the layer limit is reached. Subsequently, nodes are constructed sequentially from the window input to the output. Preferably, setting the number of inputs to the local window to ≤16 and the layer from the target node to the window output to ≤4 effectively controls the time.
[0025] Retrieve the truth signature of the target node from the global cache. The maximum fanless cone (MFFC) of the target node is calculated, and available signals within a local window are collected to construct a candidate divisor set. When selecting candidate divisors, useless nodes are quickly filtered and removed using the following rules: MFFC nodes are not considered candidate divisors, the direct TFO (Transitive Fanout) of the target node is not considered a candidate divisor, and the input of the target node is not considered a candidate divisor. After obtaining the candidate divisor set, the simulation signature of each candidate divisor is obtained.
[0026] S3. Select any two divisors from the candidate divisor set to form a candidate pair. Use the pairwise constraint property of majority functions to filter them. The pairwise constraint property of majority functions is as follows: Suppose there are three inputs a, b, and c. When a and b are both 0, the output f must be 0. At this time, c can be any value. Similarly, when a and b are both 1, the output f must be 1. At this time, c can be any value. If the values of a and b are complementary, the value of f is equal to the value of c.
[0027] For the candidate pairs that pass the screening Enumerate the third divisor from the remaining candidate divisors in the candidate divisor set. Perform a matching process; if a match is found, generate a single-node resubstitution (1-resub) candidate structure. Then jump to S5; otherwise, proceed to S4.
[0028] In S3, filtering is implemented based on bitwise operations. The filtering process is as follows: Construct the mask region: (1) (2) If and only if When determining candidate pairs Through screening; In this context, any three candidate divisors in the candidate divisor set are referred to as the first candidate divisor, the second candidate divisor, and the third candidate divisor, respectively. , They represent the first candidate divisors respectively. Second candidate divisor Truth signature; The truth signature representing the target node. represent The bitwise inverse result; The bitmask representing that the first and second candidate divisors are both 1. A bitmask representing a first and second candidate divisor that are both zero; the symbol " "Represents the logical operator AND, symbol" " represents the logical operator OR.
[0029] In S3, when enumerating the third divisor... During the matching process, a bitmask for the difference regions is constructed: (3) Calculate the candidate structure for single-node replacement Output truth signature The calculation formula is as follows: (4) like and If they are equal or opposite, the match is successful; otherwise, the match is unsuccessful. in, The bitmask representing the difference region between the first and second candidate divisors; The truth signature representing the third candidate divisor; the symbol " " represents the logical operator XOR.
[0030] S4. When no match is found in S3 and the search space needs to be expanded, the replacement structure of the fixed target node is used. and candidate pairs Derive the third divisor in reverse The irrelevant item mask and truth signature, and the third divisor among the remaining candidate divisors in the candidate divisor set. Recursive screening and synthesis are performed to obtain Candidate structures for level-replacement.
[0031] In S4, the third divisor is derived in reverse. The formulas for calculating the irrelevant item mask and the truth signature are as follows: (5) (6) in, The third divisor irrelevant item mask, The third divisor Truth signature; According to formula (6), the truth signature Equivalent to the truth signature of the target node In irrelevant item mask The value under the cover; In S4, the recursive filtering and synthesis are: to calculate the truth signature... As the new target signature, construct an internal majority gate structure or an internal XOR gate structure from the remaining candidate divisors in the candidate divisor set, and determine whether its output signature is in the irrelevant term mask. Is it covered by Consistency is achieved to form a candidate structure for two-node resubstitution (2-resub), and this is used to deduce... Level replacement ( k -resub) candidate structure.
[0032] S5. Since random simulation cannot capture all the information of network nodes, a satisfiability solver (SAT solver) is used to verify the functional equivalence of the replacement candidate structure. The verification method is as follows: construct the miter circuit between the replacement candidate structure and the target node, and call the SAT verifier to perform functional equivalence verification. Since the simulation signature only covers 1024 input patterns, if the SAT solver returns "sat", it means that the verification failed (there is an uncovered counterexample input). The counterexample is then extracted and added to the aforementioned random simulation test pattern, and the truth signature of the node in the logic network is updated. The process returns to step S3 to re-select and match until the verification passes or the set maximum number of iterations is exceeded.
[0033] If the SAT solver returns "unsat", it means the verification passed, proving that the replacement structure is completely equivalent to the original target node in global logic. The replacement candidate structure is then integrated into the logical network to replace the target node, and redundant nodes in its MFFC are removed to reduce the number of gates. Specifically, the replacement candidate structure is formally written back to the logical network, and the structure replacement operation is performed, including: replacing the corresponding subgraph of the target node with the replacement candidate structure; deleting all redundant nodes in the target node's MFFC; updating the logical network structure and node-driven relationships; updating the topological order and signature index structure of the global cache; and marking replaced nodes to avoid duplicate processing.
[0034] Figure 2 For target node-based XMG networks n An example of a small local window that is constructed. Figure 2 In the diagram, circles represent three-input majority gates (MAJ) and three-input XOR gates (XOR3). White circles represent ordinary XMG network nodes, blue circles represent candidate divisors, orange circles represent MFFC nodes, and red circles represent candidate structures (i.e., nodes). n’ The blue triangle represents the input of the local window (which is also the candidate divisor); the solid black and red arrows represent non-inverted edges, and the dashed black and red arrows represent inverted edges. (This is used for SAT verification.) n and n’ After equivalence, delete the MFFC node and use the candidate structure. n’ Replace Node n .
[0035] S6. Traverse all nodes in the logical network in topological order from main input to main output, repeating S2 to S5 until the traversal and replacement of all nodes in the logical network are completed. For the target node, if the replacement is successful, immediately update the local topology and perform incremental update on the affected successor nodes; if the replacement fails, retain the original node structure and continue traversing the next node.
[0036] At the global level, this process constitutes an iterative optimization framework, characterized by: forward consistency guarantee: topological order ensures that any node depends only on its stable and optimized predecessor node; incremental update mechanism: avoids repeated signature construction and repeated SAT solving, improving overall efficiency; convergence control mechanism: the algorithm terminates when no node is replaced in a complete traversal or when the preset number of iterations is reached.
[0037] Table 1 shows the test results of some EPFL circuit test cases using the method of this invention and the conventional method.
[0038] Table 1
[0039] The test results in Table 1 show that, compared with the traditional resubstitution method, the method of the present invention, using 1-resub, achieves an average speedup of 2.93 times while maintaining the optimization quality. Furthermore, the method of the present invention, combined with the 2-resub extension derived by reverse derivation, further reduces the total number of network nodes by an average of 18.83% and the logic depth by only an average of 2.53%, demonstrating extremely high engineering practical value.
Claims
1. A majority logic re-replacement optimization method based on two-step screening and reverse derivation, characterized in that, Includes the following steps: S1. Convert the netlist of the circuit to be optimized into a logic network containing a majority of gate operators, and obtain the truth signature of each node in the logic network by random simulation. S2. Select the target node and its truth signature in the logical network to obtain the set of candidate divisors; S3. Select two divisors from the candidate divisor set to form a candidate pair. Use the pairwise constraint property of majority functions to filter the candidates. Select the candidate pairs that pass the filter. Enumerate the third divisor from the remaining candidate divisors in the candidate divisor set. Perform a matching process; if a match is found, generate a single-node replacement candidate structure. Then jump to S5; otherwise proceed to S4. S4. When no match is found in S3 and the search space needs to be expanded, the replacement structure of the fixed target node is used. and candidate pairs Derive the third divisor in reverse The irrelevant item mask and truth signature, and the third divisor among the remaining candidate divisors in the candidate divisor set. Recursive screening and synthesis are performed to obtain Candidate structures for level-replacement; S5. Perform functional equivalence verification on the candidate replacement structure. If the verification passes, replace the target node with the candidate replacement structure and remove redundant nodes. If the verification fails, extract counterexamples for simulation and update the truth signatures of nodes in the logic network. Return to S3 until the verification passes or the maximum number of iterations is exceeded. S6. Traverse all nodes in the logical network in topological order, and repeat S2 to S5.
2. The majority logic re-replacement optimization method based on two-step screening and reverse derivation according to claim 1, characterized in that, In S1, the logic network containing majority gate operators is an XOR-majority graph network or a majority-inverse graph network, which stores and retrieves the truth signature data based on bit vectors.
3. The majority logic re-replacement optimization method based on two-step screening and reverse derivation according to claim 1, characterized in that, In S2, the maximum fanless cone of the target node is extracted, and the available signals within the local window are obtained as a set of candidate divisors; in S5, if the verification is successful, the target node is replaced with a replacement candidate structure and redundant nodes in the maximum fanless cone are removed.
4. The majority logic re-replacement optimization method based on two-step screening and reverse derivation according to claim 1, characterized in that, In S3, the filtering is implemented based on bitwise operations, and the filtering process is as follows: Construct the mask region: (1) (2) If and only if When determining candidate pairs Through screening; In this context, any three candidate divisors in the candidate divisor set are referred to as the first candidate divisor, the second candidate divisor, and the third candidate divisor, respectively. , These represent the truth signatures of the first and second candidate divisors, respectively. The truth signature representing the target node. represent The bitwise inverse result; The bitmask representing that the first and second candidate divisors are both 1. A bitmask representing a first and second candidate divisor that are both zero; the symbol " "Represents the logical operators AND, , symbol" " represents the logical operator OR.
5. The majority logic re-replacement optimization method based on two-step screening and reverse derivation according to claim 4, characterized in that, In S3, when enumerating the third divisor... During the matching process, a bitmask for the difference regions is constructed: (3) Calculate the candidate structure for single-node replacement Output truth signature The calculation formula is as follows: (4) like and If they are equal or opposite, the match is successful; otherwise, the match is unsuccessful. in, The bitmask representing the difference region between the first and second candidate divisors; The truth signature representing the third candidate divisor; the symbol " " represents the logical operator XOR.
6. The majority logic re-replacement optimization method based on two-step screening and reverse derivation according to claim 1, characterized in that, In S4, the third divisor is derived in reverse. The formulas for calculating the irrelevant item mask and the truth signature are as follows: (5) (6) in, The third divisor irrelevant item mask, The third divisor Truth signature; According to formula (6), the truth signature Equivalent to the truth signature of the target node In irrelevant item mask The value under the cover; The recursive filtering and synthesis process involves: calculating the truth signature... As the new target signature, an internal majority gate structure or an internal XOR gate structure is constructed from the remaining candidate divisors in the candidate divisor set, and its output signature is determined in the irrelevant term mask. Is it covered by Consistency is achieved to form a candidate structure for dual-node replacement, and this is used to deduce... Candidate structures for level-replacement.
7. The majority logic replacement optimization method based on two-step screening and reverse derivation according to claim 1, characterized in that, In S5, the method for verifying the functional equivalence of replacement candidate structures is as follows: construct the miter circuit between the replacement candidate structure and the target node, and call the SAT verifier to perform functional equivalence verification.
8. The majority logic re-replacement optimization method based on two-step screening and reverse derivation according to claim 1, characterized in that, In S6, all nodes in the logic network are traversed in topological order from main input to main output.