A fast detailed layout method and system for FPGA based on greedy algorithm
By employing a two-level strategy of greedy algorithm to optimize timing critical line length and bus length in FPGA detailed placement, combined with clock driving and congestion awareness, the problem of single optimization objective in existing technologies is solved, achieving efficient placement optimization and fast convergence.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGDONG UNIV OF TECH
- Filing Date
- 2026-03-24
- Publication Date
- 2026-06-12
AI Technical Summary
Existing technologies focus only on a single optimization objective in FPGA detailed placement, failing to comprehensively optimize timing critical line lengths and bus lengths, leading to issues such as unroutable conditions and unmet timing constraints during the routing phase.
A greedy algorithm combined with a clock-driven approach is used to first optimize the length of timing critical lines and then the bus length. Fine-grained parallel acceleration is achieved through OpenMP4.0. A two-level detailed layout strategy and a congestion-aware strategy are employed to ensure clock validity and congestion validity. Bounding box overlap regions are used to filter candidate sites.
Significantly optimized timing-critical line length by 16.92%, non-timing-critical line length by 11.16%, pin density by 5.84%, runtime reduced to within 4 minutes, performance improved by 5 times, ensuring routeability and timing correctness during the routing phase.
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Figure CN122197767A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the technical field of digital integrated circuit electronic design automation, and in particular to a method and system for rapid detailed placement of FPGAs based on a greedy algorithm. Background Technology
[0002] Detailed placement is a crucial step in the physical design process of VLSI (Very Large Scale Integration). Its purpose is to reduce overall routing requirements by moving and swapping basic cell positions (LUTs and DFFs) without affecting global placement timing and cell density. The quality of the detailed placement directly impacts the optimization effects of subsequent routing and static timing analysis, thus significantly affecting chip performance. Furthermore, due to the interrelationships among various performance metrics, detailed placement becomes an NP-hard problem, requiring various algorithms to solve the complex detailed placement problem in order to optimize chip performance.
[0003] In recent years, a great deal of research has been conducted in the field of global layout. In contrast, detailed layout problems have not received much attention. Detailed layouters can further improve the quality of solutions generated by global layouters. Researchers have designed a variety of time-driven detailed layout algorithms, including the Greedy Algorithm (GA), Network-Based (NB), Linear Programming (LP), Discrete Optimization (DO), and Branch and Bound Algorithm (BBA). These detailed layout algorithms obtain layout schemes with shorter line lengths through global movement and swapping units. Among them, the Greedy Algorithm is widely used in the field of detailed layout due to its simplicity and obvious effectiveness.
[0004] To improve algorithm efficiency, accelerate convergence, and enhance placement quality, previous researchers have conducted extensive studies on optimizing line length in detailed placement. Based on a greedy detailed placement algorithm, the paper (Chen G, Pui CW, Chow WK, et al. RippleFPGA: Routability-driven simultaneous packing and placement for modern FPGAs[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 37(10): 2022-2035) employs a greedy cell movement method to optimize bus length and proposes a new objective function to improve algorithm efficiency. The paper (Dhar S, Iyer MA, Adya S, et al. An effective timing-driven detailed placement algorithm for FPGAs[C] / / Proceedings of the 2017 ACM on International Symposium on PhysicalDesign. 2017: 151-157) mentions that network-based detailed placement is prone to oscillations, and there is still significant room for improvement in the output. The branch and bound algorithm proposed in the literature (Moffitt MD, Papa DA, Li Z, et al. Path smoothing via discrete optimization[C] / / Proceedings of 45th annual Design Automation Conference.2008: 724-727) can significantly improve the quality of large-scale designs, but its efficiency is not high.The paper (Li W, Dhar S, Pan D Z. UTPlaceF: A routability-driven FPGA placer with physical and congestion aware packing[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 37(4): 869-882) developed a detailed placement algorithm based on Independent Set Matching (ISM), which can simultaneously minimize line length and the number of external pins, thereby improving line length and routerizability. The paper (Abuowaimer Z, Maarouf D, Martin T, et al. GPlace3.0: Routability-driven analytic placer for UltraScale FPGA architectures[J]. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2018, 23(5): 1-33) proposed a dual-objective optimization (DOISM) detailed placement method based on Independent Set Matching (ISM), further improving line length and routerizability.
[0005] However, the above-mentioned improvement methods only achieve better optimization results for a specific target, focusing on a local aspect. Therefore, they do not comprehensively optimize the timing critical line length and bus length. Focusing only on bus length optimization without considering timing critical line length and clock region constraints is unreasonable. Such circuits often become unroutable during the routing phase and cannot meet timing constraints during the static timing analysis phase. Summary of the Invention
[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method and system for rapid detailed placement of FPGAs based on a greedy algorithm. By adding a clock-driven method to the greedy algorithm, the strategy of first considering the length of timing-critical lines and then optimizing the bus length is adopted. At the same time, OpenMP4.0 fine-grained parallel acceleration is used to improve the efficiency of the algorithm and achieve the goal of rapidly optimizing line length.
[0007] To achieve the above objectives, the technical solution provided by this invention is as follows:
[0008] A fast detailed placement method for FPGAs based on a greedy algorithm includes:
[0009] S1. Parse the FPGA architecture information and circuit netlist file to generate a global library mapping table, a global cell mapping table, and a global network mapping table. The global library mapping table stores the library cell types and attribute information of the FPGA architecture, providing a mapping basis for cell type identification and attribute querying. The global cell mapping table stores the location and connection information of all cells in the circuit netlist. The global network mapping table stores the connection relationships of all networks.
[0010] S2. Based on the global unit mapping table and the global network mapping table, update the unit and network information, and use an adjacency table to store the relationship between the network to which the unit is connected and the relationship between the unit to which the network is connected, so as to improve space utilization and traversal efficiency by utilizing the characteristics of sparse graphs.
[0011] S3. Update the Tile control signal based on the FPGA architecture information, initialize the Tile congestion density, and analyze the number of clock signals in each clock region to establish the basic constraints for congestion perception and clock validity judgment.
[0012] S4. Using the global cell mapping table and the global network mapping table, calculate the total FLUTX line length based on the line length of the cell, and calculate the total length of the time-critical line and the total length of the non-time-critical line based on the line length of the network; wherein, the total length of the time-critical line is the sum of the network lengths on the time-critical path, and the total length of the non-time-critical line is the sum of the network lengths on the non-time-critical path.
[0013] S5. Based on the statistical results of the total length of the time-critical lines, conditionally calculate the overlapping area of the bounding box formed by the connected network of units, screen out suitable candidate sites and sort them; under the constraints of the congestion density and the number of clock signals, move the units on the critical path to the candidate sites one by one through the greedy algorithm, and accept the move only when the congestion is legal, the clock signal does not overflow and the length of the time-critical line is optimally optimized, until all units on the critical path have found suitable sites that meet the constraints.
[0014] S6. Based on the optimization of critical path units, optimize the global line length; the global line length includes the sum of the time-series critical line lengths and the sum of the non-time-series critical line lengths; unconditionally calculate the overlapping area of the bounding box formed by the connected network of units, filter out suitable candidate sites and sort them; under the constraints of the congestion density and the number of clock signals, use a greedy algorithm to traverse all units one by one and move them to candidate sites, accepting the move only when the congestion is legal, the clock signal does not overflow and the global line length is optimally optimized, until all units find suitable sites that meet the constraints;
[0015] S7. Determine if the stopping criterion is met, i.e., all cells on the critical path and all cells globally have found suitable candidate sites; if met, output the best detailed layout solution; if not met, return to step S5 to continue iterative execution until convergence.
[0016] Furthermore, in step S3, the congestion-aware mechanism includes:
[0017] Preliminary check: If the cell is already in the current target tile, the current pin density of the target tile is directly accepted, and congestion estimation is not required; if the current tile has reached the cross-tile network connection limit, congestion estimation for that tile is abandoned.
[0018] Input pin increment calculation: For each input pin, obtain its network ID. If the network is valid and has a driver unit, increment the input pin increment by 1.
[0019] Output pin increment calculation: For each output pin, obtain its network ID. If the network is valid and spans multiple Tile networks, increment the output pin increment by 1.
[0020] Cross-Tile network constraint judgment: If the final number of cross-Tile network connections is less than the maximum allowed number of cross-Tile connections, then attempt to move the unit; otherwise, abandon the move.
[0021] Further, in step S5, the overlapping region of the bounding box formed by the interconnected network of cells is conditionally calculated, including:
[0022] If the current unit is the driving unit, then each network connected to this unit, excluding the driving unit, forms a bounding box with the remaining driven units. The median coordinate interval formed by all the bounding boxes determines the optimization area that the current driving unit can move.
[0023] If the current unit is a driven unit, then each network connected to this unit, excluding the driven unit, forms a Bounding Box with the remaining driving units. The median coordinate interval formed by all the Bounding Boxes determines the optimization region that the current driven unit can move.
[0024] Furthermore, the median coordinate interval formed by all bounding boxes determines the optimized region where the current drive unit can move, including:
[0025] Let the x-coordinate of all bounding boxes be represented as... ,right Sort:
[0026] ;
[0027] in, The x-coordinate before sorting; The x-coordinates are sorted and increase sequentially.
[0028] Let the ordinate of all bounding boxes be represented as... ,right Sort:
[0029] ;
[0030] in, The vertical axis before sorting; The vertical coordinates are sorted and increase sequentially.
[0031] The lower left coordinate of the optimization region is ( , The coordinates of the upper left corner are ( , The lower right coordinate is ( , The upper right coordinate is ( , ).
[0032] Further, in step S6, the overlapping region of the bounding box formed by the interconnected network of cells is calculated unconditionally, including:
[0033] Considering all units connected by the network, including driving units and driven units, calculate the overlapping area of the Bounding Box formed by all related units to expand the search range and achieve overall optimization of the global line length.
[0034] Furthermore, steps S5 and S6 employ OpenMP4.0 for fine-grained parallelization acceleration, achieving near-linear runtime scalability when multiple threads are started simultaneously.
[0035] Furthermore, to achieve the above objectives, the present invention also provides an FPGA fast detailed placement system based on a greedy algorithm, used to implement the above-mentioned FPGA fast detailed placement method based on a greedy algorithm, comprising:
[0036] Data initialization module: used to parse FPGA architecture information and circuit netlist files, and generate a global library mapping table, a global cell mapping table, and a global network mapping table; wherein, the global library mapping table is used to store the library cell type and attribute information of the FPGA architecture, providing a mapping basis for cell type identification and attribute query; the global cell mapping table is used to store the location and connection information of all cells in the circuit netlist; the global network mapping table is used to store the connection relationship of all networks;
[0037] The adjacency list construction module is connected to the data initialization module and is used to update the unit and network list information based on the global unit mapping table and the global network mapping table. It uses an adjacency list to store the relationship between the networks connected to the unit and the relationship between the units connected to the network, respectively, providing an efficient data access structure for the congestion and clock management module and the line length calculation module.
[0038] Congestion and Clock Management Module: Connected to the adjacency list construction module, it is used to update the Tile control signal based on the FPGA architecture information, initialize the congestion density of the Tile, and analyze the number of clock signals in each clock region one by one, providing constraint judgment conditions for the timing critical line length optimization module and the global line length optimization module.
[0039] Line length calculation module: Connected to the data initialization module and the adjacency list construction module, it is used to calculate the total FLUTX line length based on the line length of a cell, and to calculate the total time-critical line length and the total non-time-critical line length based on the line length of the network; wherein, the total time-critical line length is the sum of the network lengths on the time-critical path, and the total non-time-critical line length is the sum of the network lengths on the non-time-critical path; it provides an optimization evaluation benchmark for the time-critical line length optimization module and the global line length optimization module;
[0040] The timing critical line length optimization module is connected to the line length calculation module and the congestion and clock management module. It is used to conditionally calculate the overlapping area of the bounding box formed by the connected network of units based on the statistical results of the sum of the timing critical line lengths, screen candidate sites, and move the units on the critical path to the optimal candidate site through a greedy algorithm under the constraints of congestion density and clock signal number.
[0041] Global line length optimization module: connected to the timing critical line length optimization module, the line length calculation module, and the congestion and clock management module, used to optimize the global line length after completing the critical path optimization; the global line length includes the sum of the timing critical line lengths and the sum of the non-timing critical line lengths; unconditionally calculates the overlapping area of the bounding box formed by the network of connected units, filters candidate sites, and moves all units to the optimal candidate site through a greedy algorithm under the constraints of congestion density and clock signal number;
[0042] Iteration control module: Connected to the timing critical line length optimization module and the global line length optimization module, it is used to determine whether the stopping criteria are met, control the convergence of the iteration process, and output the final detailed layout solution.
[0043] Furthermore, the timing critical line length optimization module includes:
[0044] Driving unit optimization unit: When the current unit is a driving unit, it is used to form a bounding box by the remaining driven units after removing the driving unit from each network connected to the unit. The median coordinate interval formed by all the bounding boxes determines the optimized position that the current driving unit can move.
[0045] Driven unit optimization unit: When the current unit is a driven unit, it is used to form a bounding box by removing the driven units from each network connected to the current unit, and the median coordinate interval formed by all the bounding boxes determines the optimized position that the current driven unit can move.
[0046] Furthermore, the congestion and clock management module includes:
[0047] Preliminary check unit: Used to determine whether the unit is already in the current target tile, or whether the current tile has reached the cross-tile network connection limit;
[0048] Input pin increment calculation unit: used to obtain the network ID of each input pin. When the network is valid and a driving unit exists, the increment of the input pin is incremented by 1.
[0049] Output pin increment calculation unit: used to obtain the network ID of each output pin. When the network is valid and spans multiple Tile networks, the increment of the output pin is incremented by 1.
[0050] Cross-Tile Network Decision Unit: Used to determine whether the final number of cross-Tile network connections is less than the maximum allowed number of cross-Tile connections, in order to decide whether to allow the unit to move.
[0051] Compared with existing technologies, the principles and advantages of this technical solution are as follows:
[0052] 1. A two-level detailed layout strategy is adopted, first optimizing the length of critical timing lines and then optimizing the bus length. This can significantly reduce the length of critical timing lines while optimizing the bus length, overcoming the shortcomings of existing technologies that only focus on a single optimization objective.
[0053] 2. Clock constraints are considered in multiple stages. In each stage, all clock regions in the FPGA always satisfy clock validity to ensure correct timing representation and avoid unroutable problems during the routing stage.
[0054] 3. By employing congestion-aware strategies, we can optimize the layout while minimizing or even improving congestion levels, thus ensuring that subsequent cabling meets the requirements for cabling availability.
[0055] 4. Fine-grained parallelization is achieved using OpenMP4.0. With 8 threads running simultaneously, the detailed layout process can be accelerated by several times. As the number of threads increases, the algorithm has near-linear scalability in terms of runtime.
[0056] 5. Experimental results show that the algorithm of this invention optimizes timing critical line length by an average of 16.92%, non-timing critical line length by an average of 11.16%, and pin density by an average of 5.84%. The running time is completed within 4 minutes, which is 5 times better than the industrial requirement of 20 minutes. Attached Figure Description
[0057] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0058] Figure 1 This is a flowchart illustrating the principle of a fast detailed placement method for FPGA based on a greedy algorithm according to the present invention.
[0059] Figure 2 This is a circuit netlist diagram (Net stands for network).
[0060] Figure 3 The adjacency representation of all networks in each cell (Net is a network).
[0061] Figure 4 The adjacency representation of all units in each network (Net is a network).
[0062] Figure 5 A schematic diagram for identifying the overlapping area of Bounding Boxes;
[0063] Figure 6 A schematic diagram illustrating the process of unconditionally finding the overlapping region of the Bounding Box and searching for the best candidate site. Detailed Implementation
[0064] The present invention will be further described below with reference to specific embodiments:
[0065] The FPGA fast detailed placement method based on a greedy algorithm described in this embodiment adopts a two-level optimization strategy: the first level optimizes the timing critical path line length through timing driving units and timing driven units; the second level optimizes the global line length, and finally finds the best detailed placement result.
[0066] like Figure 1 As shown, the specific process is as follows:
[0067] S1. Parse the FPGA architecture information and circuit netlist file to generate a global library mapping table, a global cell mapping table, and a global network mapping table. The global library mapping table stores the library cell types and attribute information of the FPGA architecture, providing a mapping basis for cell type identification and attribute query. The global cell mapping table stores the location and connection information of all cells in the circuit netlist. The global network mapping table stores the connection relationships of all networks.
[0068] S2. Based on the global cell mapping table and the global network mapping table, update the cell and network information, and use an adjacency list to store the relationships between the networks connected to the cells and the relationships between the cells connected to the networks. For example... Figure 2 The example circuit netlist shown illustrates the construction of the relationships between cells and networks as follows: Figure 3 and Figure 4 As shown. For sparse graphs such as cells or networks in a circuit netlist, the adjacency list method can save more space and has the characteristic of high space utilization; at the same time, when traversing all vertices adjacent to a certain vertex, the time complexity of the adjacency list is proportional to the degree of the vertex.
[0069] S3. Update the Tile control signal based on FPGA architecture information, initialize the Tile congestion density, and analyze the number of clock signals in each clock region to establish the basic constraints for congestion perception and clock validity judgment.
[0070] In this step, the congestion-aware mechanism includes:
[0071] Preliminary check: If the cell is already in the current target tile, the current pin density of the target tile is directly accepted, and congestion estimation is not required; if the current tile has reached the cross-tile network connection limit, congestion estimation for that tile is abandoned.
[0072] Input pin increment calculation: For each input pin, obtain its network ID. If the network is valid and has a driver unit, increment the input pin increment by 1.
[0073] Output pin increment calculation: For each output pin, obtain its network ID. If the network is valid and spans multiple Tile networks, increment the output pin increment by 1.
[0074] Cross-Tile network constraint judgment: If the final number of cross-Tile network connections is less than the maximum allowed number of cross-Tile connections, then attempt to move the unit; otherwise, abandon the move.
[0075] S4. Using the global cell mapping table and the global network mapping table, calculate the total FLUTX line length based on the line length of the cell, and calculate the total length of the time-critical line and the total length of the non-time-critical line based on the line length of the network; wherein, the total length of the time-critical line is the sum of the network lengths on the time-critical path, and the total length of the non-time-critical line is the sum of the network lengths on the non-time-critical path.
[0076] S5, Optimization of timing critical line length (Level 1 optimization)
[0077] Based on the statistical results of the total length of the time-series critical lines, the overlapping area of the bounding box formed by the interconnected network of units is conditionally calculated, and suitable candidate sites are selected and sorted.
[0078] like Figure 5 As shown in (a), if the current unit is the driving unit, then each network connected to this unit, excluding the driving unit, forms a bounding box with the remaining driven units. The median coordinate interval formed by all the bounding boxes determines the movable optimization region of the current driving unit; the specific calculation method is as follows:
[0079] Let the x-coordinate of all bounding boxes be represented as... ,right Sort:
[0080] ;
[0081] in, The x-coordinate before sorting; The x-coordinates are sorted and increase sequentially;
[0082] Let the ordinate of all bounding boxes be represented as... ,right Sort:
[0083] ;
[0084] in, The vertical axis before sorting; The vertical coordinates are sorted and increase sequentially.
[0085] The lower left coordinate of the optimization region is ( , The coordinates of the upper left corner are ( , The lower right coordinate is ( , The upper right coordinate is ( , ).
[0086] Similarly, if the current unit is a driven unit, then each network connected to this unit, excluding the driven unit, forms a Bounding Box with the remaining driving units. The median coordinate interval formed by all the Bounding Boxes determines the optimization region that the current driven unit can move.
[0087] Under the constraints of congestion density and clock signal number, a greedy algorithm is used to traverse the critical path and move the units to candidate sites one by one. The move is accepted only if the congestion is legal, the clock signal does not overflow, and the timing critical line length is optimally optimized. The first-level optimization stops when all units on the critical path have found suitable sites that meet the constraints.
[0088] S6. Global Line Length Optimization (Second-Level Optimization): Based on the optimization of critical path units, global line length is optimized; the global line length includes the sum of the time-series critical line lengths and the sum of the non-time-series critical line lengths; the overlapping area of the bounding box formed by the interconnected network of units is calculated unconditionally, and suitable candidate stations are selected and sorted.
[0089] like Figure 6 As shown, this approach considers not only the driving and driven units, but all units connected to the network. Under the constraints of congestion density and clock signal count, a greedy algorithm iterates through all units and moves them to candidate sites one by one. A move is accepted only if the congestion is legal, the clock signal does not overflow, and the global line length is optimally optimized. This process continues until all units have found suitable sites that satisfy the constraints, at which point the second-level optimization stops.
[0090] S7. Determine if the stopping criterion is met, i.e., all cells on the critical path and all cells globally have found suitable candidate sites; if met, output the best detailed layout solution; if not met, return to step S5 to continue iterative execution until convergence.
[0091] In the above, steps S5 and S6 use OpenMP4.0 for fine-grained parallelization acceleration, achieving near-linear runtime scalability when multiple threads are started simultaneously.
[0092] Experimental verification
[0093] This invention has been validated on open-source and authoritative industry benchmarks, using 10 large-scale netlists provided by Shanghai Anlu Technology Co., Ltd. as test benchmarks, which differ in circuit scale.
[0094] The evaluation metrics for the experiment include timing critical line length, non-timing critical line length, pin density, and runtime.
[0095] 1. Results of Optimization of Timing Critical Path Length
[0096] As shown in Table 1, compared to the baseline, the algorithm of this invention optimizes the timing critical line length on all test benchmarks, with an average optimization magnitude of 16.92%. Among them, case 10 has the largest optimization magnitude, reaching 36.16%, while case 6 has a relatively smaller optimization magnitude of only 8.12%.
[0097] Table 1. Experimental results of Crit WL (Timing Critical Length) in 10 industrial cases.
[0098] Case BASE (Crit WL) WireDP (Crit WL) case1 17751(1.0) 14597(17.76%) case2 44912(1.0) 32628(27.35%) case3 85749(1.0) 75640(11.78%) case4 242824(1.0) 219451(9.62%) case5 410912(1.0) 355630(13.45%) case6 526210(1.0) 483456(8.12%) case 7 780093(1.0) 681071(12.69%) case8 958983(1.0) 863390(9.96%) case9 471232(1.0) 366000(22.33%) case10 669968(1.0) 427695(36.16%) total 1.0 16.92%
[0099] 2. Optimization results for non-timing critical line lengths
[0100] As shown in Table 2, compared with the baseline, the algorithm of this invention has improved the non-timing critical line length on all test benchmarks, with an average improvement of 11.16%. Among them, case 10 has the largest improvement of 26.03%, while case 8 has a relatively small improvement of only 5.24%.
[0101] Table 2. Experimental results of Non-Crit WL (Non-Timing Critical Length) in 10 industrial cases.
[0102] Case BASE(NonCrit WL) WireDP (NonCrit WL) case1 59876(1.0) 53499(10.65%) case2 164393(1.0) 138253(15.90%) case3 378099(1.0) 338321(10.52%) case4 796167(1.0) 732543(7.99%) case5 1096569(1.0) 983232(10.33%) case6 1315529(1.0) 1239193(5.80%) case 7 1379492(1.0) 1298362(5.88%) case8 2458146(1.0) 2329259(5.24%) case9 2018663(1.0) 1750911(13.26%) case10 2261984(1.0) 1672977(26.03%) total 1.0 11.16%
[0103] 3. Pin density optimization results
[0104] As shown in Table 3, compared to the baseline, the pin density of this invention is optimized on all test benchmarks, with an average optimization of 5.84%. Among them, case 5 has the largest optimization, reaching 8.12%, while case 4 has a relatively small optimization, only 2.15%.
[0105] Table 3. Pin Density Experiment Results in 10 Industrial Cases
[0106] Case BASE (Pin Density) WireDP (Pin Density) case1 26.13%(1.0) 24.46%(6.39%) case2 25.84%(1.0) 23.76%(8.04%) case3 26.55%(1.0) 25.12%(5.38%) case4 26.03%(1.0) 25.47%(2.15%) case5 25.72%(1.0) 23.63%(8.12%) case6 27.68%(1.0) 26%(6.06%) case 7 27.40%(1.0) 26.82%(2.11%) case8 29.03%(1.0) 27.34%(5.82%) case9 33.09%(1.0) 30.96%(6.43%) case10 33.22%(1.0) 30.57%(7.97%) total 1.0 5.84%
[0107] 4. Running time
[0108] Table 4 shows that the running time of this invention is all within 4 minutes, which is 5 times higher than the industrial requirement of 20 minutes, demonstrating very high efficiency.
[0109] Case WireDP (Run Time) case1 9.53s case2 9.53s case3 26.37s case4 106.17s case5 99.1s case6 79.14s case 7 28.93s case8 201s case9 128.09s case10 118.46s
[0110] Experimental results show that the present invention can achieve good solution quality within a specified time. While accelerating the convergence speed of the algorithm and improving the efficiency of the algorithm, the solution quality can be significantly improved.
[0111] Additionally, this embodiment also includes an FPGA fast detailed placement system based on a greedy algorithm, used to implement the above-described FPGA fast detailed placement method based on a greedy algorithm, including:
[0112] Data initialization module: used to parse FPGA architecture information and circuit netlist files, and generate a global library mapping table, a global cell mapping table, and a global network mapping table; wherein, the global library mapping table is used to store the library cell type and attribute information of the FPGA architecture, providing a mapping basis for cell type identification and attribute query; the global cell mapping table is used to store the location and connection information of all cells in the circuit netlist; the global network mapping table is used to store the connection relationship of all networks;
[0113] The adjacency list construction module is connected to the data initialization module and is used to update the unit and network list information based on the global unit mapping table and the global network mapping table. It uses an adjacency list to store the relationship between the networks connected to the unit and the relationship between the units connected to the network, respectively, providing an efficient data access structure for the congestion and clock management module and the line length calculation module.
[0114] Congestion and Clock Management Module: Connected to the adjacency list construction module, it is used to update the Tile control signal based on the FPGA architecture information, initialize the congestion density of the Tile, and analyze the number of clock signals in each clock region one by one, providing constraint judgment conditions for the timing critical line length optimization module and the global line length optimization module.
[0115] Line length calculation module: Connected to the data initialization module and the adjacency list construction module, it is used to calculate the total FLUTX line length based on the line length of a cell, and to calculate the total time-critical line length and the total non-time-critical line length based on the line length of the network; wherein, the total time-critical line length is the sum of the network lengths on the time-critical path, and the total non-time-critical line length is the sum of the network lengths on the non-time-critical path; it provides an optimization evaluation benchmark for the time-critical line length optimization module and the global line length optimization module;
[0116] The timing critical line length optimization module is connected to the line length calculation module and the congestion and clock management module. It is used to conditionally calculate the overlapping area of the bounding box formed by the connected network of units based on the statistical results of the sum of the timing critical line lengths, screen candidate sites, and move the units on the critical path to the optimal candidate site through a greedy algorithm under the constraints of congestion density and clock signal number.
[0117] Global line length optimization module: connected to the timing critical line length optimization module, the line length calculation module, and the congestion and clock management module, used to optimize the global line length after completing the critical path optimization; the global line length includes the sum of the timing critical line lengths and the sum of the non-timing critical line lengths; unconditionally calculates the overlapping area of the bounding box formed by the network of connected units, filters candidate sites, and moves all units to the optimal candidate site through a greedy algorithm under the constraints of congestion density and clock signal number;
[0118] Iteration control module: Connected to the timing critical line length optimization module and the global line length optimization module, it is used to determine whether the stopping criteria are met, control the convergence of the iteration process, and output the final detailed layout solution.
[0119] Specifically, the timing critical line length optimization module includes:
[0120] Driving unit optimization unit: When the current unit is a driving unit, it is used to form a bounding box by the remaining driven units after removing the driving unit from each network connected to the unit. The median coordinate interval formed by all the bounding boxes determines the optimized position that the current driving unit can move.
[0121] Driven unit optimization unit: When the current unit is a driven unit, it is used to form a bounding box by removing the driven units from each network connected to the current unit, and the median coordinate interval formed by all the bounding boxes determines the optimized position that the current driven unit can move.
[0122] Specifically, the congestion and clock management module includes:
[0123] Preliminary check unit: Used to determine whether the unit is already in the current target tile, or whether the current tile has reached the cross-tile network connection limit;
[0124] Input pin increment calculation unit: used to obtain the network ID of each input pin. When the network is valid and a driving unit exists, the increment of the input pin is incremented by 1.
[0125] Output pin increment calculation unit: used to obtain the network ID of each output pin. When the network is valid and spans multiple Tile networks, the increment of the output pin is incremented by 1.
[0126] Cross-Tile Network Decision Unit: Used to determine whether the final number of cross-Tile network connections is less than the maximum allowed number of cross-Tile connections, in order to decide whether to allow the unit to move.
[0127] The above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Therefore, any changes made in accordance with the shape and principle of the present invention should be covered within the protection scope of the present invention.
Claims
1. A fast detailed placement method for FPGA based on a greedy algorithm, characterized in that, include: S1. Parse the FPGA architecture information and circuit netlist file to generate a global library mapping table, a global cell mapping table, and a global network mapping table. The global library mapping table stores the library cell types and attribute information of the FPGA architecture, providing a mapping basis for cell type identification and attribute querying. The global cell mapping table stores the location and connection information of all cells in the circuit netlist. The global network mapping table stores the connection relationships of all networks. S2. Based on the global unit mapping table and the global network mapping table, update the unit and network information, and use an adjacency table to store the relationship between the network to which the unit is connected and the relationship between the unit to which the network is connected, so as to improve space utilization and traversal efficiency by utilizing the characteristics of sparse graphs. S3. Update the Tile control signal based on the FPGA architecture information, initialize the Tile congestion density, and analyze the number of clock signals in each clock region to establish the basic constraints for congestion perception and clock validity judgment. S4. Using the global cell mapping table and the global network mapping table, calculate the total FLUTX line length based on the line length of the cell, and calculate the total length of the time-critical line and the total length of the non-time-critical line based on the line length of the network; wherein, the total length of the time-critical line is the sum of the network lengths on the time-critical path, and the total length of the non-time-critical line is the sum of the network lengths on the non-time-critical path. S5. Based on the statistical results of the total length of the time-critical lines, conditionally calculate the overlapping area of the bounding box formed by the connected network of units, screen out suitable candidate sites and sort them; under the constraints of the congestion density and the number of clock signals, move the units on the critical path to the candidate sites one by one through the greedy algorithm, and accept the move only when the congestion is legal, the clock signal does not overflow and the length of the time-critical line is optimally optimized, until all units on the critical path have found suitable sites that meet the constraints. S6. Based on the optimization of critical path units, optimize the global line length; the global line length includes the sum of the time-series critical line lengths and the sum of the non-time-series critical line lengths; unconditionally calculate the overlapping area of the bounding box formed by the connected network of units, filter out suitable candidate sites and sort them; under the constraints of the congestion density and the number of clock signals, use a greedy algorithm to traverse all units one by one and move them to candidate sites, accepting the move only when the congestion is legal, the clock signal does not overflow and the global line length is optimally optimized, until all units find suitable sites that meet the constraints; S7. Determine if the stopping criterion is met, i.e., all cells on the critical path and all cells globally have found suitable candidate sites; if met, output the best detailed layout solution; if not met, return to step S5 to continue iterative execution until convergence.
2. The FPGA fast detailed placement method based on a greedy algorithm according to claim 1, characterized in that, In step S3, the congestion-aware mechanism includes: Preliminary check: If the cell is already in the current target tile, the current pin density of the target tile is directly accepted, and congestion estimation is not required; if the current tile has reached the cross-tile network connection limit, congestion estimation for that tile is abandoned. Input pin increment calculation: For each input pin, obtain its network ID. If the network is valid and has a driver unit, increment the input pin increment by 1. Output pin increment calculation: For each output pin, obtain its network ID. If the network is valid and spans multiple Tile networks, increment the output pin increment by 1. Cross-Tile network constraint judgment: If the final number of cross-Tile network connections is less than the maximum allowed number of cross-Tile connections, then attempt to move the unit; otherwise, abandon the move.
3. The FPGA fast detailed placement method based on a greedy algorithm according to claim 1, characterized in that, In step S5, the overlapping region of the bounding box formed by the interconnected network of cells is conditionally calculated, including: If the current unit is the driving unit, then each network connected to this unit, excluding the driving unit, forms a bounding box with the remaining driven units. The median coordinate interval formed by all the bounding boxes determines the optimization area that the current driving unit can move. If the current unit is a driven unit, then each network connected to this unit, excluding the driven unit, forms a Bounding Box with the remaining driving units. The median coordinate interval formed by all the Bounding Boxes determines the optimization region that the current driven unit can move.
4. The FPGA fast detailed placement method based on a greedy algorithm according to claim 3, characterized in that, The median coordinate interval formed by all bounding boxes determines the optimized region where the current drive unit can move, including: Let the x-coordinate of all bounding boxes be represented as... ,right Sort: ； in, The x-coordinate before sorting; The x-coordinates are sorted and increase sequentially; Let the ordinate of all bounding boxes be represented as... ,right Sort: ； in, The vertical axis before sorting; The vertical coordinates are sorted and increase sequentially. The lower left coordinate of the optimization region is ( , The coordinates of the upper left corner are ( , The lower right coordinate is ( , The upper right coordinate is ( , ).
5. The FPGA fast detailed placement method based on a greedy algorithm according to claim 1, characterized in that, In step S6, the overlapping region of the bounding box formed by the interconnected cell network is calculated unconditionally, including: Considering all units connected by the network, including driving units and driven units, calculate the overlapping area of the Bounding Box formed by all related units to expand the search range and achieve overall optimization of the global line length.
6. The FPGA fast detailed placement method based on a greedy algorithm according to claim 3, characterized in that, Steps S5 and S6 use OpenMP4.0 for fine-grained parallelization acceleration, achieving near-linear runtime scalability when multiple threads are started simultaneously.
7. A fast detailed placement system for FPGA based on a greedy algorithm, used to implement the fast detailed placement method for FPGA based on a greedy algorithm as described in any one of claims 1-6, characterized in that, include: Data initialization module: used to parse FPGA architecture information and circuit netlist files, and generate a global library mapping table, a global cell mapping table, and a global network mapping table; wherein, the global library mapping table is used to store the library cell type and attribute information of the FPGA architecture, providing a mapping basis for cell type identification and attribute query; the global cell mapping table is used to store the location and connection information of all cells in the circuit netlist; the global network mapping table is used to store the connection relationship of all networks; The adjacency list construction module is connected to the data initialization module and is used to update the unit and network list information based on the global unit mapping table and the global network mapping table. It uses an adjacency list to store the relationship between the networks connected to the unit and the relationship between the units connected to the network, respectively, providing an efficient data access structure for the congestion and clock management module and the line length calculation module. Congestion and Clock Management Module: Connected to the adjacency list construction module, it is used to update the Tile control signal based on the FPGA architecture information, initialize the congestion density of the Tile, and analyze the number of clock signals in each clock region one by one, providing constraint judgment conditions for the timing critical line length optimization module and the global line length optimization module. Line length calculation module: Connected to the data initialization module and the adjacency list construction module, it is used to calculate the total FLUTX line length based on the line length of a cell, and to calculate the total time-critical line length and the total non-time-critical line length based on the line length of the network; wherein, the total time-critical line length is the sum of the network lengths on the time-critical path, and the total non-time-critical line length is the sum of the network lengths on the non-time-critical path; it provides an optimization evaluation benchmark for the time-critical line length optimization module and the global line length optimization module; The timing critical line length optimization module is connected to the line length calculation module and the congestion and clock management module. It is used to conditionally calculate the overlapping area of the bounding box formed by the connected network of units based on the statistical results of the sum of the timing critical line lengths, screen candidate sites, and move the units on the critical path to the optimal candidate site through a greedy algorithm under the constraints of congestion density and clock signal number. Global line length optimization module: connected to the timing critical line length optimization module, the line length calculation module, and the congestion and clock management module, used to optimize the global line length after completing the critical path optimization; the global line length includes the sum of the timing critical line lengths and the sum of the non-timing critical line lengths; unconditionally calculates the overlapping area of the bounding box formed by the network of connected units, filters candidate sites, and moves all units to the optimal candidate site through a greedy algorithm under the constraints of congestion density and clock signal number; Iteration control module: Connected to the timing critical line length optimization module and the global line length optimization module, it is used to determine whether the stopping criteria are met, control the convergence of the iteration process, and output the final detailed layout solution.
8. The FPGA fast detailed placement system based on a greedy algorithm according to claim 7, characterized in that, The timing critical line length optimization module includes: Driving unit optimization unit: When the current unit is a driving unit, it is used to form a bounding box by the remaining driven units after removing the driving unit from each network connected to the unit. The median coordinate interval formed by all the bounding boxes determines the optimized position that the current driving unit can move. Driven unit optimization unit: When the current unit is a driven unit, it is used to form a bounding box by removing the driven units from each network connected to the current unit, and the median coordinate interval formed by all the bounding boxes determines the optimized position that the current driven unit can move.
9. The FPGA fast detailed placement system based on a greedy algorithm according to claim 7, characterized in that, The congestion and clock management module includes: Preliminary check unit: Used to determine whether the unit is already in the current target tile, or whether the current tile has reached the cross-tile network connection limit; Input pin increment calculation unit: used to obtain the network ID of each input pin. When the network is valid and a driving unit exists, the increment of the input pin is incremented by 1. Output pin increment calculation unit: used to obtain the network ID of each output pin. When the network is valid and spans multiple Tile networks, the increment of the output pin is incremented by 1. Cross-Tile Network Decision Unit: Used to determine whether the final number of cross-Tile network connections is less than the maximum allowed number of cross-Tile connections, in order to decide whether to allow the unit to move.